package/boot/uboot-mediatek/patches/001-eth-mtk-add-mt7531-switch.patch

   1 From patchwork Tue Feb 18 08:49:37 2020
   2 Content-Type: text/plain; charset="utf-8"
   3 MIME-Version: 1.0
   4 Content-Transfer-Encoding: 7bit
   5 X-Patchwork-Submitter: Landen Chao <landen.chao@mediatek.com>
   6 X-Patchwork-Id: 1239956
   7 X-Patchwork-Delegate: trini@ti.com
   8 Return-Path: <u-boot-bounces@lists.denx.de>
   9 X-Original-To: incoming@patchwork.ozlabs.org
  10 Delivered-To: patchwork-incoming@bilbo.ozlabs.org
  11 Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized)
  12  smtp.mailfrom=lists.denx.de
  13  (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01;
  14  helo=phobos.denx.de;
  15  envelope-from=u-boot-bounces@lists.denx.de;
  16  receiver=<UNKNOWN>)
  17 Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none)
  18  header.from=mediatek.com
  19 Authentication-Results: ozlabs.org; dkim=pass (1024-bit key;
  20  unprotected) header.d=mediatek.com header.i=@mediatek.com
  21  header.a=rsa-sha256 header.s=dk header.b=NQKfnebM;
  22  dkim-atps=neutral
  23 Received: from phobos.denx.de (phobos.denx.de
  24  [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])
  25  (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
  26  key-exchange X25519 server-signature RSA-PSS (4096 bits))
  27  (No client certificate requested)
  28  by ozlabs.org (Postfix) with ESMTPS id 48MJX54ymTz9sRf
  29  for <incoming@patchwork.ozlabs.org>;
  30  Tue, 18 Feb 2020 22:28:53 +1100 (AEDT)
  31 Received: from h2850616.stratoserver.net (localhost [IPv6:::1])
  32  by phobos.denx.de (Postfix) with ESMTP id A68D8810D8;
  33  Tue, 18 Feb 2020 12:28:47 +0100 (CET)
  34 Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none)
  35  header.from=mediatek.com
  36 Authentication-Results: phobos.denx.de;
  37  spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de
  38 Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key;
  39  unprotected) header.d=mediatek.com header.i=@mediatek.com
  40  header.b="NQKfnebM"; dkim-atps=neutral
  41 Received: by phobos.denx.de (Postfix, from userid 109)
  42  id 767F881217; Tue, 18 Feb 2020 09:50:00 +0100 (CET)
  43 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de
  44 X-Spam-Level:
  45 X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,
  46  DKIM_VALID,DKIM_VALID_AU,MIME_BASE64_TEXT,RDNS_NONE,SPF_HELO_NONE,
  47  UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=no autolearn_force=no
  48  version=3.4.2
  49 Received: from mailgw01.mediatek.com (unknown [210.61.82.183])
  50  by phobos.denx.de (Postfix) with ESMTP id 40ADE811FB
  51  for <u-boot@lists.denx.de>; Tue, 18 Feb 2020 09:49:46 +0100 (CET)
  52 Authentication-Results: phobos.denx.de;
  53  dmarc=pass (p=none dis=none) header.from=mediatek.com
  54 Authentication-Results: phobos.denx.de;
  55  spf=pass smtp.mailfrom=landen.chao@mediatek.com
  56 X-UUID: ddaa8deb3c7d4a24ba5cbcb30775fbfd-20200218
  57 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
  58  d=mediatek.com; s=dk;
  59  h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;
  60  bh=qvWp4DdC1p5SZD1XJPV3kwdXTU9lBi4hbWNZQoO2oLI=;
  61  b=NQKfnebM0mIfPJuncOxa6aNY+g5wFOnlozbm/o8ViKaVNbkd8YSB0ISWOerj8lALM7E7sSP797r514G3R4EAQPPvuAm5B2wi2VuYKssTxHkvYJvCrALXp4wmQtGF+gJytfdWuHx6Np0wfbjTsLqw+JUtcDi/0jAa8TQ5y9UHr9Q=;
  62 X-UUID: ddaa8deb3c7d4a24ba5cbcb30775fbfd-20200218
  63 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by
  64  mailgw01.mediatek.com (envelope-from <landen.chao@mediatek.com>)
  65  (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS)
  66  with ESMTP id 827129897; Tue, 18 Feb 2020 16:49:43 +0800
  67 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by
  68  mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server
  69  (TLS) id 15.0.1395.4; Tue, 18 Feb 2020 16:48:45 +0800
  70 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc
  71  (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via
  72  Frontend Transport; Tue, 18 Feb 2020 16:47:41 +0800
  73 From: Landen Chao <landen.chao@mediatek.com>
  74 To: Ryder Lee <ryder.lee@mediatek.com>, Weijie Gao <weijie.gao@mediatek.com>,
  75  GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
  76  Joe Hershberger <joe.hershberger@ni.com>, <u-boot@lists.denx.de>
  77 CC: <frank-w@public-files.de>, <steven.liu@mediatek.com>,
  78  <landen.chao@mediatek.com>, <mark-mc.lee@mediatek.com>
  79 Subject: [U-Boot 1/1] eth: mtk-eth: add mt7531 switch support in mediatek eth
  80  driver
  81 Date: Tue, 18 Feb 2020 16:49:37 +0800
  82 Message-ID: <f10c8e2e72fda3ac9d8d240b128f28c52cf06f3f.1582015221.git.landen.chao@mediatek.com>
  83 X-Mailer: git-send-email 2.18.0
  84 In-Reply-To: <cover.1582015221.git.landen.chao@mediatek.com>
  85 References: <cover.1582015221.git.landen.chao@mediatek.com>
  86 MIME-Version: 1.0
  87 X-MTK: N
  88 X-Mailman-Approved-At: Tue, 18 Feb 2020 12:28:45 +0100
  89 X-BeenThere: u-boot@lists.denx.de
  90 X-Mailman-Version: 2.1.30rc1
  91 Precedence: list
  92 List-Id: U-Boot discussion <u-boot.lists.denx.de>
  93 List-Unsubscribe: <https://lists.denx.de/options/u-boot>,
  94  <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>
  95 List-Archive: <https://lists.denx.de/pipermail/u-boot/>
  96 List-Post: <mailto:u-boot@lists.denx.de>
  97 List-Help: <mailto:u-boot-request@lists.denx.de?subject=help>
  98 List-Subscribe: <https://lists.denx.de/listinfo/u-boot>,
  99  <mailto:u-boot-request@lists.denx.de?subject=subscribe>
 100 Errors-To: u-boot-bounces@lists.denx.de
 101 Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
 102 X-Virus-Scanned: clamav-milter 0.102.1 at phobos.denx.de
 103 X-Virus-Status: Clean
 104
 105 mt7531 is a 7-ports switch with 5 embedded giga phys, and uses the same
 106 MAC design of mt7530. The cpu port6 supports SGMII only. The cpu port5
 107 supports RGMII or SGMII in different model.
 108
 109 mt7531 is connected to mt7622 via both RGMII and SGMII interfaces.
 110 In this patch, mt7531 cpu port5 or port6 is configured to maximum
 111 capability to align CPU MAC setting.
 112
 113 The dts has been committed in the commit 6efa450565cdc ("arm: dts:
 114 mediatek: add ethernet and sgmii dts node for mt7622")
 115
 116 Signed-off-by: Landen Chao <landen.chao@mediatek.com>
 117 Tested-by: Frank Wunderlich <frank-w@public-files.de>
 118 ---
 119  drivers/net/mtk_eth.c | 580 +++++++++++++++++++++++++++++++++---------
 120  drivers/net/mtk_eth.h | 124 ++++++++-
 121  2 files changed, 577 insertions(+), 127 deletions(-)
 122
 123 diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
 124 index edfa5d1ce8..f7d34a2e6b 100644
 125 --- a/drivers/net/mtk_eth.c
 126 +++ b/drivers/net/mtk_eth.c
 127 @@ -30,10 +30,12 @@
 128  #define RX_TOTAL_BUF_SIZE      (NUM_RX_DESC * PKTSIZE_ALIGN)
 129  #define TOTAL_PKT_BUF_SIZE     (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
 130
 131 -#define MT7530_NUM_PHYS                5
 132 -#define MT7530_DFL_SMI_ADDR    31
 133 +#define MT753X_NUM_PHYS                5
 134 +#define MT753X_NUM_PORTS       7
 135 +#define MT753X_DFL_SMI_ADDR    31
 136 +#define MT753X_SMI_ADDR_MASK   0x1f
 137
 138 -#define MT7530_PHY_ADDR(base, addr) \
 139 +#define MT753X_PHY_ADDR(base, addr) \
 140         (((base) + (addr)) & 0x1f)
 141
 142  #define GDMA_FWD_TO_CPU \
 143 @@ -131,7 +133,8 @@ struct pdma_txdesc {
 144
 145  enum mtk_switch {
 146         SW_NONE,
 147 -       SW_MT7530
 148 +       SW_MT7530,
 149 +       SW_MT7531
 150  };
 151
 152  enum mtk_soc {
 153 @@ -173,8 +176,8 @@ struct mtk_eth_priv {
 154
 155         enum mtk_switch sw;
 156         int (*switch_init)(struct mtk_eth_priv *priv);
 157 -       u32 mt7530_smi_addr;
 158 -       u32 mt7530_phy_base;
 159 +       u32 mt753x_smi_addr;
 160 +       u32 mt753x_phy_base;
 161
 162         struct gpio_desc rst_gpio;
 163         int mcm;
 164 @@ -349,6 +352,174 @@ static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
 165         return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
 166  }
 167
 168 +/*
 169 + * MT7530 Internal Register Address Bits
 170 + * -------------------------------------------------------------------
 171 + * | 15  14  13  12  11  10   9   8   7   6 | 5   4   3   2 | 1   0  |
 172 + * |----------------------------------------|---------------|--------|
 173 + * |              Page Address              |  Reg Address  | Unused |
 174 + * -------------------------------------------------------------------
 175 + */
 176 +
 177 +static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
 178 +{
 179 +       int ret, low_word, high_word;
 180 +
 181 +       /* Write page address */
 182 +       ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
 183 +       if (ret)
 184 +               return ret;
 185 +
 186 +       /* Read low word */
 187 +       low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf);
 188 +       if (low_word < 0)
 189 +               return low_word;
 190 +
 191 +       /* Read high word */
 192 +       high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10);
 193 +       if (high_word < 0)
 194 +               return high_word;
 195 +
 196 +       if (data)
 197 +               *data = ((u32)high_word << 16) | (low_word & 0xffff);
 198 +
 199 +       return 0;
 200 +}
 201 +
 202 +static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
 203 +{
 204 +       int ret;
 205 +
 206 +       /* Write page address */
 207 +       ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
 208 +       if (ret)
 209 +               return ret;
 210 +
 211 +       /* Write low word */
 212 +       ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf,
 213 +                           data & 0xffff);
 214 +       if (ret)
 215 +               return ret;
 216 +
 217 +       /* Write high word */
 218 +       return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16);
 219 +}
 220 +
 221 +static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
 222 +                          u32 set)
 223 +{
 224 +       u32 val;
 225 +
 226 +       mt753x_reg_read(priv, reg, &val);
 227 +       val &= ~clr;
 228 +       val |= set;
 229 +       mt753x_reg_write(priv, reg, val);
 230 +}
 231 +
 232 +/* Indirect MDIO clause 22/45 access */
 233 +static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data,
 234 +                        u32 cmd, u32 st)
 235 +{
 236 +       ulong timeout;
 237 +       u32 val, timeout_ms;
 238 +       int ret = 0;
 239 +
 240 +       val = (st << MDIO_ST_S) |
 241 +             ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
 242 +             ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
 243 +             ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
 244 +
 245 +       if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
 246 +               val |= data & MDIO_RW_DATA_M;
 247 +
 248 +       mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST);
 249 +
 250 +       timeout_ms = 100;
 251 +       timeout = get_timer(0);
 252 +       while (1) {
 253 +               mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
 254 +
 255 +               if ((val & PHY_ACS_ST) == 0)
 256 +                       break;
 257 +
 258 +               if (get_timer(timeout) > timeout_ms)
 259 +                       return -ETIMEDOUT;
 260 +       }
 261 +
 262 +       if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
 263 +               mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
 264 +               ret = val & MDIO_RW_DATA_M;
 265 +       }
 266 +
 267 +       return ret;
 268 +}
 269 +
 270 +static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
 271 +{
 272 +       u8 phy_addr;
 273 +
 274 +       if (phy >= MT753X_NUM_PHYS)
 275 +               return -EINVAL;
 276 +
 277 +       phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
 278 +
 279 +       return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ,
 280 +                            MDIO_ST_C22);
 281 +}
 282 +
 283 +static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg,
 284 +                               u16 val)
 285 +{
 286 +       u8 phy_addr;
 287 +
 288 +       if (phy >= MT753X_NUM_PHYS)
 289 +               return -EINVAL;
 290 +
 291 +       phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
 292 +
 293 +       return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE,
 294 +                            MDIO_ST_C22);
 295 +}
 296 +
 297 +int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
 298 +{
 299 +       u8 phy_addr;
 300 +       int ret;
 301 +
 302 +       if (addr >= MT753X_NUM_PHYS)
 303 +               return -EINVAL;
 304 +
 305 +       phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
 306 +
 307 +       ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
 308 +                           MDIO_ST_C45);
 309 +       if (ret)
 310 +               return ret;
 311 +
 312 +       return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45,
 313 +                            MDIO_ST_C45);
 314 +}
 315 +
 316 +static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
 317 +                               u16 reg, u16 val)
 318 +{
 319 +       u8 phy_addr;
 320 +       int ret;
 321 +
 322 +       if (addr >= MT753X_NUM_PHYS)
 323 +               return 0;
 324 +
 325 +       phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
 326 +
 327 +       ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
 328 +                           MDIO_ST_C45);
 329 +       if (ret)
 330 +               return ret;
 331 +
 332 +       return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE,
 333 +                            MDIO_ST_C45);
 334 +}
 335 +
 336  static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 337  {
 338         struct mtk_eth_priv *priv = bus->priv;
 339 @@ -387,6 +558,12 @@ static int mtk_mdio_register(struct udevice *dev)
 340                 priv->mmd_read = mtk_mmd_ind_read;
 341                 priv->mmd_write = mtk_mmd_ind_write;
 342                 break;
 343 +       case SW_MT7531:
 344 +               priv->mii_read = mt7531_mii_ind_read;
 345 +               priv->mii_write = mt7531_mii_ind_write;
 346 +               priv->mmd_read = mt7531_mmd_ind_read;
 347 +               priv->mmd_write = mt7531_mmd_ind_write;
 348 +               break;
 349         default:
 350                 priv->mii_read = mtk_mii_read;
 351                 priv->mii_write = mtk_mii_write;
 352 @@ -410,75 +587,18 @@ static int mtk_mdio_register(struct udevice *dev)
 353         return 0;
 354  }
 355
 356 -/*
 357 - * MT7530 Internal Register Address Bits
 358 - * -------------------------------------------------------------------
 359 - * | 15  14  13  12  11  10   9   8   7   6 | 5   4   3   2 | 1   0  |
 360 - * |----------------------------------------|---------------|--------|
 361 - * |              Page Address              |  Reg Address  | Unused |
 362 - * -------------------------------------------------------------------
 363 - */
 364 -
 365 -static int mt7530_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
 366 +static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg)
 367  {
 368 -       int ret, low_word, high_word;
 369 +       u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
 370
 371 -       /* Write page address */
 372 -       ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6);
 373 -       if (ret)
 374 -               return ret;
 375 -
 376 -       /* Read low word */
 377 -       low_word = mtk_mii_read(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf);
 378 -       if (low_word < 0)
 379 -               return low_word;
 380 -
 381 -       /* Read high word */
 382 -       high_word = mtk_mii_read(priv, priv->mt7530_smi_addr, 0x10);
 383 -       if (high_word < 0)
 384 -               return high_word;
 385 -
 386 -       if (data)
 387 -               *data = ((u32)high_word << 16) | (low_word & 0xffff);
 388 -
 389 -       return 0;
 390 +       return priv->mmd_read(priv, phy_addr, 0x1f, reg);
 391  }
 392
 393 -static int mt7530_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
 394 +static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
 395  {
 396 -       int ret;
 397 -
 398 -       /* Write page address */
 399 -       ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6);
 400 -       if (ret)
 401 -               return ret;
 402 +       u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
 403
 404 -       /* Write low word */
 405 -       ret = mtk_mii_write(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf,
 406 -                           data & 0xffff);
 407 -       if (ret)
 408 -               return ret;
 409 -
 410 -       /* Write high word */
 411 -       return mtk_mii_write(priv, priv->mt7530_smi_addr, 0x10, data >> 16);
 412 -}
 413 -
 414 -static void mt7530_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
 415 -                          u32 set)
 416 -{
 417 -       u32 val;
 418 -
 419 -       mt7530_reg_read(priv, reg, &val);
 420 -       val &= ~clr;
 421 -       val |= set;
 422 -       mt7530_reg_write(priv, reg, val);
 423 -}
 424 -
 425 -static void mt7530_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
 426 -{
 427 -       u8 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, 0);
 428 -
 429 -       mtk_mmd_ind_write(priv, phy_addr, 0x1f, reg, val);
 430 +       priv->mmd_write(priv, phy_addr, 0x1f, reg, val);
 431  }
 432
 433  static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
 434 @@ -496,46 +616,46 @@ static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
 435         }
 436
 437         /* Disable MT7530 core clock */
 438 -       mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
 439 +       mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
 440
 441         /* Disable MT7530 PLL */
 442 -       mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
 443 +       mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
 444                               (2 << RG_GSWPLL_POSDIV_200M_S) |
 445                               (32 << RG_GSWPLL_FBKDIV_200M_S));
 446
 447         /* For MT7530 core clock = 500Mhz */
 448 -       mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2,
 449 +       mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2,
 450                               (1 << RG_GSWPLL_POSDIV_500M_S) |
 451                               (25 << RG_GSWPLL_FBKDIV_500M_S));
 452
 453         /* Enable MT7530 PLL */
 454 -       mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
 455 +       mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
 456                               (2 << RG_GSWPLL_POSDIV_200M_S) |
 457                               (32 << RG_GSWPLL_FBKDIV_200M_S) |
 458                               RG_GSWPLL_EN_PRE);
 459
 460         udelay(20);
 461
 462 -       mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
 463 +       mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
 464
 465         /* Setup the MT7530 TRGMII Tx Clock */
 466 -       mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
 467 -       mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0);
 468 -       mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
 469 -       mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
 470 -       mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
 471 +       mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
 472 +       mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0);
 473 +       mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
 474 +       mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
 475 +       mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
 476                               RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
 477
 478 -       mt7530_core_reg_write(priv, CORE_PLL_GROUP2,
 479 +       mt753x_core_reg_write(priv, CORE_PLL_GROUP2,
 480                               RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
 481                               (1 << RG_SYSPLL_POSDIV_S));
 482
 483 -       mt7530_core_reg_write(priv, CORE_PLL_GROUP7,
 484 +       mt753x_core_reg_write(priv, CORE_PLL_GROUP7,
 485                               RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
 486                               RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
 487
 488         /* Enable MT7530 core clock */
 489 -       mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
 490 +       mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
 491                               REG_GSWCK_EN | REG_TRGMIICK_EN);
 492
 493         return 0;
 494 @@ -551,46 +671,33 @@ static int mt7530_setup(struct mtk_eth_priv *priv)
 495         mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
 496                        ETHSYS_TRGMII_CLK_SEL362_5, 0);
 497
 498 -       /* Global reset switch */
 499 -       if (priv->mcm) {
 500 -               reset_assert(&priv->rst_mcm);
 501 -               udelay(1000);
 502 -               reset_deassert(&priv->rst_mcm);
 503 -               mdelay(1000);
 504 -       } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
 505 -               dm_gpio_set_value(&priv->rst_gpio, 0);
 506 -               udelay(1000);
 507 -               dm_gpio_set_value(&priv->rst_gpio, 1);
 508 -               mdelay(1000);
 509 -       }
 510 -
 511         /* Modify HWTRAP first to allow direct access to internal PHYs */
 512 -       mt7530_reg_read(priv, HWTRAP_REG, &val);
 513 +       mt753x_reg_read(priv, HWTRAP_REG, &val);
 514         val |= CHG_TRAP;
 515         val &= ~C_MDIO_BPS;
 516 -       mt7530_reg_write(priv, MHWTRAP_REG, val);
 517 +       mt753x_reg_write(priv, MHWTRAP_REG, val);
 518
 519         /* Calculate the phy base address */
 520         val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
 521 -       priv->mt7530_phy_base = (val | 0x7) + 1;
 522 +       priv->mt753x_phy_base = (val | 0x7) + 1;
 523
 524         /* Turn off PHYs */
 525 -       for (i = 0; i < MT7530_NUM_PHYS; i++) {
 526 -               phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i);
 527 +       for (i = 0; i < MT753X_NUM_PHYS; i++) {
 528 +               phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
 529                 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
 530                 phy_val |= BMCR_PDOWN;
 531                 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
 532         }
 533
 534         /* Force MAC link down before reset */
 535 -       mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE);
 536 -       mt7530_reg_write(priv, PCMR_REG(6), FORCE_MODE);
 537 +       mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
 538 +       mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
 539
 540         /* MT7530 reset */
 541 -       mt7530_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
 542 +       mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
 543         udelay(100);
 544
 545 -       val = (1 << IPG_CFG_S) |
 546 +       val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
 547               MAC_MODE | FORCE_MODE |
 548               MAC_TX_EN | MAC_RX_EN |
 549               BKOFF_EN | BACKPR_EN |
 550 @@ -598,53 +705,280 @@ static int mt7530_setup(struct mtk_eth_priv *priv)
 551               FORCE_DPX | FORCE_LINK;
 552
 553         /* MT7530 Port6: Forced 1000M/FD, FC disabled */
 554 -       mt7530_reg_write(priv, PCMR_REG(6), val);
 555 +       mt753x_reg_write(priv, PMCR_REG(6), val);
 556
 557         /* MT7530 Port5: Forced link down */
 558 -       mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE);
 559 +       mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
 560
 561         /* MT7530 Port6: Set to RGMII */
 562 -       mt7530_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
 563 +       mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
 564
 565         /* Hardware Trap: Enable Port6, Disable Port5 */
 566 -       mt7530_reg_read(priv, HWTRAP_REG, &val);
 567 +       mt753x_reg_read(priv, HWTRAP_REG, &val);
 568         val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
 569                (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
 570                (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
 571         val &= ~(C_MDIO_BPS | P6_INTF_DIS);
 572 -       mt7530_reg_write(priv, MHWTRAP_REG, val);
 573 +       mt753x_reg_write(priv, MHWTRAP_REG, val);
 574
 575         /* Setup switch core pll */
 576         mt7530_pad_clk_setup(priv, priv->phy_interface);
 577
 578         /* Lower Tx Driving for TRGMII path */
 579         for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
 580 -               mt7530_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
 581 +               mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
 582                                  (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
 583
 584         for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
 585 -               mt7530_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
 586 +               mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
 587 +
 588 +       /* Turn on PHYs */
 589 +       for (i = 0; i < MT753X_NUM_PHYS; i++) {
 590 +               phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
 591 +               phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
 592 +               phy_val &= ~BMCR_PDOWN;
 593 +               priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
 594 +       }
 595 +
 596 +       return 0;
 597 +}
 598 +
 599 +static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm)
 600 +{
 601 +       /* Step 1 : Disable MT7531 COREPLL */
 602 +       mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0);
 603 +
 604 +       /* Step 2: switch to XTAL output */
 605 +       mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW);
 606 +
 607 +       mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0);
 608 +
 609 +       /* Step 3: disable PLLGP and enable program PLLGP */
 610 +       mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP);
 611 +
 612 +       /* Step 4: program COREPLL output frequency to 500MHz */
 613 +       mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M,
 614 +                      2 << RG_COREPLL_POSDIV_S);
 615 +       udelay(25);
 616 +
 617 +       /* Currently, support XTAL 25Mhz only */
 618 +       mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M,
 619 +                      0x140000 << RG_COREPLL_SDM_PCW_S);
 620 +
 621 +       /* Set feedback divide ratio update signal to high */
 622 +       mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG,
 623 +                      RG_COREPLL_SDM_PCW_CHG);
 624 +
 625 +       /* Wait for at least 16 XTAL clocks */
 626 +       udelay(10);
 627 +
 628 +       /* Step 5: set feedback divide ratio update signal to low */
 629 +       mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0);
 630 +
 631 +       /* add enable 325M clock for SGMII */
 632 +       mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
 633 +
 634 +       /* add enable 250SSC clock for RGMII */
 635 +       mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
 636 +
 637 +       /*Step 6: Enable MT7531 PLL */
 638 +       mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN);
 639 +
 640 +       mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL);
 641 +
 642 +       udelay(25);
 643 +}
 644 +
 645 +static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv,
 646 +                                 u32 port)
 647 +{
 648 +       if (port != 5 && port != 6) {
 649 +               printf("mt7531: port %d is not a SGMII port\n", port);
 650 +               return -EINVAL;
 651 +       }
 652 +
 653 +       /* Set SGMII GEN2 speed(2.5G) */
 654 +       mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
 655 +                      SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
 656 +
 657 +       /* Disable SGMII AN */
 658 +       mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
 659 +                      SGMII_AN_ENABLE, 0);
 660 +
 661 +       /* SGMII force mode setting */
 662 +       mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE);
 663 +
 664 +       /* Release PHYA power down state */
 665 +       mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
 666 +                      SGMII_PHYA_PWD, 0);
 667 +
 668 +       return 0;
 669 +}
 670 +
 671 +static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port)
 672 +{
 673 +       u32 val;
 674 +
 675 +       if (port != 5) {
 676 +               printf("error: RGMII mode is not available for port %d\n",
 677 +                      port);
 678 +               return -EINVAL;
 679 +       }
 680 +
 681 +       mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val);
 682 +       val |= GP_CLK_EN;
 683 +       val &= ~GP_MODE_M;
 684 +       val |= GP_MODE_RGMII << GP_MODE_S;
 685 +       val |= TXCLK_NO_REVERSE;
 686 +       val |= RXCLK_NO_DELAY;
 687 +       val &= ~CLK_SKEW_IN_M;
 688 +       val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S;
 689 +       val &= ~CLK_SKEW_OUT_M;
 690 +       val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S;
 691 +       mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val);
 692 +
 693 +       return 0;
 694 +}
 695 +
 696 +static void mt7531_phy_setting(struct mtk_eth_priv *priv)
 697 +{
 698 +       int i;
 699 +       u32 val;
 700 +
 701 +       for (i = 0; i < MT753X_NUM_PHYS; i++) {
 702 +               /* Enable HW auto downshift */
 703 +               priv->mii_write(priv, i, 0x1f, 0x1);
 704 +               val = priv->mii_read(priv, i, PHY_EXT_REG_14);
 705 +               val |= PHY_EN_DOWN_SHFIT;
 706 +               priv->mii_write(priv, i, PHY_EXT_REG_14, val);
 707 +
 708 +               /* PHY link down power saving enable */
 709 +               val = priv->mii_read(priv, i, PHY_EXT_REG_17);
 710 +               val |= PHY_LINKDOWN_POWER_SAVING_EN;
 711 +               priv->mii_write(priv, i, PHY_EXT_REG_17, val);
 712 +
 713 +               val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6);
 714 +               val &= ~PHY_POWER_SAVING_M;
 715 +               val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
 716 +               priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val);
 717 +       }
 718 +}
 719 +
 720 +static int mt7531_setup(struct mtk_eth_priv *priv)
 721 +{
 722 +       u16 phy_addr, phy_val;
 723 +       u32 val;
 724 +       u32 pmcr;
 725 +       u32 port5_sgmii;
 726 +       int i;
 727 +
 728 +       priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
 729 +                               MT753X_SMI_ADDR_MASK;
 730 +
 731 +       /* Turn off PHYs */
 732 +       for (i = 0; i < MT753X_NUM_PHYS; i++) {
 733 +               phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
 734 +               phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
 735 +               phy_val |= BMCR_PDOWN;
 736 +               priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
 737 +       }
 738 +
 739 +       /* Force MAC link down before reset */
 740 +       mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
 741 +       mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
 742 +
 743 +       /* Switch soft reset */
 744 +       mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
 745 +       udelay(100);
 746 +
 747 +       /* Enable MDC input Schmitt Trigger */
 748 +       mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN,
 749 +                      SMT_IOLB_5_SMI_MDC_EN);
 750 +
 751 +       mt7531_core_pll_setup(priv, priv->mcm);
 752 +
 753 +       mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val);
 754 +       port5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
 755 +
 756 +       /* port5 support either RGMII or SGMII, port6 only support SGMII. */
 757 +       switch (priv->phy_interface) {
 758 +       case PHY_INTERFACE_MODE_RGMII:
 759 +               if (!port5_sgmii)
 760 +                       mt7531_port_rgmii_init(priv, 5);
 761 +               break;
 762 +       case PHY_INTERFACE_MODE_SGMII:
 763 +               mt7531_port_sgmii_init(priv, 6);
 764 +               if (port5_sgmii)
 765 +                       mt7531_port_sgmii_init(priv, 5);
 766 +               break;
 767 +       default:
 768 +               break;
 769 +       }
 770 +
 771 +       pmcr = MT7531_FORCE_MODE |
 772 +              (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
 773 +              MAC_MODE | MAC_TX_EN | MAC_RX_EN |
 774 +              BKOFF_EN | BACKPR_EN |
 775 +              FORCE_RX_FC | FORCE_TX_FC |
 776 +              (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
 777 +              FORCE_LINK;
 778 +
 779 +       mt753x_reg_write(priv, PMCR_REG(5), pmcr);
 780 +       mt753x_reg_write(priv, PMCR_REG(6), pmcr);
 781
 782         /* Turn on PHYs */
 783 -       for (i = 0; i < MT7530_NUM_PHYS; i++) {
 784 -               phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i);
 785 +       for (i = 0; i < MT753X_NUM_PHYS; i++) {
 786 +               phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
 787                 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
 788                 phy_val &= ~BMCR_PDOWN;
 789                 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
 790         }
 791
 792 +       mt7531_phy_setting(priv);
 793 +
 794 +       /* Enable Internal PHYs */
 795 +       val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4);
 796 +       val |= MT7531_BYPASS_MODE;
 797 +       val &= ~MT7531_POWER_ON_OFF;
 798 +       mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val);
 799 +
 800 +       return 0;
 801 +}
 802 +
 803 +int mt753x_switch_init(struct mtk_eth_priv *priv)
 804 +{
 805 +       int ret;
 806 +       int i;
 807 +
 808 +       /* Global reset switch */
 809 +       if (priv->mcm) {
 810 +               reset_assert(&priv->rst_mcm);
 811 +               udelay(1000);
 812 +               reset_deassert(&priv->rst_mcm);
 813 +               mdelay(1000);
 814 +       } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
 815 +               dm_gpio_set_value(&priv->rst_gpio, 0);
 816 +               udelay(1000);
 817 +               dm_gpio_set_value(&priv->rst_gpio, 1);
 818 +               mdelay(1000);
 819 +       }
 820 +
 821 +       ret = priv->switch_init(priv);
 822 +       if (ret)
 823 +               return ret;
 824 +
 825         /* Set port isolation */
 826 -       for (i = 0; i < 8; i++) {
 827 +       for (i = 0; i < MT753X_NUM_PORTS; i++) {
 828                 /* Set port matrix mode */
 829                 if (i != 6)
 830 -                       mt7530_reg_write(priv, PCR_REG(i),
 831 +                       mt753x_reg_write(priv, PCR_REG(i),
 832                                          (0x40 << PORT_MATRIX_S));
 833                 else
 834 -                       mt7530_reg_write(priv, PCR_REG(i),
 835 +                       mt753x_reg_write(priv, PCR_REG(i),
 836                                          (0x3f << PORT_MATRIX_S));
 837
 838                 /* Set port mode to user port */
 839 -               mt7530_reg_write(priv, PVC_REG(i),
 840 +               mt753x_reg_write(priv, PVC_REG(i),
 841                                  (0x8100 << STAG_VPID_S) |
 842                                  (VLAN_ATTR_USER << VLAN_ATTR_S));
 843         }
 844 @@ -658,7 +992,7 @@ static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
 845         u8 flowctrl;
 846         u32 mcr;
 847
 848 -       mcr = (1 << IPG_CFG_S) |
 849 +       mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
 850               (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
 851               MAC_MODE | FORCE_MODE |
 852               MAC_TX_EN | MAC_RX_EN |
 853 @@ -803,7 +1137,7 @@ static void mtk_mac_init(struct mtk_eth_priv *priv)
 854                        ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
 855
 856         if (priv->force_mode) {
 857 -               mcr = (1 << IPG_CFG_S) |
 858 +               mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
 859                       (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
 860                       MAC_MODE | FORCE_MODE |
 861                       MAC_TX_EN | MAC_RX_EN |
 862 @@ -1050,7 +1384,7 @@ static int mtk_eth_probe(struct udevice *dev)
 863                 return mtk_phy_probe(dev);
 864
 865         /* Initialize switch */
 866 -       return priv->switch_init(priv);
 867 +       return mt753x_switch_init(priv);
 868  }
 869
 870  static int mtk_eth_remove(struct udevice *dev)
 871 @@ -1159,7 +1493,11 @@ static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
 872                 if (!strcmp(str, "mt7530")) {
 873                         priv->sw = SW_MT7530;
 874                         priv->switch_init = mt7530_setup;
 875 -                       priv->mt7530_smi_addr = MT7530_DFL_SMI_ADDR;
 876 +                       priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
 877 +               } else if (!strcmp(str, "mt7531")) {
 878 +                       priv->sw = SW_MT7531;
 879 +                       priv->switch_init = mt7531_setup;
 880 +                       priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
 881                 } else {
 882                         printf("error: unsupported switch\n");
 883                         return -EINVAL;
 884 diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
 885 index 9bb037d440..f2940c9996 100644
 886 --- a/drivers/net/mtk_eth.h
 887 +++ b/drivers/net/mtk_eth.h
 888 @@ -34,7 +34,9 @@
 889
 890  /* SGMII subsystem config registers */
 891  #define SGMSYS_PCS_CONTROL_1           0x0
 892 +#define SGMII_LINK_STATUS              BIT(18)
 893  #define SGMII_AN_ENABLE                        BIT(12)
 894 +#define SGMII_AN_RESTART               BIT(9)
 895
 896  #define SGMSYS_SGMII_MODE              0x20
 897  #define SGMII_FORCE_MODE               0x31120019
 898 @@ -139,6 +141,11 @@
 899  #define FORCE_DPX                      BIT(1)
 900  #define FORCE_LINK                     BIT(0)
 901
 902 +/* Values of IPG_CFG */
 903 +#define IPG_96BIT                      0
 904 +#define IPG_96BIT_WITH_SHORT_IPG       1
 905 +#define IPG_64BIT                      2
 906 +
 907  /* MAC_RX_PKT_LEN: Max RX packet length */
 908  #define MAC_RX_PKT_LEN_1518            0
 909  #define MAC_RX_PKT_LEN_1536            1
 910 @@ -178,17 +185,73 @@
 911  #define VLAN_ATTR_TRANSLATION          2
 912  #define VLAN_ATTR_TRANSPARENT          3
 913
 914 -#define PCMR_REG(p)                    (0x3000 + (p) * 0x100)
 915 -/* XXX: all fields are defined under GMAC_PORT_MCR */
 916 -
 917 +#define PMCR_REG(p)                    (0x3000 + (p) * 0x100)
 918 +/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR
 919 + * MT7531 specific fields are defined below
 920 + */
 921 +#define FORCE_MODE_EEE1G               BIT(25)
 922 +#define FORCE_MODE_EEE100              BIT(26)
 923 +#define FORCE_MODE_TX_FC               BIT(27)
 924 +#define FORCE_MODE_RX_FC               BIT(28)
 925 +#define FORCE_MODE_DPX                 BIT(29)
 926 +#define FORCE_MODE_SPD                 BIT(30)
 927 +#define FORCE_MODE_LNK                 BIT(31)
 928 +#define MT7531_FORCE_MODE              FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\
 929 +                                       FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
 930 +                                       FORCE_MODE_DPX   | FORCE_MODE_SPD | \
 931 +                                       FORCE_MODE_LNK
 932 +
 933 +/* MT7531 SGMII Registers */
 934 +#define MT7531_SGMII_REG_BASE          0x5000
 935 +#define MT7531_SGMII_REG_PORT_BASE     0x1000
 936 +#define MT7531_SGMII_REG(p, r)         (MT7531_SGMII_REG_BASE + \
 937 +                                       (p) * MT7531_SGMII_REG_PORT_BASE + (r))
 938 +#define MT7531_PCS_CONTROL_1(p)                MT7531_SGMII_REG(((p) - 5), 0x00)
 939 +#define MT7531_SGMII_MODE(p)           MT7531_SGMII_REG(((p) - 5), 0x20)
 940 +#define MT7531_QPHY_PWR_STATE_CTRL(p)  MT7531_SGMII_REG(((p) - 5), 0xe8)
 941 +#define MT7531_PHYA_CTRL_SIGNAL3(p)    MT7531_SGMII_REG(((p) - 5), 0x128)
 942 +/* XXX: all fields of MT7531 SGMII  are defined under SGMSYS */
 943 +
 944 +/* MT753x System Control Register */
 945  #define SYS_CTRL_REG                   0x7000
 946  #define SW_PHY_RST                     BIT(2)
 947  #define SW_SYS_RST                     BIT(1)
 948  #define SW_REG_RST                     BIT(0)
 949
 950 -#define NUM_TRGMII_CTRL                        5
 951 +/* MT7531  */
 952 +#define MT7531_PHY_IAC                 0x701c
 953 +/* XXX: all fields are defined under GMAC_PIAC_REG */
 954 +
 955 +#define MT7531_CLKGEN_CTRL             0x7500
 956 +#define CLK_SKEW_OUT_S                 8
 957 +#define CLK_SKEW_OUT_M                 0x300
 958 +#define CLK_SKEW_IN_S                  6
 959 +#define CLK_SKEW_IN_M                  0xc0
 960 +#define RXCLK_NO_DELAY                 BIT(5)
 961 +#define TXCLK_NO_REVERSE               BIT(4)
 962 +#define GP_MODE_S                      1
 963 +#define GP_MODE_M                      0x06
 964 +#define GP_CLK_EN                      BIT(0)
 965 +
 966 +/* Values of GP_MODE */
 967 +#define GP_MODE_RGMII                  0
 968 +#define GP_MODE_MII                    1
 969 +#define GP_MODE_REV_MII                        2
 970 +
 971 +/* Values of CLK_SKEW_IN */
 972 +#define CLK_SKEW_IN_NO_CHANGE          0
 973 +#define CLK_SKEW_IN_DELAY_100PPS       1
 974 +#define CLK_SKEW_IN_DELAY_200PPS       2
 975 +#define CLK_SKEW_IN_REVERSE            3
 976 +
 977 +/* Values of CLK_SKEW_OUT */
 978 +#define CLK_SKEW_OUT_NO_CHANGE         0
 979 +#define CLK_SKEW_OUT_DELAY_100PPS      1
 980 +#define CLK_SKEW_OUT_DELAY_200PPS      2
 981 +#define CLK_SKEW_OUT_REVERSE           3
 982
 983  #define HWTRAP_REG                     0x7800
 984 +/* MT7530 Modified Hardware Trap Status Registers */
 985  #define MHWTRAP_REG                    0x7804
 986  #define CHG_TRAP                       BIT(16)
 987  #define LOOPDET_DIS                    BIT(14)
 988 @@ -222,6 +285,8 @@
 989  #define P6_INTF_MODE_RGMII             0
 990  #define P6_INTF_MODE_TRGMII            1
 991
 992 +#define NUM_TRGMII_CTRL                        5
 993 +
 994  #define MT7530_TRGMII_RD(n)            (0x7a10 + (n) * 8)
 995  #define RD_TAP_S                       0
 996  #define RD_TAP_M                       0x7f
 997 @@ -229,8 +294,34 @@
 998  #define MT7530_TRGMII_TD_ODT(n)                (0x7a54 + (n) * 8)
 999  /* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
1000
1001 -/* MT7530 GPHY MDIO Indirect Access Registers */
1002 +/* TOP Signals Status Register */
1003 +#define MT7531_TOP_SIG_SR              0x780c
1004 +#define PAD_MCM_SMI_EN                 BIT(0)
1005 +#define PAD_DUAL_SGMII_EN              BIT(1)
1006 +
1007 +/* MT7531 PLLGP Registers */
1008 +#define MT7531_PLLGP_EN                        0x7820
1009 +#define EN_COREPLL                     BIT(2)
1010 +#define SW_CLKSW                       BIT(1)
1011 +#define SW_PLLGP                       BIT(0)
1012 +
1013 +#define MT7531_PLLGP_CR0               0x78a8
1014 +#define RG_COREPLL_EN                  BIT(22)
1015 +#define RG_COREPLL_POSDIV_S            23
1016 +#define RG_COREPLL_POSDIV_M            0x3800000
1017 +#define RG_COREPLL_SDM_PCW_S           1
1018 +#define RG_COREPLL_SDM_PCW_M           0x3ffffe
1019 +#define RG_COREPLL_SDM_PCW_CHG         BIT(0)
1020 +
1021 +/* MT7531 RGMII and SGMII PLL clock */
1022 +#define MT7531_ANA_PLLGP_CR2           0x78b0
1023 +#define MT7531_ANA_PLLGP_CR5           0x78bc
1024 +
1025 +/* MT7531 GPIO GROUP IOLB SMT0 Control */
1026 +#define MT7531_SMT0_IOLB               0x7f04
1027 +#define SMT_IOLB_5_SMI_MDC_EN          BIT(5)
1028
1029 +/* MT7530 GPHY MDIO Indirect Access Registers */
1030  #define MII_MMD_ACC_CTL_REG            0x0d
1031  #define MMD_CMD_S                      14
1032  #define MMD_CMD_M                      0xc000
1033 @@ -246,7 +337,6 @@
1034  #define MII_MMD_ADDR_DATA_REG          0x0e
1035
1036  /* MT7530 GPHY MDIO MMD Registers */
1037 -
1038  #define CORE_PLL_GROUP2                        0x401
1039  #define RG_SYSPLL_EN_NORMAL            BIT(15)
1040  #define RG_SYSPLL_VODEN                        BIT(14)
1041 @@ -254,6 +344,8 @@
1042  #define RG_SYSPLL_POSDIV_M             0x60
1043
1044  #define CORE_PLL_GROUP4                        0x403
1045 +#define MT7531_BYPASS_MODE             BIT(4)
1046 +#define MT7531_POWER_ON_OFF            BIT(5)
1047  #define RG_SYSPLL_DDSFBK_EN            BIT(12)
1048  #define RG_SYSPLL_BIAS_EN              BIT(11)
1049  #define RG_SYSPLL_BIAS_LPF_EN          BIT(10)
1050 @@ -298,4 +390,24 @@
1051  #define REG_GSWCK_EN                   BIT(0)
1052  #define REG_TRGMIICK_EN                        BIT(1)
1053
1054 +/* Extend PHY Control Register 3 */
1055 +#define PHY_EXT_REG_14                 0x14
1056 +
1057 +/* Fields of PHY_EXT_REG_14 */
1058 +#define PHY_EN_DOWN_SHFIT              BIT(4)
1059 +
1060 +/* Extend PHY Control Register 4 */
1061 +#define PHY_EXT_REG_17                 0x17
1062 +
1063 +/* Fields of PHY_EXT_REG_17 */
1064 +#define PHY_LINKDOWN_POWER_SAVING_EN   BIT(4)
1065 +
1066 +/* PHY RXADC Control Register 7 */
1067 +#define PHY_DEV1E_REG_0C6              0x0c6
1068 +
1069 +/* Fields of PHY_DEV1E_REG_0C6 */
1070 +#define PHY_POWER_SAVING_S             8
1071 +#define PHY_POWER_SAVING_M             0x300
1072 +#define PHY_POWER_SAVING_TX            0x0
1073 +
1074  #endif /* _MTK_ETH_H_ */