1 From bad27c737d27f8afc4d597b6de1bdbc26a152ad9 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 31 Aug 2022 19:00:22 +0800
4 Subject: [PATCH 03/32] board: mediatek: add MT7986 reference boards
6 Add general board files based on MT7986 SoCs.
8 MT7986 uses one mmc controller for booting from both SD and eMMC.
9 Both MT7986A and MT7986B use the same pins for spi controller.
11 Configs for various boot types:
12 1. mt7986_rfb_defconfig - SPI-NOR and SPI-NAND for MT7986A/B
13 2. mt7986a_bpir3_emmc_defconfig - eMMC for MT7986A only
14 3. mt7986a_bpir3_sd_defconfig - SD for MT7986A only
16 Reviewed-by: Simon Glass <sjg@chromium.org>
17 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
19 arch/arm/dts/Makefile | 6 +
20 arch/arm/dts/mt7986a-emmc-rfb.dts | 16 ++
21 arch/arm/dts/mt7986a-rfb.dts | 218 +++++++++++++++++++++++++++
22 arch/arm/dts/mt7986a-sd-rfb.dts | 177 ++++++++++++++++++++++
23 arch/arm/dts/mt7986b-emmc-rfb.dts | 16 ++
24 arch/arm/dts/mt7986b-rfb.dts | 204 +++++++++++++++++++++++++
25 arch/arm/dts/mt7986b-sd-rfb.dts | 173 +++++++++++++++++++++
26 board/mediatek/mt7986/MAINTAINERS | 10 ++
27 board/mediatek/mt7986/Makefile | 3 +
28 board/mediatek/mt7986/mt7986_rfb.c | 10 ++
29 configs/mt7986_rfb_defconfig | 66 ++++++++
30 configs/mt7986a_bpir3_emmc_defconfig | 64 ++++++++
31 configs/mt7986a_bpir3_sd_defconfig | 64 ++++++++
32 include/configs/mt7986.h | 26 ++++
33 14 files changed, 1053 insertions(+)
34 create mode 100644 arch/arm/dts/mt7986a-emmc-rfb.dts
35 create mode 100644 arch/arm/dts/mt7986a-rfb.dts
36 create mode 100644 arch/arm/dts/mt7986a-sd-rfb.dts
37 create mode 100644 arch/arm/dts/mt7986b-emmc-rfb.dts
38 create mode 100644 arch/arm/dts/mt7986b-rfb.dts
39 create mode 100644 arch/arm/dts/mt7986b-sd-rfb.dts
40 create mode 100644 board/mediatek/mt7986/MAINTAINERS
41 create mode 100644 board/mediatek/mt7986/Makefile
42 create mode 100644 board/mediatek/mt7986/mt7986_rfb.c
43 create mode 100644 configs/mt7986_rfb_defconfig
44 create mode 100644 configs/mt7986a_bpir3_emmc_defconfig
45 create mode 100644 configs/mt7986a_bpir3_sd_defconfig
46 create mode 100644 include/configs/mt7986.h
48 --- a/arch/arm/dts/Makefile
49 +++ b/arch/arm/dts/Makefile
50 @@ -1205,6 +1205,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
51 mt7622-bananapi-bpi-r64.dtb \
52 mt7623n-bananapi-bpi-r2.dtb \
56 + mt7986a-sd-rfb.dtb \
57 + mt7986b-sd-rfb.dtb \
58 + mt7986a-emmc-rfb.dtb \
59 + mt7986b-emmc-rfb.dtb \
64 +++ b/arch/arm/dts/mt7986a-emmc-rfb.dts
66 +// SPDX-License-Identifier: GPL-2.0
68 + * Copyright (c) 2022 MediaTek Inc.
69 + * Author: Sam Shih <sam.shih@mediatek.com>
73 +#include "mt7986a-rfb.dts"
76 + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
77 + "mediatek,mt7986-emmc-rfb";
79 + bl2_compatible = "emmc";
83 +++ b/arch/arm/dts/mt7986a-rfb.dts
85 +// SPDX-License-Identifier: GPL-2.0
87 + * Copyright (c) 2022 MediaTek Inc.
88 + * Author: Sam Shih <sam.shih@mediatek.com>
92 +#include "mt7986.dtsi"
93 +#include <dt-bindings/gpio/gpio.h>
96 + #address-cells = <1>;
98 + model = "mt7986-rfb";
99 + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
101 + stdout-path = &uart0;
102 + tick-timer = &timer0;
105 + reg_1p8v: regulator-1p8v {
106 + compatible = "regulator-fixed";
107 + regulator-name = "fixed-1.8V";
108 + regulator-min-microvolt = <1800000>;
109 + regulator-max-microvolt = <1800000>;
111 + regulator-always-on;
114 + reg_3p3v: regulator-3p3v {
115 + compatible = "regulator-fixed";
116 + regulator-name = "fixed-3.3V";
117 + regulator-min-microvolt = <3300000>;
118 + regulator-max-microvolt = <3300000>;
120 + regulator-always-on;
129 + pinctrl-names = "default";
130 + pinctrl-0 = <&uart1_pins>;
131 + status = "disabled";
136 + mediatek,gmac-id = <0>;
137 + phy-mode = "sgmii";
138 + mediatek,switch = "mt7531";
139 + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
148 + spi_flash_pins: spi0-pins-func-1 {
150 + function = "flash";
151 + groups = "spi0", "spi0_wp_hold";
155 + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
156 + drive-strength = <MTK_DRIVE_8mA>;
157 + bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
161 + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
162 + drive-strength = <MTK_DRIVE_8mA>;
163 + bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
167 + snfi_pins: snfi-pins-func-1 {
169 + function = "flash";
175 + drive-strength = <MTK_DRIVE_8mA>;
176 + bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
180 + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
181 + drive-strength = <MTK_DRIVE_6mA>;
182 + bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
186 + pins = "SPI0_MOSI", "SPI0_MISO";
187 + drive-strength = <MTK_DRIVE_6mA>;
188 + bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
192 + spic_pins: spi1-pins-func-1 {
199 + uart1_pins: spi1-pins-func-3 {
202 + groups = "uart1_2";
206 + pwm_pins: pwm0-pins-func-1 {
213 + mmc0_pins_default: mmc0default {
215 + function = "flash";
216 + groups = "emmc_51";
220 + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
221 + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
222 + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
224 + drive-strength = <MTK_DRIVE_4mA>;
225 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
230 + drive-strength = <MTK_DRIVE_6mA>;
231 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
236 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
240 + pins = "EMMC_RSTB";
241 + drive-strength = <MTK_DRIVE_4mA>;
242 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
248 + pinctrl-names = "default";
249 + pinctrl-0 = <&snfi_pins>;
255 + #address-cells = <1>;
257 + pinctrl-names = "default";
258 + pinctrl-0 = <&spi_flash_pins>;
269 + compatible = "jedec,spi-nor";
271 + spi-max-frequency = <52000000>;
275 + compatible = "spi-nand";
277 + spi-max-frequency = <52000000>;
282 + pinctrl-names = "default";
283 + pinctrl-0 = <&pwm_pins>;
288 + status = "disabled";
292 + pinctrl-names = "default";
293 + pinctrl-0 = <&mmc0_pins_default>;
295 + max-frequency = <52000000>;
298 + vmmc-supply = <®_3p3v>;
299 + vqmmc-supply = <®_1p8v>;
304 +++ b/arch/arm/dts/mt7986a-sd-rfb.dts
306 +// SPDX-License-Identifier: GPL-2.0
308 + * Copyright (c) 2022 MediaTek Inc.
309 + * Author: Sam Shih <sam.shih@mediatek.com>
313 +#include "mt7986.dtsi"
314 +#include <dt-bindings/gpio/gpio.h>
317 + #address-cells = <1>;
319 + model = "mt7986-rfb";
320 + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
321 + "mediatek,mt7986-sd-rfb";
323 + stdout-path = &uart0;
324 + tick-timer = &timer0;
327 + reg_3p3v: regulator-3p3v {
328 + compatible = "regulator-fixed";
329 + regulator-name = "fixed-3.3V";
330 + regulator-min-microvolt = <3300000>;
331 + regulator-max-microvolt = <3300000>;
333 + regulator-always-on;
342 + pinctrl-names = "default";
343 + pinctrl-0 = <&uart1_pins>;
344 + status = "disabled";
349 + mediatek,gmac-id = <0>;
350 + phy-mode = "sgmii";
351 + mediatek,switch = "mt7531";
352 + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
361 + spi_flash_pins: spi0-pins-func-1 {
363 + function = "flash";
364 + groups = "spi0", "spi0_wp_hold";
368 + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
369 + drive-strength = <MTK_DRIVE_8mA>;
370 + bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
374 + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
375 + drive-strength = <MTK_DRIVE_8mA>;
376 + bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
380 + spic_pins: spi1-pins-func-1 {
387 + uart1_pins: spi1-pins-func-3 {
390 + groups = "uart1_2";
394 + pwm_pins: pwm0-pins-func-1 {
401 + mmc0_pins_default: mmc0default {
403 + function = "flash";
404 + groups = "emmc_51";
408 + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
409 + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
410 + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
412 + drive-strength = <MTK_DRIVE_4mA>;
413 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
418 + drive-strength = <MTK_DRIVE_6mA>;
419 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
424 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
428 + pins = "EMMC_RSTB";
429 + drive-strength = <MTK_DRIVE_4mA>;
430 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
436 + #address-cells = <1>;
438 + pinctrl-names = "default";
439 + pinctrl-0 = <&spi_flash_pins>;
450 + compatible = "jedec,spi-nor";
452 + spi-max-frequency = <52000000>;
456 + compatible = "spi-nand";
458 + spi-max-frequency = <52000000>;
463 + pinctrl-names = "default";
464 + pinctrl-0 = <&pwm_pins>;
469 + status = "disabled";
473 + pinctrl-names = "default";
474 + pinctrl-0 = <&mmc0_pins_default>;
476 + max-frequency = <52000000>;
479 + vmmc-supply = <®_3p3v>;
480 + vqmmc-supply = <®_3p3v>;
484 +++ b/arch/arm/dts/mt7986b-emmc-rfb.dts
486 +// SPDX-License-Identifier: GPL-2.0
488 + * Copyright (c) 2022 MediaTek Inc.
489 + * Author: Sam Shih <sam.shih@mediatek.com>
493 +#include "mt7986a-rfb.dts"
496 + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
497 + "mediatek,mt7986-emmc-rfb";
499 + bl2_compatible = "emmc";
503 +++ b/arch/arm/dts/mt7986b-rfb.dts
505 +// SPDX-License-Identifier: GPL-2.0
507 + * Copyright (c) 2022 MediaTek Inc.
508 + * Author: Sam Shih <sam.shih@mediatek.com>
512 +#include "mt7986.dtsi"
513 +#include <dt-bindings/gpio/gpio.h>
516 + #address-cells = <1>;
518 + model = "mt7986-rfb";
519 + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
521 + stdout-path = &uart0;
522 + tick-timer = &timer0;
525 + reg_3p3v: regulator-3p3v {
526 + compatible = "regulator-fixed";
527 + regulator-name = "fixed-3.3V";
528 + regulator-min-microvolt = <3300000>;
529 + regulator-max-microvolt = <3300000>;
531 + regulator-always-on;
540 + pinctrl-names = "default";
541 + pinctrl-0 = <&uart1_pins>;
542 + status = "disabled";
547 + mediatek,gmac-id = <0>;
548 + phy-mode = "sgmii";
549 + mediatek,switch = "mt7531";
550 + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
559 + spi_flash_pins: spi0-pins-func-1 {
561 + function = "flash";
562 + groups = "spi0", "spi0_wp_hold";
566 + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
567 + drive-strength = <MTK_DRIVE_8mA>;
568 + bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
572 + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
573 + drive-strength = <MTK_DRIVE_8mA>;
574 + bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
578 + snfi_pins: snfi-pins-func-1 {
580 + function = "flash";
586 + drive-strength = <MTK_DRIVE_8mA>;
587 + bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
591 + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
592 + drive-strength = <MTK_DRIVE_6mA>;
593 + bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
597 + pins = "SPI0_MOSI", "SPI0_MISO";
598 + drive-strength = <MTK_DRIVE_6mA>;
599 + bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
603 + spic_pins: spi1-pins-func-1 {
610 + uart1_pins: spi1-pins-func-3 {
613 + groups = "uart1_2";
617 + pwm_pins: pwm0-pins-func-1 {
624 + mmc0_pins_default: mmc0default {
626 + function = "flash";
627 + groups = "emmc_45";
628 + input-schmitt-enable;
632 + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
633 + "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
634 + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
636 + drive-strength = <MTK_DRIVE_4mA>;
637 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
642 + drive-strength = <MTK_DRIVE_6mA>;
643 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
648 + drive-strength = <MTK_DRIVE_4mA>;
649 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
655 + pinctrl-names = "default";
656 + pinctrl-0 = <&snfi_pins>;
662 + #address-cells = <1>;
664 + pinctrl-names = "default";
665 + pinctrl-0 = <&spi_flash_pins>;
676 + compatible = "jedec,spi-nor";
678 + spi-max-frequency = <52000000>;
682 + compatible = "spi-nand";
684 + spi-max-frequency = <52000000>;
689 + pinctrl-names = "default";
690 + pinctrl-0 = <&pwm_pins>;
695 + status = "disabled";
699 + pinctrl-names = "default";
700 + pinctrl-0 = <&mmc0_pins_default>;
702 + max-frequency = <52000000>;
705 + vmmc-supply = <®_3p3v>;
710 +++ b/arch/arm/dts/mt7986b-sd-rfb.dts
712 +// SPDX-License-Identifier: GPL-2.0
714 + * Copyright (c) 2022 MediaTek Inc.
715 + * Author: Sam Shih <sam.shih@mediatek.com>
719 +#include "mt7986.dtsi"
720 +#include <dt-bindings/gpio/gpio.h>
723 + #address-cells = <1>;
725 + model = "mt7986-rfb";
726 + compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
727 + "mediatek,mt7986-sd-rfb";
729 + stdout-path = &uart0;
730 + tick-timer = &timer0;
733 + reg_3p3v: regulator-3p3v {
734 + compatible = "regulator-fixed";
735 + regulator-name = "fixed-3.3V";
736 + regulator-min-microvolt = <3300000>;
737 + regulator-max-microvolt = <3300000>;
739 + regulator-always-on;
748 + pinctrl-names = "default";
749 + pinctrl-0 = <&uart1_pins>;
750 + status = "disabled";
755 + mediatek,gmac-id = <0>;
756 + phy-mode = "sgmii";
757 + mediatek,switch = "mt7531";
758 + reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
767 + spi_flash_pins: spi0-pins-func-1 {
769 + function = "flash";
770 + groups = "spi0", "spi0_wp_hold";
774 + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
775 + drive-strength = <MTK_DRIVE_8mA>;
776 + bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
780 + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
781 + drive-strength = <MTK_DRIVE_8mA>;
782 + bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
786 + spic_pins: spi1-pins-func-1 {
793 + uart1_pins: spi1-pins-func-3 {
796 + groups = "uart1_2";
800 + pwm_pins: pwm0-pins-func-1 {
807 + mmc0_pins_default: mmc0default {
809 + function = "flash";
810 + groups = "emmc_45";
811 + input-schmitt-enable;
815 + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
816 + "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
817 + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
819 + drive-strength = <MTK_DRIVE_4mA>;
820 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
825 + drive-strength = <MTK_DRIVE_6mA>;
826 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
831 + drive-strength = <MTK_DRIVE_4mA>;
832 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
838 + #address-cells = <1>;
840 + pinctrl-names = "default";
841 + pinctrl-0 = <&spi_flash_pins>;
852 + compatible = "jedec,spi-nor";
854 + spi-max-frequency = <52000000>;
858 + compatible = "spi-nand";
860 + spi-max-frequency = <52000000>;
865 + pinctrl-names = "default";
866 + pinctrl-0 = <&pwm_pins>;
871 + status = "disabled";
875 + pinctrl-names = "default";
876 + pinctrl-0 = <&mmc0_pins_default>;
878 + max-frequency = <52000000>;
881 + vmmc-supply = <®_3p3v>;
882 + vqmmc-supply = <®_3p3v>;
886 +++ b/board/mediatek/mt7986/MAINTAINERS
889 +M: Sam Shih <sam.shih@mediatek.com>
891 +F: board/mediatek/mt7986
892 +F: include/configs/mt7986.h
893 +F: configs/mt7986_rfb_defconfig
894 +F: configs/mt7986a_emmc_rfb_defconfig
895 +F: configs/mt7986a_sd_rfb_defconfig
896 +F: configs/mt7986b_emmc_rfb_defconfig
897 +F: configs/mt7986b_sd_rfb_defconfig
899 +++ b/board/mediatek/mt7986/Makefile
901 +# SPDX-License-Identifier: GPL-2.0
903 +obj-y += mt7986_rfb.o
905 +++ b/board/mediatek/mt7986/mt7986_rfb.c
907 +// SPDX-License-Identifier: GPL-2.0
909 + * Copyright (C) 2022 MediaTek Inc.
910 + * Author: Sam Shih <sam.shih@mediatek.com>
913 +int board_init(void)
918 +++ b/configs/mt7986_rfb_defconfig
921 +CONFIG_POSITION_INDEPENDENT=y
922 +CONFIG_ARCH_MEDIATEK=y
923 +CONFIG_SYS_TEXT_BASE=0x41e00000
924 +CONFIG_SYS_MALLOC_F_LEN=0x4000
925 +CONFIG_NR_DRAM_BANKS=1
926 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-rfb"
927 +CONFIG_TARGET_MT7986=y
928 +CONFIG_DEBUG_UART_BASE=0x11002000
929 +CONFIG_DEBUG_UART_CLOCK=40000000
930 +CONFIG_SYS_LOAD_ADDR=0x46000000
932 +# CONFIG_AUTOBOOT is not set
933 +CONFIG_DEFAULT_FDT_FILE="mt7986a-rfb"
936 +CONFIG_SYS_PROMPT="MT7986> "
937 +CONFIG_SYS_CBSIZE=512
938 +CONFIG_SYS_PBSIZE=1049
939 +# CONFIG_BOOTM_NETBSD is not set
940 +# CONFIG_BOOTM_PLAN9 is not set
941 +# CONFIG_BOOTM_RTEMS is not set
942 +# CONFIG_BOOTM_VXWORKS is not set
943 +# CONFIG_CMD_ELF is not set
944 +# CONFIG_CMD_UNLZ4 is not set
945 +# CONFIG_CMD_UNZIP is not set
948 +CONFIG_CMD_SF_TEST=y
951 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
952 +CONFIG_NET_RANDOM_ETHADDR=y
956 +# CONFIG_MMC is not set
959 +CONFIG_MTD_SPI_NAND=y
960 +CONFIG_DM_SPI_FLASH=y
961 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
962 +CONFIG_SPI_FLASH_EON=y
963 +CONFIG_SPI_FLASH_GIGADEVICE=y
964 +CONFIG_SPI_FLASH_ISSI=y
965 +CONFIG_SPI_FLASH_MACRONIX=y
966 +CONFIG_SPI_FLASH_SPANSION=y
967 +CONFIG_SPI_FLASH_STMICRO=y
968 +CONFIG_SPI_FLASH_WINBOND=y
969 +CONFIG_SPI_FLASH_XMC=y
970 +CONFIG_SPI_FLASH_XTX=y
971 +CONFIG_SPI_FLASH_MTD=y
974 +CONFIG_MEDIATEK_ETH=y
977 +CONFIG_PINCTRL_MT7986=y
978 +CONFIG_POWER_DOMAIN=y
979 +CONFIG_MTK_POWER_DOMAIN=y
987 +++ b/configs/mt7986a_bpir3_emmc_defconfig
990 +CONFIG_POSITION_INDEPENDENT=y
991 +CONFIG_ARCH_MEDIATEK=y
992 +CONFIG_SYS_TEXT_BASE=0x41e00000
993 +CONFIG_SYS_MALLOC_F_LEN=0x4000
994 +CONFIG_NR_DRAM_BANKS=1
995 +CONFIG_ENV_SIZE=0x80000
996 +CONFIG_ENV_OFFSET=0x300000
997 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-emmc-rfb"
998 +CONFIG_TARGET_MT7986=y
999 +CONFIG_DEBUG_UART_BASE=0x11002000
1000 +CONFIG_DEBUG_UART_CLOCK=40000000
1001 +CONFIG_SYS_LOAD_ADDR=0x46000000
1002 +CONFIG_DEBUG_UART=y
1003 +# CONFIG_AUTOBOOT is not set
1004 +CONFIG_DEFAULT_FDT_FILE="mt7986a-emmc-rfb"
1007 +CONFIG_SYS_PROMPT="MT7986> "
1008 +CONFIG_SYS_CBSIZE=512
1009 +CONFIG_SYS_PBSIZE=1049
1010 +# CONFIG_BOOTM_NETBSD is not set
1011 +# CONFIG_BOOTM_PLAN9 is not set
1012 +# CONFIG_BOOTM_RTEMS is not set
1013 +# CONFIG_BOOTM_VXWORKS is not set
1014 +# CONFIG_CMD_ELF is not set
1015 +# CONFIG_CMD_UNLZ4 is not set
1016 +# CONFIG_CMD_UNZIP is not set
1019 +CONFIG_CMD_GPT_RENAME=y
1027 +CONFIG_CMD_FS_GENERIC=y
1028 +CONFIG_PARTITION_TYPE_GUID=y
1029 +CONFIG_ENV_OVERWRITE=y
1030 +CONFIG_ENV_IS_IN_MMC=y
1031 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
1032 +CONFIG_NET_RANDOM_ETHADDR=y
1036 +CONFIG_MMC_HS200_SUPPORT=y
1040 +CONFIG_MEDIATEK_ETH=y
1043 +CONFIG_PINCTRL_MT7986=y
1044 +CONFIG_POWER_DOMAIN=y
1045 +CONFIG_MTK_POWER_DOMAIN=y
1046 +CONFIG_DM_REGULATOR=y
1047 +CONFIG_DM_REGULATOR_FIXED=y
1049 +CONFIG_MTK_SERIAL=y
1052 +# CONFIG_EFI_LOADER is not set
1054 +++ b/configs/mt7986a_bpir3_sd_defconfig
1057 +CONFIG_POSITION_INDEPENDENT=y
1058 +CONFIG_ARCH_MEDIATEK=y
1059 +CONFIG_SYS_TEXT_BASE=0x41e00000
1060 +CONFIG_SYS_MALLOC_F_LEN=0x4000
1061 +CONFIG_NR_DRAM_BANKS=1
1062 +CONFIG_ENV_SIZE=0x80000
1063 +CONFIG_ENV_OFFSET=0x300000
1064 +CONFIG_DEFAULT_DEVICE_TREE="mt7986a-sd-rfb"
1065 +CONFIG_TARGET_MT7986=y
1066 +CONFIG_DEBUG_UART_BASE=0x11002000
1067 +CONFIG_DEBUG_UART_CLOCK=40000000
1068 +CONFIG_SYS_LOAD_ADDR=0x46000000
1069 +CONFIG_DEBUG_UART=y
1070 +# CONFIG_AUTOBOOT is not set
1071 +CONFIG_DEFAULT_FDT_FILE="mt7986a-sd-rfb"
1074 +CONFIG_SYS_PROMPT="MT7986> "
1075 +CONFIG_SYS_CBSIZE=512
1076 +CONFIG_SYS_PBSIZE=1049
1077 +# CONFIG_BOOTM_NETBSD is not set
1078 +# CONFIG_BOOTM_PLAN9 is not set
1079 +# CONFIG_BOOTM_RTEMS is not set
1080 +# CONFIG_BOOTM_VXWORKS is not set
1081 +# CONFIG_CMD_ELF is not set
1082 +# CONFIG_CMD_UNLZ4 is not set
1083 +# CONFIG_CMD_UNZIP is not set
1086 +CONFIG_CMD_GPT_RENAME=y
1094 +CONFIG_CMD_FS_GENERIC=y
1095 +CONFIG_PARTITION_TYPE_GUID=y
1096 +CONFIG_ENV_OVERWRITE=y
1097 +CONFIG_ENV_IS_IN_MMC=y
1098 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
1099 +CONFIG_NET_RANDOM_ETHADDR=y
1103 +CONFIG_MMC_HS200_SUPPORT=y
1107 +CONFIG_MEDIATEK_ETH=y
1110 +CONFIG_PINCTRL_MT7986=y
1111 +CONFIG_POWER_DOMAIN=y
1112 +CONFIG_MTK_POWER_DOMAIN=y
1113 +CONFIG_DM_REGULATOR=y
1114 +CONFIG_DM_REGULATOR_FIXED=y
1116 +CONFIG_MTK_SERIAL=y
1119 +# CONFIG_EFI_LOADER is not set
1121 +++ b/include/configs/mt7986.h
1123 +/* SPDX-License-Identifier: GPL-2.0 */
1125 + * Configuration for MediaTek MT7986 SoC
1127 + * Copyright (C) 2022 MediaTek Inc.
1128 + * Author: Sam Shih <sam.shih@mediatek.com>
1134 +#include <linux/sizes.h>
1136 +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
1137 +#define CONFIG_SYS_MMC_ENV_DEV 0
1139 +/* Uboot definition */
1140 +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
1143 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
1146 +#define CONFIG_SYS_SDRAM_BASE 0x40000000