package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch

   1 From 4569ef02981f20b236a8cdc3a57b4d27fbdbc22e Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 27 Jul 2022 11:01:34 +0800
   4 Subject: [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC
   5
   6 This patch adds PWM support for MediaTek MT7981 SoC.
   7 MT7981 uses a different register offset so we have to add a version field
   8 to indicate the IP core version.
   9
  10 Reviewed-by: Simon Glass <sjg@chromium.org>
  11 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  12 ---
  13  drivers/pwm/pwm-mtk.c | 34 ++++++++++++++++++++++++++++++++--
  14  1 file changed, 32 insertions(+), 2 deletions(-)
  15
  16 --- a/drivers/pwm/pwm-mtk.c
  17 +++ b/drivers/pwm/pwm-mtk.c
  18 @@ -29,13 +29,23 @@
  19
  20  #define NSEC_PER_SEC 1000000000L
  21
  22 -static const unsigned int mtk_pwm_reg_offset[] = {
  23 +enum mtk_pwm_reg_ver {
  24 +       PWM_REG_V1,
  25 +       PWM_REG_V2,
  26 +};
  27 +
  28 +static const unsigned int mtk_pwm_reg_offset_v1[] = {
  29         0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
  30  };
  31
  32 +static const unsigned int mtk_pwm_reg_offset_v2[] = {
  33 +       0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
  34 +};
  35 +
  36  struct mtk_pwm_soc {
  37         unsigned int num_pwms;
  38         bool pwm45_fixup;
  39 +       enum mtk_pwm_reg_ver reg_ver;
  40  };
  41
  42  struct mtk_pwm_priv {
  43 @@ -49,7 +59,16 @@ struct mtk_pwm_priv {
  44  static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
  45  {
  46         struct mtk_pwm_priv *priv = dev_get_priv(dev);
  47 -       u32 offset = mtk_pwm_reg_offset[channel];
  48 +       u32 offset;
  49 +
  50 +       switch (priv->soc->reg_ver) {
  51 +       case PWM_REG_V2:
  52 +               offset = mtk_pwm_reg_offset_v2[channel];
  53 +               break;
  54 +
  55 +       default:
  56 +               offset = mtk_pwm_reg_offset_v1[channel];
  57 +       }
  58
  59         writel(val, priv->base + offset + reg);
  60  }
  61 @@ -159,27 +178,38 @@ static const struct pwm_ops mtk_pwm_ops
  62  static const struct mtk_pwm_soc mt7622_data = {
  63         .num_pwms = 6,
  64         .pwm45_fixup = false,
  65 +       .reg_ver = PWM_REG_V1,
  66  };
  67
  68  static const struct mtk_pwm_soc mt7623_data = {
  69         .num_pwms = 5,
  70         .pwm45_fixup = true,
  71 +       .reg_ver = PWM_REG_V1,
  72  };
  73
  74  static const struct mtk_pwm_soc mt7629_data = {
  75         .num_pwms = 1,
  76         .pwm45_fixup = false,
  77 +       .reg_ver = PWM_REG_V1,
  78 +};
  79 +
  80 +static const struct mtk_pwm_soc mt7981_data = {
  81 +       .num_pwms = 2,
  82 +       .pwm45_fixup = false,
  83 +       .reg_ver = PWM_REG_V2,
  84  };
  85
  86  static const struct mtk_pwm_soc mt7986_data = {
  87         .num_pwms = 2,
  88         .pwm45_fixup = false,
  89 +       .reg_ver = PWM_REG_V1,
  90  };
  91
  92  static const struct udevice_id mtk_pwm_ids[] = {
  93         { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
  94         { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
  95         { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
  96 +       { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
  97         { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
  98         { }
  99  };