package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch

   1 From 49e7b1e01cf80437c7e22f8b6579d4a81e7f8a3a Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Thu, 28 Jul 2022 09:57:58 +0800
   4 Subject: [PATCH 20/31] pinctrl: mediatek: add pinctrl driver for MT7981 SoC
   5
   6 This patch adds pinctrl and gpio support for MT7981 SoC
   7
   8 Reviewed-by: Simon Glass <sjg@chromium.org>
   9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  10 ---
  11  drivers/pinctrl/mediatek/Kconfig          |    4 +
  12  drivers/pinctrl/mediatek/Makefile         |    1 +
  13  drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1049 +++++++++++++++++++++
  14  3 files changed, 1054 insertions(+)
  15  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c
  16
  17 --- a/drivers/pinctrl/mediatek/Kconfig
  18 +++ b/drivers/pinctrl/mediatek/Kconfig
  19 @@ -16,6 +16,10 @@ config PINCTRL_MT7629
  20         bool "MT7629 SoC pinctrl driver"
  21         select PINCTRL_MTK
  22
  23 +config PINCTRL_MT7981
  24 +       bool "MT7981 SoC pinctrl driver"
  25 +       select PINCTRL_MTK
  26 +
  27  config PINCTRL_MT8512
  28         bool "MT8512 SoC pinctrl driver"
  29         select PINCTRL_MTK
  30 --- a/drivers/pinctrl/mediatek/Makefile
  31 +++ b/drivers/pinctrl/mediatek/Makefile
  32 @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk
  33  obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
  34  obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
  35  obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
  36 +obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
  37  obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
  38  obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
  39  obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
  40 --- /dev/null
  41 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
  42 @@ -0,0 +1,1049 @@
  43 +// SPDX-License-Identifier: GPL-2.0
  44 +/*
  45 + * The MT7981 driver based on Linux generic pinctrl binding.
  46 + *
  47 + * Copyright (C) 2022 MediaTek Inc.
  48 + * Author: Sam Shih <sam.shih@mediatek.com>
  49 + */
  50 +
  51 +#include <dm.h>
  52 +#include "pinctrl-mtk-common.h"
  53 +
  54 +#define MT7981_TYPE0_PIN(_number, _name)       \
  55 +       MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
  56 +
  57 +#define MT7981_TYPE1_PIN(_number, _name)       \
  58 +       MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
  59 +
  60 +#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)     \
  61 +       PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs,       \
  62 +                           _s_bit, _x_bits, 32, 0)
  63 +
  64 +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
  65 +                      _x_bits)                                                 \
  66 +       PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
  67 +       _x_bits, 32, 0)
  68 +
  69 +/**
  70 + * enum - Locking variants of the iocfg bases
  71 + *
  72 + * MT7981 have multiple bases to program pin configuration listed as the below:
  73 + * iocfg_rt:0x11c00000, iocfg_rm:0x11c10000, iocfg_rb:0x11d20000,
  74 + * iocfg_lb:0x11e00000, iocfg_bl:0x11e20000, iocfg_tm:0x11f00000,
  75 + * iocfg_tl:0x11f10000,
  76 + * _i_based could be used to indicate what base the pin should be mapped into.
  77 + *
  78 + * Each iocfg register base control different group of pads on the SoC
  79 + *
  80 + *
  81 + *  chip carrier
  82 + *
  83 + *      A  B  C  D  E  F  G  H
  84 + *    +------------------------+
  85 + *  8 | o  o  o  o  o  o  o  o |
  86 + *  7 | o  o  o  o  o  o  o  o |
  87 + *  6 | o  o  o  o  o  o  o  o |
  88 + *  5 | o  o  o  o  o  o  o  o |
  89 + *  4 | o  o  o  o  o  o  o  o |
  90 + *  3 | o  o  o  o  o  o  o  o |
  91 + *  2 | o  o  o  o  o  o  o  o |
  92 + *  1 | o  o  o  o  o  o  o  o |
  93 + *    +------------------------+
  94 + *
  95 + *  inside Chip carrier
  96 + *
  97 + *      A  B  C  D  E  F  G  H
  98 + *    +------------------------+
  99 + *  8 |                        |
 100 + *  7 |       TL TM            |
 101 + *  6 |      +---------+       |
 102 + *  5 |      |         | RT    |
 103 + *  4 |      |         | RM    |
 104 + *  3 |   LB |         | RB    |
 105 + *  2 |      +---------+       |
 106 + *  1 |        BL              |
 107 + *    +------------------------+
 108 + *
 109 + */
 110 +
 111 +enum {
 112 +       GPIO_BASE,
 113 +       IOCFG_RT_BASE,
 114 +       IOCFG_RM_BASE,
 115 +       IOCFG_RB_BASE,
 116 +       IOCFG_LB_BASE,
 117 +       IOCFG_BL_BASE,
 118 +       IOCFG_TM_BASE,
 119 +       IOCFG_TL_BASE,
 120 +};
 121 +
 122 +static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
 123 +       PIN_FIELD_GPIO(0, 56, 0x300, 0x10, 0, 4),
 124 +};
 125 +
 126 +static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
 127 +       PIN_FIELD_GPIO(0, 56, 0x0, 0x10, 0, 1),
 128 +};
 129 +
 130 +static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
 131 +       PIN_FIELD_GPIO(0, 56, 0x200, 0x10, 0, 1),
 132 +};
 133 +
 134 +static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
 135 +       PIN_FIELD_GPIO(0, 56, 0x100, 0x10, 0, 1),
 136 +};
 137 +
 138 +static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
 139 +       PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
 140 +       PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
 141 +       PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
 142 +       PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
 143 +       PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
 144 +       PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
 145 +       PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
 146 +       PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
 147 +       PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
 148 +       PIN_FIELD_BASE(9, 9, 4, 0x20, 0x10, 9, 1),
 149 +
 150 +       PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
 151 +       PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
 152 +       PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
 153 +       PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
 154 +
 155 +       PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
 156 +
 157 +       PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
 158 +       PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
 159 +       PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
 160 +       PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
 161 +       PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
 162 +       PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
 163 +       PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
 164 +       PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
 165 +       PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
 166 +       PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
 167 +       PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
 168 +
 169 +       PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
 170 +       PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
 171 +       PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
 172 +       PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
 173 +       PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
 174 +       PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
 175 +
 176 +       PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
 177 +       PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
 178 +
 179 +       PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
 180 +       PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
 181 +
 182 +       PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
 183 +       PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
 184 +       PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
 185 +       PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
 186 +
 187 +       PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
 188 +       PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
 189 +       PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
 190 +       PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
 191 +       PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
 192 +       PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
 193 +       PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
 194 +       PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
 195 +       PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
 196 +       PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
 197 +
 198 +       PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
 199 +       PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
 200 +       PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
 201 +       PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
 202 +       PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
 203 +       PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
 204 +       PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
 205 +};
 206 +
 207 +static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
 208 +       PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
 209 +       PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
 210 +       PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
 211 +       PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
 212 +       PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
 213 +       PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
 214 +       PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
 215 +       PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
 216 +       PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
 217 +       PIN_FIELD_BASE(9, 9, 4, 0x80, 0x10, 9, 1),
 218 +
 219 +       PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
 220 +       PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
 221 +       PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
 222 +       PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
 223 +
 224 +       PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
 225 +
 226 +       PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
 227 +       PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
 228 +       PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
 229 +       PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
 230 +       PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
 231 +       PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
 232 +       PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
 233 +       PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
 234 +       PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
 235 +       PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
 236 +       PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
 237 +
 238 +       PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
 239 +       PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
 240 +       PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
 241 +       PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
 242 +       PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
 243 +       PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
 244 +
 245 +       PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
 246 +       PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
 247 +
 248 +       PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
 249 +       PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
 250 +
 251 +       PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
 252 +       PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
 253 +       PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
 254 +       PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
 255 +
 256 +       PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
 257 +       PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
 258 +       PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
 259 +       PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
 260 +       PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
 261 +       PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
 262 +       PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
 263 +       PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
 264 +       PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
 265 +       PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
 266 +
 267 +       PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
 268 +       PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
 269 +       PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
 270 +       PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
 271 +       PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
 272 +       PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
 273 +       PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
 274 +};
 275 +
 276 +static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
 277 +       PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
 278 +       PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
 279 +       PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
 280 +       PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
 281 +       PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
 282 +       PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
 283 +       PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
 284 +       PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
 285 +       PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
 286 +       PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
 287 +
 288 +       PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
 289 +       PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
 290 +       PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
 291 +       PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
 292 +       PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
 293 +       PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
 294 +       PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
 295 +};
 296 +
 297 +static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
 298 +       PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
 299 +       PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
 300 +       PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
 301 +       PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
 302 +       PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
 303 +       PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
 304 +       PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
 305 +       PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
 306 +       PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
 307 +       PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
 308 +
 309 +       PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
 310 +       PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
 311 +       PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
 312 +       PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
 313 +       PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
 314 +       PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
 315 +       PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
 316 +};
 317 +
 318 +static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
 319 +       PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
 320 +       PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
 321 +
 322 +       PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
 323 +
 324 +       PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
 325 +       PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
 326 +       PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
 327 +       PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
 328 +       PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
 329 +       PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
 330 +       PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 27, 3),
 331 +
 332 +       PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
 333 +       PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
 334 +       PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
 335 +       PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
 336 +
 337 +       PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
 338 +
 339 +       PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
 340 +       PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
 341 +       PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
 342 +       PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
 343 +       PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
 344 +       PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
 345 +       PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
 346 +       PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
 347 +       PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
 348 +       PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
 349 +       PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
 350 +
 351 +       PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
 352 +       PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
 353 +       PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
 354 +       PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
 355 +       PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
 356 +       PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
 357 +
 358 +       PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
 359 +       PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
 360 +
 361 +       PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
 362 +       PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
 363 +
 364 +       PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
 365 +       PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
 366 +       PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
 367 +       PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
 368 +
 369 +       PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
 370 +       PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
 371 +       PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
 372 +       PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
 373 +       PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
 374 +       PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
 375 +       PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
 376 +       PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
 377 +       PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
 378 +       PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
 379 +
 380 +       PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
 381 +       PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
 382 +       PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
 383 +       PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
 384 +       PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
 385 +       PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
 386 +       PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
 387 +};
 388 +
 389 +static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
 390 +       PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
 391 +       PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
 392 +       PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
 393 +       PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
 394 +       PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
 395 +       PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
 396 +       PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
 397 +       PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
 398 +       PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
 399 +       PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 9, 1),
 400 +
 401 +       PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
 402 +       PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
 403 +       PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
 404 +       PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
 405 +
 406 +       PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
 407 +
 408 +       PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
 409 +       PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
 410 +       PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
 411 +       PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
 412 +       PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
 413 +       PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
 414 +       PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
 415 +       PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
 416 +       PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
 417 +       PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
 418 +       PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
 419 +
 420 +       PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
 421 +       PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
 422 +       PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
 423 +       PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
 424 +       PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
 425 +       PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
 426 +
 427 +       PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
 428 +       PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
 429 +
 430 +       PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
 431 +       PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
 432 +
 433 +       PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
 434 +       PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
 435 +       PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
 436 +       PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
 437 +};
 438 +
 439 +static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
 440 +       PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
 441 +       PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
 442 +       PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
 443 +       PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
 444 +       PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
 445 +       PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
 446 +       PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
 447 +       PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
 448 +       PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
 449 +       PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 9, 1),
 450 +
 451 +       PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
 452 +       PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
 453 +       PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
 454 +       PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
 455 +
 456 +       PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
 457 +
 458 +       PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
 459 +       PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
 460 +       PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
 461 +       PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
 462 +       PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
 463 +       PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
 464 +       PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
 465 +       PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
 466 +       PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
 467 +       PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
 468 +       PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
 469 +
 470 +       PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
 471 +       PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
 472 +       PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
 473 +       PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
 474 +       PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
 475 +       PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
 476 +
 477 +       PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
 478 +       PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
 479 +
 480 +       PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
 481 +       PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
 482 +
 483 +       PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
 484 +       PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
 485 +       PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
 486 +       PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
 487 +};
 488 +
 489 +static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
 490 +       PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
 491 +       PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
 492 +       PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
 493 +       PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
 494 +       PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
 495 +       PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
 496 +       PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
 497 +       PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
 498 +       PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
 499 +       PIN_FIELD_BASE(9, 9, 4, 0x50, 0x10, 9, 1),
 500 +
 501 +       PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
 502 +       PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
 503 +       PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
 504 +       PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
 505 +
 506 +       PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
 507 +
 508 +       PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
 509 +       PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
 510 +       PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
 511 +       PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
 512 +       PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
 513 +       PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
 514 +       PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
 515 +       PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
 516 +       PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
 517 +       PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
 518 +       PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
 519 +
 520 +       PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
 521 +       PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
 522 +       PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
 523 +       PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
 524 +       PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
 525 +       PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
 526 +
 527 +       PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
 528 +       PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
 529 +
 530 +       PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
 531 +       PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
 532 +
 533 +       PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
 534 +       PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
 535 +       PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
 536 +       PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
 537 +};
 538 +
 539 +static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
 540 +       [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
 541 +       [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
 542 +       [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
 543 +       [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
 544 +       [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
 545 +       [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
 546 +       [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
 547 +       [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
 548 +       [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
 549 +       [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
 550 +       [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
 551 +       [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
 552 +};
 553 +
 554 +static const struct mtk_pin_desc mt7981_pins[] = {
 555 +       MT7981_TYPE0_PIN(0, "GPIO_WPS"),
 556 +       MT7981_TYPE0_PIN(1, "GPIO_RESET"),
 557 +       MT7981_TYPE0_PIN(2, "SYS_WATCHDOG"),
 558 +       MT7981_TYPE0_PIN(3, "PCIE_PERESET_N"),
 559 +       MT7981_TYPE0_PIN(4, "JTAG_JTDO"),
 560 +       MT7981_TYPE0_PIN(5, "JTAG_JTDI"),
 561 +       MT7981_TYPE0_PIN(6, "JTAG_JTMS"),
 562 +       MT7981_TYPE0_PIN(7, "JTAG_JTCLK"),
 563 +       MT7981_TYPE0_PIN(8, "JTAG_JTRST_N"),
 564 +       MT7981_TYPE0_PIN(9, "WO_JTAG_JTDO"),
 565 +       MT7981_TYPE0_PIN(10, "WO_JTAG_JTDI"),
 566 +       MT7981_TYPE0_PIN(11, "WO_JTAG_JTMS"),
 567 +       MT7981_TYPE0_PIN(12, "WO_JTAG_JTCLK"),
 568 +       MT7981_TYPE0_PIN(13, "WO_JTAG_JTRST_N"),
 569 +       MT7981_TYPE0_PIN(14, "USB_VBUS"),
 570 +       MT7981_TYPE0_PIN(15, "PWM0"),
 571 +       MT7981_TYPE0_PIN(16, "SPI0_CLK"),
 572 +       MT7981_TYPE0_PIN(17, "SPI0_MOSI"),
 573 +       MT7981_TYPE0_PIN(18, "SPI0_MISO"),
 574 +       MT7981_TYPE0_PIN(19, "SPI0_CS"),
 575 +       MT7981_TYPE0_PIN(20, "SPI0_HOLD"),
 576 +       MT7981_TYPE0_PIN(21, "SPI0_WP"),
 577 +       MT7981_TYPE0_PIN(22, "SPI1_CLK"),
 578 +       MT7981_TYPE0_PIN(23, "SPI1_MOSI"),
 579 +       MT7981_TYPE0_PIN(24, "SPI1_MISO"),
 580 +       MT7981_TYPE0_PIN(25, "SPI1_CS"),
 581 +       MT7981_TYPE0_PIN(26, "SPI2_CLK"),
 582 +       MT7981_TYPE0_PIN(27, "SPI2_MOSI"),
 583 +       MT7981_TYPE0_PIN(28, "SPI2_MISO"),
 584 +       MT7981_TYPE0_PIN(29, "SPI2_CS"),
 585 +       MT7981_TYPE0_PIN(30, "SPI2_HOLD"),
 586 +       MT7981_TYPE0_PIN(31, "SPI2_WP"),
 587 +       MT7981_TYPE0_PIN(32, "UART0_RXD"),
 588 +       MT7981_TYPE0_PIN(33, "UART0_TXD"),
 589 +       MT7981_TYPE0_PIN(34, "PCIE_CLK_REQ"),
 590 +       MT7981_TYPE0_PIN(35, "PCIE_WAKE_N"),
 591 +       MT7981_TYPE0_PIN(36, "SMI_MDC"),
 592 +       MT7981_TYPE0_PIN(37, "SMI_MDIO"),
 593 +       MT7981_TYPE0_PIN(38, "GBE_INT"),
 594 +       MT7981_TYPE0_PIN(39, "GBE_RESET"),
 595 +       MT7981_TYPE1_PIN(40, "WF_DIG_RESETB"),
 596 +       MT7981_TYPE1_PIN(41, "WF_CBA_RESETB"),
 597 +       MT7981_TYPE1_PIN(42, "WF_XO_REQ"),
 598 +       MT7981_TYPE1_PIN(43, "WF_TOP_CLK"),
 599 +       MT7981_TYPE1_PIN(44, "WF_TOP_DATA"),
 600 +       MT7981_TYPE1_PIN(45, "WF_HB1"),
 601 +       MT7981_TYPE1_PIN(46, "WF_HB2"),
 602 +       MT7981_TYPE1_PIN(47, "WF_HB3"),
 603 +       MT7981_TYPE1_PIN(48, "WF_HB4"),
 604 +       MT7981_TYPE1_PIN(49, "WF_HB0"),
 605 +       MT7981_TYPE1_PIN(50, "WF_HB0_B"),
 606 +       MT7981_TYPE1_PIN(51, "WF_HB5"),
 607 +       MT7981_TYPE1_PIN(52, "WF_HB6"),
 608 +       MT7981_TYPE1_PIN(53, "WF_HB7"),
 609 +       MT7981_TYPE1_PIN(54, "WF_HB8"),
 610 +       MT7981_TYPE1_PIN(55, "WF_HB9"),
 611 +       MT7981_TYPE1_PIN(56, "WF_HB10"),
 612 +};
 613 +
 614 +/* WA_AICE */
 615 +static int mt7981_wa_aice1_pins[] = { 0, 1, };
 616 +static int mt7981_wa_aice1_funcs[] = { 2, 2, };
 617 +
 618 +static int mt7981_wa_aice2_pins[] = { 0, 1, };
 619 +static int mt7981_wa_aice2_funcs[] = { 3, 3, };
 620 +
 621 +static int mt7981_wa_aice3_pins[] = { 28, 29, };
 622 +static int mt7981_wa_aice3_funcs[] = { 3, 3, };
 623 +
 624 +static int mt7981_wm_aice1_pins[] = { 9, 10, };
 625 +static int mt7981_wm_aice1_funcs[] = { 2, 2, };
 626 +
 627 +static int mt7981_wm_aice2_pins[] = { 30, 31, };
 628 +static int mt7981_wm_aice2_funcs[] = { 5, 5, };
 629 +
 630 +/* WM_UART */
 631 +static int mt7981_wm_uart_0_pins[] = { 0, 1, };
 632 +static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
 633 +
 634 +static int mt7981_wm_uart_1_pins[] = { 20, 21, };
 635 +static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
 636 +
 637 +static int mt7981_wm_uart_2_pins[] = { 30, 31, };
 638 +static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
 639 +
 640 +/* DFD */
 641 +static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
 642 +static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
 643 +
 644 +/* SYS_WATCHDOG */
 645 +static int mt7981_watchdog_pins[] = { 2, };
 646 +static int mt7981_watchdog_funcs[] = { 1, };
 647 +
 648 +static int mt7981_watchdog1_pins[] = { 13, };
 649 +static int mt7981_watchdog1_funcs[] = { 5, };
 650 +
 651 +/* PCIE_PERESET_N */
 652 +static int mt7981_pcie_pereset_pins[] = { 3, };
 653 +static int mt7981_pcie_pereset_funcs[] = { 1, };
 654 +
 655 +/* JTAG */
 656 +static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
 657 +static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
 658 +
 659 +/* WM_JTAG */
 660 +static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
 661 +static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
 662 +
 663 +static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
 664 +static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
 665 +
 666 +/* WO0_JTAG */
 667 +static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
 668 +static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
 669 +
 670 +static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
 671 +static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
 672 +
 673 +/* UART2 */
 674 +static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
 675 +static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
 676 +
 677 +/* GBE_LED0 */
 678 +static int mt7981_gbe_led0_pins[] = { 8, };
 679 +static int mt7981_gbe_led0_funcs[] = { 3, };
 680 +
 681 +/* PTA_EXT */
 682 +static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
 683 +static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
 684 +
 685 +static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
 686 +static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
 687 +
 688 +/* PWM2 */
 689 +static int mt7981_pwm2_pins[] = { 7, };
 690 +static int mt7981_pwm2_funcs[] = { 4, };
 691 +
 692 +/* NET_WO0_UART_TXD */
 693 +static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
 694 +static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
 695 +
 696 +static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
 697 +static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
 698 +
 699 +static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
 700 +static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
 701 +
 702 +/* SPI1 */
 703 +static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
 704 +static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
 705 +
 706 +/* I2C */
 707 +static int mt7981_i2c0_0_pins[] = { 6, 7, };
 708 +static int mt7981_i2c0_0_funcs[] = { 6, 6, };
 709 +
 710 +static int mt7981_i2c0_1_pins[] = { 30, 31, };
 711 +static int mt7981_i2c0_1_funcs[] = { 4, 4, };
 712 +
 713 +static int mt7981_i2c0_2_pins[] = { 36, 37, };
 714 +static int mt7981_i2c0_2_funcs[] = { 2, 2, };
 715 +
 716 +static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
 717 +static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
 718 +
 719 +static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
 720 +static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
 721 +
 722 +static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
 723 +static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
 724 +
 725 +static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
 726 +static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
 727 +
 728 +/* DFD_NTRST */
 729 +static int mt7981_dfd_ntrst_pins[] = { 8, };
 730 +static int mt7981_dfd_ntrst_funcs[] = { 6, };
 731 +
 732 +/* PWM0 */
 733 +static int mt7981_pwm0_0_pins[] = { 13, };
 734 +static int mt7981_pwm0_0_funcs[] = { 2, };
 735 +
 736 +static int mt7981_pwm0_1_pins[] = { 15, };
 737 +static int mt7981_pwm0_1_funcs[] = { 1, };
 738 +
 739 +/* PWM1 */
 740 +static int mt7981_pwm1_0_pins[] = { 14, };
 741 +static int mt7981_pwm1_0_funcs[] = { 2, };
 742 +
 743 +static int mt7981_pwm1_1_pins[] = { 15, };
 744 +static int mt7981_pwm1_1_funcs[] = { 3, };
 745 +
 746 +/* GBE_LED1 */
 747 +static int mt7981_gbe_led1_pins[] = { 13, };
 748 +static int mt7981_gbe_led1_funcs[] = { 3, };
 749 +
 750 +/* PCM */
 751 +static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
 752 +static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
 753 +
 754 +/* UDI */
 755 +static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
 756 +static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
 757 +
 758 +/* DRV_VBUS */
 759 +static int mt7981_drv_vbus_pins[] = { 14, };
 760 +static int mt7981_drv_vbus_funcs[] = { 1, };
 761 +
 762 +/* EMMC */
 763 +static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
 764 +static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
 765 +
 766 +/* SNFI */
 767 +static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
 768 +static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
 769 +
 770 +/* SPI0 */
 771 +static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
 772 +static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
 773 +
 774 +/* SPI0 */
 775 +static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
 776 +static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
 777 +
 778 +/* SPI1 */
 779 +static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
 780 +static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
 781 +
 782 +/* SPI2 */
 783 +static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
 784 +static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
 785 +
 786 +/* SPI2 */
 787 +static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
 788 +static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
 789 +
 790 +/* UART1 */
 791 +static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
 792 +static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
 793 +
 794 +static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
 795 +static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
 796 +
 797 +/* UART2 */
 798 +static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
 799 +static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
 800 +
 801 +/* UART0 */
 802 +static int mt7981_uart0_pins[] = { 32, 33, };
 803 +static int mt7981_uart0_funcs[] = { 1, 1, };
 804 +
 805 +/* PCIE_CLK_REQ */
 806 +static int mt7981_pcie_clk_pins[] = { 34, };
 807 +static int mt7981_pcie_clk_funcs[] = { 2, };
 808 +
 809 +/* PCIE_WAKE_N */
 810 +static int mt7981_pcie_wake_pins[] = { 35, };
 811 +static int mt7981_pcie_wake_funcs[] = { 2, };
 812 +
 813 +/* MDC_MDIO */
 814 +static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
 815 +static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
 816 +
 817 +static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
 818 +static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
 819 +
 820 +/* WF0_MODE1 */
 821 +static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
 822 +                                      50, 51, 52, 53, 54, 55, 56 };
 823 +static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 824 +                                       1, 1, 1, 1 };
 825 +
 826 +/* WF0_MODE3 */
 827 +static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
 828 +static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
 829 +
 830 +/* WF2G_LED */
 831 +static int mt7981_wf2g_led0_pins[] = { 30, };
 832 +static int mt7981_wf2g_led0_funcs[] = { 2, };
 833 +
 834 +static int mt7981_wf2g_led1_pins[] = { 34, };
 835 +static int mt7981_wf2g_led1_funcs[] = { 1, };
 836 +
 837 +/* WF5G_LED */
 838 +static int mt7981_wf5g_led0_pins[] = { 31, };
 839 +static int mt7981_wf5g_led0_funcs[] = { 2, };
 840 +
 841 +static int mt7981_wf5g_led1_pins[] = { 35, };
 842 +static int mt7981_wf5g_led1_funcs[] = { 1, };
 843 +
 844 +/* MT7531_INT */
 845 +static int mt7981_mt7531_int_pins[] = { 38, };
 846 +static int mt7981_mt7531_int_funcs[] = { 1, };
 847 +
 848 +/* ANT_SEL */
 849 +static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
 850 +static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
 851 +
 852 +static const struct mtk_group_desc mt7981_groups[] = {
 853 +       /* @GPIO(0,1): WA_AICE(2) */
 854 +       PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
 855 +       /* @GPIO(0,1): WA_AICE(3) */
 856 +       PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
 857 +       /* @GPIO(0,1): WM_UART(5) */
 858 +       PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
 859 +       /* @GPIO(0,1,4,5): DFD(6) */
 860 +       PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
 861 +       /* @GPIO(2): SYS_WATCHDOG(1) */
 862 +       PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
 863 +       /* @GPIO(3): PCIE_PERESET_N(1) */
 864 +       PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
 865 +       /* @GPIO(4,8) JTAG(1) */
 866 +       PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
 867 +       /* @GPIO(4,8) WM_JTAG(2) */
 868 +       PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
 869 +       /* @GPIO(9,13) WO0_JTAG(1) */
 870 +       PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
 871 +       /* @GPIO(4,7) WM_JTAG(3) */
 872 +       PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
 873 +       /* @GPIO(8) GBE_LED0(3) */
 874 +       PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
 875 +       /* @GPIO(4,6) PTA_EXT(4) */
 876 +       PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
 877 +       /* @GPIO(7) PWM2(4) */
 878 +       PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
 879 +       /* @GPIO(8) NET_WO0_UART_TXD(4) */
 880 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
 881 +       /* @GPIO(4,7) SPI1(5) */
 882 +       PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
 883 +       /* @GPIO(6,7) I2C(5) */
 884 +       PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
 885 +       /* @GPIO(8): DFD_NTRST(6) */
 886 +       PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
 887 +       /* @GPIO(9,10): WM_AICE(2) */
 888 +       PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
 889 +       /* @GPIO(13): PWM0(2) */
 890 +       PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
 891 +       /* @GPIO(15): PWM0(1) */
 892 +       PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
 893 +       /* @GPIO(14): PWM1(2) */
 894 +       PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
 895 +       /* @GPIO(15): PWM1(3) */
 896 +       PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
 897 +       /* @GPIO(14) NET_WO0_UART_TXD(3) */
 898 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
 899 +       /* @GPIO(15) NET_WO0_UART_TXD(4) */
 900 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
 901 +       /* @GPIO(13) GBE_LED0(3) */
 902 +       PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
 903 +       /* @GPIO(9,13) PCM(4) */
 904 +       PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
 905 +       /* @GPIO(13): SYS_WATCHDOG1(5) */
 906 +       PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
 907 +       /* @GPIO(9,13) UDI(4) */
 908 +       PINCTRL_PIN_GROUP("udi", mt7981_udi),
 909 +       /* @GPIO(14) DRV_VBUS(1) */
 910 +       PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
 911 +       /* @GPIO(15,25): EMMC(2) */
 912 +       PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
 913 +       /* @GPIO(16,21): SNFI(3) */
 914 +       PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
 915 +       /* @GPIO(16,19): SPI0(1) */
 916 +       PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
 917 +       /* @GPIO(20,21): SPI0(1) */
 918 +       PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
 919 +       /* @GPIO(22,25) SPI1(1) */
 920 +       PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
 921 +       /* @GPIO(26,29): SPI2(1) */
 922 +       PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
 923 +       /* @GPIO(30,31): SPI2(1) */
 924 +       PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
 925 +       /* @GPIO(16,19): UART1(4) */
 926 +       PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
 927 +       /* @GPIO(26,29): UART1(2) */
 928 +       PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
 929 +       /* @GPIO(22,25): UART2(3) */
 930 +       PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1),
 931 +       /* @GPIO(22,24) PTA_EXT(4) */
 932 +       PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
 933 +       /* @GPIO(20,21): WM_UART(4) */
 934 +       PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
 935 +       /* @GPIO(30,31): WM_UART(3) */
 936 +       PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
 937 +       /* @GPIO(20,24) WM_JTAG(5) */
 938 +       PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
 939 +       /* @GPIO(25,29) WO0_JTAG(5) */
 940 +       PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
 941 +       /* @GPIO(28,29): WA_AICE(3) */
 942 +       PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
 943 +       /* @GPIO(30,31): WM_AICE(5) */
 944 +       PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
 945 +       /* @GPIO(30,31): I2C(4) */
 946 +       PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
 947 +       /* @GPIO(30,31): I2C(6) */
 948 +       PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
 949 +       /* @GPIO(32,33): I2C(1) */
 950 +       PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
 951 +       /* @GPIO(32,33): I2C(2) */
 952 +       PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
 953 +       /* @GPIO(32,33): I2C(3) */
 954 +       PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
 955 +       /* @GPIO(32,33): I2C(5) */
 956 +       PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
 957 +       /* @GPIO(34): PCIE_CLK_REQ(2) */
 958 +       PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
 959 +       /* @GPIO(35): PCIE_WAKE_N(2) */
 960 +       PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
 961 +       /* @GPIO(36,37): I2C(2) */
 962 +       PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
 963 +       /* @GPIO(36,37): MDC_MDIO(1) */
 964 +       PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
 965 +       /* @GPIO(36,37): MDC_MDIO(3) */
 966 +       PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
 967 +       /* @GPIO(40,56): WF0_MODE1(1) */
 968 +       PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
 969 +       /* @GPIO(45,46,47,48,49,51): WF0_MODE3(3) */
 970 +       PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
 971 +       /* @GPIO(30): WF2G_LED(2) */
 972 +       PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
 973 +       /* @GPIO(34): WF2G_LED(1) */
 974 +       PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
 975 +       /* @GPIO(31): WF5G_LED(2) */
 976 +       PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
 977 +       /* @GPIO(35): WF5G_LED(1) */
 978 +       PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
 979 +       /* @GPIO(38): MT7531_INT(1) */
 980 +       PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
 981 +       /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
 982 +       PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
 983 +};
 984 +
 985 +static const struct mtk_io_type_desc mt7981_io_type_desc[] = {
 986 +       [IO_TYPE_GRP0] = {
 987 +               .name = "18OD33",
 988 +               .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
 989 +               .drive_set = mtk_pinconf_drive_set_v1,
 990 +               .input_enable = mtk_pinconf_input_enable_v1,
 991 +       },
 992 +       [IO_TYPE_GRP1] = {
 993 +               .name = "18A01",
 994 +               .bias_set = mtk_pinconf_bias_set_pu_pd,
 995 +               .drive_set = mtk_pinconf_drive_set_v1,
 996 +               .input_enable = mtk_pinconf_input_enable_v1,
 997 +       },
 998 +};
 999 +
1000 +/* Joint those groups owning the same capability in user point of view which
1001 + * allows that people tend to use through the device tree.
1002 + */
1003 +static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2",
1004 +       "wm_aice1_1", "wa_aice3", "wm_aice1_2", };
1005 +static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
1006 +       "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
1007 +       "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", };
1008 +static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
1009 +static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
1010 +static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk",
1011 +       "pcie_wake", };
1012 +static const char *const mt7981_jtag_groups[] = { "jtag", "wm_jtag_0",
1013 +       "wo0_jtag_0", "wo0_jtag_1", "wm_jtag_1", };
1014 +static const char *const mt7981_led_groups[] = { "gbe_led0", "gbe_led1",
1015 +       "wf2g_led0", "wf2g_led1", "wf5g_led0", "wf5g_led1", };
1016 +static const char *const mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
1017 +static const char *const mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
1018 +       "pwm1_0", "pwm1_1", };
1019 +static const char *const mt7981_spi_groups[] = { "spi1_0", "spi0",
1020 +       "spi0_wp_hold", "spi1_1", "spi2", "spi2_wp_hold", };
1021 +static const char *const mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1",
1022 +       "u2_phy_i2c", "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c",
1023 +       "i2c0_2", };
1024 +static const char *const mt7981_pcm_groups[] = { "pcm", };
1025 +static const char *const mt7981_udi_groups[] = { "udi", };
1026 +static const char *const mt7981_usb_groups[] = { "drv_vbus", };
1027 +static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", };
1028 +static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio",
1029 +       "gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", };
1030 +static const char *const mt7981_ant_groups[] = { "ant_sel", };
1031 +
1032 +static const struct mtk_function_desc mt7981_functions[] = {
1033 +       {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
1034 +       {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
1035 +       {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
1036 +       {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
1037 +       {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
1038 +       {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
1039 +       {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
1040 +       {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
1041 +       {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
1042 +       {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
1043 +       {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
1044 +       {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
1045 +       {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
1046 +       {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
1047 +       {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
1048 +       {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
1049 +       {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
1050 +};
1051 +
1052 +static const char *const mt7981_pinctrl_register_base_names[] = {
1053 +       "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base",
1054 +       "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base",
1055 +};
1056 +
1057 +static struct mtk_pinctrl_soc mt7981_data = {
1058 +       .name = "mt7981_pinctrl",
1059 +       .reg_cal = mt7981_reg_cals,
1060 +       .pins = mt7981_pins,
1061 +       .npins = ARRAY_SIZE(mt7981_pins),
1062 +       .grps = mt7981_groups,
1063 +       .ngrps = ARRAY_SIZE(mt7981_groups),
1064 +       .funcs = mt7981_functions,
1065 +       .nfuncs = ARRAY_SIZE(mt7981_functions),
1066 +       .io_type = mt7981_io_type_desc,
1067 +       .ntype = ARRAY_SIZE(mt7981_io_type_desc),
1068 +       .gpio_mode = 0,
1069 +       .base_names = mt7981_pinctrl_register_base_names,
1070 +       .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
1071 +       .base_calc = 1,
1072 +};
1073 +
1074 +static int mtk_pinctrl_mt7981_probe(struct udevice *dev)
1075 +{
1076 +       return mtk_pinctrl_common_probe(dev, &mt7981_data);
1077 +}
1078 +
1079 +static const struct udevice_id mt7981_pctrl_match[] = {
1080 +       {.compatible = "mediatek,mt7981-pinctrl"},
1081 +       { /* sentinel */ }
1082 +};
1083 +
1084 +U_BOOT_DRIVER(mt7981_pinctrl) = {
1085 +       .name = "mt7981_pinctrl",
1086 +       .id = UCLASS_PINCTRL,
1087 +       .of_match = mt7981_pctrl_match,
1088 +       .ops = &mtk_pinctrl_ops,
1089 +       .probe = mtk_pinctrl_mt7981_probe,
1090 +       .priv_auto = sizeof(struct mtk_pinctrl_priv),
1091 +};