package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch

   1 From e9c0c2ebd346aa578007c2aa88fc0974af6afb40 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 29 Jul 2022 11:14:33 +0800
   4 Subject: [PATCH 24/31] clk: mediatek: add infrasys clock mux support
   5
   6 This patch adds infrasys clock mux support for mediatek clock drivers.
   7
   8 Reviewed-by: Simon Glass <sjg@chromium.org>
   9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  10 ---
  11  drivers/clk/mediatek/clk-mtk.c | 72 ++++++++++++++++++++++++++++++++++
  12  drivers/clk/mediatek/clk-mtk.h |  4 +-
  13  2 files changed, 75 insertions(+), 1 deletion(-)
  14
  15 --- a/drivers/clk/mediatek/clk-mtk.c
  16 +++ b/drivers/clk/mediatek/clk-mtk.c
  17 @@ -303,6 +303,24 @@ static ulong mtk_topckgen_get_factor_rat
  18         return mtk_factor_recalc_rate(fdiv, rate);
  19  }
  20
  21 +static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)
  22 +{
  23 +       struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  24 +       const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
  25 +       ulong rate;
  26 +
  27 +       switch (fdiv->flags & CLK_PARENT_MASK) {
  28 +       case CLK_PARENT_TOPCKGEN:
  29 +               rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
  30 +                                               priv->parent);
  31 +               break;
  32 +       default:
  33 +               rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
  34 +       }
  35 +
  36 +       return mtk_factor_recalc_rate(fdiv, rate);
  37 +}
  38 +
  39  static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
  40  {
  41         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  42 @@ -332,6 +350,34 @@ static ulong mtk_topckgen_get_mux_rate(s
  43         return priv->tree->xtal_rate;
  44  }
  45
  46 +static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off)
  47 +{
  48 +       struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  49 +       const struct mtk_composite *mux = &priv->tree->muxes[off];
  50 +       u32 index;
  51 +       u32 flag;
  52 +
  53 +       index = readl(priv->base + mux->mux_reg);
  54 +       index &= mux->mux_mask << mux->mux_shift;
  55 +       index = index >> mux->mux_shift;
  56 +
  57 +       if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
  58 +               flag = 1;
  59 +       if (mux->parent[index] > 0 || flag == 1) {
  60 +               switch (mux->flags & CLK_PARENT_MASK) {
  61 +               case CLK_PARENT_TOPCKGEN:
  62 +                       return mtk_clk_find_parent_rate(clk, mux->parent[index],
  63 +                                                       priv->parent);
  64 +                       break;
  65 +               default:
  66 +                       return mtk_clk_find_parent_rate(clk, mux->parent[index],
  67 +                                                       NULL);
  68 +                       break;
  69 +               }
  70 +       }
  71 +       return 0;
  72 +}
  73 +
  74  static ulong mtk_topckgen_get_rate(struct clk *clk)
  75  {
  76         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  77 @@ -346,6 +392,25 @@ static ulong mtk_topckgen_get_rate(struc
  78                                                  priv->tree->muxes_offs);
  79  }
  80
  81 +static ulong mtk_infrasys_get_rate(struct clk *clk)
  82 +{
  83 +       struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  84 +
  85 +       ulong rate;
  86 +
  87 +       if (clk->id < priv->tree->fdivs_offs) {
  88 +               rate = priv->tree->fclks[clk->id].rate;
  89 +       } else if (clk->id < priv->tree->muxes_offs) {
  90 +               rate = mtk_infrasys_get_factor_rate(clk, clk->id -
  91 +                                                   priv->tree->fdivs_offs);
  92 +       } else {
  93 +               rate = mtk_infrasys_get_mux_rate(clk, clk->id -
  94 +                                                priv->tree->muxes_offs);
  95 +       }
  96 +
  97 +       return rate;
  98 +}
  99 +
 100  static int mtk_clk_mux_enable(struct clk *clk)
 101  {
 102         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
 103 @@ -494,6 +559,13 @@ const struct clk_ops mtk_clk_topckgen_op
 104         .set_parent = mtk_common_clk_set_parent,
 105  };
 106
 107 +const struct clk_ops mtk_clk_infrasys_ops = {
 108 +       .enable = mtk_clk_mux_enable,
 109 +       .disable = mtk_clk_mux_disable,
 110 +       .get_rate = mtk_infrasys_get_rate,
 111 +       .set_parent = mtk_common_clk_set_parent,
 112 +};
 113 +
 114  const struct clk_ops mtk_clk_gate_ops = {
 115         .enable = mtk_clk_gate_enable,
 116         .disable = mtk_clk_gate_disable,
 117 --- a/drivers/clk/mediatek/clk-mtk.h
 118 +++ b/drivers/clk/mediatek/clk-mtk.h
 119 @@ -28,7 +28,8 @@
 120
 121  #define CLK_PARENT_APMIXED             BIT(4)
 122  #define CLK_PARENT_TOPCKGEN            BIT(5)
 123 -#define CLK_PARENT_MASK                        GENMASK(5, 4)
 124 +#define CLK_PARENT_INFRASYS            BIT(6)
 125 +#define CLK_PARENT_MASK                        GENMASK(6, 4)
 126
 127  #define ETHSYS_HIFSYS_RST_CTRL_OFS     0x34
 128
 129 @@ -220,6 +221,7 @@ struct mtk_cg_priv {
 130
 131  extern const struct clk_ops mtk_clk_apmixedsys_ops;
 132  extern const struct clk_ops mtk_clk_topckgen_ops;
 133 +extern const struct clk_ops mtk_clk_infrasys_ops;
 134  extern const struct clk_ops mtk_clk_gate_ops;
 135
 136  int mtk_common_clk_init(struct udevice *dev,