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uboot-mediatek: replace patches with updated versions
[openwrt/staging/dedeckeh.git] / package / boot / uboot-mediatek / patches / 002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
1 From 54b66dd24310dba4798caa6e4c02b8571f522602 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 31 Aug 2022 19:05:13 +0800
4 Subject: [PATCH 26/32] clk: mediatek: add clock driver support for MediaTek
5 MT7986 SoC
6
7 This patch adds clock driver support for MediaTek MT7986 SoC
8
9 Reviewed-by: Sean Anderson <seanga2@gmail.com>
10 Reviewed-by: Simon Glass <sjg@chromium.org>
11 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
12 ---
13 drivers/clk/mediatek/Makefile | 1 +
14 drivers/clk/mediatek/clk-mt7986.c | 672 +++++++++++++++++++++++++
15 include/dt-bindings/clock/mt7986-clk.h | 249 +++++++++
16 3 files changed, 922 insertions(+)
17 create mode 100644 drivers/clk/mediatek/clk-mt7986.c
18 create mode 100644 include/dt-bindings/clock/mt7986-clk.h
19
20 --- a/drivers/clk/mediatek/Makefile
21 +++ b/drivers/clk/mediatek/Makefile
22 @@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o
23 obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
24 obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
25 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
26 +obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
27 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
28 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
29 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
30 --- /dev/null
31 +++ b/drivers/clk/mediatek/clk-mt7986.c
32 @@ -0,0 +1,672 @@
33 +// SPDX-License-Identifier: GPL-2.0
34 +/*
35 + * MediaTek clock driver for MT7986 SoC
36 + *
37 + * Copyright (C) 2022 MediaTek Inc.
38 + * Author: Sam Shih <sam.shih@mediatek.com>
39 + */
40 +
41 +#include <dm.h>
42 +#include <log.h>
43 +#include <asm/arch-mediatek/reset.h>
44 +#include <asm/io.h>
45 +#include <dt-bindings/clock/mt7986-clk.h>
46 +#include <linux/bitops.h>
47 +
48 +#include "clk-mtk.h"
49 +
50 +#define MT7986_CLK_PDN 0x250
51 +#define MT7986_CLK_PDN_EN_WRITE BIT(31)
52 +
53 +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
54 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
55 +
56 +#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
57 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
58 +
59 +#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
60 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
61 +
62 +/* FIXED PLLS */
63 +static const struct mtk_fixed_clk fixed_pll_clks[] = {
64 + FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
65 + FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
66 + FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
67 + FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
68 + FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
69 + FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
70 + FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
71 + FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
72 +};
73 +
74 +/* TOPCKGEN FIXED CLK */
75 +static const struct mtk_fixed_clk top_fixed_clks[] = {
76 + FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
77 +};
78 +
79 +/* TOPCKGEN FIXED DIV */
80 +static const struct mtk_fixed_factor top_fixed_divs[] = {
81 + PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
82 + PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
83 + PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
84 + PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
85 + PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
86 + PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
87 + PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
88 + PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
89 + PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
90 + PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16),
91 + PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8),
92 + PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30),
93 + PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
94 + 1),
95 + PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
96 + PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
97 + PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
98 + PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
99 + PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
100 + PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
101 + PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
102 + PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
103 + 1),
104 + PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
105 + PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
106 + PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
107 + PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m",
108 + CK_APMIXED_WEDMCUPLL, 1, 1),
109 + PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
110 + 10),
111 + PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
112 + TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M,
113 + 1, 2),
114 + TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
115 + 1250),
116 + TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
117 + 1220),
118 + TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
119 + TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
120 + 1),
121 + TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
122 + TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
123 + TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
124 + TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
125 + TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
126 + TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
127 + TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
128 + TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
129 + TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
130 + 1),
131 + TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
132 + TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
133 + CK_TOP_NETSYS_MCU_SEL, 1, 1),
134 + TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
135 + TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
136 + TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
137 + TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
138 + TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
139 + TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
140 + TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
141 + TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
142 + TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
143 + TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
144 + TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
145 + 1),
146 +};
147 +
148 +/* TOPCKGEN MUX PARENTS */
149 +static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8,
150 + CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2,
151 + CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2,
152 + CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
153 +
154 +static const int spinfi_parents[] = {
155 + CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
156 + CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2,
157 + CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8
158 +};
159 +
160 +static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
161 + CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2,
162 + CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4,
163 + CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 };
164 +
165 +static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
166 + CK_TOP_M_D8_D2 };
167 +
168 +static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
169 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
170 +
171 +static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
172 + CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
173 +
174 +static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
175 + CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
176 + CK_TOP_CB_RTC_32K };
177 +
178 +static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
179 + CK_TOP_NET1_D5_D2 };
180 +
181 +static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M };
182 +
183 +static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
184 +
185 +static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 };
186 +
187 +static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
188 + CK_TOP_CB_NET2_D4 };
189 +
190 +static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2,
191 + CK_TOP_NET2_D4_D2 };
192 +
193 +static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
194 + CK_TOP_NET2_D3_D2 };
195 +
196 +static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M };
197 +
198 +static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 };
199 +
200 +static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
201 + CK_TOP_CB_NET1_D5 };
202 +
203 +static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M,
204 + CK_TOP_CB_WEDMCU_760M,
205 + CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
206 + CK_TOP_CB_NET1_D5 };
207 +
208 +static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
209 + CK_TOP_CB_NET2_800M,
210 + CK_TOP_CB_WEDMCU_760M,
211 + CK_TOP_CB_MM_D2 };
212 +
213 +static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
214 + CK_TOP_CB_SGM_325M };
215 +
216 +static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
217 +
218 +static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
219 +
220 +static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M,
221 + CK_TOP_CB_MM_D2 };
222 +
223 +static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M };
224 +
225 +static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
226 + CK_TOP_M_D8_D2 };
227 +
228 +static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
229 + CK_TOP_M_D8_D2 };
230 +
231 +static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
232 +
233 +static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M,
234 + CK_TOP_CB_U2_PHYD_CK };
235 +
236 +#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
237 + _shift, _width, _gate, _upd_ofs, _upd) \
238 + { \
239 + .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \
240 + .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
241 + .upd_shift = _upd, .mux_shift = _shift, \
242 + .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
243 + .gate_shift = _gate, .parent = _parents, \
244 + .num_parents = ARRAY_SIZE(_parents), \
245 + .flags = CLK_MUX_SETCLR_UPD, \
246 + }
247 +
248 +/* TOPCKGEN MUX_GATE */
249 +static const struct mtk_composite top_muxes[] = {
250 + /* CLK_CFG_0 */
251 + TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
252 + 0x008, 0, 3, 7, 0x1C0, 0),
253 + TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
254 + 0x008, 8, 3, 15, 0x1C0, 1),
255 + TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
256 + 3, 23, 0x1C0, 2),
257 + TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
258 + 0x008, 24, 3, 31, 0x1C0, 3),
259 + /* CLK_CFG_1 */
260 + TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
261 + 0, 2, 7, 0x1C0, 4),
262 + TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
263 + 2, 15, 0x1C0, 5),
264 + TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
265 + 2, 23, 0x1C0, 6),
266 + TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
267 + 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
268 + /* CLK_CFG_2 */
269 + TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
270 + 0x024, 0x028, 0, 1, 7, 0x1C0, 8),
271 + TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
272 + 0x024, 0x028, 8, 1, 15, 0x1C0, 9),
273 + TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
274 + 0x024, 0x028, 16, 1, 23, 0x1C0, 10),
275 + TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
276 + 0x028, 24, 1, 31, 0x1C0, 11),
277 + /* CLK_CFG_3 */
278 + TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
279 + 0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12),
280 + TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
281 + 0x038, 8, 2, 15, 0x1C0, 13),
282 + TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
283 + 0x038, 16, 2, 23, 0x1C0, 14),
284 + TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
285 + 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15),
286 + /* CLK_CFG_4 */
287 + TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
288 + 0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16),
289 + TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
290 + 0x048, 8, 1, 15, 0x1C0, 17),
291 + TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
292 + 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
293 + TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
294 + 0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
295 + /* CLK_CFG_5 */
296 + TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
297 + 0x054, 0x058, 0, 2, 7, 0x1C0, 20),
298 + TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
299 + 0x054, 0x058, 8, 1, 15, 0x1C0, 21),
300 + TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
301 + 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
302 + TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
303 + 0x058, 24, 1, 31, 0x1C0, 23),
304 + /* CLK_CFG_6 */
305 + TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
306 + 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
307 + TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
308 + 0x068, 8, 1, 15, 0x1C0, 25),
309 + TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
310 + 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
311 + TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
312 + 0x064, 0x068, 24, 1, 31, 0x1C0, 27),
313 + /* CLK_CFG_7 */
314 + TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
315 + 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
316 + TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
317 + 0x078, 8, 2, 15, 0x1C0, 29),
318 + TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
319 + 0x074, 0x078, 16, 2, 23, 0x1C0, 30),
320 + TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
321 + 0x078, 24, 1, 31, 0x1C4, 0),
322 + /* CLK_CFG_8 */
323 + TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
324 + 0x084, 0x088, 0, 1, 7, 0x1C4, 1),
325 + TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
326 + 0x084, 0x088, 8, 1, 15, 0x1C4, 2),
327 + TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
328 + 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
329 + TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
330 + 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
331 + /* CLK_CFG_9 */
332 + TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
333 + 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
334 +};
335 +
336 +/* INFRA FIXED DIV */
337 +static const struct mtk_fixed_factor infra_fixed_divs[] = {
338 + TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
339 + TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
340 + TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
341 + TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
342 + TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1),
343 + TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
344 + TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
345 + TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
346 + 1),
347 + TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
348 + INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
349 + 1),
350 + INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
351 + 1),
352 + INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
353 + 1),
354 + TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
355 + TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1),
356 + INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
357 + 1),
358 + TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
359 + TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
360 + TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
361 + 1),
362 + TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
363 + INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
364 + 1, 1),
365 + INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
366 + 1, 1),
367 + INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
368 + 1, 1),
369 + TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
370 + TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
371 + INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
372 + 1),
373 + INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
374 + 1),
375 + TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
376 + TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1),
377 + TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M,
378 + 1, 1),
379 + TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
380 + TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
381 + TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
382 + TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
383 + TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
384 + 1),
385 + TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
386 + CK_TOP_PEXTP_TL, 1, 1),
387 + TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
388 + TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1),
389 +};
390 +
391 +/* INFRASYS MUX PARENTS */
392 +static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
393 +
394 +static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
395 +
396 +static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
397 +
398 +static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K,
399 + CK_INFRA_CK_F26M,
400 + CK_INFRA_66M_MCK, CK_INFRA_PWM };
401 +
402 +static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
403 + -1, CK_INFRA_PCIE_CK };
404 +
405 +#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
406 + { \
407 + .id = _id, .mux_reg = (_reg) + 0x8, \
408 + .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
409 + .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
410 + .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
411 + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
412 + }
413 +
414 +/* INFRA MUX */
415 +
416 +static const struct mtk_composite infra_muxes[] = {
417 + /* MODULE_CLK_SEL_0 */
418 + INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
419 + 0x10, 0, 1),
420 + INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
421 + 0x10, 1, 1),
422 + INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
423 + 0x10, 2, 1),
424 + INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
425 + 4, 1),
426 + INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
427 + 5, 1),
428 + INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
429 + 0x10, 9, 2),
430 + INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
431 + 0x10, 11, 2),
432 + INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
433 + 0x10, 13, 2),
434 + /* MODULE_CLK_SEL_1 */
435 + INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
436 + 0, 2),
437 +};
438 +
439 +static const struct mtk_gate_regs infra_0_cg_regs = {
440 + .set_ofs = 0x40,
441 + .clr_ofs = 0x44,
442 + .sta_ofs = 0x48,
443 +};
444 +
445 +static const struct mtk_gate_regs infra_1_cg_regs = {
446 + .set_ofs = 0x50,
447 + .clr_ofs = 0x54,
448 + .sta_ofs = 0x58,
449 +};
450 +
451 +static const struct mtk_gate_regs infra_2_cg_regs = {
452 + .set_ofs = 0x60,
453 + .clr_ofs = 0x64,
454 + .sta_ofs = 0x68,
455 +};
456 +
457 +#define GATE_INFRA0(_id, _name, _parent, _shift) \
458 + { \
459 + .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
460 + .shift = _shift, \
461 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
462 + }
463 +
464 +#define GATE_INFRA1(_id, _name, _parent, _shift) \
465 + { \
466 + .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
467 + .shift = _shift, \
468 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
469 + }
470 +
471 +#define GATE_INFRA2(_id, _name, _parent, _shift) \
472 + { \
473 + .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
474 + .shift = _shift, \
475 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
476 + }
477 +
478 +/* INFRA GATE */
479 +
480 +static const struct mtk_gate infracfg_ao_gates[] = {
481 + /* INFRA0 */
482 + GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
483 + GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
484 + GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
485 + GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
486 + GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
487 + GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
488 + GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7),
489 + GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
490 + GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
491 + GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
492 + GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
493 + 11),
494 + GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
495 + 13),
496 + GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
497 + 14),
498 + GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
499 + GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
500 + GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
501 + GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
502 + GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26),
503 + /* INFRA1 */
504 + GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
505 + GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
506 + GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
507 + GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
508 + GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
509 + GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
510 + GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
511 + 9),
512 + GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
513 + GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
514 + GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
515 + GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
516 + 13),
517 + GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
518 + 14),
519 + GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
520 + GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
521 + GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
522 + CK_INFRA_FMSDC_HCK_CK, 17),
523 + GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
524 + CK_INFRA_PERI_133M, 18),
525 + GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
526 + 19),
527 + GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20),
528 + GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21),
529 + GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
530 + 23),
531 + /* INFRA2 */
532 + GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
533 + 0),
534 + GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
535 + 1),
536 + GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
537 + 2),
538 + GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
539 + GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13),
540 + GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15),
541 + GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
542 +};
543 +
544 +static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
545 + .fdivs_offs = CLK_APMIXED_NR_CLK,
546 + .xtal_rate = 40 * MHZ,
547 + .fclks = fixed_pll_clks,
548 +};
549 +
550 +static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
551 + .fdivs_offs = CK_TOP_CB_M_416M,
552 + .muxes_offs = CK_TOP_NFI1X_SEL,
553 + .fclks = top_fixed_clks,
554 + .fdivs = top_fixed_divs,
555 + .muxes = top_muxes,
556 + .flags = CLK_BYPASS_XTAL,
557 +};
558 +
559 +static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
560 + .fdivs_offs = CK_INFRA_CK_F26M,
561 + .muxes_offs = CK_INFRA_UART0_SEL,
562 + .fdivs = infra_fixed_divs,
563 + .muxes = infra_muxes,
564 +};
565 +
566 +static const struct udevice_id mt7986_fixed_pll_compat[] = {
567 + { .compatible = "mediatek,mt7986-fixed-plls" },
568 + {}
569 +};
570 +
571 +static const struct udevice_id mt7986_topckgen_compat[] = {
572 + { .compatible = "mediatek,mt7986-topckgen" },
573 + {}
574 +};
575 +
576 +static int mt7986_fixed_pll_probe(struct udevice *dev)
577 +{
578 + return mtk_common_clk_init(dev, &mt7986_fixed_pll_clk_tree);
579 +}
580 +
581 +static int mt7986_topckgen_probe(struct udevice *dev)
582 +{
583 + struct mtk_clk_priv *priv = dev_get_priv(dev);
584 +
585 + priv->base = dev_read_addr_ptr(dev);
586 + writel(MT7986_CLK_PDN_EN_WRITE, priv->base + MT7986_CLK_PDN);
587 +
588 + return mtk_common_clk_init(dev, &mt7986_topckgen_clk_tree);
589 +}
590 +
591 +U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
592 + .name = "mt7986-clock-fixed-pll",
593 + .id = UCLASS_CLK,
594 + .of_match = mt7986_fixed_pll_compat,
595 + .probe = mt7986_fixed_pll_probe,
596 + .priv_auto = sizeof(struct mtk_clk_priv),
597 + .ops = &mtk_clk_topckgen_ops,
598 + .flags = DM_FLAG_PRE_RELOC,
599 +};
600 +
601 +U_BOOT_DRIVER(mtk_clk_topckgen) = {
602 + .name = "mt7986-clock-topckgen",
603 + .id = UCLASS_CLK,
604 + .of_match = mt7986_topckgen_compat,
605 + .probe = mt7986_topckgen_probe,
606 + .priv_auto = sizeof(struct mtk_clk_priv),
607 + .ops = &mtk_clk_topckgen_ops,
608 + .flags = DM_FLAG_PRE_RELOC,
609 +};
610 +
611 +static const struct udevice_id mt7986_infracfg_compat[] = {
612 + { .compatible = "mediatek,mt7986-infracfg" },
613 + {}
614 +};
615 +
616 +static const struct udevice_id mt7986_infracfg_ao_compat[] = {
617 + { .compatible = "mediatek,mt7986-infracfg_ao" },
618 + {}
619 +};
620 +
621 +static int mt7986_infracfg_probe(struct udevice *dev)
622 +{
623 + return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
624 +}
625 +
626 +static int mt7986_infracfg_ao_probe(struct udevice *dev)
627 +{
628 + return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree,
629 + infracfg_ao_gates);
630 +}
631 +
632 +U_BOOT_DRIVER(mtk_clk_infracfg) = {
633 + .name = "mt7986-clock-infracfg",
634 + .id = UCLASS_CLK,
635 + .of_match = mt7986_infracfg_compat,
636 + .probe = mt7986_infracfg_probe,
637 + .priv_auto = sizeof(struct mtk_clk_priv),
638 + .ops = &mtk_clk_infrasys_ops,
639 + .flags = DM_FLAG_PRE_RELOC,
640 +};
641 +
642 +U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
643 + .name = "mt7986-clock-infracfg-ao",
644 + .id = UCLASS_CLK,
645 + .of_match = mt7986_infracfg_ao_compat,
646 + .probe = mt7986_infracfg_ao_probe,
647 + .priv_auto = sizeof(struct mtk_cg_priv),
648 + .ops = &mtk_clk_gate_ops,
649 + .flags = DM_FLAG_PRE_RELOC,
650 +};
651 +
652 +/* ethsys */
653 +static const struct mtk_gate_regs eth_cg_regs = {
654 + .sta_ofs = 0x30,
655 +};
656 +
657 +#define GATE_ETH(_id, _name, _parent, _shift) \
658 + { \
659 + .id = _id, .parent = _parent, .regs = &eth_cg_regs, \
660 + .shift = _shift, \
661 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
662 + }
663 +
664 +static const struct mtk_gate eth_cgs[] = {
665 + GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7),
666 + GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8),
667 + GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
668 + GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14),
669 + GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
670 +};
671 +
672 +static int mt7986_ethsys_probe(struct udevice *dev)
673 +{
674 + return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree,
675 + eth_cgs);
676 +}
677 +
678 +static int mt7986_ethsys_bind(struct udevice *dev)
679 +{
680 + int ret = 0;
681 +
682 + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
683 + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
684 + if (ret)
685 + debug("Warning: failed to bind reset controller\n");
686 + }
687 +
688 + return ret;
689 +}
690 +
691 +static const struct udevice_id mt7986_ethsys_compat[] = {
692 + { .compatible = "mediatek,mt7986-ethsys" },
693 + { }
694 +};
695 +
696 +U_BOOT_DRIVER(mtk_clk_ethsys) = {
697 + .name = "mt7986-clock-ethsys",
698 + .id = UCLASS_CLK,
699 + .of_match = mt7986_ethsys_compat,
700 + .probe = mt7986_ethsys_probe,
701 + .bind = mt7986_ethsys_bind,
702 + .priv_auto = sizeof(struct mtk_cg_priv),
703 + .ops = &mtk_clk_gate_ops,
704 +};
705 --- /dev/null
706 +++ b/include/dt-bindings/clock/mt7986-clk.h
707 @@ -0,0 +1,249 @@
708 +/* SPDX-License-Identifier: GPL-2.0 */
709 +/*
710 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
711 + *
712 + * Author: Sam Shih <sam.shih@mediatek.com>
713 + */
714 +
715 +#ifndef _DT_BINDINGS_CLK_MT7986_H
716 +#define _DT_BINDINGS_CLK_MT7986_H
717 +
718 +/* INFRACFG */
719 +
720 +#define CK_INFRA_CK_F26M 0
721 +#define CK_INFRA_UART 1
722 +#define CK_INFRA_ISPI0 2
723 +#define CK_INFRA_I2C 3
724 +#define CK_INFRA_ISPI1 4
725 +#define CK_INFRA_PWM 5
726 +#define CK_INFRA_66M_MCK 6
727 +#define CK_INFRA_CK_F32K 7
728 +#define CK_INFRA_PCIE_CK 8
729 +#define CK_INFRA_PWM_BCK 9
730 +#define CK_INFRA_PWM_CK1 10
731 +#define CK_INFRA_PWM_CK2 11
732 +#define CK_INFRA_133M_HCK 12
733 +#define CK_INFRA_EIP_CK 13
734 +#define CK_INFRA_66M_PHCK 14
735 +#define CK_INFRA_FAUD_L_CK 15
736 +#define CK_INFRA_FAUD_AUD_CK 17
737 +#define CK_INFRA_FAUD_EG2_CK 17
738 +#define CK_INFRA_I2CS_CK 18
739 +#define CK_INFRA_MUX_UART0 19
740 +#define CK_INFRA_MUX_UART1 20
741 +#define CK_INFRA_MUX_UART2 21
742 +#define CK_INFRA_NFI_CK 22
743 +#define CK_INFRA_SPINFI_CK 23
744 +#define CK_INFRA_MUX_SPI0 24
745 +#define CK_INFRA_MUX_SPI1 25
746 +#define CK_INFRA_RTC_32K 26
747 +#define CK_INFRA_FMSDC_CK 27
748 +#define CK_INFRA_FMSDC_HCK_CK 28
749 +#define CK_INFRA_PERI_133M 29
750 +#define CK_INFRA_133M_PHCK 30
751 +#define CK_INFRA_USB_SYS_CK 31
752 +#define CK_INFRA_USB_CK 32
753 +#define CK_INFRA_USB_XHCI_CK 33
754 +#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
755 +#define CK_INFRA_F26M_CK0 35
756 +#define CK_INFRA_HD_133M 36
757 +#define CLK_INFRA_NR_CLK 37
758 +
759 +/* TOPCKGEN */
760 +
761 +#define CK_TOP_CB_CKSQ_40M 0
762 +#define CK_TOP_CB_M_416M 1
763 +#define CK_TOP_CB_M_D2 2
764 +#define CK_TOP_CB_M_D4 3
765 +#define CK_TOP_CB_M_D8 4
766 +#define CK_TOP_M_D8_D2 5
767 +#define CK_TOP_M_D3_D2 6
768 +#define CK_TOP_CB_MM_D2 7
769 +#define CK_TOP_CB_MM_D4 8
770 +#define CK_TOP_CB_MM_D8 9
771 +#define CK_TOP_MM_D8_D2 10
772 +#define CK_TOP_MM_D3_D8 11
773 +#define CK_TOP_CB_U2_PHYD_CK 12
774 +#define CK_TOP_CB_APLL2_196M 13
775 +#define CK_TOP_APLL2_D4 14
776 +#define CK_TOP_CB_NET1_D4 15
777 +#define CK_TOP_CB_NET1_D5 16
778 +#define CK_TOP_NET1_D5_D2 17
779 +#define CK_TOP_NET1_D5_D4 18
780 +#define CK_TOP_NET1_D8_D2 19
781 +#define CK_TOP_NET1_D8_D4 20
782 +#define CK_TOP_CB_NET2_800M 21
783 +#define CK_TOP_CB_NET2_D4 22
784 +#define CK_TOP_NET2_D4_D2 23
785 +#define CK_TOP_NET2_D3_D2 24
786 +#define CK_TOP_CB_WEDMCU_760M 25
787 +#define CK_TOP_WEDMCU_D5_D2 26
788 +#define CK_TOP_CB_SGM_325M 27
789 +#define CK_TOP_CB_CKSQ_40M_D2 28
790 +#define CK_TOP_CB_RTC_32K 29
791 +#define CK_TOP_CB_RTC_32P7K 30
792 +#define CK_TOP_NFI1X 31
793 +#define CK_TOP_USB_EQ_RX250M 32
794 +#define CK_TOP_USB_TX250M 33
795 +#define CK_TOP_USB_LN0_CK 34
796 +#define CK_TOP_USB_CDR_CK 35
797 +#define CK_TOP_SPINFI_BCK 36
798 +#define CK_TOP_I2C_BCK 37
799 +#define CK_TOP_PEXTP_TL 38
800 +#define CK_TOP_EMMC_250M 39
801 +#define CK_TOP_EMMC_416M 40
802 +#define CK_TOP_F_26M_ADC_CK 41
803 +#define CK_TOP_SYSAXI 42
804 +#define CK_TOP_NETSYS_WED_MCU 43
805 +#define CK_TOP_NETSYS_2X 44
806 +#define CK_TOP_SGM_325M 45
807 +#define CK_TOP_A1SYS 46
808 +#define CK_TOP_EIP_B 47
809 +#define CK_TOP_F26M 48
810 +#define CK_TOP_AUD_L 49
811 +#define CK_TOP_A_TUNER 50
812 +#define CK_TOP_U2U3_REF 51
813 +#define CK_TOP_U2U3_SYS 52
814 +#define CK_TOP_U2U3_XHCI 53
815 +#define CK_TOP_AP2CNN_HOST 54
816 +#define CK_TOP_NFI1X_SEL 55
817 +#define CK_TOP_SPINFI_SEL 56
818 +#define CK_TOP_SPI_SEL 57
819 +#define CK_TOP_SPIM_MST_SEL 58
820 +#define CK_TOP_UART_SEL 59
821 +#define CK_TOP_PWM_SEL 60
822 +#define CK_TOP_I2C_SEL 61
823 +#define CK_TOP_PEXTP_TL_SEL 62
824 +#define CK_TOP_EMMC_250M_SEL 63
825 +#define CK_TOP_EMMC_416M_SEL 64
826 +#define CK_TOP_F_26M_ADC_SEL 65
827 +#define CK_TOP_DRAMC_SEL 66
828 +#define CK_TOP_DRAMC_MD32_SEL 67
829 +#define CK_TOP_SYSAXI_SEL 68
830 +#define CK_TOP_SYSAPB_SEL 69
831 +#define CK_TOP_ARM_DB_MAIN_SEL 70
832 +#define CK_TOP_ARM_DB_JTSEL 71
833 +#define CK_TOP_NETSYS_SEL 72
834 +#define CK_TOP_NETSYS_500M_SEL 73
835 +#define CK_TOP_NETSYS_MCU_SEL 74
836 +#define CK_TOP_NETSYS_2X_SEL 75
837 +#define CK_TOP_SGM_325M_SEL 76
838 +#define CK_TOP_SGM_REG_SEL 77
839 +#define CK_TOP_A1SYS_SEL 78
840 +#define CK_TOP_CONN_MCUSYS_SEL 79
841 +#define CK_TOP_EIP_B_SEL 80
842 +#define CK_TOP_PCIE_PHY_SEL 81
843 +#define CK_TOP_USB3_PHY_SEL 82
844 +#define CK_TOP_F26M_SEL 83
845 +#define CK_TOP_AUD_L_SEL 84
846 +#define CK_TOP_A_TUNER_SEL 85
847 +#define CK_TOP_U2U3_SEL 86
848 +#define CK_TOP_U2U3_SYS_SEL 87
849 +#define CK_TOP_U2U3_XHCI_SEL 88
850 +#define CK_TOP_DA_U2_REFSEL 89
851 +#define CK_TOP_DA_U2_CK_1P_SEL 90
852 +#define CK_TOP_AP2CNN_HOST_SEL 91
853 +#define CLK_TOP_NR_CLK 92
854 +
855 +/*
856 + * INFRACFG_AO
857 + * clock muxes need to be append to infracfg domain, and clock gates
858 + * need to be keep in infracgh_ao domain
859 + */
860 +
861 +#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
862 +#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
863 +#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
864 +#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
865 +#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
866 +#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
867 +#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
868 +#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
869 +#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
870 +#define CK_INFRA_GPT_STA 0
871 +#define CK_INFRA_PWM_HCK 1
872 +#define CK_INFRA_PWM_STA 2
873 +#define CK_INFRA_PWM1_CK 3
874 +#define CK_INFRA_PWM2_CK 4
875 +#define CK_INFRA_CQ_DMA_CK 5
876 +#define CK_INFRA_EIP97_CK 6
877 +#define CK_INFRA_AUD_BUS_CK 7
878 +#define CK_INFRA_AUD_26M_CK 8
879 +#define CK_INFRA_AUD_L_CK 9
880 +#define CK_INFRA_AUD_AUD_CK 10
881 +#define CK_INFRA_AUD_EG2_CK 11
882 +#define CK_INFRA_DRAMC_26M_CK 12
883 +#define CK_INFRA_DBG_CK 13
884 +#define CK_INFRA_AP_DMA_CK 14
885 +#define CK_INFRA_SEJ_CK 15
886 +#define CK_INFRA_SEJ_13M_CK 16
887 +#define CK_INFRA_THERM_CK 17
888 +#define CK_INFRA_I2CO_CK 18
889 +#define CK_INFRA_TRNG_CK 19
890 +#define CK_INFRA_UART0_CK 20
891 +#define CK_INFRA_UART1_CK 21
892 +#define CK_INFRA_UART2_CK 22
893 +#define CK_INFRA_NFI1_CK 23
894 +#define CK_INFRA_SPINFI1_CK 24
895 +#define CK_INFRA_NFI_HCK_CK 25
896 +#define CK_INFRA_SPI0_CK 26
897 +#define CK_INFRA_SPI1_CK 27
898 +#define CK_INFRA_SPI0_HCK_CK 28
899 +#define CK_INFRA_SPI1_HCK_CK 29
900 +#define CK_INFRA_FRTC_CK 30
901 +#define CK_INFRA_MSDC_CK 31
902 +#define CK_INFRA_MSDC_HCK_CK 32
903 +#define CK_INFRA_MSDC_133M_CK 33
904 +#define CK_INFRA_MSDC_66M_CK 34
905 +#define CK_INFRA_ADC_26M_CK 35
906 +#define CK_INFRA_ADC_FRC_CK 36
907 +#define CK_INFRA_FBIST2FPC_CK 37
908 +#define CK_INFRA_IUSB_133_CK 38
909 +#define CK_INFRA_IUSB_66M_CK 39
910 +#define CK_INFRA_IUSB_SYS_CK 40
911 +#define CK_INFRA_IUSB_CK 41
912 +#define CK_INFRA_IPCIE_CK 42
913 +#define CK_INFRA_IPCIER_CK 43
914 +#define CK_INFRA_IPCIEB_CK 44
915 +#define CLK_INFRA_AO_NR_CLK 45
916 +
917 +/* APMIXEDSYS */
918 +
919 +#define CK_APMIXED_ARMPLL 0
920 +#define CK_APMIXED_NET2PLL 1
921 +#define CK_APMIXED_MMPLL 2
922 +#define CK_APMIXED_SGMPLL 3
923 +#define CK_APMIXED_WEDMCUPLL 4
924 +#define CK_APMIXED_NET1PLL 5
925 +#define CK_APMIXED_MPLL 6
926 +#define CK_APMIXED_APLL2 7
927 +#define CLK_APMIXED_NR_CLK 8
928 +
929 +/* SGMIISYS_0 */
930 +
931 +#define CK_SGM0_TX_EN 0
932 +#define CK_SGM0_RX_EN 1
933 +#define CK_SGM0_CK0_EN 2
934 +#define CK_SGM0_CDR_CK0_EN 3
935 +#define CLK_SGMII0_NR_CLK 4
936 +
937 +/* SGMIISYS_1 */
938 +
939 +#define CK_SGM1_TX_EN 0
940 +#define CK_SGM1_RX_EN 1
941 +#define CK_SGM1_CK1_EN 2
942 +#define CK_SGM1_CDR_CK1_EN 3
943 +#define CLK_SGMII1_NR_CLK 4
944 +
945 +/* ETHSYS */
946 +
947 +#define CK_ETH_FE_EN 0
948 +#define CK_ETH_GP2_EN 1
949 +#define CK_ETH_GP1_EN 2
950 +#define CK_ETH_WOCPU1_EN 3
951 +#define CK_ETH_WOCPU0_EN 4
952 +#define CLK_ETH_NR_CLK 5
953 +
954 +#endif
955 +
956 +/* _DT_BINDINGS_CLK_MT7986_H */
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