1 From b1b3c3d2ce62872c8dec4a7d645af6b3c565e094 Mon Sep 17 00:00:00 2001
2 From: Sam Shih <sam.shih@mediatek.com>
3 Date: Mon, 20 Apr 2020 17:11:32 +0800
4 Subject: [PATCH 2/3] mt7622 uboot: add dts and config for spi nand
6 This patch add dts and config for mt7622 spi nand
8 Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
10 arch/arm/dts/mt7622-rfb.dts | 6 ++++++
11 arch/arm/dts/mt7622.dtsi | 20 ++++++++++++++++++++
12 2 files changed, 26 insertions(+)
14 --- a/arch/arm/dts/mt7622-rfb.dts
15 +++ b/arch/arm/dts/mt7622-rfb.dts
21 + pinctrl-names = "default";
22 + pinctrl-0 = <&snfi_pins>;
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins>;
29 --- a/arch/arm/dts/mt7622.dtsi
30 +++ b/arch/arm/dts/mt7622.dtsi
35 + nandc: nfi@1100d000 {
36 + compatible = "mediatek,mt7622-nfc";
37 + reg = <0x1100d000 0x1000>,
38 + <0x1100e000 0x1000>;
39 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
40 + <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
41 + clocks = <&pericfg CLK_PERI_NFI_PD>,
42 + <&pericfg CLK_PERI_NFIECC_PD>,
43 + <&pericfg CLK_PERI_SNFI_PD>,
44 + <&topckgen CLK_TOP_NFI_INFRA_SEL>,
45 + <&topckgen CLK_TOP_UNIVPLL2_D8>;
46 + clock-names = "nfi_clk",
50 + "spinfi_parent_50m";
51 + nand-ecc-mode = "hw";
52 + status = "disabled";
56 compatible = "arm,armv8-timer";
57 interrupt-parent = <&gic>;