1 From 884430dadcc2c5d0a2b248795001955a9fa5a1a9 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 19 Jul 2023 17:17:49 +0800
4 Subject: [PATCH 28/29] arm: mediatek: add support for MediaTek MT7988 SoC
6 This patch adds basic support for MediaTek MT7988 SoC.
7 This includes files that will initialize the SoC after boot and
10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
12 arch/arm/dts/mt7988-u-boot.dtsi | 25 ++
13 arch/arm/dts/mt7988.dtsi | 391 ++++++++++++++++++
14 arch/arm/mach-mediatek/Kconfig | 13 +-
15 arch/arm/mach-mediatek/Makefile | 1 +
16 arch/arm/mach-mediatek/mt7988/Makefile | 4 +
17 arch/arm/mach-mediatek/mt7988/init.c | 63 +++
18 arch/arm/mach-mediatek/mt7988/lowlevel_init.S | 30 ++
19 7 files changed, 526 insertions(+), 1 deletion(-)
20 create mode 100644 arch/arm/dts/mt7988-u-boot.dtsi
21 create mode 100644 arch/arm/dts/mt7988.dtsi
22 create mode 100644 arch/arm/mach-mediatek/mt7988/Makefile
23 create mode 100644 arch/arm/mach-mediatek/mt7988/init.c
24 create mode 100644 arch/arm/mach-mediatek/mt7988/lowlevel_init.S
27 +++ b/arch/arm/dts/mt7988-u-boot.dtsi
29 +// SPDX-License-Identifier: GPL-2.0
31 + * Copyright (c) 2022 MediaTek Inc.
32 + * Author: Sam Shih <sam.shih@mediatek.com>
55 +++ b/arch/arm/dts/mt7988.dtsi
57 +// SPDX-License-Identifier: GPL-2.0
59 + * Copyright (c) 2022 MediaTek Inc.
60 + * Author: Sam Shih <sam.shih@mediatek.com>
63 +#include <dt-bindings/interrupt-controller/irq.h>
64 +#include <dt-bindings/interrupt-controller/arm-gic.h>
65 +#include <dt-bindings/clock/mt7988-clk.h>
66 +#include <dt-bindings/reset/mt7988-reset.h>
67 +#include <dt-bindings/gpio/gpio.h>
70 + compatible = "mediatek,mt7988-rfb";
71 + interrupt-parent = <&gic>;
72 + #address-cells = <2>;
76 + #address-cells = <1>;
80 + device_type = "cpu";
81 + compatible = "arm,cortex-a73";
83 + mediatek,hwver = <&hwver>;
87 + device_type = "cpu";
88 + compatible = "arm,cortex-a73";
90 + mediatek,hwver = <&hwver>;
94 + device_type = "cpu";
95 + compatible = "arm,cortex-a73";
97 + mediatek,hwver = <&hwver>;
101 + device_type = "cpu";
102 + compatible = "arm,cortex-a73";
104 + mediatek,hwver = <&hwver>;
108 + system_clk: dummy40m {
109 + compatible = "fixed-clock";
110 + clock-frequency = <40000000>;
111 + #clock-cells = <0>;
114 + spi_clk: dummy208m {
115 + compatible = "fixed-clock";
116 + clock-frequency = <208000000>;
117 + #clock-cells = <0>;
121 + compatible = "mediatek,hwver", "syscon";
122 + reg = <0 0x8000000 0 0x1000>;
126 + compatible = "arm,armv8-timer";
127 + interrupt-parent = <&gic>;
128 + clock-frequency = <13000000>;
129 + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
130 + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
131 + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
132 + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
135 + watchdog: watchdog@1001c000 {
136 + compatible = "mediatek,mt7622-wdt",
137 + "mediatek,mt6589-wdt",
139 + reg = <0 0x1001c000 0 0x1000>;
140 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
141 + #reset-cells = <1>;
144 + gic: interrupt-controller@c000000 {
145 + compatible = "arm,gic-v3";
146 + #interrupt-cells = <3>;
147 + interrupt-parent = <&gic>;
148 + interrupt-controller;
149 + reg = <0 0x0c000000 0 0x40000>, /* GICD */
150 + <0 0x0c080000 0 0x200000>; /* GICR */
151 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
154 + infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
155 + compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
156 + reg = <0 0x10001000 0 0x1000>;
157 + clock-parent = <&infracfg_ao>;
158 + #clock-cells = <1>;
161 + apmixedsys: apmixedsys@1001e000 {
162 + compatible = "mediatek,mt7988-fixed-plls", "syscon";
163 + reg = <0 0x1001e000 0 0x1000>;
164 + #clock-cells = <1>;
167 + topckgen: topckgen@1001b000 {
168 + compatible = "mediatek,mt7988-topckgen", "syscon";
169 + reg = <0 0x1001b000 0 0x1000>;
170 + clock-parent = <&apmixedsys>;
171 + #clock-cells = <1>;
174 + pinctrl: pinctrl@1001f000 {
175 + compatible = "mediatek,mt7988-pinctrl";
176 + reg = <0 0x1001f000 0 0x1000>,
177 + <0 0x11c10000 0 0x1000>,
178 + <0 0x11d00000 0 0x1000>,
179 + <0 0x11d20000 0 0x1000>,
180 + <0 0x11e00000 0 0x1000>,
181 + <0 0x11f00000 0 0x1000>,
182 + <0 0x1000b000 0 0x1000>;
183 + reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
184 + "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
186 + gpio: gpio-controller {
192 + sgmiisys0: syscon@10060000 {
193 + compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
194 + reg = <0 0x10060000 0 0x1000>;
195 + clock-parent = <&topckgen>;
196 + #clock-cells = <1>;
199 + sgmiisys1: syscon@10070000 {
200 + compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
201 + reg = <0 0x10070000 0 0x1000>;
202 + clock-parent = <&topckgen>;
203 + #clock-cells = <1>;
206 + usxgmiisys0: syscon@10080000 {
207 + compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
208 + reg = <0 0x10080000 0 0x1000>;
209 + clock-parent = <&topckgen>;
210 + #clock-cells = <1>;
213 + usxgmiisys1: syscon@10081000 {
214 + compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
215 + reg = <0 0x10081000 0 0x1000>;
216 + clock-parent = <&topckgen>;
217 + #clock-cells = <1>;
220 + xfi_pextp0: syscon@11f20000 {
221 + compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
222 + reg = <0 0x11f20000 0 0x10000>;
223 + clock-parent = <&topckgen>;
224 + #clock-cells = <1>;
227 + xfi_pextp1: syscon@11f30000 {
228 + compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
229 + reg = <0 0x11f30000 0 0x10000>;
230 + clock-parent = <&topckgen>;
231 + #clock-cells = <1>;
234 + xfi_pll: syscon@11f40000 {
235 + compatible = "mediatek,mt7988-xfi_pll", "syscon";
236 + reg = <0 0x11f40000 0 0x1000>;
237 + clock-parent = <&topckgen>;
238 + #clock-cells = <1>;
241 + topmisc: topmisc@11d10000 {
242 + compatible = "mediatek,mt7988-topmisc", "syscon",
243 + "mediatek,mt7988-power-controller";
244 + reg = <0 0x11d10000 0 0x10000>;
245 + clock-parent = <&topckgen>;
246 + #clock-cells = <1>;
249 + infracfg_ao: infracfg@10001000 {
250 + compatible = "mediatek,mt7988-infracfg", "syscon";
251 + reg = <0 0x10001000 0 0x1000>;
252 + clock-parent = <&topckgen>;
253 + #clock-cells = <1>;
256 + uart0: serial@11000000 {
257 + compatible = "mediatek,hsuart";
258 + reg = <0 0x11000000 0 0x100>;
259 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
260 + clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
261 + assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
262 + <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
263 + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
264 + <&infracfg_ao CK_INFRA_UART_O0>;
265 + status = "disabled";
268 + uart1: serial@11000100 {
269 + compatible = "mediatek,hsuart";
270 + reg = <0 0x11000100 0 0x100>;
271 + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
272 + clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
273 + assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
274 + <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
275 + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
276 + <&infracfg_ao CK_INFRA_UART_O1>;
277 + status = "disabled";
280 + uart2: serial@11000200 {
281 + compatible = "mediatek,hsuart";
282 + reg = <0 0x11000200 0 0x100>;
283 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
284 + clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
285 + assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
286 + <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
287 + assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
288 + <&infracfg_ao CK_INFRA_UART_O2>;
289 + status = "disabled";
292 + i2c0: i2c@11003000 {
293 + compatible = "mediatek,mt7988-i2c",
294 + "mediatek,mt7981-i2c";
295 + reg = <0 0x11003000 0 0x1000>,
296 + <0 0x10217080 0 0x80>;
297 + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
299 + clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
300 + <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
301 + clock-names = "main", "dma";
302 + #address-cells = <1>;
304 + status = "disabled";
307 + i2c1: i2c@11004000 {
308 + compatible = "mediatek,mt7988-i2c",
309 + "mediatek,mt7981-i2c";
310 + reg = <0 0x11004000 0 0x1000>,
311 + <0 0x10217100 0 0x80>;
312 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
314 + clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
315 + <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
316 + clock-names = "main", "dma";
317 + #address-cells = <1>;
319 + status = "disabled";
322 + i2c2: i2c@11005000 {
323 + compatible = "mediatek,mt7988-i2c",
324 + "mediatek,mt7981-i2c";
325 + reg = <0 0x11005000 0 0x1000>,
326 + <0 0x10217180 0 0x80>;
327 + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
329 + clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
330 + <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
331 + clock-names = "main", "dma";
332 + #address-cells = <1>;
334 + status = "disabled";
337 + pwm: pwm@10048000 {
338 + compatible = "mediatek,mt7988-pwm";
339 + reg = <0 0x10048000 0 0x1000>;
341 + clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
342 + <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
343 + <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
344 + <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
345 + <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
346 + <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
347 + <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
348 + <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
349 + <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
350 + <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
351 + clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
352 + "pwm4","pwm5","pwm6","pwm7","pwm8";
353 + status = "disabled";
356 + snand: snand@11001000 {
357 + compatible = "mediatek,mt7988-snand",
358 + "mediatek,mt7986-snand";
359 + reg = <0 0x11001000 0 0x1000>,
360 + <0 0x11002000 0 0x1000>;
361 + reg-names = "nfi", "ecc";
362 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
363 + clocks = <&infracfg_ao CK_INFRA_SPINFI>,
364 + <&infracfg_ao CK_INFRA_NFI>,
365 + <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
366 + clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
367 + assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
368 + <&topckgen CK_TOP_NFI1X_SEL>;
369 + assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
370 + <&topckgen CK_TOP_CB_M_D8>;
371 + status = "disabled";
374 + spi0: spi@1100a000 {
375 + compatible = "mediatek,ipm-spi";
376 + reg = <0 0x11007000 0 0x100>;
377 + clocks = <&spi_clk>,
379 + clock-names = "sel-clk", "spi-clk";
380 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
381 + status = "disabled";
384 + spi1: spi@1100b000 {
385 + compatible = "mediatek,ipm-spi";
386 + reg = <0 0x11008000 0 0x100>;
387 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
388 + status = "disabled";
391 + spi2: spi@11009000 {
392 + compatible = "mediatek,ipm-spi";
393 + reg = <0 0x11009000 0 0x100>;
394 + clocks = <&spi_clk>,
396 + clock-names = "sel-clk", "spi-clk";
397 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
398 + status = "disabled";
401 + mmc0: mmc@11230000 {
402 + compatible = "mediatek,mt7988-mmc",
403 + "mediatek,mt7986-mmc";
404 + reg = <0 0x11230000 0 0x1000>;
405 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
406 + clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
407 + <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
408 + <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
409 + <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
410 + clock-names = "source", "hclk", "source_cg", "axi_cg";
411 + status = "disabled";
414 + ethdma: syscon@15000000 {
415 + compatible = "mediatek,mt7988-ethdma", "syscon";
416 + reg = <0 0x15000000 0 0x20000>;
417 + clock-parent = <&topckgen>;
418 + #clock-cells = <1>;
419 + #reset-cells = <1>;
422 + ethwarp: syscon@15031000 {
423 + compatible = "mediatek,mt7988-ethwarp", "syscon";
424 + reg = <0 0x15031000 0 0x1000>;
425 + clock-parent = <&topckgen>;
426 + #clock-cells = <1>;
427 + #reset-cells = <1>;
430 + eth: ethernet@15100000 {
431 + compatible = "mediatek,mt7988-eth", "syscon";
432 + reg = <0 0x15100000 0 0x20000>;
433 + mediatek,ethsys = <ðdma>;
434 + mediatek,sgmiisys = <&sgmiisys0>;
435 + mediatek,usxgmiisys = <&usxgmiisys0>;
436 + mediatek,xfi_pextp = <&xfi_pextp0>;
437 + mediatek,xfi_pll = <&xfi_pll>;
438 + mediatek,infracfg = <&topmisc>;
439 + mediatek,toprgu = <&watchdog>;
440 + resets = <ðdma ETHDMA_FE_RST>, <ðwarp ETHWARP_GSW_RST>;
441 + reset-names = "fe", "mcm";
442 + #address-cells = <1>;
445 + status = "disabled";
448 --- a/arch/arm/mach-mediatek/Kconfig
449 +++ b/arch/arm/mach-mediatek/Kconfig
450 @@ -58,6 +58,15 @@ config TARGET_MT7986
451 including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
452 Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe.
454 +config TARGET_MT7988
455 + bool "MediaTek MT7988 SoC"
459 + The MediaTek MT7988 is a ARM64-based SoC with a quad-core Cortex-A73.
460 + including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe,
461 + 10 Gigabit Ethernet , I2C, and PCIe.
464 bool "MediaTek MT8183 SoC"
466 @@ -104,6 +113,7 @@ config SYS_BOARD
467 default "mt7629" if TARGET_MT7629
468 default "mt7981" if TARGET_MT7981
469 default "mt7986" if TARGET_MT7986
470 + default "mt7988" if TARGET_MT7988
471 default "mt8183" if TARGET_MT8183
472 default "mt8512" if TARGET_MT8512
473 default "mt8516" if TARGET_MT8516
474 @@ -121,6 +131,7 @@ config SYS_CONFIG_NAME
475 default "mt7629" if TARGET_MT7629
476 default "mt7981" if TARGET_MT7981
477 default "mt7986" if TARGET_MT7986
478 + default "mt7988" if TARGET_MT7988
479 default "mt8183" if TARGET_MT8183
480 default "mt8512" if TARGET_MT8512
481 default "mt8516" if TARGET_MT8516
482 @@ -135,7 +146,7 @@ config MTK_BROM_HEADER_INFO
484 default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622
485 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
486 - default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
487 + default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988
488 default "lk=1" if TARGET_MT7623
490 source "board/mediatek/mt7629/Kconfig"
491 --- a/arch/arm/mach-mediatek/Makefile
492 +++ b/arch/arm/mach-mediatek/Makefile
493 @@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/
494 obj-$(CONFIG_TARGET_MT7629) += mt7629/
495 obj-$(CONFIG_TARGET_MT7981) += mt7981/
496 obj-$(CONFIG_TARGET_MT7986) += mt7986/
497 +obj-$(CONFIG_TARGET_MT7988) += mt7988/
498 obj-$(CONFIG_TARGET_MT8183) += mt8183/
499 obj-$(CONFIG_TARGET_MT8516) += mt8516/
500 obj-$(CONFIG_TARGET_MT8518) += mt8518/
502 +++ b/arch/arm/mach-mediatek/mt7988/Makefile
504 +# SPDX-License-Identifier: GPL-2.0
507 +obj-y += lowlevel_init.o
509 +++ b/arch/arm/mach-mediatek/mt7988/init.c
511 +// SPDX-License-Identifier: GPL-2.0
513 + * Copyright (C) 2022 MediaTek Inc.
514 + * Author: Sam Shih <sam.shih@mediatek.com>
519 +#include <asm/armv8/mmu.h>
520 +#include <asm/global_data.h>
521 +#include <asm/u-boot.h>
522 +#include <asm/system.h>
524 +DECLARE_GLOBAL_DATA_PTR;
526 +#define SZ_8G _AC(0x200000000, ULL)
532 + ret = fdtdec_setup_mem_size_base();
536 + gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
541 +int dram_init_banksize(void)
543 + gd->bd->bi_dram[0].start = gd->ram_base;
544 + gd->bd->bi_dram[0].size = gd->ram_size;
549 +void reset_cpu(ulong addr)
551 + psci_system_reset();
554 +static struct mm_region mt7988_mem_map[] = {
557 + .virt = 0x40000000UL,
558 + .phys = 0x40000000UL,
559 + .size = 0x200000000ULL,
560 + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
562 + .virt = 0x00000000UL,
563 + .phys = 0x00000000UL,
564 + .size = 0x40000000UL,
565 + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
566 + PTE_BLOCK_NON_SHARE |
567 + PTE_BLOCK_PXN | PTE_BLOCK_UXN
573 +struct mm_region *mem_map = mt7988_mem_map;
575 +++ b/arch/arm/mach-mediatek/mt7988/lowlevel_init.S
577 +/* SPDX-License-Identifier: GPL-2.0 */
579 + * Copyright (C) 2020 MediaTek Inc.
580 + * Author: Sam Shih <sam.shih@mediatek.com>
584 + * Switch from AArch64 EL2 to AArch32 EL2
586 + * x0: argument, zero
589 + * x3: input argument
590 + * x4: kernel entry point
591 + * @param outputs for secure firmware:
593 + * x1: kernel entry point
598 +.global armv8_el2_to_aarch32
599 +armv8_el2_to_aarch32:
604 + ldr x0, =0x82000200