1 From 67f4c228c2bf515386cd54073104dc2e6eae85ea Mon Sep 17 00:00:00 2001
2 From: David Bauer <mail@david-bauer.net>
3 Date: Fri, 10 Jul 2020 14:58:30 +0200
4 Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
6 This adds support for the NanoPi R2S from FriendlyArm.
10 Gigabit Ethernet (WAN)
11 Gigabit Ethernet (USB3) (LAN)
17 Signed-off-by: David Bauer <mail@david-bauer.net>
19 arch/arm/dts/Makefile | 1 +
20 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 34 +++
21 arch/arm/dts/rk3328-nanopi-r2s.dts | 334 +++++++++++++++++++++
22 board/rockchip/evb_rk3328/MAINTAINERS | 7 +
23 configs/nanopi-r2s-rk3328_defconfig | 99 ++++++
24 5 files changed, 475 insertions(+)
25 create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
26 create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts
27 create mode 100644 configs/nanopi-r2s-rk3328_defconfig
29 --- a/arch/arm/dts/Makefile
30 +++ b/arch/arm/dts/Makefile
31 @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
33 dtb-$(CONFIG_ROCKCHIP_RK3328) += \
35 + rk3328-nanopi-r2s.dtb \
40 +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
42 +// SPDX-License-Identifier: GPL-2.0+
44 + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
45 + * (C) Copyright 2020 David Bauer
48 +#include "rk3328-u-boot.dtsi"
49 +#include "rk3328-sdram-ddr4-666.dtsi"
52 + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
72 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
77 +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
79 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
81 + * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
86 +#include <dt-bindings/input/input.h>
87 +#include <dt-bindings/gpio/gpio.h>
88 +#include "rk3328.dtsi"
91 + model = "FriendlyARM NanoPi R2S";
92 + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
95 + stdout-path = "serial2:1500000n8";
98 + gmac_clkin: external-gmac-clock {
99 + compatible = "fixed-clock";
100 + clock-frequency = <125000000>;
101 + clock-output-names = "gmac_clkin";
102 + #clock-cells = <0>;
105 + vcc_sd: sdmmc-regulator {
106 + compatible = "regulator-fixed";
107 + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
108 + pinctrl-names = "default";
109 + pinctrl-0 = <&sdmmc0m1_gpio>;
110 + regulator-name = "vcc_sd";
111 + regulator-min-microvolt = <3300000>;
112 + regulator-max-microvolt = <3300000>;
113 + vin-supply = <&vcc_io>;
116 + vcc_sdio: sdmmcio-regulator {
117 + compatible = "regulator-gpio";
118 + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
119 + enable-active-high;
120 + states = <1800000 0x1
122 + pinctrl-names = "default";
123 + pinctrl-0 = <&sdio_vcc_pin>;
124 + regulator-always-on;
125 + regulator-min-microvolt = <1800000>;
126 + regulator-max-microvolt = <3300000>;
127 + regulator-name = "vcc_sdio";
128 + regulator-settling-time-us = <5000>;
129 + regulator-type = "voltage";
130 + vin-supply = <&vcc_io>;
134 + compatible = "regulator-fixed";
135 + regulator-name = "vcc_sys";
136 + regulator-always-on;
138 + regulator-min-microvolt = <5000000>;
139 + regulator-max-microvolt = <5000000>;
143 + compatible = "gpio-leds";
145 + pinctrl-names = "default";
146 + pinctrl-0 = <&led_pins>;
149 + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
150 + label = "nanopi-r2s:red:sys";
154 + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
155 + label = "nanopi-r2s:green:lan";
159 + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
160 + label = "nanopi-r2s:green:wan";
165 + compatible = "gpio-keys-polled";
166 + poll-interval = <100>;
168 + pinctrl-names = "default";
169 + pinctrl-0 = <&button_pins>;
172 + label = "Reset Button";
173 + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
174 + linux,code = <KEY_RESTART>;
175 + debounce-interval = <50>;
181 + cpu-supply = <&vdd_arm>;
185 + cpu-supply = <&vdd_arm>;
189 + cpu-supply = <&vdd_arm>;
193 + cpu-supply = <&vdd_arm>;
197 + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
198 + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
199 + clock_in_out = "input";
200 + phy-supply = <&vcc_io>;
201 + phy-handle = <&rtl8211e>;
202 + phy-mode = "rgmii";
203 + pinctrl-names = "default";
204 + pinctrl-0 = <&rgmiim1_pins>;
206 + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
207 + snps,reset-active-low;
208 + snps,reset-delays-us = <0 10000 50000>;
214 + compatible = "snps,dwmac-mdio";
215 + #address-cells = <1>;
218 + rtl8211e: ethernet-phy@0 {
228 + compatible = "rockchip,rk805";
230 + interrupt-parent = <&gpio2>;
231 + interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
232 + #clock-cells = <1>;
233 + clock-output-names = "xin32k", "rk805-clkout2";
236 + pinctrl-names = "default";
237 + pinctrl-0 = <&pmic_int_l>;
238 + rockchip,system-power-controller;
241 + vcc1-supply = <&vcc_sys>;
242 + vcc2-supply = <&vcc_sys>;
243 + vcc3-supply = <&vcc_sys>;
244 + vcc4-supply = <&vcc_sys>;
245 + vcc5-supply = <&vcc_io>;
246 + vcc6-supply = <&vcc_sys>;
249 + vdd_logic: DCDC_REG1 {
250 + regulator-name = "vdd_logic";
251 + regulator-min-microvolt = <712500>;
252 + regulator-max-microvolt = <1450000>;
253 + regulator-ramp-delay = <12500>;
254 + regulator-always-on;
256 + regulator-state-mem {
257 + regulator-on-in-suspend;
258 + regulator-suspend-microvolt = <1000000>;
262 + vdd_arm: DCDC_REG2 {
263 + regulator-name = "vdd_arm";
264 + regulator-min-microvolt = <712500>;
265 + regulator-max-microvolt = <1450000>;
266 + regulator-ramp-delay = <12500>;
267 + regulator-always-on;
269 + regulator-state-mem {
270 + regulator-on-in-suspend;
271 + regulator-suspend-microvolt = <950000>;
275 + vcc_ddr: DCDC_REG3 {
276 + regulator-name = "vcc_ddr";
277 + regulator-always-on;
279 + regulator-state-mem {
280 + regulator-on-in-suspend;
284 + vcc_io: DCDC_REG4 {
285 + regulator-name = "vcc_io";
286 + regulator-min-microvolt = <3300000>;
287 + regulator-max-microvolt = <3300000>;
288 + regulator-always-on;
290 + regulator-state-mem {
291 + regulator-on-in-suspend;
292 + regulator-suspend-microvolt = <3300000>;
297 + regulator-name = "vcc_18";
298 + regulator-min-microvolt = <1800000>;
299 + regulator-max-microvolt = <1800000>;
300 + regulator-always-on;
302 + regulator-state-mem {
303 + regulator-on-in-suspend;
304 + regulator-suspend-microvolt = <1800000>;
308 + vcc18_emmc: LDO_REG2 {
309 + regulator-name = "vcc18_emmc";
310 + regulator-min-microvolt = <1800000>;
311 + regulator-max-microvolt = <1800000>;
312 + regulator-always-on;
314 + regulator-state-mem {
315 + regulator-on-in-suspend;
316 + regulator-suspend-microvolt = <1800000>;
321 + regulator-name = "vdd_10";
322 + regulator-min-microvolt = <1000000>;
323 + regulator-max-microvolt = <1000000>;
324 + regulator-always-on;
326 + regulator-state-mem {
327 + regulator-on-in-suspend;
328 + regulator-suspend-microvolt = <1000000>;
338 + vccio1-supply = <&vcc_io>;
339 + vccio2-supply = <&vcc18_emmc>;
340 + vccio3-supply = <&vcc_sdio>;
341 + vccio4-supply = <&vcc_18>;
342 + vccio5-supply = <&vcc_io>;
343 + vccio6-supply = <&vcc_io>;
344 + pmuio-supply = <&vcc_io>;
349 + led_pins: led-pins {
350 + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
351 + <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
352 + <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
357 + button_pins: button-pins {
358 + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
363 + pmic_int_l: pmic-int-l {
364 + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
369 + sdio_vcc_pin: sdio-vcc-pin {
370 + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
380 + max-frequency = <150000000>;
381 + pinctrl-names = "default";
382 + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
383 + vmmc-supply = <&vcc_sd>;
384 + vqmmc-supply = <&vcc_sdio>;
389 + rockchip,hw-tshut-mode = <0>;
390 + rockchip,hw-tshut-polarity = <0>;
401 + u2phy_host: host-port {
413 --- a/board/rockchip/evb_rk3328/MAINTAINERS
414 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
415 @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328
416 F: include/configs/evb_rk3328.h
417 F: configs/evb-rk3328_defconfig
420 +M: David Bauer <mail@david-bauer.net>
422 +F: configs/nanopi-r2s-rk3328_defconfig
423 +F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
424 +F: arch/arm/dts/rk3328-nanopi-r2s.dts
427 M: Loic Devulder <ldevulder@suse.com>
428 M: Chen-Yu Tsai <wens@csie.org>
430 +++ b/configs/nanopi-r2s-rk3328_defconfig
433 +CONFIG_ARCH_ROCKCHIP=y
434 +CONFIG_SYS_TEXT_BASE=0x00200000
435 +CONFIG_SPL_GPIO_SUPPORT=y
436 +CONFIG_ENV_OFFSET=0x3F8000
437 +CONFIG_ROCKCHIP_RK3328=y
438 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
439 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
440 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
441 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
442 +CONFIG_SPL_STACK_R_ADDR=0x600000
443 +CONFIG_NR_DRAM_BANKS=1
444 +CONFIG_DEBUG_UART_BASE=0xFF130000
445 +CONFIG_DEBUG_UART_CLOCK=24000000
446 +CONFIG_SMBIOS_PRODUCT_NAME="nanopi_r2s_rk3328"
448 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
449 +# CONFIG_ANDROID_BOOT_IMAGE is not set
451 +CONFIG_FIT_VERBOSE=y
452 +CONFIG_SPL_LOAD_FIT=y
453 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
454 +CONFIG_MISC_INIT_R=y
455 +# CONFIG_DISPLAY_CPUINFO is not set
456 +CONFIG_DISPLAY_BOARDINFO_LATE=y
457 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
458 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
459 +CONFIG_SPL_STACK_R=y
460 +CONFIG_SPL_I2C_SUPPORT=y
461 +CONFIG_SPL_POWER_SUPPORT=y
463 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
468 +# CONFIG_CMD_SETEXPR is not set
470 +CONFIG_SPL_OF_CONTROL=y
471 +CONFIG_TPL_OF_CONTROL=y
472 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
473 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
474 +CONFIG_TPL_OF_PLATDATA=y
475 +CONFIG_ENV_IS_IN_MMC=y
476 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
477 +CONFIG_NET_RANDOM_ETHADDR=y
487 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
488 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
489 +CONFIG_ROCKCHIP_GPIO=y
490 +CONFIG_SYS_I2C_ROCKCHIP=y
492 +CONFIG_MMC_DW_ROCKCHIP=y
493 +CONFIG_SF_DEFAULT_SPEED=20000000
495 +CONFIG_ETH_DESIGNWARE=y
496 +CONFIG_GMAC_ROCKCHIP=y
498 +CONFIG_SPL_PINCTRL=y
501 +CONFIG_SPL_DM_REGULATOR=y
502 +CONFIG_REGULATOR_PWM=y
503 +CONFIG_DM_REGULATOR_FIXED=y
504 +CONFIG_SPL_DM_REGULATOR_FIXED=y
505 +CONFIG_REGULATOR_RK8XX=y
506 +CONFIG_PWM_ROCKCHIP=y
511 +CONFIG_BAUDRATE=1500000
512 +CONFIG_DEBUG_UART_SHIFT=2
514 +# CONFIG_TPL_SYSRESET is not set
516 +CONFIG_USB_XHCI_HCD=y
517 +CONFIG_USB_XHCI_DWC3=y
518 +CONFIG_USB_EHCI_HCD=y
519 +CONFIG_USB_EHCI_GENERIC=y
520 +CONFIG_USB_OHCI_HCD=y
521 +CONFIG_USB_OHCI_GENERIC=y
524 +# CONFIG_USB_DWC3_GADGET is not set
526 +CONFIG_USB_GADGET_DWC2_OTG=y
527 +CONFIG_SPL_TINY_MEMSET=y
528 +CONFIG_TPL_TINY_MEMSET=y
530 +CONFIG_SMBIOS_MANUFACTURER="pine64"