package/boot/uboot-rockchip/patches/103-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch

   1 From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001
   2 From: Tianling Shen <cnsztl@gmail.com>
   3 Date: Sat, 20 May 2023 18:50:38 +0800
   4 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus
   5
   6 Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
   7
   8 This device is similar to the NanoPi R2S, and has a 16MB
   9 SPI NOR (mx25l12805d). The reset button is changed to
  10 directly reset the power supply, another detail is that
  11 both network ports have independent MAC addresses.
  12
  13 The device tree and description are taken from kernel v6.3-rc1.
  14
  15 Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
  16 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  17 ---
  18  arch/arm/dts/Makefile                         |   1 +
  19  .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi   |  46 +++
  20  arch/arm/dts/rk3328-orangepi-r1-plus.dts      | 373 ++++++++++++++++++
  21  board/rockchip/evb_rk3328/MAINTAINERS         |   6 +
  22  configs/orangepi-r1-plus-rk3328_defconfig     | 114 ++++++
  23  5 files changed, 540 insertions(+)
  24  create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
  25  create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts
  26  create mode 100644 configs/orangepi-r1-plus-rk3328_defconfig
  27
  28 --- a/arch/arm/dts/Makefile
  29 +++ b/arch/arm/dts/Makefile
  30 @@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  31         rk3328-evb.dtb \
  32         rk3328-nanopi-r2c.dtb \
  33         rk3328-nanopi-r2s.dtb \
  34 +       rk3328-orangepi-r1-plus.dtb \
  35         rk3328-roc-cc.dtb \
  36         rk3328-rock64.dtb \
  37         rk3328-rock-pi-e.dtb
  38 --- /dev/null
  39 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
  40 @@ -0,0 +1,46 @@
  41 +// SPDX-License-Identifier: GPL-2.0-or-later
  42 +/*
  43 + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
  44 + * (C) Copyright 2020 David Bauer
  45 + */
  46 +
  47 +#include "rk3328-u-boot.dtsi"
  48 +#include "rk3328-sdram-ddr4-666.dtsi"
  49 +/ {
  50 +       chosen {
  51 +               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
  52 +       };
  53 +};
  54 +
  55 +&gpio0 {
  56 +       u-boot,dm-spl;
  57 +};
  58 +
  59 +&pinctrl {
  60 +       u-boot,dm-spl;
  61 +};
  62 +
  63 +&sdmmc0m1_gpio {
  64 +       u-boot,dm-spl;
  65 +};
  66 +
  67 +&pcfg_pull_up_4ma {
  68 +       u-boot,dm-spl;
  69 +};
  70 +
  71 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
  72 +&vcc_sd {
  73 +       u-boot,dm-spl;
  74 +};
  75 +
  76 +&gmac2io {
  77 +       snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  78 +       snps,reset-active-low;
  79 +       snps,reset-delays-us = <0 10000 50000>;
  80 +};
  81 +
  82 +&spi0 {
  83 +       spi_flash: spiflash@0 {
  84 +               u-boot,dm-pre-reloc;
  85 +       };
  86 +};
  87 --- /dev/null
  88 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
  89 @@ -0,0 +1,359 @@
  90 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  91 +/*
  92 + * Based on rk3328-nanopi-r2s.dts, which is:
  93 + *   Copyright (c) 2020 David Bauer <mail@david-bauer.net>
  94 + */
  95 +
  96 +/dts-v1/;
  97 +
  98 +#include <dt-bindings/gpio/gpio.h>
  99 +#include <dt-bindings/leds/common.h>
 100 +#include "rk3328.dtsi"
 101 +
 102 +/ {
 103 +       model = "Xunlong Orange Pi R1 Plus";
 104 +       compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
 105 +
 106 +       aliases {
 107 +               mmc0 = &sdmmc;
 108 +       };
 109 +
 110 +       chosen {
 111 +               stdout-path = "serial2:1500000n8";
 112 +       };
 113 +
 114 +       gmac_clk: gmac-clock {
 115 +               compatible = "fixed-clock";
 116 +               clock-frequency = <125000000>;
 117 +               clock-output-names = "gmac_clkin";
 118 +               #clock-cells = <0>;
 119 +       };
 120 +
 121 +       leds {
 122 +               compatible = "gpio-leds";
 123 +               pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
 124 +               pinctrl-names = "default";
 125 +
 126 +               led-0 {
 127 +                       function = LED_FUNCTION_LAN;
 128 +                       color = <LED_COLOR_ID_GREEN>;
 129 +                       gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
 130 +               };
 131 +
 132 +               led-1 {
 133 +                       function = LED_FUNCTION_STATUS;
 134 +                       color = <LED_COLOR_ID_RED>;
 135 +                       gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
 136 +                       linux,default-trigger = "heartbeat";
 137 +               };
 138 +
 139 +               led-2 {
 140 +                       function = LED_FUNCTION_WAN;
 141 +                       color = <LED_COLOR_ID_GREEN>;
 142 +                       gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
 143 +               };
 144 +       };
 145 +
 146 +       vcc_sd: sdmmc-regulator {
 147 +               compatible = "regulator-fixed";
 148 +               gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
 149 +               pinctrl-0 = <&sdmmc0m1_gpio>;
 150 +               pinctrl-names = "default";
 151 +               regulator-name = "vcc_sd";
 152 +               regulator-boot-on;
 153 +               vin-supply = <&vcc_io>;
 154 +       };
 155 +
 156 +       vcc_sys: vcc-sys-regulator {
 157 +               compatible = "regulator-fixed";
 158 +               regulator-name = "vcc_sys";
 159 +               regulator-always-on;
 160 +               regulator-boot-on;
 161 +               regulator-min-microvolt = <5000000>;
 162 +               regulator-max-microvolt = <5000000>;
 163 +       };
 164 +
 165 +       vdd_5v_lan: vdd-5v-lan-regulator {
 166 +               compatible = "regulator-fixed";
 167 +               enable-active-high;
 168 +               gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
 169 +               pinctrl-0 = <&lan_vdd_pin>;
 170 +               pinctrl-names = "default";
 171 +               regulator-name = "vdd_5v_lan";
 172 +               regulator-always-on;
 173 +               regulator-boot-on;
 174 +               vin-supply = <&vcc_sys>;
 175 +       };
 176 +};
 177 +
 178 +&cpu0 {
 179 +       cpu-supply = <&vdd_arm>;
 180 +};
 181 +
 182 +&cpu1 {
 183 +       cpu-supply = <&vdd_arm>;
 184 +};
 185 +
 186 +&cpu2 {
 187 +       cpu-supply = <&vdd_arm>;
 188 +};
 189 +
 190 +&cpu3 {
 191 +       cpu-supply = <&vdd_arm>;
 192 +};
 193 +
 194 +&display_subsystem {
 195 +       status = "disabled";
 196 +};
 197 +
 198 +&gmac2io {
 199 +       assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
 200 +       assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
 201 +       clock_in_out = "input";
 202 +       phy-handle = <&rtl8211e>;
 203 +       phy-mode = "rgmii";
 204 +       phy-supply = <&vcc_io>;
 205 +       pinctrl-0 = <&rgmiim1_pins>;
 206 +       pinctrl-names = "default";
 207 +       snps,aal;
 208 +       rx_delay = <0x18>;
 209 +       tx_delay = <0x24>;
 210 +       status = "okay";
 211 +
 212 +       mdio {
 213 +               compatible = "snps,dwmac-mdio";
 214 +               #address-cells = <1>;
 215 +               #size-cells = <0>;
 216 +
 217 +               rtl8211e: ethernet-phy@1 {
 218 +                       reg = <1>;
 219 +                       pinctrl-0 = <&eth_phy_reset_pin>;
 220 +                       pinctrl-names = "default";
 221 +                       reset-assert-us = <10000>;
 222 +                       reset-deassert-us = <50000>;
 223 +                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
 224 +               };
 225 +       };
 226 +};
 227 +
 228 +&i2c1 {
 229 +       status = "okay";
 230 +
 231 +       rk805: pmic@18 {
 232 +               compatible = "rockchip,rk805";
 233 +               reg = <0x18>;
 234 +               interrupt-parent = <&gpio1>;
 235 +               interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
 236 +               #clock-cells = <1>;
 237 +               clock-output-names = "xin32k", "rk805-clkout2";
 238 +               gpio-controller;
 239 +               #gpio-cells = <2>;
 240 +               pinctrl-0 = <&pmic_int_l>;
 241 +               pinctrl-names = "default";
 242 +               rockchip,system-power-controller;
 243 +               wakeup-source;
 244 +
 245 +               vcc1-supply = <&vcc_sys>;
 246 +               vcc2-supply = <&vcc_sys>;
 247 +               vcc3-supply = <&vcc_sys>;
 248 +               vcc4-supply = <&vcc_sys>;
 249 +               vcc5-supply = <&vcc_io>;
 250 +               vcc6-supply = <&vcc_sys>;
 251 +
 252 +               regulators {
 253 +                       vdd_log: DCDC_REG1 {
 254 +                               regulator-name = "vdd_log";
 255 +                               regulator-always-on;
 256 +                               regulator-boot-on;
 257 +                               regulator-min-microvolt = <712500>;
 258 +                               regulator-max-microvolt = <1450000>;
 259 +                               regulator-ramp-delay = <12500>;
 260 +
 261 +                               regulator-state-mem {
 262 +                                       regulator-on-in-suspend;
 263 +                                       regulator-suspend-microvolt = <1000000>;
 264 +                               };
 265 +                       };
 266 +
 267 +                       vdd_arm: DCDC_REG2 {
 268 +                               regulator-name = "vdd_arm";
 269 +                               regulator-always-on;
 270 +                               regulator-boot-on;
 271 +                               regulator-min-microvolt = <712500>;
 272 +                               regulator-max-microvolt = <1450000>;
 273 +                               regulator-ramp-delay = <12500>;
 274 +
 275 +                               regulator-state-mem {
 276 +                                       regulator-on-in-suspend;
 277 +                                       regulator-suspend-microvolt = <950000>;
 278 +                               };
 279 +                       };
 280 +
 281 +                       vcc_ddr: DCDC_REG3 {
 282 +                               regulator-name = "vcc_ddr";
 283 +                               regulator-always-on;
 284 +                               regulator-boot-on;
 285 +
 286 +                               regulator-state-mem {
 287 +                                       regulator-on-in-suspend;
 288 +                               };
 289 +                       };
 290 +
 291 +                       vcc_io: DCDC_REG4 {
 292 +                               regulator-name = "vcc_io";
 293 +                               regulator-always-on;
 294 +                               regulator-boot-on;
 295 +                               regulator-min-microvolt = <3300000>;
 296 +                               regulator-max-microvolt = <3300000>;
 297 +
 298 +                               regulator-state-mem {
 299 +                                       regulator-on-in-suspend;
 300 +                                       regulator-suspend-microvolt = <3300000>;
 301 +                               };
 302 +                       };
 303 +
 304 +                       vcc_18: LDO_REG1 {
 305 +                               regulator-name = "vcc_18";
 306 +                               regulator-always-on;
 307 +                               regulator-boot-on;
 308 +                               regulator-min-microvolt = <1800000>;
 309 +                               regulator-max-microvolt = <1800000>;
 310 +
 311 +                               regulator-state-mem {
 312 +                                       regulator-on-in-suspend;
 313 +                                       regulator-suspend-microvolt = <1800000>;
 314 +                               };
 315 +                       };
 316 +
 317 +                       vcc18_emmc: LDO_REG2 {
 318 +                               regulator-name = "vcc18_emmc";
 319 +                               regulator-always-on;
 320 +                               regulator-boot-on;
 321 +                               regulator-min-microvolt = <1800000>;
 322 +                               regulator-max-microvolt = <1800000>;
 323 +
 324 +                               regulator-state-mem {
 325 +                                       regulator-on-in-suspend;
 326 +                                       regulator-suspend-microvolt = <1800000>;
 327 +                               };
 328 +                       };
 329 +
 330 +                       vdd_10: LDO_REG3 {
 331 +                               regulator-name = "vdd_10";
 332 +                               regulator-always-on;
 333 +                               regulator-boot-on;
 334 +                               regulator-min-microvolt = <1000000>;
 335 +                               regulator-max-microvolt = <1000000>;
 336 +
 337 +                               regulator-state-mem {
 338 +                                       regulator-on-in-suspend;
 339 +                                       regulator-suspend-microvolt = <1000000>;
 340 +                               };
 341 +                       };
 342 +               };
 343 +       };
 344 +};
 345 +
 346 +&io_domains {
 347 +       pmuio-supply = <&vcc_io>;
 348 +       vccio1-supply = <&vcc_io>;
 349 +       vccio2-supply = <&vcc18_emmc>;
 350 +       vccio3-supply = <&vcc_io>;
 351 +       vccio4-supply = <&vcc_io>;
 352 +       vccio5-supply = <&vcc_io>;
 353 +       vccio6-supply = <&vcc_io>;
 354 +       status = "okay";
 355 +};
 356 +
 357 +&pinctrl {
 358 +       gmac2io {
 359 +               eth_phy_reset_pin: eth-phy-reset-pin {
 360 +                       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
 361 +               };
 362 +       };
 363 +
 364 +       leds {
 365 +               lan_led_pin: lan-led-pin {
 366 +                       rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 367 +               };
 368 +
 369 +               sys_led_pin: sys-led-pin {
 370 +                       rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 371 +               };
 372 +
 373 +               wan_led_pin: wan-led-pin {
 374 +                       rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
 375 +               };
 376 +       };
 377 +
 378 +       lan {
 379 +               lan_vdd_pin: lan-vdd-pin {
 380 +                       rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 381 +               };
 382 +       };
 383 +
 384 +       pmic {
 385 +               pmic_int_l: pmic-int-l {
 386 +                       rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
 387 +               };
 388 +       };
 389 +};
 390 +
 391 +&pwm2 {
 392 +       status = "okay";
 393 +};
 394 +
 395 +&sdmmc {
 396 +       bus-width = <4>;
 397 +       cap-sd-highspeed;
 398 +       disable-wp;
 399 +       pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
 400 +       pinctrl-names = "default";
 401 +       vmmc-supply = <&vcc_sd>;
 402 +       status = "okay";
 403 +};
 404 +
 405 +&spi0 {
 406 +       status = "okay";
 407 +
 408 +       flash@0 {
 409 +               compatible = "jedec,spi-nor";
 410 +               reg = <0>;
 411 +               spi-max-frequency = <50000000>;
 412 +       };
 413 +};
 414 +
 415 +&tsadc {
 416 +       rockchip,hw-tshut-mode = <0>;
 417 +       rockchip,hw-tshut-polarity = <0>;
 418 +       status = "okay";
 419 +};
 420 +
 421 +&u2phy {
 422 +       status = "okay";
 423 +};
 424 +
 425 +&u2phy_host {
 426 +       status = "okay";
 427 +};
 428 +
 429 +&u2phy_otg {
 430 +       status = "okay";
 431 +};
 432 +
 433 +&uart2 {
 434 +       status = "okay";
 435 +};
 436 +
 437 +&usb20_otg {
 438 +       dr_mode = "host";
 439 +       status = "okay";
 440 +};
 441 +
 442 +&usb_host0_ehci {
 443 +       status = "okay";
 444 +};
 445 +
 446 +&usb_host0_ohci {
 447 +       status = "okay";
 448 +};
 449 --- a/board/rockchip/evb_rk3328/MAINTAINERS
 450 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
 451 @@ -18,6 +18,12 @@ F:      configs/nanopi-r2s-rk3328_defcon
 452  F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
 453  F:      arch/arm/dts/rk3328-nanopi-r2s.dts
 454
 455 +ORANGEPI-R1-PLUS-RK3328
 456 +M:      Tianling Shen <cnsztl@gmail.com>
 457 +S:      Maintained
 458 +F:      configs/orangepi-r1-plus-rk3328_defconfig
 459 +F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
 460 +
 461  ROC-RK3328-CC
 462  M:      Loic Devulder <ldevulder@suse.com>
 463  M:      Chen-Yu Tsai <wens@csie.org>
 464 --- /dev/null
 465 +++ b/configs/orangepi-r1-plus-rk3328_defconfig
 466 @@ -0,0 +1,98 @@
 467 +CONFIG_ARM=y
 468 +CONFIG_ARCH_ROCKCHIP=y
 469 +CONFIG_SYS_TEXT_BASE=0x00200000
 470 +CONFIG_SPL_GPIO_SUPPORT=y
 471 +CONFIG_ENV_OFFSET=0x3F8000
 472 +CONFIG_ROCKCHIP_RK3328=y
 473 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 474 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 475 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
 476 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 477 +CONFIG_SPL_STACK_R_ADDR=0x600000
 478 +CONFIG_NR_DRAM_BANKS=1
 479 +CONFIG_DEBUG_UART_BASE=0xFF130000
 480 +CONFIG_DEBUG_UART_CLOCK=24000000
 481 +CONFIG_SYSINFO=y
 482 +CONFIG_DEBUG_UART=y
 483 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 484 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 485 +CONFIG_FIT=y
 486 +CONFIG_FIT_VERBOSE=y
 487 +CONFIG_SPL_LOAD_FIT=y
 488 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
 489 +CONFIG_MISC_INIT_R=y
 490 +# CONFIG_DISPLAY_CPUINFO is not set
 491 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 492 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 493 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 494 +CONFIG_SPL_STACK_R=y
 495 +CONFIG_SPL_I2C_SUPPORT=y
 496 +CONFIG_SPL_POWER_SUPPORT=y
 497 +CONFIG_SPL_ATF=y
 498 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 499 +CONFIG_CMD_BOOTZ=y
 500 +CONFIG_CMD_GPT=y
 501 +CONFIG_CMD_MMC=y
 502 +CONFIG_CMD_USB=y
 503 +# CONFIG_CMD_SETEXPR is not set
 504 +CONFIG_CMD_TIME=y
 505 +CONFIG_SPL_OF_CONTROL=y
 506 +CONFIG_TPL_OF_CONTROL=y
 507 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
 508 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 509 +CONFIG_TPL_OF_PLATDATA=y
 510 +CONFIG_ENV_IS_IN_MMC=y
 511 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 512 +CONFIG_NET_RANDOM_ETHADDR=y
 513 +CONFIG_TPL_DM=y
 514 +CONFIG_REGMAP=y
 515 +CONFIG_SPL_REGMAP=y
 516 +CONFIG_TPL_REGMAP=y
 517 +CONFIG_SYSCON=y
 518 +CONFIG_SPL_SYSCON=y
 519 +CONFIG_TPL_SYSCON=y
 520 +CONFIG_CLK=y
 521 +CONFIG_SPL_CLK=y
 522 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
 523 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 524 +CONFIG_ROCKCHIP_GPIO=y
 525 +CONFIG_SYS_I2C_ROCKCHIP=y
 526 +CONFIG_MMC_DW=y
 527 +CONFIG_MMC_DW_ROCKCHIP=y
 528 +CONFIG_SF_DEFAULT_SPEED=20000000
 529 +CONFIG_DM_ETH=y
 530 +CONFIG_ETH_DESIGNWARE=y
 531 +CONFIG_GMAC_ROCKCHIP=y
 532 +CONFIG_PINCTRL=y
 533 +CONFIG_SPL_PINCTRL=y
 534 +CONFIG_DM_PMIC=y
 535 +CONFIG_PMIC_RK8XX=y
 536 +CONFIG_SPL_DM_REGULATOR=y
 537 +CONFIG_REGULATOR_PWM=y
 538 +CONFIG_DM_REGULATOR_FIXED=y
 539 +CONFIG_SPL_DM_REGULATOR_FIXED=y
 540 +CONFIG_REGULATOR_RK8XX=y
 541 +CONFIG_PWM_ROCKCHIP=y
 542 +CONFIG_RAM=y
 543 +CONFIG_SPL_RAM=y
 544 +CONFIG_TPL_RAM=y
 545 +CONFIG_DM_RESET=y
 546 +CONFIG_BAUDRATE=1500000
 547 +CONFIG_DEBUG_UART_SHIFT=2
 548 +CONFIG_SYSRESET=y
 549 +# CONFIG_TPL_SYSRESET is not set
 550 +CONFIG_USB=y
 551 +CONFIG_USB_XHCI_HCD=y
 552 +CONFIG_USB_XHCI_DWC3=y
 553 +CONFIG_USB_EHCI_HCD=y
 554 +CONFIG_USB_EHCI_GENERIC=y
 555 +CONFIG_USB_OHCI_HCD=y
 556 +CONFIG_USB_OHCI_GENERIC=y
 557 +CONFIG_USB_DWC2=y
 558 +CONFIG_USB_DWC3=y
 559 +# CONFIG_USB_DWC3_GADGET is not set
 560 +CONFIG_USB_GADGET=y
 561 +CONFIG_USB_GADGET_DWC2_OTG=y
 562 +CONFIG_SPL_TINY_MEMSET=y
 563 +CONFIG_TPL_TINY_MEMSET=y
 564 +CONFIG_ERRNO_STR=y