1 From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001
2 From: Tianling Shen <cnsztl@gmail.com>
3 Date: Sat, 20 May 2023 18:50:38 +0800
4 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus
6 Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
8 This device is similar to the NanoPi R2S, and has a 16MB
9 SPI NOR (mx25l12805d). The reset button is changed to
10 directly reset the power supply, another detail is that
11 both network ports have independent MAC addresses.
13 The device tree and description are taken from kernel v6.3-rc1.
15 Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
16 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
18 arch/arm/dts/Makefile | 1 +
19 .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 46 +++
20 arch/arm/dts/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
21 board/rockchip/evb_rk3328/MAINTAINERS | 6 +
22 configs/orangepi-r1-plus-rk3328_defconfig | 114 ++++++
23 5 files changed, 540 insertions(+)
24 create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
25 create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts
26 create mode 100644 configs/orangepi-r1-plus-rk3328_defconfig
28 --- a/arch/arm/dts/Makefile
29 +++ b/arch/arm/dts/Makefile
30 @@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
32 rk3328-nanopi-r2c.dtb \
33 rk3328-nanopi-r2s.dtb \
34 + rk3328-orangepi-r1-plus.dtb \
39 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
41 +// SPDX-License-Identifier: GPL-2.0-or-later
43 + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
44 + * (C) Copyright 2020 David Bauer
47 +#include "rk3328-u-boot.dtsi"
48 +#include "rk3328-sdram-ddr4-666.dtsi"
51 + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
71 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
77 + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
78 + snps,reset-active-low;
79 + snps,reset-delays-us = <0 10000 50000>;
83 + spi_flash: spiflash@0 {
84 + u-boot,dm-pre-reloc;
88 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
90 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
92 + * Based on rk3328-nanopi-r2s.dts, which is:
93 + * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
98 +#include <dt-bindings/gpio/gpio.h>
99 +#include <dt-bindings/leds/common.h>
100 +#include "rk3328.dtsi"
103 + model = "Xunlong Orange Pi R1 Plus";
104 + compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
111 + stdout-path = "serial2:1500000n8";
114 + gmac_clk: gmac-clock {
115 + compatible = "fixed-clock";
116 + clock-frequency = <125000000>;
117 + clock-output-names = "gmac_clkin";
118 + #clock-cells = <0>;
122 + compatible = "gpio-leds";
123 + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
124 + pinctrl-names = "default";
127 + function = LED_FUNCTION_LAN;
128 + color = <LED_COLOR_ID_GREEN>;
129 + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
133 + function = LED_FUNCTION_STATUS;
134 + color = <LED_COLOR_ID_RED>;
135 + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
136 + linux,default-trigger = "heartbeat";
140 + function = LED_FUNCTION_WAN;
141 + color = <LED_COLOR_ID_GREEN>;
142 + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
146 + vcc_sd: sdmmc-regulator {
147 + compatible = "regulator-fixed";
148 + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
149 + pinctrl-0 = <&sdmmc0m1_gpio>;
150 + pinctrl-names = "default";
151 + regulator-name = "vcc_sd";
153 + vin-supply = <&vcc_io>;
156 + vcc_sys: vcc-sys-regulator {
157 + compatible = "regulator-fixed";
158 + regulator-name = "vcc_sys";
159 + regulator-always-on;
161 + regulator-min-microvolt = <5000000>;
162 + regulator-max-microvolt = <5000000>;
165 + vdd_5v_lan: vdd-5v-lan-regulator {
166 + compatible = "regulator-fixed";
167 + enable-active-high;
168 + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
169 + pinctrl-0 = <&lan_vdd_pin>;
170 + pinctrl-names = "default";
171 + regulator-name = "vdd_5v_lan";
172 + regulator-always-on;
174 + vin-supply = <&vcc_sys>;
179 + cpu-supply = <&vdd_arm>;
183 + cpu-supply = <&vdd_arm>;
187 + cpu-supply = <&vdd_arm>;
191 + cpu-supply = <&vdd_arm>;
194 +&display_subsystem {
195 + status = "disabled";
199 + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
200 + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
201 + clock_in_out = "input";
202 + phy-handle = <&rtl8211e>;
203 + phy-mode = "rgmii";
204 + phy-supply = <&vcc_io>;
205 + pinctrl-0 = <&rgmiim1_pins>;
206 + pinctrl-names = "default";
213 + compatible = "snps,dwmac-mdio";
214 + #address-cells = <1>;
217 + rtl8211e: ethernet-phy@1 {
219 + pinctrl-0 = <ð_phy_reset_pin>;
220 + pinctrl-names = "default";
221 + reset-assert-us = <10000>;
222 + reset-deassert-us = <50000>;
223 + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
232 + compatible = "rockchip,rk805";
234 + interrupt-parent = <&gpio1>;
235 + interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
236 + #clock-cells = <1>;
237 + clock-output-names = "xin32k", "rk805-clkout2";
240 + pinctrl-0 = <&pmic_int_l>;
241 + pinctrl-names = "default";
242 + rockchip,system-power-controller;
245 + vcc1-supply = <&vcc_sys>;
246 + vcc2-supply = <&vcc_sys>;
247 + vcc3-supply = <&vcc_sys>;
248 + vcc4-supply = <&vcc_sys>;
249 + vcc5-supply = <&vcc_io>;
250 + vcc6-supply = <&vcc_sys>;
253 + vdd_log: DCDC_REG1 {
254 + regulator-name = "vdd_log";
255 + regulator-always-on;
257 + regulator-min-microvolt = <712500>;
258 + regulator-max-microvolt = <1450000>;
259 + regulator-ramp-delay = <12500>;
261 + regulator-state-mem {
262 + regulator-on-in-suspend;
263 + regulator-suspend-microvolt = <1000000>;
267 + vdd_arm: DCDC_REG2 {
268 + regulator-name = "vdd_arm";
269 + regulator-always-on;
271 + regulator-min-microvolt = <712500>;
272 + regulator-max-microvolt = <1450000>;
273 + regulator-ramp-delay = <12500>;
275 + regulator-state-mem {
276 + regulator-on-in-suspend;
277 + regulator-suspend-microvolt = <950000>;
281 + vcc_ddr: DCDC_REG3 {
282 + regulator-name = "vcc_ddr";
283 + regulator-always-on;
286 + regulator-state-mem {
287 + regulator-on-in-suspend;
291 + vcc_io: DCDC_REG4 {
292 + regulator-name = "vcc_io";
293 + regulator-always-on;
295 + regulator-min-microvolt = <3300000>;
296 + regulator-max-microvolt = <3300000>;
298 + regulator-state-mem {
299 + regulator-on-in-suspend;
300 + regulator-suspend-microvolt = <3300000>;
305 + regulator-name = "vcc_18";
306 + regulator-always-on;
308 + regulator-min-microvolt = <1800000>;
309 + regulator-max-microvolt = <1800000>;
311 + regulator-state-mem {
312 + regulator-on-in-suspend;
313 + regulator-suspend-microvolt = <1800000>;
317 + vcc18_emmc: LDO_REG2 {
318 + regulator-name = "vcc18_emmc";
319 + regulator-always-on;
321 + regulator-min-microvolt = <1800000>;
322 + regulator-max-microvolt = <1800000>;
324 + regulator-state-mem {
325 + regulator-on-in-suspend;
326 + regulator-suspend-microvolt = <1800000>;
331 + regulator-name = "vdd_10";
332 + regulator-always-on;
334 + regulator-min-microvolt = <1000000>;
335 + regulator-max-microvolt = <1000000>;
337 + regulator-state-mem {
338 + regulator-on-in-suspend;
339 + regulator-suspend-microvolt = <1000000>;
347 + pmuio-supply = <&vcc_io>;
348 + vccio1-supply = <&vcc_io>;
349 + vccio2-supply = <&vcc18_emmc>;
350 + vccio3-supply = <&vcc_io>;
351 + vccio4-supply = <&vcc_io>;
352 + vccio5-supply = <&vcc_io>;
353 + vccio6-supply = <&vcc_io>;
359 + eth_phy_reset_pin: eth-phy-reset-pin {
360 + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
365 + lan_led_pin: lan-led-pin {
366 + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
369 + sys_led_pin: sys-led-pin {
370 + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
373 + wan_led_pin: wan-led-pin {
374 + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
379 + lan_vdd_pin: lan-vdd-pin {
380 + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
385 + pmic_int_l: pmic-int-l {
386 + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
399 + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
400 + pinctrl-names = "default";
401 + vmmc-supply = <&vcc_sd>;
409 + compatible = "jedec,spi-nor";
411 + spi-max-frequency = <50000000>;
416 + rockchip,hw-tshut-mode = <0>;
417 + rockchip,hw-tshut-polarity = <0>;
449 --- a/board/rockchip/evb_rk3328/MAINTAINERS
450 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
451 @@ -18,6 +18,12 @@ F: configs/nanopi-r2s-rk3328_defcon
452 F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
453 F: arch/arm/dts/rk3328-nanopi-r2s.dts
455 +ORANGEPI-R1-PLUS-RK3328
456 +M: Tianling Shen <cnsztl@gmail.com>
458 +F: configs/orangepi-r1-plus-rk3328_defconfig
459 +F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
462 M: Loic Devulder <ldevulder@suse.com>
463 M: Chen-Yu Tsai <wens@csie.org>
465 +++ b/configs/orangepi-r1-plus-rk3328_defconfig
468 +CONFIG_ARCH_ROCKCHIP=y
469 +CONFIG_SYS_TEXT_BASE=0x00200000
470 +CONFIG_SPL_GPIO_SUPPORT=y
471 +CONFIG_ENV_OFFSET=0x3F8000
472 +CONFIG_ROCKCHIP_RK3328=y
473 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
474 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
475 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
476 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
477 +CONFIG_SPL_STACK_R_ADDR=0x600000
478 +CONFIG_NR_DRAM_BANKS=1
479 +CONFIG_DEBUG_UART_BASE=0xFF130000
480 +CONFIG_DEBUG_UART_CLOCK=24000000
483 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
484 +# CONFIG_ANDROID_BOOT_IMAGE is not set
486 +CONFIG_FIT_VERBOSE=y
487 +CONFIG_SPL_LOAD_FIT=y
488 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
489 +CONFIG_MISC_INIT_R=y
490 +# CONFIG_DISPLAY_CPUINFO is not set
491 +CONFIG_DISPLAY_BOARDINFO_LATE=y
492 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
493 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
494 +CONFIG_SPL_STACK_R=y
495 +CONFIG_SPL_I2C_SUPPORT=y
496 +CONFIG_SPL_POWER_SUPPORT=y
498 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
503 +# CONFIG_CMD_SETEXPR is not set
505 +CONFIG_SPL_OF_CONTROL=y
506 +CONFIG_TPL_OF_CONTROL=y
507 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
508 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
509 +CONFIG_TPL_OF_PLATDATA=y
510 +CONFIG_ENV_IS_IN_MMC=y
511 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
512 +CONFIG_NET_RANDOM_ETHADDR=y
522 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
523 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
524 +CONFIG_ROCKCHIP_GPIO=y
525 +CONFIG_SYS_I2C_ROCKCHIP=y
527 +CONFIG_MMC_DW_ROCKCHIP=y
528 +CONFIG_SF_DEFAULT_SPEED=20000000
530 +CONFIG_ETH_DESIGNWARE=y
531 +CONFIG_GMAC_ROCKCHIP=y
533 +CONFIG_SPL_PINCTRL=y
536 +CONFIG_SPL_DM_REGULATOR=y
537 +CONFIG_REGULATOR_PWM=y
538 +CONFIG_DM_REGULATOR_FIXED=y
539 +CONFIG_SPL_DM_REGULATOR_FIXED=y
540 +CONFIG_REGULATOR_RK8XX=y
541 +CONFIG_PWM_ROCKCHIP=y
546 +CONFIG_BAUDRATE=1500000
547 +CONFIG_DEBUG_UART_SHIFT=2
549 +# CONFIG_TPL_SYSRESET is not set
551 +CONFIG_USB_XHCI_HCD=y
552 +CONFIG_USB_XHCI_DWC3=y
553 +CONFIG_USB_EHCI_HCD=y
554 +CONFIG_USB_EHCI_GENERIC=y
555 +CONFIG_USB_OHCI_HCD=y
556 +CONFIG_USB_OHCI_GENERIC=y
559 +# CONFIG_USB_DWC3_GADGET is not set
561 +CONFIG_USB_GADGET_DWC2_OTG=y
562 +CONFIG_SPL_TINY_MEMSET=y
563 +CONFIG_TPL_TINY_MEMSET=y