1 From 7a9326a96098bc63d2b60538f657c3a533415276 Mon Sep 17 00:00:00 2001
2 From: Tianling Shen <cnsztl@gmail.com>
3 Date: Sat, 20 May 2023 18:52:14 +0800
4 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS
6 The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
7 the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type
8 changed from DDR4 to LPDDR3.
10 The device tree is taken from kernel v6.4-rc1.
12 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
15 arch/arm/dts/Makefile | 1 +
16 .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++
17 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 40 ++++++
18 board/rockchip/evb_rk3328/MAINTAINERS | 6 +
19 configs/orangepi-r1-plus-lts-rk3328_defconfig | 114 ++++++++++++++++++
20 5 files changed, 207 insertions(+)
21 create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
22 create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
23 create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
25 --- a/arch/arm/dts/Makefile
26 +++ b/arch/arm/dts/Makefile
27 @@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
28 rk3328-nanopi-r2c.dtb \
29 rk3328-nanopi-r2s.dtb \
30 rk3328-orangepi-r1-plus.dtb \
31 + rk3328-orangepi-r1-plus-lts.dtb \
36 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
38 +// SPDX-License-Identifier: GPL-2.0-or-later
40 + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
41 + * (C) Copyright 2020 David Bauer
44 +#include "rk3328-u-boot.dtsi"
45 +#include "rk3328-sdram-lpddr3-666.dtsi"
48 + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
68 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
74 + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
75 + snps,reset-active-low;
76 + snps,reset-delays-us = <0 10000 50000>;
80 + spi_flash: spiflash@0 {
81 + u-boot,dm-pre-reloc;
85 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
87 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
89 + * Copyright (c) 2016 Xunlong Software. Co., Ltd.
90 + * (http://www.orangepi.org)
92 + * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
96 +#include "rk3328-orangepi-r1-plus.dts"
99 + model = "Xunlong Orange Pi R1 Plus LTS";
100 + compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
104 + phy-handle = <&yt8531c>;
109 + /delete-node/ ethernet-phy@1;
111 + yt8531c: ethernet-phy@0 {
112 + compatible = "ethernet-phy-ieee802.3-c22";
115 + motorcomm,clk-out-frequency-hz = <125000000>;
116 + motorcomm,keep-pll-enabled;
117 + motorcomm,auto-sleep-disabled;
119 + pinctrl-0 = <ð_phy_reset_pin>;
120 + pinctrl-names = "default";
121 + reset-assert-us = <15000>;
122 + reset-deassert-us = <50000>;
123 + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
127 --- a/board/rockchip/evb_rk3328/MAINTAINERS
128 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
129 @@ -24,6 +24,12 @@ S: Maintained
130 F: configs/orangepi-r1-plus-rk3328_defconfig
131 F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
133 +ORANGEPI-R1-PLUS-LTS-RK3328
134 +M: Tianling Shen <cnsztl@gmail.com>
136 +F: configs/orangepi-r1-plus-lts-rk3328_defconfig
137 +F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
140 M: Loic Devulder <ldevulder@suse.com>
141 M: Chen-Yu Tsai <wens@csie.org>
143 +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
146 +CONFIG_ARCH_ROCKCHIP=y
147 +CONFIG_SYS_TEXT_BASE=0x00200000
148 +CONFIG_SPL_GPIO_SUPPORT=y
149 +CONFIG_ENV_OFFSET=0x3F8000
150 +CONFIG_ROCKCHIP_RK3328=y
151 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
152 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
153 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
154 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
155 +CONFIG_SPL_STACK_R_ADDR=0x600000
156 +CONFIG_NR_DRAM_BANKS=1
157 +CONFIG_DEBUG_UART_BASE=0xFF130000
158 +CONFIG_DEBUG_UART_CLOCK=24000000
161 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
162 +# CONFIG_ANDROID_BOOT_IMAGE is not set
164 +CONFIG_FIT_VERBOSE=y
165 +CONFIG_SPL_LOAD_FIT=y
166 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
167 +CONFIG_MISC_INIT_R=y
168 +# CONFIG_DISPLAY_CPUINFO is not set
169 +CONFIG_DISPLAY_BOARDINFO_LATE=y
170 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
171 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
172 +CONFIG_SPL_STACK_R=y
173 +CONFIG_SPL_I2C_SUPPORT=y
174 +CONFIG_SPL_POWER_SUPPORT=y
176 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
181 +# CONFIG_CMD_SETEXPR is not set
183 +CONFIG_SPL_OF_CONTROL=y
184 +CONFIG_TPL_OF_CONTROL=y
185 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
186 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
187 +CONFIG_TPL_OF_PLATDATA=y
188 +CONFIG_ENV_IS_IN_MMC=y
189 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
190 +CONFIG_NET_RANDOM_ETHADDR=y
200 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
201 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
202 +CONFIG_ROCKCHIP_GPIO=y
203 +CONFIG_SYS_I2C_ROCKCHIP=y
205 +CONFIG_MMC_DW_ROCKCHIP=y
206 +CONFIG_SF_DEFAULT_SPEED=20000000
208 +CONFIG_ETH_DESIGNWARE=y
209 +CONFIG_GMAC_ROCKCHIP=y
211 +CONFIG_SPL_PINCTRL=y
214 +CONFIG_SPL_DM_REGULATOR=y
215 +CONFIG_REGULATOR_PWM=y
216 +CONFIG_DM_REGULATOR_FIXED=y
217 +CONFIG_SPL_DM_REGULATOR_FIXED=y
218 +CONFIG_REGULATOR_RK8XX=y
219 +CONFIG_PWM_ROCKCHIP=y
224 +CONFIG_BAUDRATE=1500000
225 +CONFIG_DEBUG_UART_SHIFT=2
227 +# CONFIG_TPL_SYSRESET is not set
229 +CONFIG_USB_XHCI_HCD=y
230 +CONFIG_USB_XHCI_DWC3=y
231 +CONFIG_USB_EHCI_HCD=y
232 +CONFIG_USB_EHCI_GENERIC=y
233 +CONFIG_USB_OHCI_HCD=y
234 +CONFIG_USB_OHCI_GENERIC=y
237 +# CONFIG_USB_DWC3_GADGET is not set
239 +CONFIG_USB_GADGET_DWC2_OTG=y
240 +CONFIG_SPL_TINY_MEMSET=y
241 +CONFIG_TPL_TINY_MEMSET=y