1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_amazon_se.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
46 * Chip Specific Head File
48 #include "ifxmips_atm_core.h"
49 #include "ifxmips_atm_fw_amazon_se.h"
51 #include <lantiq_soc.h>
53 #define EMA_CMD_BUF_LEN 0x0040
54 #define EMA_CMD_BASE_ADDR (0x00001580 << 2)
55 #define EMA_DATA_BUF_LEN 0x0100
56 #define EMA_DATA_BASE_ADDR (0x00001900 << 2)
57 #define EMA_WRITE_BURST 0x2
58 #define EMA_READ_BURST 0x2
63 * ####################################
65 * ####################################
71 #define EMA_CMD_BUF_LEN 0x0040
72 #define EMA_CMD_BASE_ADDR (0x00001580 << 2)
73 #define EMA_DATA_BUF_LEN 0x0100
74 #define EMA_DATA_BASE_ADDR (0x00000B00 << 2)
75 #define EMA_WRITE_BURST 0x2
76 #define EMA_READ_BURST 0x2
81 * ####################################
83 * ####################################
87 * Hardware Init/Uninit Functions
89 static inline void init_pmu(void);
90 static inline void uninit_pmu(void);
91 static inline void reset_ppe(void);
92 static inline void init_ema(void);
93 static inline void init_mailbox(void);
94 static inline void init_atm_tc(void);
95 static inline void clear_share_buffer(void);
100 * ####################################
102 * ####################################
108 * ####################################
110 * ####################################
112 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
113 #define IFX_PMU_MODULE_PPE_TC BIT(21)
114 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
115 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
116 #define IFX_PMU_MODULE_TPE BIT(13)
117 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
119 static inline void init_pmu(void)
121 //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
122 //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
123 /* PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
124 PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
125 PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
126 //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
127 PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
128 DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
129 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01
|
130 IFX_PMU_MODULE_PPE_TC
|
131 IFX_PMU_MODULE_PPE_EMA
|
133 IFX_PMU_MODULE_DSL_DFE
);
136 static inline void uninit_pmu(void)
138 /*PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
139 PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
140 PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
141 //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
142 PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
143 DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
144 //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);*/
147 static inline void reset_ppe(void)
150 unsigned int etop_cfg
;
151 unsigned int etop_mdio_cfg
;
152 unsigned int etop_ig_plen_ctrl
;
153 unsigned int enet_mac_cfg
;
155 etop_cfg
= *IFX_PP32_ETOP_CFG
;
156 etop_mdio_cfg
= *IFX_PP32_ETOP_MDIO_CFG
;
157 etop_ig_plen_ctrl
= *IFX_PP32_ETOP_IG_PLEN_CTRL
;
158 enet_mac_cfg
= *IFX_PP32_ENET_MAC_CFG
;
160 *IFX_PP32_ETOP_CFG
= (*IFX_PP32_ETOP_CFG
& ~0x03C0) | 0x0001;
163 ifx_rcu_rst(IFX_RCU_DOMAIN_PPE
, IFX_RCU_MODULE_ATM
);
165 *IFX_PP32_ETOP_MDIO_CFG
= etop_mdio_cfg
;
166 *IFX_PP32_ETOP_IG_PLEN_CTRL
= etop_ig_plen_ctrl
;
167 *IFX_PP32_ENET_MAC_CFG
= enet_mac_cfg
;
168 *IFX_PP32_ETOP_CFG
= etop_cfg
;
172 static inline void init_ema(void)
174 IFX_REG_W32((EMA_CMD_BUF_LEN
<< 16) | (EMA_CMD_BASE_ADDR
>> 2), EMA_CMDCFG
);
175 IFX_REG_W32((EMA_DATA_BUF_LEN
<< 16) | (EMA_DATA_BASE_ADDR
>> 2), EMA_DATACFG
);
176 IFX_REG_W32(0x000000FF, EMA_IER
);
177 IFX_REG_W32(EMA_READ_BURST
| (EMA_WRITE_BURST
<< 2), EMA_CFG
);
180 static inline void init_mailbox(void)
182 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC
);
183 IFX_REG_W32(0x00000000, MBOX_IGU1_IER
);
184 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC
);
185 IFX_REG_W32(0x00000000, MBOX_IGU3_IER
);
188 static inline void init_atm_tc(void)
190 IFX_REG_W32(0x0000, DREG_AT_CTRL
);
191 IFX_REG_W32(0x0000, DREG_AR_CTRL
);
192 IFX_REG_W32(0x0, DREG_AT_IDLE0
);
193 IFX_REG_W32(0x0, DREG_AT_IDLE1
);
194 IFX_REG_W32(0x0, DREG_AR_IDLE0
);
195 IFX_REG_W32(0x0, DREG_AR_IDLE1
);
196 IFX_REG_W32(0x40, RFBI_CFG
);
197 IFX_REG_W32(0x0700, SFSM_DBA0
);
198 IFX_REG_W32(0x0818, SFSM_DBA1
);
199 IFX_REG_W32(0x0930, SFSM_CBA0
);
200 IFX_REG_W32(0x0944, SFSM_CBA1
);
201 IFX_REG_W32(0x14014, SFSM_CFG0
);
202 IFX_REG_W32(0x14014, SFSM_CFG1
);
203 IFX_REG_W32(0x0958, FFSM_DBA0
);
204 IFX_REG_W32(0x09AC, FFSM_DBA1
);
205 IFX_REG_W32(0x10006, FFSM_CFG0
);
206 IFX_REG_W32(0x10006, FFSM_CFG1
);
207 IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0
);
208 IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1
);
211 static inline void clear_share_buffer(void)
213 volatile u32
*p
= SB_RAM0_ADDR(0);
216 for ( i
= 0; i
< SB_RAM0_DWLEN
+ SB_RAM1_DWLEN
; i
++ )
222 * Download PPE firmware binary code.
224 * src --- u32 *, binary code buffer
225 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
230 static inline int pp32_download_code(u32
*code_src
, unsigned int code_dword_len
, u32
*data_src
, unsigned int data_dword_len
)
234 if ( code_src
== 0 || ((unsigned long)code_src
& 0x03) != 0
235 || data_src
== 0 || ((unsigned long)data_src
& 0x03) != 0 )
238 if ( code_dword_len
<= CDM_CODE_MEMORYn_DWLEN(0) )
239 IFX_REG_W32(0x00, CDM_CFG
);
241 IFX_REG_W32(0x04, CDM_CFG
);
244 dest
= CDM_CODE_MEMORY(0, 0);
245 while ( code_dword_len
-- > 0 )
246 IFX_REG_W32(*code_src
++, dest
++);
249 dest
= CDM_DATA_MEMORY(0, 0);
250 while ( data_dword_len
-- > 0 )
251 IFX_REG_W32(*data_src
++, dest
++);
259 * ####################################
261 * ####################################
264 extern void ase_fw_ver(unsigned int *major
, unsigned int *minor
)
266 ASSERT(major
!= NULL
, "pointer is NULL");
267 ASSERT(minor
!= NULL
, "pointer is NULL");
269 *major
= FW_VER_ID
->major
;
270 *minor
= FW_VER_ID
->minor
;
285 clear_share_buffer();
288 void ase_shutdown(void)
295 * Initialize and start up PP32.
302 int ase_start(int pp32
)
306 /* download firmware */
307 ret
= pp32_download_code(firmware_binary_code
, sizeof(firmware_binary_code
) / sizeof(*firmware_binary_code
), firmware_binary_data
, sizeof(firmware_binary_data
) / sizeof(*firmware_binary_data
));
312 IFX_REG_W32(DBG_CTRL_RESTART
, PP32_DBG_CTRL
);
314 /* idle for a while to let PP32 init itself */
328 void ase_stop(int pp32
)
331 IFX_REG_W32(DBG_CTRL_STOP
, PP32_DBG_CTRL
);
334 struct ltq_atm_ops ase_ops
= {
336 .shutdown
= ase_shutdown
,
339 .fw_ver
= ase_fw_ver
,