1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_ar9.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <linux/platform_device.h>
44 #include <asm/delay.h>
47 * Chip Specific Head File
49 #include "ifxmips_atm_core.h"
51 #include "ifxmips_atm_fw_ar9.h"
52 #include "ifxmips_atm_fw_regs_ar9.h"
54 #include <lantiq_soc.h>
59 * ####################################
61 * ####################################
67 #define EMA_CMD_BUF_LEN 0x0040
68 #define EMA_CMD_BASE_ADDR (0x00003B80 << 2)
69 #define EMA_DATA_BUF_LEN 0x0100
70 #define EMA_DATA_BASE_ADDR (0x00003C00 << 2)
71 #define EMA_WRITE_BURST 0x2
72 #define EMA_READ_BURST 0x2
77 * ####################################
79 * ####################################
83 * Hardware Init/Uninit Functions
85 static inline void init_pmu(void);
86 static inline void uninit_pmu(void);
87 static inline void reset_ppe(struct platform_device
*pdev
);
88 static inline void init_ema(void);
89 static inline void init_mailbox(void);
90 static inline void clear_share_buffer(void);
95 * ####################################
97 * ####################################
103 * ####################################
105 * ####################################
108 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
109 #define IFX_PMU_MODULE_PPE_TC BIT(21)
110 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
111 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
112 #define IFX_PMU_MODULE_TPE BIT(13)
113 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
115 static inline void init_pmu(void)
117 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01
|
118 IFX_PMU_MODULE_PPE_TC
|
119 IFX_PMU_MODULE_PPE_EMA
|
120 IFX_PMU_MODULE_PPE_QSB
|
122 IFX_PMU_MODULE_DSL_DFE
);
125 static inline void uninit_pmu(void)
129 static inline void reset_ppe(struct platform_device
*pdev
)
133 // ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
137 static inline void init_ema(void)
139 IFX_REG_W32((EMA_CMD_BUF_LEN
<< 16) | (EMA_CMD_BASE_ADDR
>> 2), EMA_CMDCFG
);
140 IFX_REG_W32((EMA_DATA_BUF_LEN
<< 16) | (EMA_DATA_BASE_ADDR
>> 2), EMA_DATACFG
);
141 IFX_REG_W32(0x000000FF, EMA_IER
);
142 IFX_REG_W32(EMA_READ_BURST
| (EMA_WRITE_BURST
<< 2), EMA_CFG
);
145 static inline void init_mailbox(void)
147 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC
);
148 IFX_REG_W32(0x00000000, MBOX_IGU1_IER
);
149 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC
);
150 IFX_REG_W32(0x00000000, MBOX_IGU3_IER
);
153 static inline void clear_share_buffer(void)
155 volatile u32
*p
= SB_RAM0_ADDR(0);
158 for ( i
= 0; i
< SB_RAM0_DWLEN
+ SB_RAM1_DWLEN
+ SB_RAM2_DWLEN
+ SB_RAM3_DWLEN
+ SB_RAM4_DWLEN
; i
++ )
162 static inline int pp32_download_code(u32
*code_src
, unsigned int code_dword_len
, u32
*data_src
, unsigned int data_dword_len
)
166 if ( code_src
== 0 || ((unsigned long)code_src
& 0x03) != 0
167 || data_src
== 0 || ((unsigned long)data_src
& 0x03) != 0 )
170 if ( code_dword_len
<= CDM_CODE_MEMORYn_DWLEN(0) )
171 IFX_REG_W32(0x00, CDM_CFG
);
173 IFX_REG_W32(0x04, CDM_CFG
);
176 dest
= CDM_CODE_MEMORY(0, 0);
177 while ( code_dword_len
-- > 0 )
178 IFX_REG_W32(*code_src
++, dest
++);
181 dest
= CDM_DATA_MEMORY(0, 0);
182 while ( data_dword_len
-- > 0 )
183 IFX_REG_W32(*data_src
++, dest
++);
188 void ar9_fw_ver(unsigned int *major
, unsigned int *minor
)
190 ASSERT(major
!= NULL
, "pointer is NULL");
191 ASSERT(minor
!= NULL
, "pointer is NULL");
193 *major
= FW_VER_ID
->major
;
194 *minor
= FW_VER_ID
->minor
;
197 void ar9_init(struct platform_device
*pdev
)
203 clear_share_buffer();
206 void ar9_shutdown(void)
208 ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01
|
209 IFX_PMU_MODULE_PPE_TC
|
210 IFX_PMU_MODULE_PPE_EMA
|
211 IFX_PMU_MODULE_PPE_QSB
|
213 IFX_PMU_MODULE_DSL_DFE
);
216 int ar9_start(int pp32
)
220 ret
= pp32_download_code(ar9_fw_bin
, sizeof(ar9_fw_bin
) / sizeof(*ar9_fw_bin
),
221 ar9_fw_data
, sizeof(ar9_fw_data
) / sizeof(*ar9_fw_data
));
225 IFX_REG_W32(DBG_CTRL_RESTART
, PP32_DBG_CTRL(0));
232 void ar9_stop(int pp32
)
234 IFX_REG_W32(DBG_CTRL_STOP
, PP32_DBG_CTRL(0));
237 struct ltq_atm_ops ar9_ops
= {
239 .shutdown
= ar9_shutdown
,
242 .fw_ver
= ar9_fw_ver
,