package/kernel/lantiq/ltq-atm/src/ifxmips_atm_vr9.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_vr9.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/reset.h>
  45 #include <asm/delay.h>
  46
  47 #include "ifxmips_atm_core.h"
  48 #include "ifxmips_atm_fw_vr9.h"
  49
  50 #ifdef CONFIG_VR9
  51
  52 #include <lantiq_soc.h>
  53
  54 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
  55 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
  56 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
  57 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
  58 #define IFX_PMU_MODULE_AHBS       BIT(13)
  59 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
  60
  61 static inline void vr9_reset_ppe(struct platform_device *pdev)
  62 {
  63 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0)
  64         struct device *dev = &pdev->dev;
  65         struct reset_control *dsp;
  66         struct reset_control *dfe;
  67         struct reset_control *tc;
  68
  69         dsp = devm_reset_control_get(dev, "dsp");
  70         if (IS_ERR(dsp)) {
  71                 if (PTR_ERR(dsp) != -EPROBE_DEFER)
  72                         dev_err(dev, "Failed to lookup dsp reset\n");
  73 //              return PTR_ERR(dsp);
  74         }
  75
  76         dfe = devm_reset_control_get(dev, "dfe");
  77         if (IS_ERR(dfe)) {
  78                 if (PTR_ERR(dfe) != -EPROBE_DEFER)
  79                         dev_err(dev, "Failed to lookup dfe reset\n");
  80 //              return PTR_ERR(dfe);
  81         }
  82
  83         tc = devm_reset_control_get(dev, "tc");
  84         if (IS_ERR(tc)) {
  85                 if (PTR_ERR(tc) != -EPROBE_DEFER)
  86                         dev_err(dev, "Failed to lookup tc reset\n");
  87 //              return PTR_ERR(tc);
  88         }
  89
  90         reset_control_assert(dsp);
  91         udelay(1000);
  92         reset_control_assert(dfe);
  93         udelay(1000);
  94         reset_control_assert(tc);
  95         udelay(1000);
  96         *PP32_SRST &= ~0x000303CF;
  97         udelay(1000);
  98         *PP32_SRST |= 0x000303CF;
  99         udelay(1000);
 100 #endif
 101 }
 102
 103 static inline int vr9_pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 104 {
 105         unsigned int clr, set;
 106         volatile u32 *dest;
 107
 108         if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 109                         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 110                 return -1;
 111
 112         clr = pp32 ? 0xF0 : 0x0F;
 113         if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 114                 set = pp32 ? (3 << 6): (2 << 2);
 115         else
 116                 set = 0x00;
 117         IFX_REG_W32_MASK(clr, set, CDM_CFG);
 118
 119         dest = CDM_CODE_MEMORY(pp32, 0);
 120         while ( code_dword_len-- > 0 )
 121                 IFX_REG_W32(*code_src++, dest++);
 122
 123         dest = CDM_DATA_MEMORY(pp32, 0);
 124         while ( data_dword_len-- > 0 )
 125                 IFX_REG_W32(*data_src++, dest++);
 126
 127         return 0;
 128 }
 129
 130 static void vr9_fw_ver(unsigned int *major, unsigned int *minor)
 131 {
 132
 133     *major = FW_VER_ID->major;
 134     *minor = FW_VER_ID->minor;
 135 }
 136
 137 static void vr9_init(struct platform_device *pdev)
 138 {
 139         volatile u32 *p;
 140         unsigned int i;
 141
 142         /* setup pmu */
 143         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
 144                 IFX_PMU_MODULE_PPE_TC |
 145                 IFX_PMU_MODULE_PPE_EMA |
 146                 IFX_PMU_MODULE_PPE_QSB |
 147                 IFX_PMU_MODULE_AHBS |
 148                 IFX_PMU_MODULE_DSL_DFE);
 149
 150         vr9_reset_ppe(pdev);
 151
 152         /* pdma init */
 153         IFX_REG_W32(0x08,       PDMA_CFG);
 154         IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG);
 155         IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG);
 156
 157         /* mailbox init */
 158         IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 159         IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 160         IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 161         IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 162
 163         /* tc init - clear sync state */
 164         *SFSM_STATE0 = 0;
 165         *SFSM_STATE1 = 0;
 166
 167         /* init shared buffer */
 168         p = SB_RAM0_ADDR(0);
 169         for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 170                 IFX_REG_W32(0, p++);
 171
 172         p = SB_RAM6_ADDR(0);
 173         for ( i = 0; i < SB_RAM6_DWLEN; i++ )
 174                 IFX_REG_W32(0, p++);
 175 }
 176
 177 static void vr9_shutdown(void)
 178 {
 179 }
 180
 181 static int vr9_start(int pp32)
 182 {
 183         unsigned int mask = 1 << (pp32 << 4);
 184         int ret;
 185
 186         /*  download firmware   */
 187         ret = vr9_pp32_download_code(pp32,
 188                 vr9_fw_bin, sizeof(vr9_fw_bin) / sizeof(*vr9_fw_bin),
 189                 vr9_fw_data, sizeof(vr9_fw_data) / sizeof(*vr9_fw_data));
 190         if ( ret != 0 )
 191                 return ret;
 192
 193         /*  run PP32    */
 194         IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
 195
 196         /*  idle for a while to let PP32 init itself    */
 197         udelay(10);
 198
 199         return 0;
 200 }
 201
 202 static void vr9_stop(int pp32)
 203 {
 204         unsigned int mask = 1 << (pp32 << 4);
 205
 206         IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
 207 }
 208
 209 struct ltq_atm_ops vr9_ops = {
 210         .init = vr9_init,
 211         .shutdown = vr9_shutdown,
 212         .start = vr9_start,
 213         .stop = vr9_stop,
 214         .fw_ver = vr9_fw_ver,
 215 };
 216
 217 #endif