1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_vr9.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
45 #include "ifxmips_atm_core.h"
46 #include "ifxmips_atm_fw_vr9.h"
50 #include <lantiq_soc.h>
52 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
53 #define IFX_PMU_MODULE_PPE_TC BIT(21)
54 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
55 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
56 #define IFX_PMU_MODULE_AHBS BIT(13)
57 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
59 static inline void vr9_reset_ppe(void)
63 ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_ATM);
65 ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_ATM);
67 ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
69 *PP32_SRST &= ~0x000303CF;
71 *PP32_SRST |= 0x000303CF;
76 static inline int vr9_pp32_download_code(int pp32
, u32
*code_src
, unsigned int code_dword_len
, u32
*data_src
, unsigned int data_dword_len
)
78 unsigned int clr
, set
;
81 if ( code_src
== 0 || ((unsigned long)code_src
& 0x03) != 0
82 || data_src
== 0 || ((unsigned long)data_src
& 0x03) != 0 )
85 clr
= pp32
? 0xF0 : 0x0F;
86 if ( code_dword_len
<= CDM_CODE_MEMORYn_DWLEN(0) )
87 set
= pp32
? (3 << 6): (2 << 2);
90 IFX_REG_W32_MASK(clr
, set
, CDM_CFG
);
92 dest
= CDM_CODE_MEMORY(pp32
, 0);
93 while ( code_dword_len
-- > 0 )
94 IFX_REG_W32(*code_src
++, dest
++);
96 dest
= CDM_DATA_MEMORY(pp32
, 0);
97 while ( data_dword_len
-- > 0 )
98 IFX_REG_W32(*data_src
++, dest
++);
103 static void vr9_fw_ver(unsigned int *major
, unsigned int *minor
)
106 *major
= FW_VER_ID
->major
;
107 *minor
= FW_VER_ID
->minor
;
110 static void vr9_init(void)
116 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01
|
117 IFX_PMU_MODULE_PPE_TC
|
118 IFX_PMU_MODULE_PPE_EMA
|
119 IFX_PMU_MODULE_PPE_QSB
|
120 IFX_PMU_MODULE_AHBS
|
121 IFX_PMU_MODULE_DSL_DFE
);
126 IFX_REG_W32(0x08, PDMA_CFG
);
127 IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG
);
128 IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG
);
131 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC
);
132 IFX_REG_W32(0x00000000, MBOX_IGU1_IER
);
133 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC
);
134 IFX_REG_W32(0x00000000, MBOX_IGU3_IER
);
136 /* tc init - clear sync state */
140 /* init shared buffer */
142 for ( i
= 0; i
< SB_RAM0_DWLEN
+ SB_RAM1_DWLEN
+ SB_RAM2_DWLEN
+ SB_RAM3_DWLEN
; i
++ )
146 for ( i
= 0; i
< SB_RAM6_DWLEN
; i
++ )
150 static void vr9_shutdown(void)
154 static int vr9_start(int pp32
)
156 unsigned int mask
= 1 << (pp32
<< 4);
159 /* download firmware */
160 ret
= vr9_pp32_download_code(pp32
,
161 vr9_fw_bin
, sizeof(vr9_fw_bin
) / sizeof(*vr9_fw_bin
),
162 vr9_fw_data
, sizeof(vr9_fw_data
) / sizeof(*vr9_fw_data
));
167 IFX_REG_W32_MASK(mask
, 0, PP32_FREEZE
);
169 /* idle for a while to let PP32 init itself */
175 static void vr9_stop(int pp32
)
177 unsigned int mask
= 1 << (pp32
<< 4);
179 IFX_REG_W32_MASK(0, mask
, PP32_FREEZE
);
182 struct ltq_atm_ops vr9_ops
= {
184 .shutdown
= vr9_shutdown
,
187 .fw_ver
= vr9_fw_ver
,