1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_core.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
24 *******************************************************************************/
26 #define IFX_ATM_VER_MAJOR 1
27 #define IFX_ATM_VER_MID 0
28 #define IFX_ATM_VER_MINOR 26
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/version.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/proc_fs.h>
36 #include <linux/init.h>
37 #include <linux/ioctl.h>
38 #include <linux/atmdev.h>
39 #include <linux/platform_device.h>
40 #include <linux/of_device.h>
41 #include <linux/atm.h>
42 #include <linux/clk.h>
43 #include <linux/interrupt.h>
48 #include <lantiq_soc.h>
50 #include "ifxmips_atm_core.h"
52 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
53 #define MODULE_PARM(a, b) module_param(a, int, 0)
56 \brief QSB cell delay variation due to concurrency
58 static int qsb_tau
= 1; /* QSB cell delay variation due to concurrency */
60 \brief QSB scheduler burst length
62 static int qsb_srvm
= 0x0F; /* QSB scheduler burst length */
64 \brief QSB time step, all legal values are 1, 2, 4
66 static int qsb_tstep
= 4 ; /* QSB time step, all legal values are 1, 2, 4 */
69 \brief Write descriptor delay
71 static int write_descriptor_delay
= 0x20; /* Write descriptor delay */
74 \brief AAL5 padding byte ('~')
76 static int aal5_fill_pattern
= 0x007E; /* AAL5 padding byte ('~') */
78 \brief Max frame size for RX
80 static int aal5r_max_packet_size
= 0x0700; /* Max frame size for RX */
82 \brief Min frame size for RX
84 static int aal5r_min_packet_size
= 0x0000; /* Min frame size for RX */
86 \brief Max frame size for TX
88 static int aal5s_max_packet_size
= 0x0700; /* Max frame size for TX */
90 \brief Min frame size for TX
92 static int aal5s_min_packet_size
= 0x0000; /* Min frame size for TX */
94 \brief Drop error packet in RX path
96 static int aal5r_drop_error_packet
= 1; /* Drop error packet in RX path */
99 \brief Number of descriptors per DMA RX channel
101 static int dma_rx_descriptor_length
= 128; /* Number of descriptors per DMA RX channel */
103 \brief Number of descriptors per DMA TX channel
105 static int dma_tx_descriptor_length
= 64; /* Number of descriptors per DMA TX channel */
107 \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
109 static int dma_rx_clp1_descriptor_threshold
= 38;
112 MODULE_PARM(qsb_tau
, "i");
113 MODULE_PARM_DESC(qsb_tau
, "Cell delay variation. Value must be > 0");
114 MODULE_PARM(qsb_srvm
, "i");
115 MODULE_PARM_DESC(qsb_srvm
, "Maximum burst size");
116 MODULE_PARM(qsb_tstep
, "i");
117 MODULE_PARM_DESC(qsb_tstep
, "n*32 cycles per sbs cycles n=1,2,4");
119 MODULE_PARM(write_descriptor_delay
, "i");
120 MODULE_PARM_DESC(write_descriptor_delay
, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
122 MODULE_PARM(aal5_fill_pattern
, "i");
123 MODULE_PARM_DESC(aal5_fill_pattern
, "Filling pattern (PAD) for AAL5 frames");
124 MODULE_PARM(aal5r_max_packet_size
, "i");
125 MODULE_PARM_DESC(aal5r_max_packet_size
, "Max packet size in byte for downstream AAL5 frames");
126 MODULE_PARM(aal5r_min_packet_size
, "i");
127 MODULE_PARM_DESC(aal5r_min_packet_size
, "Min packet size in byte for downstream AAL5 frames");
128 MODULE_PARM(aal5s_max_packet_size
, "i");
129 MODULE_PARM_DESC(aal5s_max_packet_size
, "Max packet size in byte for upstream AAL5 frames");
130 MODULE_PARM(aal5s_min_packet_size
, "i");
131 MODULE_PARM_DESC(aal5s_min_packet_size
, "Min packet size in byte for upstream AAL5 frames");
132 MODULE_PARM(aal5r_drop_error_packet
, "i");
133 MODULE_PARM_DESC(aal5r_drop_error_packet
, "Non-zero value to drop error packet for downstream");
135 MODULE_PARM(dma_rx_descriptor_length
, "i");
136 MODULE_PARM_DESC(dma_rx_descriptor_length
, "Number of descriptor assigned to DMA RX channel (>16)");
137 MODULE_PARM(dma_tx_descriptor_length
, "i");
138 MODULE_PARM_DESC(dma_tx_descriptor_length
, "Number of descriptor assigned to DMA TX channel (>16)");
139 MODULE_PARM(dma_rx_clp1_descriptor_threshold
, "i");
140 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold
, "Descriptor threshold for cells with cell loss priority 1");
145 * ####################################
147 * ####################################
150 #ifdef CONFIG_AMAZON_SE
151 #define ENABLE_LESS_CACHE_INV 1
152 #define LESS_CACHE_INV_LEN 96
155 #define DUMP_SKB_LEN ~0
160 * ####################################
162 * ####################################
168 static int ppe_ioctl(struct atm_dev
*, unsigned int, void *);
169 static int ppe_open(struct atm_vcc
*);
170 static void ppe_close(struct atm_vcc
*);
171 static int ppe_send(struct atm_vcc
*, struct sk_buff
*);
172 static int ppe_send_oam(struct atm_vcc
*, void *, int);
173 static int ppe_change_qos(struct atm_vcc
*, struct atm_qos
*, int);
178 static inline void adsl_led_flash(void);
181 * 64-bit operation used by MIB calculation
183 static inline void u64_add_u32(ppe_u64_t
, unsigned int, ppe_u64_t
*);
186 * buffer manage functions
188 static inline struct sk_buff
* alloc_skb_rx(void);
189 static inline struct sk_buff
* alloc_skb_tx(unsigned int);
190 static inline void atm_free_tx_skb_vcc(struct sk_buff
*, struct atm_vcc
*);
191 static inline struct sk_buff
*get_skb_rx_pointer(unsigned int);
192 static inline int get_tx_desc(unsigned int);
195 * mailbox handler and signal function
197 static inline void mailbox_oam_rx_handler(void);
198 static inline void mailbox_aal_rx_handler(void);
199 static irqreturn_t
mailbox_irq_handler(int, void *);
200 static inline void mailbox_signal(unsigned int, int);
201 static void do_ppe_tasklet(unsigned long);
202 DECLARE_TASKLET(g_dma_tasklet
, do_ppe_tasklet
, 0);
205 * QSB & HTU setting functions
207 static void set_qsb(struct atm_vcc
*, struct atm_qos
*, unsigned int);
208 static void qsb_global_set(void);
209 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
210 static inline void clear_htu_entry(unsigned int);
211 static void validate_oam_htu_entry(void);
212 static void invalidate_oam_htu_entry(void);
215 * look up for connection ID
217 static inline int find_vpi(unsigned int);
218 static inline int find_vpivci(unsigned int, unsigned int);
219 static inline int find_vcc(struct atm_vcc
*);
221 static inline int ifx_atm_version(const struct ltq_atm_ops
*ops
, char *);
224 * Init & clean-up functions
226 static inline void check_parameters(void);
227 static inline int init_priv_data(void);
228 static inline void clear_priv_data(void);
229 static inline void init_rx_tables(void);
230 static inline void init_tx_tables(void);
235 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
236 extern void ifx_push_oam(unsigned char *);
238 static inline void ifx_push_oam(unsigned char *dummy
) {}
241 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
242 extern int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
);
243 extern int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *);
245 extern int (*ifx_mei_atm_showtime_exit
)(void);
246 extern int ifx_mei_atm_led_blink(void);
248 static inline int ifx_mei_atm_led_blink(void) { return 0; }
249 static inline int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
)
251 if ( is_showtime
!= NULL
)
255 int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *) = NULL
;
256 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter
);
258 int (*ifx_mei_atm_showtime_exit
)(void) = NULL
;
259 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit
);
263 static struct atm_priv_data g_atm_priv_data
;
265 static struct atmdev_ops g_ifx_atm_ops
= {
270 .send_oam
= ppe_send_oam
,
271 .change_qos
= ppe_change_qos
,
272 .owner
= THIS_MODULE
,
275 static int g_showtime
= 0;
276 static void *g_xdata_addr
= NULL
;
278 static int ppe_ioctl(struct atm_dev
*dev
, unsigned int cmd
, void *arg
)
281 atm_cell_ifEntry_t mib_cell
;
282 atm_aal5_ifEntry_t mib_aal5
;
283 atm_aal5_vcc_x_t mib_vcc
;
287 if ( _IOC_TYPE(cmd
) != PPE_ATM_IOC_MAGIC
288 || _IOC_NR(cmd
) >= PPE_ATM_IOC_MAXNR
)
291 if ( _IOC_DIR(cmd
) & _IOC_READ
)
292 ret
= !access_ok(arg
, _IOC_SIZE(cmd
));
293 else if ( _IOC_DIR(cmd
) & _IOC_WRITE
)
294 ret
= !access_ok(arg
, _IOC_SIZE(cmd
));
299 case PPE_ATM_MIB_CELL
: /* cell level MIB */
300 /* These MIB should be read at ARC side, now put zero only. */
301 mib_cell
.ifHCInOctets_h
= 0;
302 mib_cell
.ifHCInOctets_l
= 0;
303 mib_cell
.ifHCOutOctets_h
= 0;
304 mib_cell
.ifHCOutOctets_l
= 0;
305 mib_cell
.ifInErrors
= 0;
306 mib_cell
.ifInUnknownProtos
= WAN_MIB_TABLE
->wrx_drophtu_cell
;
307 mib_cell
.ifOutErrors
= 0;
309 ret
= sizeof(mib_cell
) - copy_to_user(arg
, &mib_cell
, sizeof(mib_cell
));
312 case PPE_ATM_MIB_AAL5
: /* AAL5 MIB */
313 value
= WAN_MIB_TABLE
->wrx_total_byte
;
314 u64_add_u32(g_atm_priv_data
.wrx_total_byte
, value
- g_atm_priv_data
.prev_wrx_total_byte
, &g_atm_priv_data
.wrx_total_byte
);
315 g_atm_priv_data
.prev_wrx_total_byte
= value
;
316 mib_aal5
.ifHCInOctets_h
= g_atm_priv_data
.wrx_total_byte
.h
;
317 mib_aal5
.ifHCInOctets_l
= g_atm_priv_data
.wrx_total_byte
.l
;
319 value
= WAN_MIB_TABLE
->wtx_total_byte
;
320 u64_add_u32(g_atm_priv_data
.wtx_total_byte
, value
- g_atm_priv_data
.prev_wtx_total_byte
, &g_atm_priv_data
.wtx_total_byte
);
321 g_atm_priv_data
.prev_wtx_total_byte
= value
;
322 mib_aal5
.ifHCOutOctets_h
= g_atm_priv_data
.wtx_total_byte
.h
;
323 mib_aal5
.ifHCOutOctets_l
= g_atm_priv_data
.wtx_total_byte
.l
;
325 mib_aal5
.ifInUcastPkts
= g_atm_priv_data
.wrx_pdu
;
326 mib_aal5
.ifOutUcastPkts
= WAN_MIB_TABLE
->wtx_total_pdu
;
327 mib_aal5
.ifInErrors
= WAN_MIB_TABLE
->wrx_err_pdu
;
328 mib_aal5
.ifInDiscards
= WAN_MIB_TABLE
->wrx_dropdes_pdu
+ g_atm_priv_data
.wrx_drop_pdu
;
329 mib_aal5
.ifOutErros
= g_atm_priv_data
.wtx_err_pdu
;
330 mib_aal5
.ifOutDiscards
= g_atm_priv_data
.wtx_drop_pdu
;
332 ret
= sizeof(mib_aal5
) - copy_to_user(arg
, &mib_aal5
, sizeof(mib_aal5
));
335 case PPE_ATM_MIB_VCC
: /* VCC related MIB */
336 copy_from_user(&mib_vcc
, arg
, sizeof(mib_vcc
));
337 conn
= find_vpivci(mib_vcc
.vpi
, mib_vcc
.vci
);
339 mib_vcc
.mib_vcc
.aal5VccCrcErrors
= g_atm_priv_data
.conn
[conn
].aal5_vcc_crc_err
;
340 mib_vcc
.mib_vcc
.aal5VccOverSizedSDUs
= g_atm_priv_data
.conn
[conn
].aal5_vcc_oversize_sdu
;
341 mib_vcc
.mib_vcc
.aal5VccSarTimeOuts
= 0; /* no timer support */
342 ret
= sizeof(mib_vcc
) - copy_to_user(arg
, &mib_vcc
, sizeof(mib_vcc
));
354 static int ppe_open(struct atm_vcc
*vcc
)
357 short vpi
= vcc
->vpi
;
359 struct port
*port
= &g_atm_priv_data
.port
[(int)vcc
->dev
->dev_data
];
361 int f_enable_irq
= 0;
363 if ( vcc
->qos
.aal
!= ATM_AAL5
&& vcc
->qos
.aal
!= ATM_AAL0
)
364 return -EPROTONOSUPPORT
;
366 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
367 /* check bandwidth */
368 if ( (vcc
->qos
.txtp
.traffic_class
== ATM_CBR
&& vcc
->qos
.txtp
.max_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
369 || (vcc
->qos
.txtp
.traffic_class
== ATM_VBR_RT
&& vcc
->qos
.txtp
.max_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
371 || (vcc
->qos
.txtp
.traffic_class
== ATM_VBR_NRT
&& vcc
->qos
.txtp
.scr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
373 || (vcc
->qos
.txtp
.traffic_class
== ATM_UBR_PLUS
&& vcc
->qos
.txtp
.min_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
)) )
380 /* check existing vpi,vci */
381 conn
= find_vpivci(vpi
, vci
);
387 /* check whether it need to enable irq */
388 if ( g_atm_priv_data
.conn_table
== 0 )
391 /* allocate connection */
392 for ( conn
= 0; conn
< MAX_PVC_NUMBER
; conn
++ ) {
393 if ( test_and_set_bit(conn
, &g_atm_priv_data
.conn_table
) == 0 ) {
394 g_atm_priv_data
.conn
[conn
].vcc
= vcc
;
398 if ( conn
== MAX_PVC_NUMBER
) {
403 /* reserve bandwidth */
404 switch ( vcc
->qos
.txtp
.traffic_class
) {
407 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.max_pcr
;
411 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.scr
;
415 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.min_pcr
;
420 set_qsb(vcc
, &vcc
->qos
, conn
);
422 /* update atm_vcc structure */
423 vcc
->itf
= (int)vcc
->dev
->dev_data
;
426 set_bit(ATM_VF_READY
, &vcc
->flags
);
429 if ( f_enable_irq
) {
430 *MBOX_IGU1_ISRC
= (1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
);
431 *MBOX_IGU1_IER
= (1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
);
433 enable_irq(PPE_MAILBOX_IGU1_INT
);
437 WTX_QUEUE_CONFIG(conn
+ FIRST_QSB_QID
)->sbid
= (int)vcc
->dev
->dev_data
;
440 set_htu_entry(vpi
, vci
, conn
, vcc
->qos
.aal
== ATM_AAL5
? 1 : 0, 0);
442 *MBOX_IGU1_ISRC
|= (1 << (conn
+ FIRST_QSB_QID
+ 16));
443 *MBOX_IGU1_IER
|= (1 << (conn
+ FIRST_QSB_QID
+ 16));
451 static void ppe_close(struct atm_vcc
*vcc
)
455 struct connection
*connection
;
459 /* get connection id */
460 conn
= find_vcc(vcc
);
462 pr_err("can't find vcc\n");
465 connection
= &g_atm_priv_data
.conn
[conn
];
466 port
= &g_atm_priv_data
.port
[connection
->port
];
469 clear_htu_entry(conn
);
471 /* release connection */
472 connection
->vcc
= NULL
;
473 connection
->aal5_vcc_crc_err
= 0;
474 connection
->aal5_vcc_oversize_sdu
= 0;
475 clear_bit(conn
, &g_atm_priv_data
.conn_table
);
478 if ( g_atm_priv_data
.conn_table
== 0 )
479 disable_irq(PPE_MAILBOX_IGU1_INT
);
481 /* release bandwidth */
482 switch ( vcc
->qos
.txtp
.traffic_class
)
486 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.max_pcr
;
490 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.scr
;
494 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.min_pcr
;
498 /* wait for incoming packets to be processed by upper layers */
499 tasklet_unlock_wait(&g_dma_tasklet
);
505 static int ppe_send(struct atm_vcc
*vcc
, struct sk_buff
*skb
)
512 /* the len of the data without offset and header */
515 struct tx_descriptor reg_desc
= {0};
516 struct tx_inband_header
*header
;
518 if ( vcc
== NULL
|| skb
== NULL
)
522 conn
= find_vcc(vcc
);
529 pr_debug("not in showtime\n");
534 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
535 required
= sizeof(*header
) + byteoff
;
536 if (!skb_clone_writable(skb
, required
)) {
540 if (skb_headroom(skb
) < required
)
541 expand_by
= required
- skb_headroom(skb
);
543 ret
= pskb_expand_head(skb
, expand_by
, 0, GFP_ATOMIC
);
545 printk("pskb_expand_head failed.\n");
546 atm_free_tx_skb_vcc(skb
, vcc
);
552 header
= (void *)skb_push(skb
, byteoff
+ TX_INBAND_HEADER_LENGTH
);
555 if ( vcc
->qos
.aal
== ATM_AAL5
) {
556 /* setup inband trailer */
559 header
->pad
= aal5_fill_pattern
;
562 /* setup cell header */
563 header
->clp
= (vcc
->atm_options
& ATM_ATMOPT_CLP
) ? 1 : 0;
564 header
->pti
= ATM_PTI_US0
;
565 header
->vci
= vcc
->vci
;
566 header
->vpi
= vcc
->vpi
;
569 /* setup descriptor */
570 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
571 reg_desc
.datalen
= datalen
;
572 reg_desc
.byteoff
= byteoff
;
575 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
576 reg_desc
.datalen
= skb
->len
;
577 reg_desc
.byteoff
= byteoff
;
583 reg_desc
.sop
= reg_desc
.eop
= 1;
585 spin_lock_irqsave(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
586 desc_base
= get_tx_desc(conn
);
587 if ( desc_base
< 0 ) {
588 spin_unlock_irqrestore(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
589 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
593 /* update descriptor send pointer */
594 if ( g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] != NULL
)
595 dev_kfree_skb_any(g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
]);
596 g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] = skb
;
598 spin_unlock_irqrestore(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
601 atomic_inc(&vcc
->stats
->tx
);
602 if ( vcc
->qos
.aal
== ATM_AAL5
)
603 g_atm_priv_data
.wtx_pdu
++;
604 /* write discriptor to memory and write back cache */
605 g_atm_priv_data
.conn
[conn
].tx_desc
[desc_base
] = reg_desc
;
606 dma_cache_wback((unsigned long)skb
->data
, skb
->len
);
608 mailbox_signal(conn
, 1);
615 pr_err("FIND_VCC_FAIL\n");
616 g_atm_priv_data
.wtx_err_pdu
++;
617 dev_kfree_skb_any(skb
);
621 if ( vcc
->qos
.aal
== ATM_AAL5
)
622 g_atm_priv_data
.wtx_drop_pdu
++;
624 atomic_inc(&vcc
->stats
->tx_err
);
625 dev_kfree_skb_any(skb
);
629 /* operation and maintainance */
630 static int ppe_send_oam(struct atm_vcc
*vcc
, void *cell
, int flags
)
633 struct uni_cell_header
*uni_cell_header
= (struct uni_cell_header
*)cell
;
636 struct tx_descriptor reg_desc
= {0};
638 if ( ((uni_cell_header
->pti
== ATM_PTI_SEGF5
|| uni_cell_header
->pti
== ATM_PTI_E2EF5
)
639 && find_vpivci(uni_cell_header
->vpi
, uni_cell_header
->vci
) < 0)
640 || ((uni_cell_header
->vci
== 0x03 || uni_cell_header
->vci
== 0x04)
641 && find_vpi(uni_cell_header
->vpi
) < 0) )
643 g_atm_priv_data
.wtx_err_oam
++;
648 pr_err("not in showtime\n");
649 g_atm_priv_data
.wtx_drop_oam
++;
653 conn
= find_vcc(vcc
);
655 pr_err("FIND_VCC_FAIL\n");
656 g_atm_priv_data
.wtx_drop_oam
++;
660 skb
= alloc_skb_tx(CELL_SIZE
);
662 pr_err("ALLOC_SKB_TX_FAIL\n");
663 g_atm_priv_data
.wtx_drop_oam
++;
666 skb_put(skb
, CELL_SIZE
);
667 memcpy(skb
->data
, cell
, CELL_SIZE
);
669 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
670 reg_desc
.datalen
= CELL_SIZE
;
671 reg_desc
.byteoff
= 0;
676 reg_desc
.sop
= reg_desc
.eop
= 1;
678 desc_base
= get_tx_desc(conn
);
679 if ( desc_base
< 0 ) {
680 dev_kfree_skb_any(skb
);
681 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
682 g_atm_priv_data
.wtx_drop_oam
++;
687 atomic_inc(&vcc
->stats
->tx
);
689 /* update descriptor send pointer */
690 if ( g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] != NULL
)
691 dev_kfree_skb_any(g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
]);
692 g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] = skb
;
694 /* write discriptor to memory and write back cache */
695 g_atm_priv_data
.conn
[conn
].tx_desc
[desc_base
] = reg_desc
;
696 dma_cache_wback((unsigned long)skb
->data
, CELL_SIZE
);
698 mailbox_signal(conn
, 1);
700 g_atm_priv_data
.wtx_oam
++;
706 static int ppe_change_qos(struct atm_vcc
*vcc
, struct atm_qos
*qos
, int flags
)
710 if ( vcc
== NULL
|| qos
== NULL
)
713 conn
= find_vcc(vcc
);
717 set_qsb(vcc
, qos
, conn
);
722 static inline void adsl_led_flash(void)
724 ifx_mei_atm_led_blink();
729 * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
731 * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
732 * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
733 * ret --- ppe_u64_t, pointer to a variable to hold result
737 static inline void u64_add_u32(ppe_u64_t opt1
, unsigned int opt2
, ppe_u64_t
*ret
)
739 ret
->l
= opt1
.l
+ opt2
;
740 if ( ret
->l
< opt1
.l
|| ret
->l
< opt2
)
744 static inline struct sk_buff
* alloc_skb_rx(void)
748 skb
= dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
);
750 /* must be burst length alignment */
751 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 )
752 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
753 /* pub skb in reserved area "skb->data - 4" */
754 *((struct sk_buff
**)skb
->data
- 1) = skb
;
755 /* write back and invalidate cache */
756 dma_cache_wback_inv((unsigned long)skb
->data
- sizeof(skb
), sizeof(skb
));
757 /* invalidate cache */
758 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
759 dma_cache_inv((unsigned long)skb
->data
, LESS_CACHE_INV_LEN
);
761 dma_cache_inv((unsigned long)skb
->data
, RX_DMA_CH_AAL_BUF_SIZE
);
767 static inline struct sk_buff
* alloc_skb_tx(unsigned int size
)
771 /* allocate memory including header and padding */
772 size
+= TX_INBAND_HEADER_LENGTH
+ MAX_TX_PACKET_ALIGN_BYTES
+ MAX_TX_PACKET_PADDING_BYTES
;
773 size
&= ~(DATA_BUFFER_ALIGNMENT
- 1);
774 skb
= dev_alloc_skb(size
+ DATA_BUFFER_ALIGNMENT
);
775 /* must be burst length alignment */
777 skb_reserve(skb
, (~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1)) + TX_INBAND_HEADER_LENGTH
);
781 static inline void atm_free_tx_skb_vcc(struct sk_buff
*skb
, struct atm_vcc
*vcc
)
783 if ( vcc
->pop
!= NULL
)
786 dev_kfree_skb_any(skb
);
789 static inline struct sk_buff
*get_skb_rx_pointer(unsigned int dataptr
)
791 unsigned int skb_dataptr
;
794 skb_dataptr
= ((dataptr
- 1) << 2) | KSEG1
;
795 skb
= *(struct sk_buff
**)skb_dataptr
;
797 ASSERT((unsigned int)skb
>= KSEG0
, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb
, dataptr
);
798 ASSERT(((unsigned int)skb
->data
| KSEG1
) == ((dataptr
<< 2) | KSEG1
), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb
, (unsigned int)skb
->data
, dataptr
);
803 static inline int get_tx_desc(unsigned int conn
)
806 struct connection
*p_conn
= &g_atm_priv_data
.conn
[conn
];
808 if ( p_conn
->tx_desc
[p_conn
->tx_desc_pos
].own
== 0 ) {
809 desc_base
= p_conn
->tx_desc_pos
;
810 if ( ++(p_conn
->tx_desc_pos
) == dma_tx_descriptor_length
)
811 p_conn
->tx_desc_pos
= 0;
817 static void free_tx_ring(unsigned int queue
)
821 struct connection
*conn
= &g_atm_priv_data
.conn
[queue
];
827 spin_lock_irqsave(&conn
->lock
, flags
);
829 for (i
= 0; i
< dma_tx_descriptor_length
; i
++) {
830 if (conn
->tx_desc
[i
].own
== 0 && conn
->tx_skb
[i
] != NULL
) {
831 skb
= conn
->tx_skb
[i
];
832 conn
->tx_skb
[i
] = NULL
;
833 atm_free_tx_skb_vcc(skb
, ATM_SKB(skb
)->vcc
);
836 spin_unlock_irqrestore(&conn
->lock
, flags
);
839 static void mailbox_tx_handler(unsigned int queue_bitmap
)
844 /* only get valid queues */
845 queue_bitmap
&= g_atm_priv_data
.conn_table
;
847 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
848 if (queue_bitmap
& bit
)
853 static inline void mailbox_oam_rx_handler(void)
855 unsigned int vlddes
= WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM
)->vlddes
;
856 struct rx_descriptor reg_desc
;
857 struct uni_cell_header
*header
;
862 for ( i
= 0; i
< vlddes
; i
++ ) {
863 unsigned int loop_count
= 0;
866 reg_desc
= g_atm_priv_data
.oam_desc
[g_atm_priv_data
.oam_desc_pos
];
867 if ( ++loop_count
== 1000 )
869 } while ( reg_desc
.own
|| !reg_desc
.c
); // keep test OWN and C bit until data is ready
870 ASSERT(loop_count
== 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count
, (int)reg_desc
.own
, (int)reg_desc
.c
, g_atm_priv_data
.oam_desc_pos
);
872 header
= (struct uni_cell_header
*)&g_atm_priv_data
.oam_buf
[g_atm_priv_data
.oam_desc_pos
* RX_DMA_CH_OAM_BUF_SIZE
];
874 if ( header
->pti
== ATM_PTI_SEGF5
|| header
->pti
== ATM_PTI_E2EF5
)
875 conn
= find_vpivci(header
->vpi
, header
->vci
);
876 else if ( header
->vci
== 0x03 || header
->vci
== 0x04 )
877 conn
= find_vpi(header
->vpi
);
881 if ( conn
>= 0 && g_atm_priv_data
.conn
[conn
].vcc
!= NULL
) {
882 vcc
= g_atm_priv_data
.conn
[conn
].vcc
;
884 if ( vcc
->push_oam
!= NULL
)
885 vcc
->push_oam(vcc
, header
);
887 ifx_push_oam((unsigned char *)header
);
889 g_atm_priv_data
.wrx_oam
++;
893 g_atm_priv_data
.wrx_drop_oam
++;
895 reg_desc
.byteoff
= 0;
896 reg_desc
.datalen
= RX_DMA_CH_OAM_BUF_SIZE
;
900 g_atm_priv_data
.oam_desc
[g_atm_priv_data
.oam_desc_pos
] = reg_desc
;
901 if ( ++g_atm_priv_data
.oam_desc_pos
== RX_DMA_CH_OAM_DESC_LEN
)
902 g_atm_priv_data
.oam_desc_pos
= 0;
904 dma_cache_inv((unsigned long)header
, CELL_SIZE
);
905 mailbox_signal(RX_DMA_CH_OAM
, 0);
909 static inline void mailbox_aal_rx_handler(void)
911 unsigned int vlddes
= WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL
)->vlddes
;
912 struct rx_descriptor reg_desc
;
915 struct sk_buff
*skb
, *new_skb
;
916 struct rx_inband_trailer
*trailer
;
919 for ( i
= 0; i
< vlddes
; i
++ ) {
920 unsigned int loop_count
= 0;
923 reg_desc
= g_atm_priv_data
.aal_desc
[g_atm_priv_data
.aal_desc_pos
];
924 if ( ++loop_count
== 1000 )
926 } while ( reg_desc
.own
|| !reg_desc
.c
); // keep test OWN and C bit until data is ready
927 ASSERT(loop_count
== 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count
, (int)reg_desc
.own
, (int)reg_desc
.c
, g_atm_priv_data
.aal_desc_pos
);
931 if ( g_atm_priv_data
.conn
[conn
].vcc
!= NULL
) {
932 vcc
= g_atm_priv_data
.conn
[conn
].vcc
;
934 skb
= get_skb_rx_pointer(reg_desc
.dataptr
);
936 if ( reg_desc
.err
) {
937 if ( vcc
->qos
.aal
== ATM_AAL5
) {
938 trailer
= (struct rx_inband_trailer
*)((unsigned int)skb
->data
+ ((reg_desc
.byteoff
+ reg_desc
.datalen
+ MAX_RX_PACKET_PADDING_BYTES
) & ~MAX_RX_PACKET_PADDING_BYTES
));
939 if ( trailer
->stw_crc
)
940 g_atm_priv_data
.conn
[conn
].aal5_vcc_crc_err
++;
941 if ( trailer
->stw_ovz
)
942 g_atm_priv_data
.conn
[conn
].aal5_vcc_oversize_sdu
++;
943 g_atm_priv_data
.wrx_drop_pdu
++;
946 atomic_inc(&vcc
->stats
->rx_drop
);
947 atomic_inc(&vcc
->stats
->rx_err
);
950 } else if ( atm_charge(vcc
, skb
->truesize
) ) {
951 new_skb
= alloc_skb_rx();
952 if ( new_skb
!= NULL
) {
953 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
954 if ( reg_desc
.byteoff
+ reg_desc
.datalen
> LESS_CACHE_INV_LEN
)
955 dma_cache_inv((unsigned long)skb
->data
+ LESS_CACHE_INV_LEN
, reg_desc
.byteoff
+ reg_desc
.datalen
- LESS_CACHE_INV_LEN
);
958 skb_reserve(skb
, reg_desc
.byteoff
);
959 skb_put(skb
, reg_desc
.datalen
);
960 ATM_SKB(skb
)->vcc
= vcc
;
964 if ( vcc
->qos
.aal
== ATM_AAL5
)
965 g_atm_priv_data
.wrx_pdu
++;
967 atomic_inc(&vcc
->stats
->rx
);
970 reg_desc
.dataptr
= (unsigned int)new_skb
->data
>> 2;
972 atm_return(vcc
, skb
->truesize
);
973 if ( vcc
->qos
.aal
== ATM_AAL5
)
974 g_atm_priv_data
.wrx_drop_pdu
++;
976 atomic_inc(&vcc
->stats
->rx_drop
);
979 if ( vcc
->qos
.aal
== ATM_AAL5
)
980 g_atm_priv_data
.wrx_drop_pdu
++;
982 atomic_inc(&vcc
->stats
->rx_drop
);
985 g_atm_priv_data
.wrx_drop_pdu
++;
988 reg_desc
.byteoff
= 0;
989 reg_desc
.datalen
= RX_DMA_CH_AAL_BUF_SIZE
;
993 g_atm_priv_data
.aal_desc
[g_atm_priv_data
.aal_desc_pos
] = reg_desc
;
994 if ( ++g_atm_priv_data
.aal_desc_pos
== dma_rx_descriptor_length
)
995 g_atm_priv_data
.aal_desc_pos
= 0;
997 mailbox_signal(RX_DMA_CH_AAL
, 0);
1001 static void do_ppe_tasklet(unsigned long data
)
1003 unsigned int irqs
= *MBOX_IGU1_ISR
;
1004 *MBOX_IGU1_ISRC
= *MBOX_IGU1_ISR
;
1006 if (irqs
& (1 << RX_DMA_CH_AAL
))
1007 mailbox_aal_rx_handler();
1008 if (irqs
& (1 << RX_DMA_CH_OAM
))
1009 mailbox_oam_rx_handler();
1011 /* any valid tx irqs */
1012 if ((irqs
>> (FIRST_QSB_QID
+ 16)) & g_atm_priv_data
.conn_table
)
1013 mailbox_tx_handler(irqs
>> (FIRST_QSB_QID
+ 16));
1015 if ((*MBOX_IGU1_ISR
& ((1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
))) != 0)
1016 tasklet_schedule(&g_dma_tasklet
);
1017 else if (*MBOX_IGU1_ISR
>> (FIRST_QSB_QID
+ 16)) /* TX queue */
1018 tasklet_schedule(&g_dma_tasklet
);
1020 enable_irq(PPE_MAILBOX_IGU1_INT
);
1023 static irqreturn_t
mailbox_irq_handler(int irq
, void *dev_id
)
1025 if ( !*MBOX_IGU1_ISR
)
1028 disable_irq_nosync(PPE_MAILBOX_IGU1_INT
);
1029 tasklet_schedule(&g_dma_tasklet
);
1034 static inline void mailbox_signal(unsigned int queue
, int is_tx
)
1039 while ( MBOX_IGU3_ISR_ISR(queue
+ FIRST_QSB_QID
+ 16) && count
> 0 )
1041 *MBOX_IGU3_ISRS
= MBOX_IGU3_ISRS_SET(queue
+ FIRST_QSB_QID
+ 16);
1043 while ( MBOX_IGU3_ISR_ISR(queue
) && count
> 0 )
1045 *MBOX_IGU3_ISRS
= MBOX_IGU3_ISRS_SET(queue
);
1048 ASSERT(count
> 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue
, is_tx
, IFX_REG_R32(MBOX_IGU3_ISR
));
1051 static void set_qsb(struct atm_vcc
*vcc
, struct atm_qos
*qos
, unsigned int queue
)
1053 struct clk
*fpi_clk
= clk_get_fpi();
1054 unsigned int qsb_clk
= clk_get_rate(fpi_clk
);
1055 unsigned int qsb_qid
= queue
+ FIRST_QSB_QID
;
1056 union qsb_queue_parameter_table qsb_queue_parameter_table
= {{0}};
1057 union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table
= {{0}};
1062 * Peak Cell Rate (PCR) Limiter
1064 if ( qos
->txtp
.max_pcr
== 0 )
1065 qsb_queue_parameter_table
.bit
.tp
= 0; /* disable PCR limiter */
1067 /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1068 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / qos
->txtp
.max_pcr
+ 1;
1069 /* check if overflow takes place */
1070 qsb_queue_parameter_table
.bit
.tp
= tmp
> QSB_TP_TS_MAX
? QSB_TP_TS_MAX
: tmp
;
1073 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1074 // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1075 // Send packets to these two PVCs at same time, it trigger strange behavior.
1076 // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1077 // In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1078 // To work around, create UBR always with max_pcr.
1079 // If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1080 if ( qos
->txtp
.traffic_class
== ATM_UBR
&& qsb_queue_parameter_table
.bit
.tp
== 0 ) {
1081 int port
= g_atm_priv_data
.conn
[queue
].port
;
1082 unsigned int max_pcr
= g_atm_priv_data
.port
[port
].tx_max_cell_rate
+ 1000;
1084 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / max_pcr
+ 1;
1085 if ( tmp
> QSB_TP_TS_MAX
)
1086 tmp
= QSB_TP_TS_MAX
;
1089 qsb_queue_parameter_table
.bit
.tp
= tmp
;
1094 * Weighted Fair Queueing Factor (WFQF)
1096 switch ( qos
->txtp
.traffic_class
) {
1099 /* real time queue gets weighted fair queueing bypass */
1100 qsb_queue_parameter_table
.bit
.wfqf
= 0;
1104 /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */
1105 /* WFQF is maximum cell rate / garenteed cell rate */
1106 /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */
1107 if ( qos
->txtp
.min_pcr
== 0 )
1108 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_NONUBR_MAX
;
1110 tmp
= QSB_GCR_MIN
* QSB_WFQ_NONUBR_MAX
/ qos
->txtp
.min_pcr
;
1112 qsb_queue_parameter_table
.bit
.wfqf
= 1;
1113 else if ( tmp
> QSB_WFQ_NONUBR_MAX
)
1114 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_NONUBR_MAX
;
1116 qsb_queue_parameter_table
.bit
.wfqf
= tmp
;
1121 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_UBR_BYPASS
;
1125 * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1127 if ( qos
->txtp
.traffic_class
== ATM_VBR_RT
|| qos
->txtp
.traffic_class
== ATM_VBR_NRT
) {
1129 if ( qos
->txtp
.scr
== 0 ) {
1131 /* disable shaper */
1132 qsb_queue_vbr_parameter_table
.bit
.taus
= 0;
1133 qsb_queue_vbr_parameter_table
.bit
.ts
= 0;
1136 /* Cell Loss Priority (CLP) */
1137 if ( (vcc
->atm_options
& ATM_ATMOPT_CLP
) )
1139 qsb_queue_parameter_table
.bit
.vbr
= 1;
1142 qsb_queue_parameter_table
.bit
.vbr
= 0;
1143 /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1144 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / qos
->txtp
.scr
+ 1;
1145 qsb_queue_vbr_parameter_table
.bit
.ts
= tmp
> QSB_TP_TS_MAX
? QSB_TP_TS_MAX
: tmp
;
1146 tmp
= (qos
->txtp
.mbs
- 1) * (qsb_queue_vbr_parameter_table
.bit
.ts
- qsb_queue_parameter_table
.bit
.tp
) / 64;
1148 qsb_queue_vbr_parameter_table
.bit
.taus
= 1;
1149 else if ( tmp
> QSB_TAUS_MAX
)
1150 qsb_queue_vbr_parameter_table
.bit
.taus
= QSB_TAUS_MAX
;
1152 qsb_queue_vbr_parameter_table
.bit
.taus
= tmp
;
1156 qsb_queue_vbr_parameter_table
.bit
.taus
= 0;
1157 qsb_queue_vbr_parameter_table
.bit
.ts
= 0;
1160 /* Queue Parameter Table (QPT) */
1161 *QSB_RTM
= QSB_RTM_DM_SET(QSB_QPT_SET_MASK
);
1162 *QSB_RTD
= QSB_RTD_TTV_SET(qsb_queue_parameter_table
.dword
);
1163 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT
) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) | QSB_RAMAC_TESEL_SET(qsb_qid
);
1164 /* Queue VBR Paramter Table (QVPT) */
1165 *QSB_RTM
= QSB_RTM_DM_SET(QSB_QVPT_SET_MASK
);
1166 *QSB_RTD
= QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table
.dword
);
1167 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR
) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) | QSB_RAMAC_TESEL_SET(qsb_qid
);
1171 static void qsb_global_set(void)
1173 struct clk
*fpi_clk
= clk_get_fpi();
1174 unsigned int qsb_clk
= clk_get_rate(fpi_clk
);
1176 unsigned int tmp1
, tmp2
, tmp3
;
1178 *QSB_ICDV
= QSB_ICDV_TAU_SET(qsb_tau
);
1179 *QSB_SBL
= QSB_SBL_SBL_SET(qsb_srvm
);
1180 *QSB_CFG
= QSB_CFG_TSTEPC_SET(qsb_tstep
>> 1);
1183 * set SCT and SPT per port
1185 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ ) {
1186 if ( g_atm_priv_data
.port
[i
].tx_max_cell_rate
!= 0 ) {
1187 tmp1
= ((qsb_clk
* qsb_tstep
) >> 1) / g_atm_priv_data
.port
[i
].tx_max_cell_rate
;
1188 tmp2
= tmp1
>> 6; /* integer value of Tsb */
1189 tmp3
= (tmp1
& ((1 << 6) - 1)) + 1; /* fractional part of Tsb */
1190 /* carry over to integer part (?) */
1191 if ( tmp3
== (1 << 6) ) {
1198 /* 2. write value to data transfer register */
1199 /* 3. start the tranfer */
1200 /* SCT (FracRate) */
1201 *QSB_RTM
= QSB_RTM_DM_SET(QSB_SET_SCT_MASK
);
1202 *QSB_RTD
= QSB_RTD_TTV_SET(tmp3
);
1203 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) |
1204 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT
) |
1205 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) |
1206 QSB_RAMAC_TESEL_SET(i
& 0x01);
1207 /* SPT (SBV + PN + IntRage) */
1208 *QSB_RTM
= QSB_RTM_DM_SET(QSB_SET_SPT_MASK
);
1209 *QSB_RTD
= QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID
| QSB_SPT_PN_SET(i
& 0x01) | QSB_SPT_INTRATE_SET(tmp2
));
1210 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) |
1211 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT
) |
1212 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) |
1213 QSB_RAMAC_TESEL_SET(i
& 0x01);
1218 static inline void set_htu_entry(unsigned int vpi
, unsigned int vci
, unsigned int queue
, int aal5
, int is_retx
)
1220 struct htu_entry htu_entry
= {
1222 clp
: is_retx
? 0x01 : 0x00,
1223 pid
: g_atm_priv_data
.conn
[queue
].port
& 0x01,
1229 struct htu_mask htu_mask
= {
1235 pti_mask
: 0x03, // 0xx, user data
1238 struct htu_result htu_result
= {
1242 type
: aal5
? 0x00 : 0x01,
1247 *HTU_RESULT(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_result
;
1248 *HTU_MASK(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_mask
;
1249 *HTU_ENTRY(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_entry
;
1252 static inline void clear_htu_entry(unsigned int queue
)
1254 HTU_ENTRY(queue
+ OAM_HTU_ENTRY_NUMBER
)->vld
= 0;
1257 static void validate_oam_htu_entry(void)
1259 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
)->vld
= 1;
1260 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
)->vld
= 1;
1261 HTU_ENTRY(OAM_F5_HTU_ENTRY
)->vld
= 1;
1264 static void invalidate_oam_htu_entry(void)
1266 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
)->vld
= 0;
1267 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
)->vld
= 0;
1268 HTU_ENTRY(OAM_F5_HTU_ENTRY
)->vld
= 0;
1271 static inline int find_vpi(unsigned int vpi
)
1276 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1277 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1278 && g_atm_priv_data
.conn
[i
].vcc
!= NULL
1279 && vpi
== g_atm_priv_data
.conn
[i
].vcc
->vpi
)
1286 static inline int find_vpivci(unsigned int vpi
, unsigned int vci
)
1291 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1292 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1293 && g_atm_priv_data
.conn
[i
].vcc
!= NULL
1294 && vpi
== g_atm_priv_data
.conn
[i
].vcc
->vpi
1295 && vci
== g_atm_priv_data
.conn
[i
].vcc
->vci
)
1302 static inline int find_vcc(struct atm_vcc
*vcc
)
1307 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1308 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1309 && g_atm_priv_data
.conn
[i
].vcc
== vcc
)
1316 static inline int ifx_atm_version(const struct ltq_atm_ops
*ops
, char *buf
)
1319 unsigned int major
, minor
;
1321 ops
->fw_ver(&major
, &minor
);
1323 len
+= sprintf(buf
+ len
, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR
, IFX_ATM_VER_MID
, IFX_ATM_VER_MINOR
);
1324 len
+= sprintf(buf
+ len
, " ATM (A1) firmware version %d.%d\n", major
, minor
);
1329 static inline void check_parameters(void)
1331 /* Please refer to Amazon spec 15.4 for setting these values. */
1334 if ( qsb_tstep
< 1 )
1336 else if ( qsb_tstep
> 4 )
1338 else if ( qsb_tstep
== 3 )
1341 /* There is a delay between PPE write descriptor and descriptor is */
1342 /* really stored in memory. Host also has this delay when writing */
1343 /* descriptor. So PPE will use this value to determine if the write */
1344 /* operation makes effect. */
1345 if ( write_descriptor_delay
< 0 )
1346 write_descriptor_delay
= 0;
1348 if ( aal5_fill_pattern
< 0 )
1349 aal5_fill_pattern
= 0;
1351 aal5_fill_pattern
&= 0xFF;
1353 /* Because of the limitation of length field in descriptors, the packet */
1354 /* size could not be larger than 64K minus overhead size. */
1355 if ( aal5r_max_packet_size
< 0 )
1356 aal5r_max_packet_size
= 0;
1357 else if ( aal5r_max_packet_size
>= 65535 - MAX_RX_FRAME_EXTRA_BYTES
)
1358 aal5r_max_packet_size
= 65535 - MAX_RX_FRAME_EXTRA_BYTES
;
1359 if ( aal5r_min_packet_size
< 0 )
1360 aal5r_min_packet_size
= 0;
1361 else if ( aal5r_min_packet_size
> aal5r_max_packet_size
)
1362 aal5r_min_packet_size
= aal5r_max_packet_size
;
1363 if ( aal5s_max_packet_size
< 0 )
1364 aal5s_max_packet_size
= 0;
1365 else if ( aal5s_max_packet_size
>= 65535 - MAX_TX_FRAME_EXTRA_BYTES
)
1366 aal5s_max_packet_size
= 65535 - MAX_TX_FRAME_EXTRA_BYTES
;
1367 if ( aal5s_min_packet_size
< 0 )
1368 aal5s_min_packet_size
= 0;
1369 else if ( aal5s_min_packet_size
> aal5s_max_packet_size
)
1370 aal5s_min_packet_size
= aal5s_max_packet_size
;
1372 if ( dma_rx_descriptor_length
< 2 )
1373 dma_rx_descriptor_length
= 2;
1374 if ( dma_tx_descriptor_length
< 2 )
1375 dma_tx_descriptor_length
= 2;
1376 if ( dma_rx_clp1_descriptor_threshold
< 0 )
1377 dma_rx_clp1_descriptor_threshold
= 0;
1378 else if ( dma_rx_clp1_descriptor_threshold
> dma_rx_descriptor_length
)
1379 dma_rx_clp1_descriptor_threshold
= dma_rx_descriptor_length
;
1381 if ( dma_tx_descriptor_length
< 2 )
1382 dma_tx_descriptor_length
= 2;
1385 static inline int init_priv_data(void)
1389 struct rx_descriptor rx_desc
= {0};
1390 struct sk_buff
*skb
;
1391 volatile struct tx_descriptor
*p_tx_desc
;
1392 struct sk_buff
**ppskb
;
1394 // clear atm private data structure
1395 memset(&g_atm_priv_data
, 0, sizeof(g_atm_priv_data
));
1397 // allocate memory for RX (AAL) descriptors
1398 p
= kzalloc(dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1401 dma_cache_wback_inv((unsigned long)p
, dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1402 g_atm_priv_data
.aal_desc_base
= p
;
1403 p
= (void *)((((unsigned int)p
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1404 g_atm_priv_data
.aal_desc
= (volatile struct rx_descriptor
*)p
;
1406 // allocate memory for RX (OAM) descriptors
1407 p
= kzalloc(RX_DMA_CH_OAM_DESC_LEN
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1410 dma_cache_wback_inv((unsigned long)p
, RX_DMA_CH_OAM_DESC_LEN
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1411 g_atm_priv_data
.oam_desc_base
= p
;
1412 p
= (void *)((((unsigned int)p
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1413 g_atm_priv_data
.oam_desc
= (volatile struct rx_descriptor
*)p
;
1415 // allocate memory for RX (OAM) buffer
1416 p
= kzalloc(RX_DMA_CH_OAM_DESC_LEN
* RX_DMA_CH_OAM_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
, GFP_KERNEL
);
1419 dma_cache_wback_inv((unsigned long)p
, RX_DMA_CH_OAM_DESC_LEN
* RX_DMA_CH_OAM_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
);
1420 g_atm_priv_data
.oam_buf_base
= p
;
1421 p
= (void *)(((unsigned int)p
+ DATA_BUFFER_ALIGNMENT
- 1) & ~(DATA_BUFFER_ALIGNMENT
- 1));
1422 g_atm_priv_data
.oam_buf
= p
;
1424 // allocate memory for TX descriptors
1425 p
= kzalloc(MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1428 dma_cache_wback_inv((unsigned long)p
, MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
);
1429 g_atm_priv_data
.tx_desc_base
= p
;
1431 // allocate memory for TX skb pointers
1432 p
= kzalloc(MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4, GFP_KERNEL
);
1435 dma_cache_wback_inv((unsigned long)p
, MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4);
1436 g_atm_priv_data
.tx_skb_base
= p
;
1438 // setup RX (AAL) descriptors
1443 rx_desc
.byteoff
= 0;
1446 rx_desc
.datalen
= RX_DMA_CH_AAL_BUF_SIZE
;
1447 for ( i
= 0; i
< dma_rx_descriptor_length
; i
++ ) {
1448 skb
= alloc_skb_rx();
1451 rx_desc
.dataptr
= ((unsigned int)skb
->data
>> 2) & 0x0FFFFFFF;
1452 g_atm_priv_data
.aal_desc
[i
] = rx_desc
;
1455 // setup RX (OAM) descriptors
1456 p
= (void *)((unsigned int)g_atm_priv_data
.oam_buf
| KSEG1
);
1461 rx_desc
.byteoff
= 0;
1464 rx_desc
.datalen
= RX_DMA_CH_OAM_BUF_SIZE
;
1465 for ( i
= 0; i
< RX_DMA_CH_OAM_DESC_LEN
; i
++ ) {
1466 rx_desc
.dataptr
= ((unsigned int)p
>> 2) & 0x0FFFFFFF;
1467 g_atm_priv_data
.oam_desc
[i
] = rx_desc
;
1468 p
= (void *)((unsigned int)p
+ RX_DMA_CH_OAM_BUF_SIZE
);
1471 // setup TX descriptors and skb pointers
1472 p_tx_desc
= (volatile struct tx_descriptor
*)((((unsigned int)g_atm_priv_data
.tx_desc_base
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1473 ppskb
= (struct sk_buff
**)(((unsigned int)g_atm_priv_data
.tx_skb_base
+ 3) & ~3);
1474 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ ) {
1475 spin_lock_init(&g_atm_priv_data
.conn
[i
].lock
);
1476 g_atm_priv_data
.conn
[i
].tx_desc
= &p_tx_desc
[i
* dma_tx_descriptor_length
];
1477 g_atm_priv_data
.conn
[i
].tx_skb
= &ppskb
[i
* dma_tx_descriptor_length
];
1480 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1481 g_atm_priv_data
.port
[i
].tx_max_cell_rate
= DEFAULT_TX_LINK_RATE
;
1486 static inline void clear_priv_data(void)
1489 struct sk_buff
*skb
;
1491 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ ) {
1492 if ( g_atm_priv_data
.conn
[i
].tx_skb
!= NULL
) {
1493 for ( j
= 0; j
< dma_tx_descriptor_length
; j
++ )
1494 if ( g_atm_priv_data
.conn
[i
].tx_skb
[j
] != NULL
)
1495 dev_kfree_skb_any(g_atm_priv_data
.conn
[i
].tx_skb
[j
]);
1499 if ( g_atm_priv_data
.tx_skb_base
!= NULL
)
1500 kfree(g_atm_priv_data
.tx_skb_base
);
1502 if ( g_atm_priv_data
.tx_desc_base
!= NULL
)
1503 kfree(g_atm_priv_data
.tx_desc_base
);
1505 if ( g_atm_priv_data
.oam_buf_base
!= NULL
)
1506 kfree(g_atm_priv_data
.oam_buf_base
);
1508 if ( g_atm_priv_data
.oam_desc_base
!= NULL
)
1509 kfree(g_atm_priv_data
.oam_desc_base
);
1511 if ( g_atm_priv_data
.aal_desc_base
!= NULL
) {
1512 for ( i
= 0; i
< dma_rx_descriptor_length
; i
++ ) {
1513 if ( g_atm_priv_data
.aal_desc
[i
].sop
|| g_atm_priv_data
.aal_desc
[i
].eop
) { // descriptor initialized
1514 skb
= get_skb_rx_pointer(g_atm_priv_data
.aal_desc
[i
].dataptr
);
1515 dev_kfree_skb_any(skb
);
1518 kfree(g_atm_priv_data
.aal_desc_base
);
1522 static inline void init_rx_tables(void)
1525 struct wrx_queue_config wrx_queue_config
= {0};
1526 struct wrx_dma_channel_config wrx_dma_channel_config
= {0};
1527 struct htu_entry htu_entry
= {0};
1528 struct htu_result htu_result
= {0};
1529 struct htu_mask htu_mask
= {
1542 *CFG_WRX_HTUTS
= MAX_PVC_NUMBER
+ OAM_HTU_ENTRY_NUMBER
;
1543 #ifndef CONFIG_AMAZON_SE
1544 *CFG_WRX_QNUM
= MAX_QUEUE_NUMBER
;
1546 *CFG_WRX_DCHNUM
= RX_DMA_CH_TOTAL
;
1547 *WRX_DMACH_ON
= (1 << RX_DMA_CH_TOTAL
) - 1;
1548 *WRX_HUNT_BITTH
= DEFAULT_RX_HUNT_BITTH
;
1551 * WRX Queue Configuration Table
1553 wrx_queue_config
.uumask
= 0xFF;
1554 wrx_queue_config
.cpimask
= 0xFF;
1555 wrx_queue_config
.uuexp
= 0;
1556 wrx_queue_config
.cpiexp
= 0;
1557 wrx_queue_config
.mfs
= aal5r_max_packet_size
;
1558 wrx_queue_config
.oversize
= aal5r_max_packet_size
;
1559 wrx_queue_config
.undersize
= aal5r_min_packet_size
;
1560 wrx_queue_config
.errdp
= aal5r_drop_error_packet
;
1561 wrx_queue_config
.dmach
= RX_DMA_CH_AAL
;
1562 for ( i
= 0; i
< MAX_QUEUE_NUMBER
; i
++ )
1563 *WRX_QUEUE_CONFIG(i
) = wrx_queue_config
;
1564 WRX_QUEUE_CONFIG(OAM_RX_QUEUE
)->dmach
= RX_DMA_CH_OAM
;
1567 * WRX DMA Channel Configuration Table
1569 wrx_dma_channel_config
.chrl
= 0;
1570 wrx_dma_channel_config
.clp1th
= dma_rx_clp1_descriptor_threshold
;
1571 wrx_dma_channel_config
.mode
= 0;
1572 wrx_dma_channel_config
.rlcfg
= 0;
1574 wrx_dma_channel_config
.deslen
= RX_DMA_CH_OAM_DESC_LEN
;
1575 wrx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.oam_desc
>> 2) & 0x0FFFFFFF;
1576 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM
) = wrx_dma_channel_config
;
1578 wrx_dma_channel_config
.deslen
= dma_rx_descriptor_length
;
1579 wrx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.aal_desc
>> 2) & 0x0FFFFFFF;
1580 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL
) = wrx_dma_channel_config
;
1585 for (i
= 0; i
< MAX_PVC_NUMBER
; i
++) {
1586 htu_result
.qid
= (unsigned int)i
;
1588 *HTU_ENTRY(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_entry
;
1589 *HTU_MASK(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_mask
;
1590 *HTU_RESULT(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_result
;
1594 htu_entry
.vci
= 0x03;
1595 htu_mask
.pid_mask
= 0x03;
1596 htu_mask
.vpi_mask
= 0xFF;
1597 htu_mask
.vci_mask
= 0x0000;
1598 htu_mask
.pti_mask
= 0x07;
1599 htu_result
.cellid
= OAM_RX_QUEUE
;
1600 htu_result
.type
= 1;
1602 htu_result
.qid
= OAM_RX_QUEUE
;
1603 *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY
) = htu_result
;
1604 *HTU_MASK(OAM_F4_SEG_HTU_ENTRY
) = htu_mask
;
1605 *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
) = htu_entry
;
1606 htu_entry
.vci
= 0x04;
1607 htu_result
.cellid
= OAM_RX_QUEUE
;
1608 htu_result
.type
= 1;
1610 htu_result
.qid
= OAM_RX_QUEUE
;
1611 *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY
) = htu_result
;
1612 *HTU_MASK(OAM_F4_TOT_HTU_ENTRY
) = htu_mask
;
1613 *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
) = htu_entry
;
1614 htu_entry
.vci
= 0x00;
1615 htu_entry
.pti
= 0x04;
1616 htu_mask
.vci_mask
= 0xFFFF;
1617 htu_mask
.pti_mask
= 0x01;
1618 htu_result
.cellid
= OAM_RX_QUEUE
;
1619 htu_result
.type
= 1;
1621 htu_result
.qid
= OAM_RX_QUEUE
;
1622 *HTU_RESULT(OAM_F5_HTU_ENTRY
) = htu_result
;
1623 *HTU_MASK(OAM_F5_HTU_ENTRY
) = htu_mask
;
1624 *HTU_ENTRY(OAM_F5_HTU_ENTRY
) = htu_entry
;
1627 static inline void init_tx_tables(void)
1630 struct wtx_queue_config wtx_queue_config
= {0};
1631 struct wtx_dma_channel_config wtx_dma_channel_config
= {0};
1632 struct wtx_port_config wtx_port_config
= {
1641 *CFG_WTX_DCHNUM
= MAX_TX_DMA_CHANNEL_NUMBER
;
1642 *WTX_DMACH_ON
= ((1 << MAX_TX_DMA_CHANNEL_NUMBER
) - 1) ^ ((1 << FIRST_QSB_QID
) - 1);
1643 *CFG_WRDES_DELAY
= write_descriptor_delay
;
1646 * WTX Port Configuration Table
1648 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1649 *WTX_PORT_CONFIG(i
) = wtx_port_config
;
1652 * WTX Queue Configuration Table
1654 wtx_queue_config
.qsben
= 1;
1655 wtx_queue_config
.sbid
= 0;
1656 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1657 wtx_queue_config
.qsb_vcid
= i
;
1658 *WTX_QUEUE_CONFIG(i
) = wtx_queue_config
;
1662 * WTX DMA Channel Configuration Table
1664 wtx_dma_channel_config
.mode
= 0;
1665 wtx_dma_channel_config
.deslen
= 0;
1666 wtx_dma_channel_config
.desba
= 0;
1667 for ( i
= 0; i
< FIRST_QSB_QID
; i
++ )
1668 *WTX_DMA_CHANNEL_CONFIG(i
) = wtx_dma_channel_config
;
1669 /* normal connection */
1670 wtx_dma_channel_config
.deslen
= dma_tx_descriptor_length
;
1671 for ( ; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1672 wtx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.conn
[i
- FIRST_QSB_QID
].tx_desc
>> 2) & 0x0FFFFFFF;
1673 *WTX_DMA_CHANNEL_CONFIG(i
) = wtx_dma_channel_config
;
1677 static int atm_showtime_enter(struct port_cell_info
*port_cell
, void *xdata_addr
)
1681 ASSERT(port_cell
!= NULL
, "port_cell is NULL");
1682 ASSERT(xdata_addr
!= NULL
, "xdata_addr is NULL");
1684 for ( j
= 0; j
< ATM_PORT_NUMBER
&& j
< port_cell
->port_num
; j
++ )
1685 if ( port_cell
->tx_link_rate
[j
] > 0 )
1687 for ( i
= 0; i
< ATM_PORT_NUMBER
&& i
< port_cell
->port_num
; i
++ )
1688 g_atm_priv_data
.port
[i
].tx_max_cell_rate
=
1689 port_cell
->tx_link_rate
[i
] > 0 ? port_cell
->tx_link_rate
[i
] : port_cell
->tx_link_rate
[j
];
1693 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ )
1694 if ( g_atm_priv_data
.conn
[i
].vcc
!= NULL
)
1695 set_qsb(g_atm_priv_data
.conn
[i
].vcc
, &g_atm_priv_data
.conn
[i
].vcc
->qos
, i
);
1697 // TODO: ReTX set xdata_addr
1698 g_xdata_addr
= xdata_addr
;
1702 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1703 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_FOUND
);
1705 #if defined(CONFIG_VR9)
1706 IFX_REG_W32(0x0F, UTP_CFG
);
1709 printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1710 g_atm_priv_data
.port
[0].tx_max_cell_rate
,
1711 g_atm_priv_data
.port
[1].tx_max_cell_rate
,
1712 (unsigned int)g_xdata_addr
);
1717 static int atm_showtime_exit(void)
1724 #if defined(CONFIG_VR9)
1725 IFX_REG_W32(0x00, UTP_CFG
);
1728 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1729 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_LOST
);
1732 g_xdata_addr
= NULL
;
1733 printk("leave showtime\n");
1737 extern struct ltq_atm_ops ar9_ops
;
1738 extern struct ltq_atm_ops vr9_ops
;
1739 extern struct ltq_atm_ops danube_ops
;
1740 extern struct ltq_atm_ops ase_ops
;
1742 static const struct of_device_id ltq_atm_match
[] = {
1743 #ifdef CONFIG_DANUBE
1744 { .compatible
= "lantiq,ppe-danube", .data
= &danube_ops
},
1745 #elif defined CONFIG_AMAZON_SE
1746 { .compatible
= "lantiq,ppe-ase", .data
= &ase_ops
},
1747 #elif defined CONFIG_AR9
1748 { .compatible
= "lantiq,ppe-arx100", .data
= &ar9_ops
},
1749 #elif defined CONFIG_VR9
1750 { .compatible
= "lantiq,ppe-xrx200", .data
= &vr9_ops
},
1754 MODULE_DEVICE_TABLE(of
, ltq_atm_match
);
1756 static int ltq_atm_probe(struct platform_device
*pdev
)
1758 const struct of_device_id
*match
;
1759 struct ltq_atm_ops
*ops
= NULL
;
1762 struct port_cell_info port_cell
= {0};
1765 match
= of_match_device(ltq_atm_match
, &pdev
->dev
);
1767 dev_err(&pdev
->dev
, "failed to find matching device\n");
1770 ops
= (struct ltq_atm_ops
*) match
->data
;
1774 ret
= init_priv_data();
1776 pr_err("INIT_PRIV_DATA_FAIL\n");
1777 goto INIT_PRIV_DATA_FAIL
;
1784 /* create devices */
1785 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ ) {
1786 g_atm_priv_data
.port
[port_num
].dev
= atm_dev_register("ifxmips_atm", NULL
, &g_ifx_atm_ops
, -1, NULL
);
1787 if ( !g_atm_priv_data
.port
[port_num
].dev
) {
1788 pr_err("failed to register atm device %d!\n", port_num
);
1790 goto ATM_DEV_REGISTER_FAIL
;
1792 g_atm_priv_data
.port
[port_num
].dev
->ci_range
.vpi_bits
= 8;
1793 g_atm_priv_data
.port
[port_num
].dev
->ci_range
.vci_bits
= 16;
1794 g_atm_priv_data
.port
[port_num
].dev
->link_rate
= g_atm_priv_data
.port
[port_num
].tx_max_cell_rate
;
1795 g_atm_priv_data
.port
[port_num
].dev
->dev_data
= (void*)port_num
;
1797 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1798 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_LOST
);
1803 /* register interrupt handler */
1804 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, 0, "atm_mailbox_isr", &g_atm_priv_data
);
1806 if ( ret
== -EBUSY
) {
1807 pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1809 pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT
);
1811 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
1813 disable_irq(PPE_MAILBOX_IGU1_INT
);
1816 ret
= ops
->start(0);
1818 pr_err("ifx_pp32_start fail!\n");
1819 goto PP32_START_FAIL
;
1822 port_cell
.port_num
= ATM_PORT_NUMBER
;
1823 ifx_mei_atm_showtime_check(&g_showtime
, &port_cell
, &g_xdata_addr
);
1825 atm_showtime_enter(&port_cell
, &g_xdata_addr
);
1830 validate_oam_htu_entry();
1832 ifx_mei_atm_showtime_enter
= atm_showtime_enter
;
1833 ifx_mei_atm_showtime_exit
= atm_showtime_exit
;
1835 ifx_atm_version(ops
, ver_str
);
1836 printk(KERN_INFO
"%s", ver_str
);
1837 platform_set_drvdata(pdev
, ops
);
1838 printk("ifxmips_atm: ATM init succeed\n");
1843 free_irq(PPE_MAILBOX_IGU1_INT
, &g_atm_priv_data
);
1844 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
:
1845 ATM_DEV_REGISTER_FAIL
:
1846 while ( port_num
-- > 0 )
1847 atm_dev_deregister(g_atm_priv_data
.port
[port_num
].dev
);
1848 INIT_PRIV_DATA_FAIL
:
1850 printk("ifxmips_atm: ATM init failed\n");
1854 static int ltq_atm_remove(struct platform_device
*pdev
)
1857 struct ltq_atm_ops
*ops
= platform_get_drvdata(pdev
);
1859 ifx_mei_atm_showtime_enter
= NULL
;
1860 ifx_mei_atm_showtime_exit
= NULL
;
1862 invalidate_oam_htu_entry();
1866 free_irq(PPE_MAILBOX_IGU1_INT
, &g_atm_priv_data
);
1868 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1869 atm_dev_deregister(g_atm_priv_data
.port
[port_num
].dev
);
1878 static struct platform_driver ltq_atm_driver
= {
1879 .probe
= ltq_atm_probe
,
1880 .remove
= ltq_atm_remove
,
1883 .owner
= THIS_MODULE
,
1884 .of_match_table
= ltq_atm_match
,
1888 module_platform_driver(ltq_atm_driver
);
1890 MODULE_LICENSE("Dual BSD/GPL");