1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_core.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
24 *******************************************************************************/
26 #define IFX_ATM_VER_MAJOR 1
27 #define IFX_ATM_VER_MID 0
28 #define IFX_ATM_VER_MINOR 26
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/version.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/proc_fs.h>
36 #include <linux/init.h>
37 #include <linux/ioctl.h>
38 #include <linux/atmdev.h>
39 #include <linux/platform_device.h>
40 #include <linux/of_device.h>
41 #include <linux/atm.h>
42 #include <linux/clk.h>
43 #include <linux/interrupt.h>
44 #include <linux/version.h>
49 #include <lantiq_soc.h>
51 #include "ifxmips_atm_core.h"
53 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
54 #define MODULE_PARM(a, b) module_param(a, int, 0)
57 \brief QSB cell delay variation due to concurrency
59 static int qsb_tau
= 1; /* QSB cell delay variation due to concurrency */
61 \brief QSB scheduler burst length
63 static int qsb_srvm
= 0x0F; /* QSB scheduler burst length */
65 \brief QSB time step, all legal values are 1, 2, 4
67 static int qsb_tstep
= 4 ; /* QSB time step, all legal values are 1, 2, 4 */
70 \brief Write descriptor delay
72 static int write_descriptor_delay
= 0x20; /* Write descriptor delay */
75 \brief AAL5 padding byte ('~')
77 static int aal5_fill_pattern
= 0x007E; /* AAL5 padding byte ('~') */
79 \brief Max frame size for RX
81 static int aal5r_max_packet_size
= 0x0700; /* Max frame size for RX */
83 \brief Min frame size for RX
85 static int aal5r_min_packet_size
= 0x0000; /* Min frame size for RX */
87 \brief Max frame size for TX
89 static int aal5s_max_packet_size
= 0x0700; /* Max frame size for TX */
91 \brief Min frame size for TX
93 static int aal5s_min_packet_size
= 0x0000; /* Min frame size for TX */
95 \brief Drop error packet in RX path
97 static int aal5r_drop_error_packet
= 1; /* Drop error packet in RX path */
100 \brief Number of descriptors per DMA RX channel
102 static int dma_rx_descriptor_length
= 128; /* Number of descriptors per DMA RX channel */
104 \brief Number of descriptors per DMA TX channel
106 static int dma_tx_descriptor_length
= 64; /* Number of descriptors per DMA TX channel */
108 \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
110 static int dma_rx_clp1_descriptor_threshold
= 38;
113 MODULE_PARM(qsb_tau
, "i");
114 MODULE_PARM_DESC(qsb_tau
, "Cell delay variation. Value must be > 0");
115 MODULE_PARM(qsb_srvm
, "i");
116 MODULE_PARM_DESC(qsb_srvm
, "Maximum burst size");
117 MODULE_PARM(qsb_tstep
, "i");
118 MODULE_PARM_DESC(qsb_tstep
, "n*32 cycles per sbs cycles n=1,2,4");
120 MODULE_PARM(write_descriptor_delay
, "i");
121 MODULE_PARM_DESC(write_descriptor_delay
, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
123 MODULE_PARM(aal5_fill_pattern
, "i");
124 MODULE_PARM_DESC(aal5_fill_pattern
, "Filling pattern (PAD) for AAL5 frames");
125 MODULE_PARM(aal5r_max_packet_size
, "i");
126 MODULE_PARM_DESC(aal5r_max_packet_size
, "Max packet size in byte for downstream AAL5 frames");
127 MODULE_PARM(aal5r_min_packet_size
, "i");
128 MODULE_PARM_DESC(aal5r_min_packet_size
, "Min packet size in byte for downstream AAL5 frames");
129 MODULE_PARM(aal5s_max_packet_size
, "i");
130 MODULE_PARM_DESC(aal5s_max_packet_size
, "Max packet size in byte for upstream AAL5 frames");
131 MODULE_PARM(aal5s_min_packet_size
, "i");
132 MODULE_PARM_DESC(aal5s_min_packet_size
, "Min packet size in byte for upstream AAL5 frames");
133 MODULE_PARM(aal5r_drop_error_packet
, "i");
134 MODULE_PARM_DESC(aal5r_drop_error_packet
, "Non-zero value to drop error packet for downstream");
136 MODULE_PARM(dma_rx_descriptor_length
, "i");
137 MODULE_PARM_DESC(dma_rx_descriptor_length
, "Number of descriptor assigned to DMA RX channel (>16)");
138 MODULE_PARM(dma_tx_descriptor_length
, "i");
139 MODULE_PARM_DESC(dma_tx_descriptor_length
, "Number of descriptor assigned to DMA TX channel (>16)");
140 MODULE_PARM(dma_rx_clp1_descriptor_threshold
, "i");
141 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold
, "Descriptor threshold for cells with cell loss priority 1");
146 * ####################################
148 * ####################################
151 #ifdef CONFIG_AMAZON_SE
152 #define ENABLE_LESS_CACHE_INV 1
153 #define LESS_CACHE_INV_LEN 96
156 #define DUMP_SKB_LEN ~0
161 * ####################################
163 * ####################################
169 static int ppe_ioctl(struct atm_dev
*, unsigned int, void *);
170 static int ppe_open(struct atm_vcc
*);
171 static void ppe_close(struct atm_vcc
*);
172 static int ppe_send(struct atm_vcc
*, struct sk_buff
*);
173 static int ppe_send_oam(struct atm_vcc
*, void *, int);
174 static int ppe_change_qos(struct atm_vcc
*, struct atm_qos
*, int);
179 static inline void adsl_led_flash(void);
182 * 64-bit operation used by MIB calculation
184 static inline void u64_add_u32(ppe_u64_t
, unsigned int, ppe_u64_t
*);
187 * buffer manage functions
189 static inline struct sk_buff
* alloc_skb_rx(void);
190 static inline struct sk_buff
* alloc_skb_tx(unsigned int);
191 static inline void atm_free_tx_skb_vcc(struct sk_buff
*, struct atm_vcc
*);
192 static inline struct sk_buff
*get_skb_rx_pointer(unsigned int);
193 static inline int get_tx_desc(unsigned int);
196 * mailbox handler and signal function
198 static inline void mailbox_oam_rx_handler(void);
199 static inline void mailbox_aal_rx_handler(void);
200 static irqreturn_t
mailbox_irq_handler(int, void *);
201 static inline void mailbox_signal(unsigned int, int);
202 static void do_ppe_tasklet(unsigned long);
203 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)
204 DECLARE_TASKLET(g_dma_tasklet
, do_ppe_tasklet
, 0);
206 DECLARE_TASKLET_OLD(g_dma_tasklet
, do_ppe_tasklet
);
210 * QSB & HTU setting functions
212 static void set_qsb(struct atm_vcc
*, struct atm_qos
*, unsigned int);
213 static void qsb_global_set(void);
214 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
215 static inline void clear_htu_entry(unsigned int);
216 static void validate_oam_htu_entry(void);
217 static void invalidate_oam_htu_entry(void);
220 * look up for connection ID
222 static inline int find_vpi(unsigned int);
223 static inline int find_vpivci(unsigned int, unsigned int);
224 static inline int find_vcc(struct atm_vcc
*);
226 static inline int ifx_atm_version(const struct ltq_atm_ops
*ops
, char *);
229 * Init & clean-up functions
231 static inline void check_parameters(void);
232 static inline int init_priv_data(void);
233 static inline void clear_priv_data(void);
234 static inline void init_rx_tables(void);
235 static inline void init_tx_tables(void);
240 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
241 extern void ifx_push_oam(unsigned char *);
243 static inline void ifx_push_oam(unsigned char *dummy
) {}
246 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
247 extern int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
);
248 extern int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *);
250 extern int (*ifx_mei_atm_showtime_exit
)(void);
251 extern int ifx_mei_atm_led_blink(void);
253 static inline int ifx_mei_atm_led_blink(void) { return 0; }
254 static inline int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
)
256 if ( is_showtime
!= NULL
)
260 int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *) = NULL
;
261 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter
);
263 int (*ifx_mei_atm_showtime_exit
)(void) = NULL
;
264 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit
);
268 static struct atm_priv_data g_atm_priv_data
;
270 static struct atmdev_ops g_ifx_atm_ops
= {
275 .send_oam
= ppe_send_oam
,
276 .change_qos
= ppe_change_qos
,
277 .owner
= THIS_MODULE
,
280 static int g_showtime
= 0;
281 static void *g_xdata_addr
= NULL
;
283 static int ppe_ioctl(struct atm_dev
*dev
, unsigned int cmd
, void *arg
)
286 atm_cell_ifEntry_t mib_cell
;
287 atm_aal5_ifEntry_t mib_aal5
;
288 atm_aal5_vcc_x_t mib_vcc
;
292 if ( _IOC_TYPE(cmd
) != PPE_ATM_IOC_MAGIC
293 || _IOC_NR(cmd
) >= PPE_ATM_IOC_MAXNR
)
296 if ( _IOC_DIR(cmd
) & _IOC_READ
)
297 ret
= !access_ok(arg
, _IOC_SIZE(cmd
));
298 else if ( _IOC_DIR(cmd
) & _IOC_WRITE
)
299 ret
= !access_ok(arg
, _IOC_SIZE(cmd
));
304 case PPE_ATM_MIB_CELL
: /* cell level MIB */
305 /* These MIB should be read at ARC side, now put zero only. */
306 mib_cell
.ifHCInOctets_h
= 0;
307 mib_cell
.ifHCInOctets_l
= 0;
308 mib_cell
.ifHCOutOctets_h
= 0;
309 mib_cell
.ifHCOutOctets_l
= 0;
310 mib_cell
.ifInErrors
= 0;
311 mib_cell
.ifInUnknownProtos
= WAN_MIB_TABLE
->wrx_drophtu_cell
;
312 mib_cell
.ifOutErrors
= 0;
314 ret
= sizeof(mib_cell
) - copy_to_user(arg
, &mib_cell
, sizeof(mib_cell
));
317 case PPE_ATM_MIB_AAL5
: /* AAL5 MIB */
318 value
= WAN_MIB_TABLE
->wrx_total_byte
;
319 u64_add_u32(g_atm_priv_data
.wrx_total_byte
, value
- g_atm_priv_data
.prev_wrx_total_byte
, &g_atm_priv_data
.wrx_total_byte
);
320 g_atm_priv_data
.prev_wrx_total_byte
= value
;
321 mib_aal5
.ifHCInOctets_h
= g_atm_priv_data
.wrx_total_byte
.h
;
322 mib_aal5
.ifHCInOctets_l
= g_atm_priv_data
.wrx_total_byte
.l
;
324 value
= WAN_MIB_TABLE
->wtx_total_byte
;
325 u64_add_u32(g_atm_priv_data
.wtx_total_byte
, value
- g_atm_priv_data
.prev_wtx_total_byte
, &g_atm_priv_data
.wtx_total_byte
);
326 g_atm_priv_data
.prev_wtx_total_byte
= value
;
327 mib_aal5
.ifHCOutOctets_h
= g_atm_priv_data
.wtx_total_byte
.h
;
328 mib_aal5
.ifHCOutOctets_l
= g_atm_priv_data
.wtx_total_byte
.l
;
330 mib_aal5
.ifInUcastPkts
= g_atm_priv_data
.wrx_pdu
;
331 mib_aal5
.ifOutUcastPkts
= WAN_MIB_TABLE
->wtx_total_pdu
;
332 mib_aal5
.ifInErrors
= WAN_MIB_TABLE
->wrx_err_pdu
;
333 mib_aal5
.ifInDiscards
= WAN_MIB_TABLE
->wrx_dropdes_pdu
+ g_atm_priv_data
.wrx_drop_pdu
;
334 mib_aal5
.ifOutErros
= g_atm_priv_data
.wtx_err_pdu
;
335 mib_aal5
.ifOutDiscards
= g_atm_priv_data
.wtx_drop_pdu
;
337 ret
= sizeof(mib_aal5
) - copy_to_user(arg
, &mib_aal5
, sizeof(mib_aal5
));
340 case PPE_ATM_MIB_VCC
: /* VCC related MIB */
341 copy_from_user(&mib_vcc
, arg
, sizeof(mib_vcc
));
342 conn
= find_vpivci(mib_vcc
.vpi
, mib_vcc
.vci
);
344 mib_vcc
.mib_vcc
.aal5VccCrcErrors
= g_atm_priv_data
.conn
[conn
].aal5_vcc_crc_err
;
345 mib_vcc
.mib_vcc
.aal5VccOverSizedSDUs
= g_atm_priv_data
.conn
[conn
].aal5_vcc_oversize_sdu
;
346 mib_vcc
.mib_vcc
.aal5VccSarTimeOuts
= 0; /* no timer support */
347 ret
= sizeof(mib_vcc
) - copy_to_user(arg
, &mib_vcc
, sizeof(mib_vcc
));
359 static int ppe_open(struct atm_vcc
*vcc
)
362 short vpi
= vcc
->vpi
;
364 struct port
*port
= &g_atm_priv_data
.port
[(int)vcc
->dev
->dev_data
];
366 int f_enable_irq
= 0;
368 if ( vcc
->qos
.aal
!= ATM_AAL5
&& vcc
->qos
.aal
!= ATM_AAL0
)
369 return -EPROTONOSUPPORT
;
371 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
372 /* check bandwidth */
373 if ( (vcc
->qos
.txtp
.traffic_class
== ATM_CBR
&& vcc
->qos
.txtp
.max_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
374 || (vcc
->qos
.txtp
.traffic_class
== ATM_VBR_RT
&& vcc
->qos
.txtp
.max_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
376 || (vcc
->qos
.txtp
.traffic_class
== ATM_VBR_NRT
&& vcc
->qos
.txtp
.scr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
378 || (vcc
->qos
.txtp
.traffic_class
== ATM_UBR_PLUS
&& vcc
->qos
.txtp
.min_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
)) )
385 /* check existing vpi,vci */
386 conn
= find_vpivci(vpi
, vci
);
392 /* check whether it need to enable irq */
393 if ( g_atm_priv_data
.conn_table
== 0 )
396 /* allocate connection */
397 for ( conn
= 0; conn
< MAX_PVC_NUMBER
; conn
++ ) {
398 if ( test_and_set_bit(conn
, &g_atm_priv_data
.conn_table
) == 0 ) {
399 g_atm_priv_data
.conn
[conn
].vcc
= vcc
;
403 if ( conn
== MAX_PVC_NUMBER
) {
408 /* reserve bandwidth */
409 switch ( vcc
->qos
.txtp
.traffic_class
) {
412 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.max_pcr
;
416 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.scr
;
420 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.min_pcr
;
425 set_qsb(vcc
, &vcc
->qos
, conn
);
427 /* update atm_vcc structure */
428 vcc
->itf
= (int)vcc
->dev
->dev_data
;
431 set_bit(ATM_VF_READY
, &vcc
->flags
);
434 if ( f_enable_irq
) {
435 *MBOX_IGU1_ISRC
= (1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
);
436 *MBOX_IGU1_IER
= (1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
);
438 enable_irq(g_atm_priv_data
.irq
);
442 WTX_QUEUE_CONFIG(conn
+ FIRST_QSB_QID
)->sbid
= (int)vcc
->dev
->dev_data
;
445 set_htu_entry(vpi
, vci
, conn
, vcc
->qos
.aal
== ATM_AAL5
? 1 : 0, 0);
447 *MBOX_IGU1_ISRC
|= (1 << (conn
+ FIRST_QSB_QID
+ 16));
448 *MBOX_IGU1_IER
|= (1 << (conn
+ FIRST_QSB_QID
+ 16));
456 static void ppe_close(struct atm_vcc
*vcc
)
460 struct connection
*connection
;
464 /* get connection id */
465 conn
= find_vcc(vcc
);
467 pr_err("can't find vcc\n");
470 connection
= &g_atm_priv_data
.conn
[conn
];
471 port
= &g_atm_priv_data
.port
[connection
->port
];
474 clear_htu_entry(conn
);
476 /* release connection */
477 connection
->vcc
= NULL
;
478 connection
->aal5_vcc_crc_err
= 0;
479 connection
->aal5_vcc_oversize_sdu
= 0;
480 clear_bit(conn
, &g_atm_priv_data
.conn_table
);
483 if ( g_atm_priv_data
.conn_table
== 0 )
484 disable_irq(g_atm_priv_data
.irq
);
486 /* release bandwidth */
487 switch ( vcc
->qos
.txtp
.traffic_class
)
491 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.max_pcr
;
495 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.scr
;
499 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.min_pcr
;
503 /* wait for incoming packets to be processed by upper layers */
504 tasklet_unlock_wait(&g_dma_tasklet
);
510 static int ppe_send(struct atm_vcc
*vcc
, struct sk_buff
*skb
)
517 /* the len of the data without offset and header */
520 struct tx_descriptor reg_desc
= {0};
521 struct tx_inband_header
*header
;
523 if ( vcc
== NULL
|| skb
== NULL
)
527 conn
= find_vcc(vcc
);
534 pr_debug("not in showtime\n");
539 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
540 required
= sizeof(*header
) + byteoff
;
541 if (!skb_clone_writable(skb
, required
)) {
545 if (skb_headroom(skb
) < required
)
546 expand_by
= required
- skb_headroom(skb
);
548 ret
= pskb_expand_head(skb
, expand_by
, 0, GFP_ATOMIC
);
550 printk("pskb_expand_head failed.\n");
551 atm_free_tx_skb_vcc(skb
, vcc
);
557 header
= (void *)skb_push(skb
, byteoff
+ TX_INBAND_HEADER_LENGTH
);
560 if ( vcc
->qos
.aal
== ATM_AAL5
) {
561 /* setup inband trailer */
564 header
->pad
= aal5_fill_pattern
;
567 /* setup cell header */
568 header
->clp
= (vcc
->atm_options
& ATM_ATMOPT_CLP
) ? 1 : 0;
569 header
->pti
= ATM_PTI_US0
;
570 header
->vci
= vcc
->vci
;
571 header
->vpi
= vcc
->vpi
;
574 /* setup descriptor */
575 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
576 reg_desc
.datalen
= datalen
;
577 reg_desc
.byteoff
= byteoff
;
580 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
581 reg_desc
.datalen
= skb
->len
;
582 reg_desc
.byteoff
= byteoff
;
588 reg_desc
.sop
= reg_desc
.eop
= 1;
590 spin_lock_irqsave(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
591 desc_base
= get_tx_desc(conn
);
592 if ( desc_base
< 0 ) {
593 spin_unlock_irqrestore(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
594 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
598 /* update descriptor send pointer */
599 if ( g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] != NULL
)
600 dev_kfree_skb_any(g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
]);
601 g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] = skb
;
603 spin_unlock_irqrestore(&g_atm_priv_data
.conn
[conn
].lock
, flags
);
606 atomic_inc(&vcc
->stats
->tx
);
607 if ( vcc
->qos
.aal
== ATM_AAL5
)
608 g_atm_priv_data
.wtx_pdu
++;
609 /* write discriptor to memory and write back cache */
610 g_atm_priv_data
.conn
[conn
].tx_desc
[desc_base
] = reg_desc
;
611 dma_cache_wback((unsigned long)skb
->data
, skb
->len
);
613 mailbox_signal(conn
, 1);
620 pr_err("FIND_VCC_FAIL\n");
621 g_atm_priv_data
.wtx_err_pdu
++;
622 dev_kfree_skb_any(skb
);
626 if ( vcc
->qos
.aal
== ATM_AAL5
)
627 g_atm_priv_data
.wtx_drop_pdu
++;
629 atomic_inc(&vcc
->stats
->tx_err
);
630 dev_kfree_skb_any(skb
);
634 /* operation and maintainance */
635 static int ppe_send_oam(struct atm_vcc
*vcc
, void *cell
, int flags
)
638 struct uni_cell_header
*uni_cell_header
= (struct uni_cell_header
*)cell
;
641 struct tx_descriptor reg_desc
= {0};
643 if ( ((uni_cell_header
->pti
== ATM_PTI_SEGF5
|| uni_cell_header
->pti
== ATM_PTI_E2EF5
)
644 && find_vpivci(uni_cell_header
->vpi
, uni_cell_header
->vci
) < 0)
645 || ((uni_cell_header
->vci
== 0x03 || uni_cell_header
->vci
== 0x04)
646 && find_vpi(uni_cell_header
->vpi
) < 0) )
648 g_atm_priv_data
.wtx_err_oam
++;
653 pr_err("not in showtime\n");
654 g_atm_priv_data
.wtx_drop_oam
++;
658 conn
= find_vcc(vcc
);
660 pr_err("FIND_VCC_FAIL\n");
661 g_atm_priv_data
.wtx_drop_oam
++;
665 skb
= alloc_skb_tx(CELL_SIZE
);
667 pr_err("ALLOC_SKB_TX_FAIL\n");
668 g_atm_priv_data
.wtx_drop_oam
++;
671 skb_put(skb
, CELL_SIZE
);
672 memcpy(skb
->data
, cell
, CELL_SIZE
);
674 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
675 reg_desc
.datalen
= CELL_SIZE
;
676 reg_desc
.byteoff
= 0;
681 reg_desc
.sop
= reg_desc
.eop
= 1;
683 desc_base
= get_tx_desc(conn
);
684 if ( desc_base
< 0 ) {
685 dev_kfree_skb_any(skb
);
686 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
687 g_atm_priv_data
.wtx_drop_oam
++;
692 atomic_inc(&vcc
->stats
->tx
);
694 /* update descriptor send pointer */
695 if ( g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] != NULL
)
696 dev_kfree_skb_any(g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
]);
697 g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] = skb
;
699 /* write discriptor to memory and write back cache */
700 g_atm_priv_data
.conn
[conn
].tx_desc
[desc_base
] = reg_desc
;
701 dma_cache_wback((unsigned long)skb
->data
, CELL_SIZE
);
703 mailbox_signal(conn
, 1);
705 g_atm_priv_data
.wtx_oam
++;
711 static int ppe_change_qos(struct atm_vcc
*vcc
, struct atm_qos
*qos
, int flags
)
715 if ( vcc
== NULL
|| qos
== NULL
)
718 conn
= find_vcc(vcc
);
722 set_qsb(vcc
, qos
, conn
);
727 static inline void adsl_led_flash(void)
729 ifx_mei_atm_led_blink();
734 * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
736 * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
737 * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
738 * ret --- ppe_u64_t, pointer to a variable to hold result
742 static inline void u64_add_u32(ppe_u64_t opt1
, unsigned int opt2
, ppe_u64_t
*ret
)
744 ret
->l
= opt1
.l
+ opt2
;
745 if ( ret
->l
< opt1
.l
|| ret
->l
< opt2
)
749 static inline struct sk_buff
* alloc_skb_rx(void)
753 skb
= dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
);
755 /* must be burst length alignment */
756 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 )
757 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
758 /* pub skb in reserved area "skb->data - 4" */
759 *((struct sk_buff
**)skb
->data
- 1) = skb
;
760 /* write back and invalidate cache */
761 dma_cache_wback_inv((unsigned long)skb
->data
- sizeof(skb
), sizeof(skb
));
762 /* invalidate cache */
763 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
764 dma_cache_inv((unsigned long)skb
->data
, LESS_CACHE_INV_LEN
);
766 dma_cache_inv((unsigned long)skb
->data
, RX_DMA_CH_AAL_BUF_SIZE
);
772 static inline struct sk_buff
* alloc_skb_tx(unsigned int size
)
776 /* allocate memory including header and padding */
777 size
+= TX_INBAND_HEADER_LENGTH
+ MAX_TX_PACKET_ALIGN_BYTES
+ MAX_TX_PACKET_PADDING_BYTES
;
778 size
&= ~(DATA_BUFFER_ALIGNMENT
- 1);
779 skb
= dev_alloc_skb(size
+ DATA_BUFFER_ALIGNMENT
);
780 /* must be burst length alignment */
782 skb_reserve(skb
, (~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1)) + TX_INBAND_HEADER_LENGTH
);
786 static inline void atm_free_tx_skb_vcc(struct sk_buff
*skb
, struct atm_vcc
*vcc
)
788 if ( vcc
->pop
!= NULL
)
791 dev_kfree_skb_any(skb
);
794 static inline struct sk_buff
*get_skb_rx_pointer(unsigned int dataptr
)
796 unsigned int skb_dataptr
;
799 skb_dataptr
= ((dataptr
- 1) << 2) | KSEG1
;
800 skb
= *(struct sk_buff
**)skb_dataptr
;
802 ASSERT((unsigned int)skb
>= KSEG0
, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb
, dataptr
);
803 ASSERT(((unsigned int)skb
->data
| KSEG1
) == ((dataptr
<< 2) | KSEG1
), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb
, (unsigned int)skb
->data
, dataptr
);
808 static inline int get_tx_desc(unsigned int conn
)
811 struct connection
*p_conn
= &g_atm_priv_data
.conn
[conn
];
813 if ( p_conn
->tx_desc
[p_conn
->tx_desc_pos
].own
== 0 ) {
814 desc_base
= p_conn
->tx_desc_pos
;
815 if ( ++(p_conn
->tx_desc_pos
) == dma_tx_descriptor_length
)
816 p_conn
->tx_desc_pos
= 0;
822 static void free_tx_ring(unsigned int queue
)
826 struct connection
*conn
= &g_atm_priv_data
.conn
[queue
];
832 spin_lock_irqsave(&conn
->lock
, flags
);
834 for (i
= 0; i
< dma_tx_descriptor_length
; i
++) {
835 if (conn
->tx_desc
[i
].own
== 0 && conn
->tx_skb
[i
] != NULL
) {
836 skb
= conn
->tx_skb
[i
];
837 conn
->tx_skb
[i
] = NULL
;
838 atm_free_tx_skb_vcc(skb
, ATM_SKB(skb
)->vcc
);
841 spin_unlock_irqrestore(&conn
->lock
, flags
);
844 static void mailbox_tx_handler(unsigned int queue_bitmap
)
849 /* only get valid queues */
850 queue_bitmap
&= g_atm_priv_data
.conn_table
;
852 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
853 if (queue_bitmap
& bit
)
858 static inline void mailbox_oam_rx_handler(void)
860 unsigned int vlddes
= WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM
)->vlddes
;
861 struct rx_descriptor reg_desc
;
862 struct uni_cell_header
*header
;
867 for ( i
= 0; i
< vlddes
; i
++ ) {
868 unsigned int loop_count
= 0;
871 reg_desc
= g_atm_priv_data
.oam_desc
[g_atm_priv_data
.oam_desc_pos
];
872 if ( ++loop_count
== 1000 )
874 } while ( reg_desc
.own
|| !reg_desc
.c
); // keep test OWN and C bit until data is ready
875 ASSERT(loop_count
== 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count
, (int)reg_desc
.own
, (int)reg_desc
.c
, g_atm_priv_data
.oam_desc_pos
);
877 header
= (struct uni_cell_header
*)&g_atm_priv_data
.oam_buf
[g_atm_priv_data
.oam_desc_pos
* RX_DMA_CH_OAM_BUF_SIZE
];
879 if ( header
->pti
== ATM_PTI_SEGF5
|| header
->pti
== ATM_PTI_E2EF5
)
880 conn
= find_vpivci(header
->vpi
, header
->vci
);
881 else if ( header
->vci
== 0x03 || header
->vci
== 0x04 )
882 conn
= find_vpi(header
->vpi
);
886 if ( conn
>= 0 && g_atm_priv_data
.conn
[conn
].vcc
!= NULL
) {
887 vcc
= g_atm_priv_data
.conn
[conn
].vcc
;
889 if ( vcc
->push_oam
!= NULL
)
890 vcc
->push_oam(vcc
, header
);
892 ifx_push_oam((unsigned char *)header
);
894 g_atm_priv_data
.wrx_oam
++;
898 g_atm_priv_data
.wrx_drop_oam
++;
900 reg_desc
.byteoff
= 0;
901 reg_desc
.datalen
= RX_DMA_CH_OAM_BUF_SIZE
;
905 g_atm_priv_data
.oam_desc
[g_atm_priv_data
.oam_desc_pos
] = reg_desc
;
906 if ( ++g_atm_priv_data
.oam_desc_pos
== RX_DMA_CH_OAM_DESC_LEN
)
907 g_atm_priv_data
.oam_desc_pos
= 0;
909 dma_cache_inv((unsigned long)header
, CELL_SIZE
);
910 mailbox_signal(RX_DMA_CH_OAM
, 0);
914 static inline void mailbox_aal_rx_handler(void)
916 unsigned int vlddes
= WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL
)->vlddes
;
917 struct rx_descriptor reg_desc
;
920 struct sk_buff
*skb
, *new_skb
;
921 struct rx_inband_trailer
*trailer
;
924 for ( i
= 0; i
< vlddes
; i
++ ) {
925 unsigned int loop_count
= 0;
928 reg_desc
= g_atm_priv_data
.aal_desc
[g_atm_priv_data
.aal_desc_pos
];
929 if ( ++loop_count
== 1000 )
931 } while ( reg_desc
.own
|| !reg_desc
.c
); // keep test OWN and C bit until data is ready
932 ASSERT(loop_count
== 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count
, (int)reg_desc
.own
, (int)reg_desc
.c
, g_atm_priv_data
.aal_desc_pos
);
936 if ( g_atm_priv_data
.conn
[conn
].vcc
!= NULL
) {
937 vcc
= g_atm_priv_data
.conn
[conn
].vcc
;
939 skb
= get_skb_rx_pointer(reg_desc
.dataptr
);
941 if ( reg_desc
.err
) {
942 if ( vcc
->qos
.aal
== ATM_AAL5
) {
943 trailer
= (struct rx_inband_trailer
*)((unsigned int)skb
->data
+ ((reg_desc
.byteoff
+ reg_desc
.datalen
+ MAX_RX_PACKET_PADDING_BYTES
) & ~MAX_RX_PACKET_PADDING_BYTES
));
944 if ( trailer
->stw_crc
)
945 g_atm_priv_data
.conn
[conn
].aal5_vcc_crc_err
++;
946 if ( trailer
->stw_ovz
)
947 g_atm_priv_data
.conn
[conn
].aal5_vcc_oversize_sdu
++;
948 g_atm_priv_data
.wrx_drop_pdu
++;
951 atomic_inc(&vcc
->stats
->rx_drop
);
952 atomic_inc(&vcc
->stats
->rx_err
);
955 } else if ( atm_charge(vcc
, skb
->truesize
) ) {
956 new_skb
= alloc_skb_rx();
957 if ( new_skb
!= NULL
) {
958 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
959 if ( reg_desc
.byteoff
+ reg_desc
.datalen
> LESS_CACHE_INV_LEN
)
960 dma_cache_inv((unsigned long)skb
->data
+ LESS_CACHE_INV_LEN
, reg_desc
.byteoff
+ reg_desc
.datalen
- LESS_CACHE_INV_LEN
);
963 skb_reserve(skb
, reg_desc
.byteoff
);
964 skb_put(skb
, reg_desc
.datalen
);
965 ATM_SKB(skb
)->vcc
= vcc
;
969 if ( vcc
->qos
.aal
== ATM_AAL5
)
970 g_atm_priv_data
.wrx_pdu
++;
972 atomic_inc(&vcc
->stats
->rx
);
975 reg_desc
.dataptr
= (unsigned int)new_skb
->data
>> 2;
977 atm_return(vcc
, skb
->truesize
);
978 if ( vcc
->qos
.aal
== ATM_AAL5
)
979 g_atm_priv_data
.wrx_drop_pdu
++;
981 atomic_inc(&vcc
->stats
->rx_drop
);
984 if ( vcc
->qos
.aal
== ATM_AAL5
)
985 g_atm_priv_data
.wrx_drop_pdu
++;
987 atomic_inc(&vcc
->stats
->rx_drop
);
990 g_atm_priv_data
.wrx_drop_pdu
++;
993 reg_desc
.byteoff
= 0;
994 reg_desc
.datalen
= RX_DMA_CH_AAL_BUF_SIZE
;
998 g_atm_priv_data
.aal_desc
[g_atm_priv_data
.aal_desc_pos
] = reg_desc
;
999 if ( ++g_atm_priv_data
.aal_desc_pos
== dma_rx_descriptor_length
)
1000 g_atm_priv_data
.aal_desc_pos
= 0;
1002 mailbox_signal(RX_DMA_CH_AAL
, 0);
1006 static void do_ppe_tasklet(unsigned long data
)
1008 unsigned int irqs
= *MBOX_IGU1_ISR
;
1009 *MBOX_IGU1_ISRC
= *MBOX_IGU1_ISR
;
1011 if (irqs
& (1 << RX_DMA_CH_AAL
))
1012 mailbox_aal_rx_handler();
1013 if (irqs
& (1 << RX_DMA_CH_OAM
))
1014 mailbox_oam_rx_handler();
1016 /* any valid tx irqs */
1017 if ((irqs
>> (FIRST_QSB_QID
+ 16)) & g_atm_priv_data
.conn_table
)
1018 mailbox_tx_handler(irqs
>> (FIRST_QSB_QID
+ 16));
1020 if ((*MBOX_IGU1_ISR
& ((1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
))) != 0)
1021 tasklet_schedule(&g_dma_tasklet
);
1022 else if (*MBOX_IGU1_ISR
>> (FIRST_QSB_QID
+ 16)) /* TX queue */
1023 tasklet_schedule(&g_dma_tasklet
);
1025 enable_irq(g_atm_priv_data
.irq
);
1028 static irqreturn_t
mailbox_irq_handler(int irq
, void *dev_id
)
1030 if ( !*MBOX_IGU1_ISR
)
1033 disable_irq_nosync(g_atm_priv_data
.irq
);
1034 tasklet_schedule(&g_dma_tasklet
);
1039 static inline void mailbox_signal(unsigned int queue
, int is_tx
)
1044 while ( MBOX_IGU3_ISR_ISR(queue
+ FIRST_QSB_QID
+ 16) && count
> 0 )
1046 *MBOX_IGU3_ISRS
= MBOX_IGU3_ISRS_SET(queue
+ FIRST_QSB_QID
+ 16);
1048 while ( MBOX_IGU3_ISR_ISR(queue
) && count
> 0 )
1050 *MBOX_IGU3_ISRS
= MBOX_IGU3_ISRS_SET(queue
);
1053 ASSERT(count
> 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue
, is_tx
, IFX_REG_R32(MBOX_IGU3_ISR
));
1056 static void set_qsb(struct atm_vcc
*vcc
, struct atm_qos
*qos
, unsigned int queue
)
1058 struct clk
*fpi_clk
= clk_get_fpi();
1059 unsigned int qsb_clk
= clk_get_rate(fpi_clk
);
1060 unsigned int qsb_qid
= queue
+ FIRST_QSB_QID
;
1061 union qsb_queue_parameter_table qsb_queue_parameter_table
= {{0}};
1062 union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table
= {{0}};
1067 * Peak Cell Rate (PCR) Limiter
1069 if ( qos
->txtp
.max_pcr
== 0 )
1070 qsb_queue_parameter_table
.bit
.tp
= 0; /* disable PCR limiter */
1072 /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1073 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / qos
->txtp
.max_pcr
+ 1;
1074 /* check if overflow takes place */
1075 qsb_queue_parameter_table
.bit
.tp
= tmp
> QSB_TP_TS_MAX
? QSB_TP_TS_MAX
: tmp
;
1078 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1079 // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1080 // Send packets to these two PVCs at same time, it trigger strange behavior.
1081 // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1082 // In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1083 // To work around, create UBR always with max_pcr.
1084 // If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1085 if ( qos
->txtp
.traffic_class
== ATM_UBR
&& qsb_queue_parameter_table
.bit
.tp
== 0 ) {
1086 int port
= g_atm_priv_data
.conn
[queue
].port
;
1087 unsigned int max_pcr
= g_atm_priv_data
.port
[port
].tx_max_cell_rate
+ 1000;
1089 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / max_pcr
+ 1;
1090 if ( tmp
> QSB_TP_TS_MAX
)
1091 tmp
= QSB_TP_TS_MAX
;
1094 qsb_queue_parameter_table
.bit
.tp
= tmp
;
1099 * Weighted Fair Queueing Factor (WFQF)
1101 switch ( qos
->txtp
.traffic_class
) {
1104 /* real time queue gets weighted fair queueing bypass */
1105 qsb_queue_parameter_table
.bit
.wfqf
= 0;
1109 /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */
1110 /* WFQF is maximum cell rate / garenteed cell rate */
1111 /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */
1112 if ( qos
->txtp
.min_pcr
== 0 )
1113 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_NONUBR_MAX
;
1115 tmp
= QSB_GCR_MIN
* QSB_WFQ_NONUBR_MAX
/ qos
->txtp
.min_pcr
;
1117 qsb_queue_parameter_table
.bit
.wfqf
= 1;
1118 else if ( tmp
> QSB_WFQ_NONUBR_MAX
)
1119 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_NONUBR_MAX
;
1121 qsb_queue_parameter_table
.bit
.wfqf
= tmp
;
1126 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_UBR_BYPASS
;
1130 * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1132 if ( qos
->txtp
.traffic_class
== ATM_VBR_RT
|| qos
->txtp
.traffic_class
== ATM_VBR_NRT
) {
1134 if ( qos
->txtp
.scr
== 0 ) {
1136 /* disable shaper */
1137 qsb_queue_vbr_parameter_table
.bit
.taus
= 0;
1138 qsb_queue_vbr_parameter_table
.bit
.ts
= 0;
1141 /* Cell Loss Priority (CLP) */
1142 if ( (vcc
->atm_options
& ATM_ATMOPT_CLP
) )
1144 qsb_queue_parameter_table
.bit
.vbr
= 1;
1147 qsb_queue_parameter_table
.bit
.vbr
= 0;
1148 /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1149 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / qos
->txtp
.scr
+ 1;
1150 qsb_queue_vbr_parameter_table
.bit
.ts
= tmp
> QSB_TP_TS_MAX
? QSB_TP_TS_MAX
: tmp
;
1151 tmp
= (qos
->txtp
.mbs
- 1) * (qsb_queue_vbr_parameter_table
.bit
.ts
- qsb_queue_parameter_table
.bit
.tp
) / 64;
1153 qsb_queue_vbr_parameter_table
.bit
.taus
= 1;
1154 else if ( tmp
> QSB_TAUS_MAX
)
1155 qsb_queue_vbr_parameter_table
.bit
.taus
= QSB_TAUS_MAX
;
1157 qsb_queue_vbr_parameter_table
.bit
.taus
= tmp
;
1161 qsb_queue_vbr_parameter_table
.bit
.taus
= 0;
1162 qsb_queue_vbr_parameter_table
.bit
.ts
= 0;
1165 /* Queue Parameter Table (QPT) */
1166 *QSB_RTM
= QSB_RTM_DM_SET(QSB_QPT_SET_MASK
);
1167 *QSB_RTD
= QSB_RTD_TTV_SET(qsb_queue_parameter_table
.dword
);
1168 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT
) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) | QSB_RAMAC_TESEL_SET(qsb_qid
);
1169 /* Queue VBR Paramter Table (QVPT) */
1170 *QSB_RTM
= QSB_RTM_DM_SET(QSB_QVPT_SET_MASK
);
1171 *QSB_RTD
= QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table
.dword
);
1172 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR
) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) | QSB_RAMAC_TESEL_SET(qsb_qid
);
1176 static void qsb_global_set(void)
1178 struct clk
*fpi_clk
= clk_get_fpi();
1179 unsigned int qsb_clk
= clk_get_rate(fpi_clk
);
1181 unsigned int tmp1
, tmp2
, tmp3
;
1183 *QSB_ICDV
= QSB_ICDV_TAU_SET(qsb_tau
);
1184 *QSB_SBL
= QSB_SBL_SBL_SET(qsb_srvm
);
1185 *QSB_CFG
= QSB_CFG_TSTEPC_SET(qsb_tstep
>> 1);
1188 * set SCT and SPT per port
1190 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ ) {
1191 if ( g_atm_priv_data
.port
[i
].tx_max_cell_rate
!= 0 ) {
1192 tmp1
= ((qsb_clk
* qsb_tstep
) >> 1) / g_atm_priv_data
.port
[i
].tx_max_cell_rate
;
1193 tmp2
= tmp1
>> 6; /* integer value of Tsb */
1194 tmp3
= (tmp1
& ((1 << 6) - 1)) + 1; /* fractional part of Tsb */
1195 /* carry over to integer part (?) */
1196 if ( tmp3
== (1 << 6) ) {
1203 /* 2. write value to data transfer register */
1204 /* 3. start the tranfer */
1205 /* SCT (FracRate) */
1206 *QSB_RTM
= QSB_RTM_DM_SET(QSB_SET_SCT_MASK
);
1207 *QSB_RTD
= QSB_RTD_TTV_SET(tmp3
);
1208 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) |
1209 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT
) |
1210 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) |
1211 QSB_RAMAC_TESEL_SET(i
& 0x01);
1212 /* SPT (SBV + PN + IntRage) */
1213 *QSB_RTM
= QSB_RTM_DM_SET(QSB_SET_SPT_MASK
);
1214 *QSB_RTD
= QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID
| QSB_SPT_PN_SET(i
& 0x01) | QSB_SPT_INTRATE_SET(tmp2
));
1215 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) |
1216 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT
) |
1217 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) |
1218 QSB_RAMAC_TESEL_SET(i
& 0x01);
1223 static inline void set_htu_entry(unsigned int vpi
, unsigned int vci
, unsigned int queue
, int aal5
, int is_retx
)
1225 struct htu_entry htu_entry
= {
1227 clp
: is_retx
? 0x01 : 0x00,
1228 pid
: g_atm_priv_data
.conn
[queue
].port
& 0x01,
1234 struct htu_mask htu_mask
= {
1240 pti_mask
: 0x03, // 0xx, user data
1243 struct htu_result htu_result
= {
1247 type
: aal5
? 0x00 : 0x01,
1252 *HTU_RESULT(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_result
;
1253 *HTU_MASK(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_mask
;
1254 *HTU_ENTRY(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_entry
;
1257 static inline void clear_htu_entry(unsigned int queue
)
1259 HTU_ENTRY(queue
+ OAM_HTU_ENTRY_NUMBER
)->vld
= 0;
1262 static void validate_oam_htu_entry(void)
1264 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
)->vld
= 1;
1265 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
)->vld
= 1;
1266 HTU_ENTRY(OAM_F5_HTU_ENTRY
)->vld
= 1;
1269 static void invalidate_oam_htu_entry(void)
1271 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
)->vld
= 0;
1272 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
)->vld
= 0;
1273 HTU_ENTRY(OAM_F5_HTU_ENTRY
)->vld
= 0;
1276 static inline int find_vpi(unsigned int vpi
)
1281 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1282 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1283 && g_atm_priv_data
.conn
[i
].vcc
!= NULL
1284 && vpi
== g_atm_priv_data
.conn
[i
].vcc
->vpi
)
1291 static inline int find_vpivci(unsigned int vpi
, unsigned int vci
)
1296 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1297 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1298 && g_atm_priv_data
.conn
[i
].vcc
!= NULL
1299 && vpi
== g_atm_priv_data
.conn
[i
].vcc
->vpi
1300 && vci
== g_atm_priv_data
.conn
[i
].vcc
->vci
)
1307 static inline int find_vcc(struct atm_vcc
*vcc
)
1312 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1313 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1314 && g_atm_priv_data
.conn
[i
].vcc
== vcc
)
1321 static inline int ifx_atm_version(const struct ltq_atm_ops
*ops
, char *buf
)
1324 unsigned int major
, minor
;
1326 ops
->fw_ver(&major
, &minor
);
1328 len
+= sprintf(buf
+ len
, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR
, IFX_ATM_VER_MID
, IFX_ATM_VER_MINOR
);
1329 len
+= sprintf(buf
+ len
, " ATM (A1) firmware version %d.%d\n", major
, minor
);
1334 static inline void check_parameters(void)
1336 /* Please refer to Amazon spec 15.4 for setting these values. */
1339 if ( qsb_tstep
< 1 )
1341 else if ( qsb_tstep
> 4 )
1343 else if ( qsb_tstep
== 3 )
1346 /* There is a delay between PPE write descriptor and descriptor is */
1347 /* really stored in memory. Host also has this delay when writing */
1348 /* descriptor. So PPE will use this value to determine if the write */
1349 /* operation makes effect. */
1350 if ( write_descriptor_delay
< 0 )
1351 write_descriptor_delay
= 0;
1353 if ( aal5_fill_pattern
< 0 )
1354 aal5_fill_pattern
= 0;
1356 aal5_fill_pattern
&= 0xFF;
1358 /* Because of the limitation of length field in descriptors, the packet */
1359 /* size could not be larger than 64K minus overhead size. */
1360 if ( aal5r_max_packet_size
< 0 )
1361 aal5r_max_packet_size
= 0;
1362 else if ( aal5r_max_packet_size
>= 65535 - MAX_RX_FRAME_EXTRA_BYTES
)
1363 aal5r_max_packet_size
= 65535 - MAX_RX_FRAME_EXTRA_BYTES
;
1364 if ( aal5r_min_packet_size
< 0 )
1365 aal5r_min_packet_size
= 0;
1366 else if ( aal5r_min_packet_size
> aal5r_max_packet_size
)
1367 aal5r_min_packet_size
= aal5r_max_packet_size
;
1368 if ( aal5s_max_packet_size
< 0 )
1369 aal5s_max_packet_size
= 0;
1370 else if ( aal5s_max_packet_size
>= 65535 - MAX_TX_FRAME_EXTRA_BYTES
)
1371 aal5s_max_packet_size
= 65535 - MAX_TX_FRAME_EXTRA_BYTES
;
1372 if ( aal5s_min_packet_size
< 0 )
1373 aal5s_min_packet_size
= 0;
1374 else if ( aal5s_min_packet_size
> aal5s_max_packet_size
)
1375 aal5s_min_packet_size
= aal5s_max_packet_size
;
1377 if ( dma_rx_descriptor_length
< 2 )
1378 dma_rx_descriptor_length
= 2;
1379 if ( dma_tx_descriptor_length
< 2 )
1380 dma_tx_descriptor_length
= 2;
1381 if ( dma_rx_clp1_descriptor_threshold
< 0 )
1382 dma_rx_clp1_descriptor_threshold
= 0;
1383 else if ( dma_rx_clp1_descriptor_threshold
> dma_rx_descriptor_length
)
1384 dma_rx_clp1_descriptor_threshold
= dma_rx_descriptor_length
;
1386 if ( dma_tx_descriptor_length
< 2 )
1387 dma_tx_descriptor_length
= 2;
1390 static inline int init_priv_data(void)
1394 struct rx_descriptor rx_desc
= {0};
1395 struct sk_buff
*skb
;
1396 volatile struct tx_descriptor
*p_tx_desc
;
1397 struct sk_buff
**ppskb
;
1399 // clear atm private data structure
1400 memset(&g_atm_priv_data
, 0, sizeof(g_atm_priv_data
));
1402 // allocate memory for RX (AAL) descriptors
1403 p
= kzalloc(dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1406 dma_cache_wback_inv((unsigned long)p
, dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1407 g_atm_priv_data
.aal_desc_base
= p
;
1408 p
= (void *)((((unsigned int)p
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1409 g_atm_priv_data
.aal_desc
= (volatile struct rx_descriptor
*)p
;
1411 // allocate memory for RX (OAM) descriptors
1412 p
= kzalloc(RX_DMA_CH_OAM_DESC_LEN
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1415 dma_cache_wback_inv((unsigned long)p
, RX_DMA_CH_OAM_DESC_LEN
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1416 g_atm_priv_data
.oam_desc_base
= p
;
1417 p
= (void *)((((unsigned int)p
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1418 g_atm_priv_data
.oam_desc
= (volatile struct rx_descriptor
*)p
;
1420 // allocate memory for RX (OAM) buffer
1421 p
= kzalloc(RX_DMA_CH_OAM_DESC_LEN
* RX_DMA_CH_OAM_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
, GFP_KERNEL
);
1424 dma_cache_wback_inv((unsigned long)p
, RX_DMA_CH_OAM_DESC_LEN
* RX_DMA_CH_OAM_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
);
1425 g_atm_priv_data
.oam_buf_base
= p
;
1426 p
= (void *)(((unsigned int)p
+ DATA_BUFFER_ALIGNMENT
- 1) & ~(DATA_BUFFER_ALIGNMENT
- 1));
1427 g_atm_priv_data
.oam_buf
= p
;
1429 // allocate memory for TX descriptors
1430 p
= kzalloc(MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1433 dma_cache_wback_inv((unsigned long)p
, MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
);
1434 g_atm_priv_data
.tx_desc_base
= p
;
1436 // allocate memory for TX skb pointers
1437 p
= kzalloc(MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4, GFP_KERNEL
);
1440 dma_cache_wback_inv((unsigned long)p
, MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4);
1441 g_atm_priv_data
.tx_skb_base
= p
;
1443 // setup RX (AAL) descriptors
1448 rx_desc
.byteoff
= 0;
1451 rx_desc
.datalen
= RX_DMA_CH_AAL_BUF_SIZE
;
1452 for ( i
= 0; i
< dma_rx_descriptor_length
; i
++ ) {
1453 skb
= alloc_skb_rx();
1456 rx_desc
.dataptr
= ((unsigned int)skb
->data
>> 2) & 0x0FFFFFFF;
1457 g_atm_priv_data
.aal_desc
[i
] = rx_desc
;
1460 // setup RX (OAM) descriptors
1461 p
= (void *)((unsigned int)g_atm_priv_data
.oam_buf
| KSEG1
);
1466 rx_desc
.byteoff
= 0;
1469 rx_desc
.datalen
= RX_DMA_CH_OAM_BUF_SIZE
;
1470 for ( i
= 0; i
< RX_DMA_CH_OAM_DESC_LEN
; i
++ ) {
1471 rx_desc
.dataptr
= ((unsigned int)p
>> 2) & 0x0FFFFFFF;
1472 g_atm_priv_data
.oam_desc
[i
] = rx_desc
;
1473 p
= (void *)((unsigned int)p
+ RX_DMA_CH_OAM_BUF_SIZE
);
1476 // setup TX descriptors and skb pointers
1477 p_tx_desc
= (volatile struct tx_descriptor
*)((((unsigned int)g_atm_priv_data
.tx_desc_base
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1478 ppskb
= (struct sk_buff
**)(((unsigned int)g_atm_priv_data
.tx_skb_base
+ 3) & ~3);
1479 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ ) {
1480 spin_lock_init(&g_atm_priv_data
.conn
[i
].lock
);
1481 g_atm_priv_data
.conn
[i
].tx_desc
= &p_tx_desc
[i
* dma_tx_descriptor_length
];
1482 g_atm_priv_data
.conn
[i
].tx_skb
= &ppskb
[i
* dma_tx_descriptor_length
];
1485 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1486 g_atm_priv_data
.port
[i
].tx_max_cell_rate
= DEFAULT_TX_LINK_RATE
;
1491 static inline void clear_priv_data(void)
1494 struct sk_buff
*skb
;
1496 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ ) {
1497 if ( g_atm_priv_data
.conn
[i
].tx_skb
!= NULL
) {
1498 for ( j
= 0; j
< dma_tx_descriptor_length
; j
++ )
1499 if ( g_atm_priv_data
.conn
[i
].tx_skb
[j
] != NULL
)
1500 dev_kfree_skb_any(g_atm_priv_data
.conn
[i
].tx_skb
[j
]);
1504 if ( g_atm_priv_data
.tx_skb_base
!= NULL
)
1505 kfree(g_atm_priv_data
.tx_skb_base
);
1507 if ( g_atm_priv_data
.tx_desc_base
!= NULL
)
1508 kfree(g_atm_priv_data
.tx_desc_base
);
1510 if ( g_atm_priv_data
.oam_buf_base
!= NULL
)
1511 kfree(g_atm_priv_data
.oam_buf_base
);
1513 if ( g_atm_priv_data
.oam_desc_base
!= NULL
)
1514 kfree(g_atm_priv_data
.oam_desc_base
);
1516 if ( g_atm_priv_data
.aal_desc_base
!= NULL
) {
1517 for ( i
= 0; i
< dma_rx_descriptor_length
; i
++ ) {
1518 if ( g_atm_priv_data
.aal_desc
[i
].sop
|| g_atm_priv_data
.aal_desc
[i
].eop
) { // descriptor initialized
1519 skb
= get_skb_rx_pointer(g_atm_priv_data
.aal_desc
[i
].dataptr
);
1520 dev_kfree_skb_any(skb
);
1523 kfree(g_atm_priv_data
.aal_desc_base
);
1527 static inline void init_rx_tables(void)
1530 struct wrx_queue_config wrx_queue_config
= {0};
1531 struct wrx_dma_channel_config wrx_dma_channel_config
= {0};
1532 struct htu_entry htu_entry
= {0};
1533 struct htu_result htu_result
= {0};
1534 struct htu_mask htu_mask
= {
1547 *CFG_WRX_HTUTS
= MAX_PVC_NUMBER
+ OAM_HTU_ENTRY_NUMBER
;
1548 #ifndef CONFIG_AMAZON_SE
1549 *CFG_WRX_QNUM
= MAX_QUEUE_NUMBER
;
1551 *CFG_WRX_DCHNUM
= RX_DMA_CH_TOTAL
;
1552 *WRX_DMACH_ON
= (1 << RX_DMA_CH_TOTAL
) - 1;
1553 *WRX_HUNT_BITTH
= DEFAULT_RX_HUNT_BITTH
;
1556 * WRX Queue Configuration Table
1558 wrx_queue_config
.uumask
= 0xFF;
1559 wrx_queue_config
.cpimask
= 0xFF;
1560 wrx_queue_config
.uuexp
= 0;
1561 wrx_queue_config
.cpiexp
= 0;
1562 wrx_queue_config
.mfs
= aal5r_max_packet_size
;
1563 wrx_queue_config
.oversize
= aal5r_max_packet_size
;
1564 wrx_queue_config
.undersize
= aal5r_min_packet_size
;
1565 wrx_queue_config
.errdp
= aal5r_drop_error_packet
;
1566 wrx_queue_config
.dmach
= RX_DMA_CH_AAL
;
1567 for ( i
= 0; i
< MAX_QUEUE_NUMBER
; i
++ )
1568 *WRX_QUEUE_CONFIG(i
) = wrx_queue_config
;
1569 WRX_QUEUE_CONFIG(OAM_RX_QUEUE
)->dmach
= RX_DMA_CH_OAM
;
1572 * WRX DMA Channel Configuration Table
1574 wrx_dma_channel_config
.chrl
= 0;
1575 wrx_dma_channel_config
.clp1th
= dma_rx_clp1_descriptor_threshold
;
1576 wrx_dma_channel_config
.mode
= 0;
1577 wrx_dma_channel_config
.rlcfg
= 0;
1579 wrx_dma_channel_config
.deslen
= RX_DMA_CH_OAM_DESC_LEN
;
1580 wrx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.oam_desc
>> 2) & 0x0FFFFFFF;
1581 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM
) = wrx_dma_channel_config
;
1583 wrx_dma_channel_config
.deslen
= dma_rx_descriptor_length
;
1584 wrx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.aal_desc
>> 2) & 0x0FFFFFFF;
1585 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL
) = wrx_dma_channel_config
;
1590 for (i
= 0; i
< MAX_PVC_NUMBER
; i
++) {
1591 htu_result
.qid
= (unsigned int)i
;
1593 *HTU_ENTRY(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_entry
;
1594 *HTU_MASK(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_mask
;
1595 *HTU_RESULT(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_result
;
1599 htu_entry
.vci
= 0x03;
1600 htu_mask
.pid_mask
= 0x03;
1601 htu_mask
.vpi_mask
= 0xFF;
1602 htu_mask
.vci_mask
= 0x0000;
1603 htu_mask
.pti_mask
= 0x07;
1604 htu_result
.cellid
= OAM_RX_QUEUE
;
1605 htu_result
.type
= 1;
1607 htu_result
.qid
= OAM_RX_QUEUE
;
1608 *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY
) = htu_result
;
1609 *HTU_MASK(OAM_F4_SEG_HTU_ENTRY
) = htu_mask
;
1610 *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
) = htu_entry
;
1611 htu_entry
.vci
= 0x04;
1612 htu_result
.cellid
= OAM_RX_QUEUE
;
1613 htu_result
.type
= 1;
1615 htu_result
.qid
= OAM_RX_QUEUE
;
1616 *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY
) = htu_result
;
1617 *HTU_MASK(OAM_F4_TOT_HTU_ENTRY
) = htu_mask
;
1618 *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
) = htu_entry
;
1619 htu_entry
.vci
= 0x00;
1620 htu_entry
.pti
= 0x04;
1621 htu_mask
.vci_mask
= 0xFFFF;
1622 htu_mask
.pti_mask
= 0x01;
1623 htu_result
.cellid
= OAM_RX_QUEUE
;
1624 htu_result
.type
= 1;
1626 htu_result
.qid
= OAM_RX_QUEUE
;
1627 *HTU_RESULT(OAM_F5_HTU_ENTRY
) = htu_result
;
1628 *HTU_MASK(OAM_F5_HTU_ENTRY
) = htu_mask
;
1629 *HTU_ENTRY(OAM_F5_HTU_ENTRY
) = htu_entry
;
1632 static inline void init_tx_tables(void)
1635 struct wtx_queue_config wtx_queue_config
= {0};
1636 struct wtx_dma_channel_config wtx_dma_channel_config
= {0};
1637 struct wtx_port_config wtx_port_config
= {
1646 *CFG_WTX_DCHNUM
= MAX_TX_DMA_CHANNEL_NUMBER
;
1647 *WTX_DMACH_ON
= ((1 << MAX_TX_DMA_CHANNEL_NUMBER
) - 1) ^ ((1 << FIRST_QSB_QID
) - 1);
1648 *CFG_WRDES_DELAY
= write_descriptor_delay
;
1651 * WTX Port Configuration Table
1653 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1654 *WTX_PORT_CONFIG(i
) = wtx_port_config
;
1657 * WTX Queue Configuration Table
1659 wtx_queue_config
.qsben
= 1;
1660 wtx_queue_config
.sbid
= 0;
1661 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1662 wtx_queue_config
.qsb_vcid
= i
;
1663 *WTX_QUEUE_CONFIG(i
) = wtx_queue_config
;
1667 * WTX DMA Channel Configuration Table
1669 wtx_dma_channel_config
.mode
= 0;
1670 wtx_dma_channel_config
.deslen
= 0;
1671 wtx_dma_channel_config
.desba
= 0;
1672 for ( i
= 0; i
< FIRST_QSB_QID
; i
++ )
1673 *WTX_DMA_CHANNEL_CONFIG(i
) = wtx_dma_channel_config
;
1674 /* normal connection */
1675 wtx_dma_channel_config
.deslen
= dma_tx_descriptor_length
;
1676 for ( ; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1677 wtx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.conn
[i
- FIRST_QSB_QID
].tx_desc
>> 2) & 0x0FFFFFFF;
1678 *WTX_DMA_CHANNEL_CONFIG(i
) = wtx_dma_channel_config
;
1682 static int atm_showtime_enter(struct port_cell_info
*port_cell
, void *xdata_addr
)
1686 ASSERT(port_cell
!= NULL
, "port_cell is NULL");
1687 ASSERT(xdata_addr
!= NULL
, "xdata_addr is NULL");
1689 for ( j
= 0; j
< ATM_PORT_NUMBER
&& j
< port_cell
->port_num
; j
++ )
1690 if ( port_cell
->tx_link_rate
[j
] > 0 )
1692 for ( i
= 0; i
< ATM_PORT_NUMBER
&& i
< port_cell
->port_num
; i
++ )
1693 g_atm_priv_data
.port
[i
].tx_max_cell_rate
=
1694 port_cell
->tx_link_rate
[i
] > 0 ? port_cell
->tx_link_rate
[i
] : port_cell
->tx_link_rate
[j
];
1698 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ )
1699 if ( g_atm_priv_data
.conn
[i
].vcc
!= NULL
)
1700 set_qsb(g_atm_priv_data
.conn
[i
].vcc
, &g_atm_priv_data
.conn
[i
].vcc
->qos
, i
);
1702 // TODO: ReTX set xdata_addr
1703 g_xdata_addr
= xdata_addr
;
1707 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1708 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_FOUND
);
1710 #if defined(CONFIG_VR9)
1711 IFX_REG_W32(0x0F, UTP_CFG
);
1714 printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1715 g_atm_priv_data
.port
[0].tx_max_cell_rate
,
1716 g_atm_priv_data
.port
[1].tx_max_cell_rate
,
1717 (unsigned int)g_xdata_addr
);
1722 static int atm_showtime_exit(void)
1729 #if defined(CONFIG_VR9)
1730 IFX_REG_W32(0x00, UTP_CFG
);
1733 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1734 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_LOST
);
1737 g_xdata_addr
= NULL
;
1738 printk("leave showtime\n");
1742 extern struct ltq_atm_ops ar9_ops
;
1743 extern struct ltq_atm_ops vr9_ops
;
1744 extern struct ltq_atm_ops danube_ops
;
1745 extern struct ltq_atm_ops ase_ops
;
1747 static const struct of_device_id ltq_atm_match
[] = {
1748 #ifdef CONFIG_DANUBE
1749 { .compatible
= "lantiq,ppe-danube", .data
= &danube_ops
},
1750 #elif defined CONFIG_AMAZON_SE
1751 { .compatible
= "lantiq,ppe-ase", .data
= &ase_ops
},
1752 #elif defined CONFIG_AR9
1753 { .compatible
= "lantiq,ppe-arx100", .data
= &ar9_ops
},
1754 #elif defined CONFIG_VR9
1755 { .compatible
= "lantiq,ppe-xrx200", .data
= &vr9_ops
},
1759 MODULE_DEVICE_TABLE(of
, ltq_atm_match
);
1761 static int ltq_atm_probe(struct platform_device
*pdev
)
1763 const struct of_device_id
*match
;
1764 struct ltq_atm_ops
*ops
= NULL
;
1767 struct port_cell_info port_cell
= {0};
1770 match
= of_match_device(ltq_atm_match
, &pdev
->dev
);
1772 dev_err(&pdev
->dev
, "failed to find matching device\n");
1775 ops
= (struct ltq_atm_ops
*) match
->data
;
1779 ret
= init_priv_data();
1781 pr_err("INIT_PRIV_DATA_FAIL\n");
1782 goto INIT_PRIV_DATA_FAIL
;
1789 /* create devices */
1790 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ ) {
1791 g_atm_priv_data
.port
[port_num
].dev
= atm_dev_register("ifxmips_atm", NULL
, &g_ifx_atm_ops
, -1, NULL
);
1792 if ( !g_atm_priv_data
.port
[port_num
].dev
) {
1793 pr_err("failed to register atm device %d!\n", port_num
);
1795 goto ATM_DEV_REGISTER_FAIL
;
1797 g_atm_priv_data
.port
[port_num
].dev
->ci_range
.vpi_bits
= 8;
1798 g_atm_priv_data
.port
[port_num
].dev
->ci_range
.vci_bits
= 16;
1799 g_atm_priv_data
.port
[port_num
].dev
->link_rate
= g_atm_priv_data
.port
[port_num
].tx_max_cell_rate
;
1800 g_atm_priv_data
.port
[port_num
].dev
->dev_data
= (void*)port_num
;
1802 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1803 atm_dev_signal_change(g_atm_priv_data
.port
[port_num
].dev
, ATM_PHY_SIG_LOST
);
1808 g_atm_priv_data
.irq
= platform_get_irq(pdev
, 0);
1809 if (g_atm_priv_data
.irq
< 0) {
1810 pr_err("platform_get_irq fail");
1811 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
1814 /* register interrupt handler */
1815 ret
= request_irq(g_atm_priv_data
.irq
, mailbox_irq_handler
, 0, "atm_mailbox_isr", &g_atm_priv_data
);
1817 if ( ret
== -EBUSY
) {
1818 pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1820 pr_err("request_irq fail irq:%d\n", g_atm_priv_data
.irq
);
1822 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
1824 disable_irq(g_atm_priv_data
.irq
);
1827 ret
= ops
->start(0);
1829 pr_err("ifx_pp32_start fail!\n");
1830 goto PP32_START_FAIL
;
1833 port_cell
.port_num
= ATM_PORT_NUMBER
;
1834 ifx_mei_atm_showtime_check(&g_showtime
, &port_cell
, &g_xdata_addr
);
1836 atm_showtime_enter(&port_cell
, &g_xdata_addr
);
1841 validate_oam_htu_entry();
1843 ifx_mei_atm_showtime_enter
= atm_showtime_enter
;
1844 ifx_mei_atm_showtime_exit
= atm_showtime_exit
;
1846 ifx_atm_version(ops
, ver_str
);
1847 printk(KERN_INFO
"%s", ver_str
);
1848 platform_set_drvdata(pdev
, ops
);
1849 printk("ifxmips_atm: ATM init succeed\n");
1854 free_irq(g_atm_priv_data
.irq
, &g_atm_priv_data
);
1855 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
:
1856 ATM_DEV_REGISTER_FAIL
:
1857 while ( port_num
-- > 0 )
1858 atm_dev_deregister(g_atm_priv_data
.port
[port_num
].dev
);
1859 INIT_PRIV_DATA_FAIL
:
1861 printk("ifxmips_atm: ATM init failed\n");
1865 static int ltq_atm_remove(struct platform_device
*pdev
)
1868 struct ltq_atm_ops
*ops
= platform_get_drvdata(pdev
);
1870 ifx_mei_atm_showtime_enter
= NULL
;
1871 ifx_mei_atm_showtime_exit
= NULL
;
1873 invalidate_oam_htu_entry();
1877 free_irq(g_atm_priv_data
.irq
, &g_atm_priv_data
);
1879 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1880 atm_dev_deregister(g_atm_priv_data
.port
[port_num
].dev
);
1889 static struct platform_driver ltq_atm_driver
= {
1890 .probe
= ltq_atm_probe
,
1891 .remove
= ltq_atm_remove
,
1894 .owner
= THIS_MODULE
,
1895 .of_match_table
= ltq_atm_match
,
1899 module_platform_driver(ltq_atm_driver
);
1901 MODULE_LICENSE("Dual BSD/GPL");