package/kernel/lantiq/ltq-deu/src/ifxmips_aes.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_aes.c
   4 ** PROJECT      : IFX UEIP
   5 ** MODULES      : DEU Module
   6 **
   7 ** DATE         : September 8, 2009
   8 ** AUTHOR       : Mohammad Firdaus
   9 ** DESCRIPTION  : Data Encryption Unit Driver for AES Algorithm
  10 ** COPYRIGHT    :       Copyright (c) 2009
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author             $Comment
  21 ** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release
  22 *******************************************************************************/
  23 /*!
  24  \defgroup IFX_DEU IFX_DEU_DRIVERS
  25  \ingroup API
  26  \brief ifx DEU driver module
  27 */
  28
  29 /*!
  30   \file ifxmips_aes.c
  31   \ingroup IFX_DEU
  32   \brief AES Encryption Driver main file
  33 */
  34
  35 /*!
  36  \defgroup IFX_AES_FUNCTIONS IFX_AES_FUNCTIONS
  37  \ingroup IFX_DEU
  38  \brief IFX AES driver Functions
  39 */
  40
  41
  42 /* Project Header Files */
  43 #if defined(CONFIG_MODVERSIONS)
  44 #define MODVERSIONS
  45 #include <linux/modeversions>
  46 #endif
  47
  48 #include <linux/version.h>
  49 #include <linux/module.h>
  50 #include <linux/init.h>
  51 #include <linux/proc_fs.h>
  52 #include <linux/fs.h>
  53 #include <linux/types.h>
  54 #include <linux/errno.h>
  55 #include <linux/crypto.h>
  56 #include <linux/interrupt.h>
  57 #include <linux/delay.h>
  58 #include <asm/byteorder.h>
  59 #include <crypto/algapi.h>
  60 #include <crypto/internal/skcipher.h>
  61
  62 #include "ifxmips_deu.h"
  63
  64 #if defined(CONFIG_DANUBE)
  65 #include "ifxmips_deu_danube.h"
  66 extern int ifx_danube_pre_1_4;
  67 #elif defined(CONFIG_AR9)
  68 #include "ifxmips_deu_ar9.h"
  69 #elif defined(CONFIG_VR9) || defined(CONFIG_AR10)
  70 #include "ifxmips_deu_vr9.h"
  71 #else
  72 #error "Unkown platform"
  73 #endif
  74
  75 /* DMA related header and variables */
  76
  77 spinlock_t aes_lock;
  78 #define CRTCL_SECT_INIT        spin_lock_init(&aes_lock)
  79 #define CRTCL_SECT_START       spin_lock_irqsave(&aes_lock, flag)
  80 #define CRTCL_SECT_END         spin_unlock_irqrestore(&aes_lock, flag)
  81
  82 /* Definition of constants */
  83 #define AES_START   IFX_AES_CON
  84 #define AES_MIN_KEY_SIZE    16
  85 #define AES_MAX_KEY_SIZE    32
  86 #define AES_BLOCK_SIZE      16
  87 #define CTR_RFC3686_NONCE_SIZE    4
  88 #define CTR_RFC3686_IV_SIZE       8
  89 #define CTR_RFC3686_MAX_KEY_SIZE  (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE)
  90
  91 #ifdef CRYPTO_DEBUG
  92 extern char debug_level;
  93 #define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO "[%s %s %d]: " format, __FILE__, __func__, __LINE__, ##args);
  94 #else
  95 #define DPRINTF(level, format, args...)
  96 #endif /* CRYPTO_DEBUG */
  97
  98 /* Function decleration */
  99 int aes_chip_init(void);
 100 u32 endian_swap(u32 input);
 101 u32 input_swap(u32 input);
 102 u32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);
 103 void aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
 104 void des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
 105 int aes_memory_allocate(int value);
 106 int des_memory_allocate(int value);
 107 void memory_release(u32 *addr);
 108
 109
 110 extern void ifx_deu_aes (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg,
 111         uint8_t *iv_arg, size_t nbytes, int encdec, int mode);
 112 /* End of function decleration */
 113
 114 struct aes_ctx {
 115     int key_length;
 116     u32 buf[AES_MAX_KEY_SIZE];
 117     u8 nonce[CTR_RFC3686_NONCE_SIZE];
 118 };
 119
 120 extern int disable_deudma;
 121 extern int disable_multiblock;
 122
 123 /*! \fn int aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
 124  *  \ingroup IFX_AES_FUNCTIONS
 125  *  \brief sets the AES keys
 126  *  \param tfm linux crypto algo transform
 127  *  \param in_key input key
 128  *  \param key_len key lengths of 16, 24 and 32 bytes supported
 129  *  \return -EINVAL - bad key length, 0 - SUCCESS
 130 */
 131 int aes_set_key (struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len)
 132 {
 133     struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
 134
 135     //printk("set_key in %s\n", __FILE__);
 136
 137     //aes_chip_init();
 138
 139     if (key_len != 16 && key_len != 24 && key_len != 32) {
 140         return -EINVAL;
 141     }
 142
 143     ctx->key_length = key_len;
 144     DPRINTF(0, "ctx @%p, key_len %d, ctx->key_length %d\n", ctx, key_len, ctx->key_length);
 145     memcpy ((u8 *) (ctx->buf), in_key, key_len);
 146
 147     return 0;
 148 }
 149
 150
 151 /*! \fn int aes_set_key_skcipher (struct crypto_skcipher *tfm, const uint8_t *in_key, unsigned int key_len)
 152  *  \ingroup IFX_AES_FUNCTIONS
 153  *  \brief sets the AES keys for skcipher
 154  *  \param tfm linux crypto skcipher
 155  *  \param in_key input key
 156  *  \param key_len key lengths of 16, 24 and 32 bytes supported
 157  *  \return -EINVAL - bad key length, 0 - SUCCESS
 158 */
 159 int aes_set_key_skcipher (struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len)
 160 {
 161     return aes_set_key(crypto_skcipher_tfm(tfm), in_key, key_len);
 162 }
 163
 164
 165 /*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode)
 166  *  \ingroup IFX_AES_FUNCTIONS
 167  *  \brief main interface to AES hardware
 168  *  \param ctx_arg crypto algo context
 169  *  \param out_arg output bytestream
 170  *  \param in_arg input bytestream
 171  *  \param iv_arg initialization vector
 172  *  \param nbytes length of bytestream
 173  *  \param encdec 1 for encrypt; 0 for decrypt
 174  *  \param mode operation mode such as ebc, cbc, ctr
 175  *
 176 */
 177 void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
 178         u8 *iv_arg, size_t nbytes, int encdec, int mode)
 179
 180 {
 181     /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
 182     volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;
 183     struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg;
 184     u32 *in_key = ctx->buf;
 185     unsigned long flag;
 186     /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
 187     int key_len = ctx->key_length;
 188
 189     int i = 0;
 190     int byte_cnt = nbytes;
 191
 192
 193     CRTCL_SECT_START;
 194     /* 128, 192 or 256 bit key length */
 195     aes->controlr.K = key_len / 8 - 2;
 196         if (key_len == 128 / 8) {
 197         aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
 198         aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
 199         aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
 200         aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
 201     }
 202     else if (key_len == 192 / 8) {
 203         aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
 204         aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
 205         aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
 206         aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
 207         aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));
 208         aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));
 209     }
 210     else if (key_len == 256 / 8) {
 211         aes->K7R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
 212         aes->K6R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
 213         aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
 214         aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
 215         aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));
 216         aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));
 217         aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 6));
 218         aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 7));
 219     }
 220     else {
 221         printk (KERN_ERR "[%s %s %d]: Invalid key_len : %d\n", __FILE__, __func__, __LINE__, key_len);
 222         CRTCL_SECT_END;
 223         return;// -EINVAL;
 224     }
 225
 226     /* let HW pre-process DEcryption key in any case (even if
 227        ENcryption is used). Key Valid (KV) bit is then only
 228        checked in decryption routine! */
 229     aes->controlr.PNK = 1;
 230
 231
 232     aes->controlr.E_D = !encdec;    //encryption
 233     aes->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR
 234
 235     //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps
 236     if (mode > 0) {
 237         aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);
 238         aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));
 239         aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));
 240         aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));
 241     };
 242
 243
 244     i = 0;
 245     while (byte_cnt >= 16) {
 246
 247         aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 0));
 248         aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 1));
 249         aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 2));
 250         aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 3));    /* start crypto */
 251
 252         while (aes->controlr.BUS) {
 253             // this will not take long
 254         }
 255
 256         *((volatile u32 *) out_arg + (i * 4) + 0) = aes->OD3R;
 257         *((volatile u32 *) out_arg + (i * 4) + 1) = aes->OD2R;
 258         *((volatile u32 *) out_arg + (i * 4) + 2) = aes->OD1R;
 259         *((volatile u32 *) out_arg + (i * 4) + 3) = aes->OD0R;
 260
 261         i++;
 262         byte_cnt -= 16;
 263     }
 264
 265     /* To handle all non-aligned bytes (not aligned to 16B size) */
 266     if (byte_cnt) {
 267         u8 temparea[16] = {0,};
 268
 269         memcpy(temparea, ((u32 *) in_arg + (i * 4)), byte_cnt);
 270
 271         aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) temparea + 0));
 272         aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) temparea + 1));
 273         aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) temparea + 2));
 274         aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) temparea + 3));    /* start crypto */
 275
 276         while (aes->controlr.BUS) {
 277         }
 278
 279         *((volatile u32 *) temparea + 0) = aes->OD3R;
 280         *((volatile u32 *) temparea + 1) = aes->OD2R;
 281         *((volatile u32 *) temparea + 2) = aes->OD1R;
 282         *((volatile u32 *) temparea + 3) = aes->OD0R;
 283
 284         memcpy(((u32 *) out_arg + (i * 4)), temparea, byte_cnt);
 285     }
 286
 287     //tc.chen : copy iv_arg back
 288     if (mode > 0) {
 289         *((u32 *) iv_arg) = DEU_ENDIAN_SWAP(aes->IV3R);
 290         *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(aes->IV2R);
 291         *((u32 *) iv_arg + 2) = DEU_ENDIAN_SWAP(aes->IV1R);
 292         *((u32 *) iv_arg + 3) = DEU_ENDIAN_SWAP(aes->IV0R);
 293     }
 294
 295     CRTCL_SECT_END;
 296 }
 297
 298 /*!
 299  *  \fn int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
 300  *  \ingroup IFX_AES_FUNCTIONS
 301  *  \brief sets RFC3686 key
 302  *  \param tfm linux crypto algo transform
 303  *  \param in_key input key
 304  *  \param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce
 305  *  \return 0 - SUCCESS
 306  *          -EINVAL - bad key length
 307 */
 308 int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
 309 {
 310     struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
 311
 312     //printk("ctr_rfc3686_aes_set_key in %s\n", __FILE__);
 313
 314     memcpy(ctx->nonce, in_key + (key_len - CTR_RFC3686_NONCE_SIZE),
 315            CTR_RFC3686_NONCE_SIZE);
 316
 317     key_len -= CTR_RFC3686_NONCE_SIZE; // remove 4 bytes of nonce
 318
 319     if (key_len != 16 && key_len != 24 && key_len != 32) {
 320         return -EINVAL;
 321     }
 322
 323     ctx->key_length = key_len;
 324
 325     memcpy ((u8 *) (ctx->buf), in_key, key_len);
 326
 327     return 0;
 328 }
 329
 330 /*!
 331  *  \fn int ctr_rfc3686_aes_set_key_skcipher (struct crypto_skcipher *tfm, const uint8_t *in_key, unsigned int key_len)
 332  *  \ingroup IFX_AES_FUNCTIONS
 333  *  \brief sets RFC3686 key for skcipher
 334  *  \param tfm linux crypto skcipher
 335  *  \param in_key input key
 336  *  \param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce
 337  *  \return 0 - SUCCESS
 338  *          -EINVAL - bad key length
 339 */
 340 int ctr_rfc3686_aes_set_key_skcipher (struct crypto_skcipher *tfm, const uint8_t *in_key, unsigned int key_len)
 341 {
 342     return ctr_rfc3686_aes_set_key(crypto_skcipher_tfm(tfm), in_key, key_len);
 343 }
 344
 345
 346 /*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)
 347  *  \ingroup IFX_AES_FUNCTIONS
 348  *  \brief main interface with deu hardware in DMA mode
 349  *  \param ctx_arg crypto algo context
 350  *  \param out_arg output bytestream
 351  *  \param in_arg input bytestream
 352  *  \param iv_arg initialization vector
 353  *  \param nbytes length of bytestream
 354  *  \param encdec 1 for encrypt; 0 for decrypt
 355  *  \param mode operation mode such as ebc, cbc, ctr
 356 */
 357
 358
 359 //definitions from linux/include/crypto.h:
 360 //#define CRYPTO_TFM_MODE_ECB       0x00000001
 361 //#define CRYPTO_TFM_MODE_CBC       0x00000002
 362 //#define CRYPTO_TFM_MODE_CFB       0x00000004
 363 //#define CRYPTO_TFM_MODE_CTR       0x00000008
 364 //#define CRYPTO_TFM_MODE_OFB       0x00000010 // not even defined
 365 //but hardware definition: 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR
 366
 367 /*! \fn void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
 368  *  \ingroup IFX_AES_FUNCTIONS
 369  *  \brief sets AES hardware to ECB mode
 370  *  \param ctx crypto algo context
 371  *  \param dst output bytestream
 372  *  \param src input bytestream
 373  *  \param iv initialization vector
 374  *  \param nbytes length of bytestream
 375  *  \param encdec 1 for encrypt; 0 for decrypt
 376  *  \param inplace not used
 377 */
 378 void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src,
 379         uint8_t *iv, size_t nbytes, int encdec, int inplace)
 380 {
 381      ifx_deu_aes (ctx, dst, src, NULL, nbytes, encdec, 0);
 382 }
 383
 384 /*! \fn void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
 385  *  \ingroup IFX_AES_FUNCTIONS
 386  *  \brief sets AES hardware to CBC mode
 387  *  \param ctx crypto algo context
 388  *  \param dst output bytestream
 389  *  \param src input bytestream
 390  *  \param iv initialization vector
 391  *  \param nbytes length of bytestream
 392  *  \param encdec 1 for encrypt; 0 for decrypt
 393  *  \param inplace not used
 394 */
 395 void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src,
 396         uint8_t *iv, size_t nbytes, int encdec, int inplace)
 397 {
 398      ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 1);
 399 }
 400
 401 /*! \fn void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
 402  *  \ingroup IFX_AES_FUNCTIONS
 403  *  \brief sets AES hardware to OFB mode
 404  *  \param ctx crypto algo context
 405  *  \param dst output bytestream
 406  *  \param src input bytestream
 407  *  \param iv initialization vector
 408  *  \param nbytes length of bytestream
 409  *  \param encdec 1 for encrypt; 0 for decrypt
 410  *  \param inplace not used
 411 */
 412 void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src,
 413         uint8_t *iv, size_t nbytes, int encdec, int inplace)
 414 {
 415      ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 2);
 416 }
 417
 418 /*! \fn void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
 419  *  \ingroup IFX_AES_FUNCTIONS
 420  *  \brief sets AES hardware to CFB mode
 421  *  \param ctx crypto algo context
 422  *  \param dst output bytestream
 423  *  \param src input bytestream
 424  *  \param iv initialization vector
 425  *  \param nbytes length of bytestream
 426  *  \param encdec 1 for encrypt; 0 for decrypt
 427  *  \param inplace not used
 428 */
 429 void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src,
 430         uint8_t *iv, size_t nbytes, int encdec, int inplace)
 431 {
 432      ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 3);
 433 }
 434
 435 /*! \fn void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
 436  *  \ingroup IFX_AES_FUNCTIONS
 437  *  \brief sets AES hardware to CTR mode
 438  *  \param ctx crypto algo context
 439  *  \param dst output bytestream
 440  *  \param src input bytestream
 441  *  \param iv initialization vector
 442  *  \param nbytes length of bytestream
 443  *  \param encdec 1 for encrypt; 0 for decrypt
 444  *  \param inplace not used
 445 */
 446 void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src,
 447         uint8_t *iv, size_t nbytes, int encdec, int inplace)
 448 {
 449      ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 4);
 450 }
 451
 452 /*! \fn void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
 453  *  \ingroup IFX_AES_FUNCTIONS
 454  *  \brief encrypt AES_BLOCK_SIZE of data
 455  *  \param tfm linux crypto algo transform
 456  *  \param out output bytestream
 457  *  \param in input bytestream
 458 */
 459 void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
 460 {
 461     struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
 462     ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,
 463             CRYPTO_DIR_ENCRYPT, 0);
 464 }
 465
 466 /*! \fn void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
 467  *  \ingroup IFX_AES_FUNCTIONS
 468  *  \brief decrypt AES_BLOCK_SIZE of data
 469  *  \param tfm linux crypto algo transform
 470  *  \param out output bytestream
 471  *  \param in input bytestream
 472 */
 473 void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
 474 {
 475     struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
 476     ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,
 477             CRYPTO_DIR_DECRYPT, 0);
 478 }
 479
 480 /*
 481  * \brief AES function mappings
 482 */
 483 struct crypto_alg ifxdeu_aes_alg = {
 484     .cra_name       =   "aes",
 485     .cra_driver_name    =   "ifxdeu-aes",
 486     .cra_priority   =   300,
 487     .cra_flags      =   CRYPTO_ALG_TYPE_CIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,
 488     .cra_blocksize      =   AES_BLOCK_SIZE,
 489     .cra_ctxsize        =   sizeof(struct aes_ctx),
 490     .cra_module     =   THIS_MODULE,
 491     .cra_list       =   LIST_HEAD_INIT(ifxdeu_aes_alg.cra_list),
 492     .cra_u          =   {
 493         .cipher = {
 494             .cia_min_keysize    =   AES_MIN_KEY_SIZE,
 495             .cia_max_keysize    =   AES_MAX_KEY_SIZE,
 496             .cia_setkey     =   aes_set_key,
 497             .cia_encrypt        =   aes_encrypt,
 498             .cia_decrypt        =   aes_decrypt,
 499         }
 500     }
 501 };
 502
 503 /*! \fn int ecb_aes_encrypt(struct skcipher_req *req)
 504  *  \ingroup IFX_AES_FUNCTIONS
 505  *  \brief ECB AES encrypt using linux crypto skcipher
 506  *  \param req skcipher request
 507  *  \return err
 508 */
 509 int ecb_aes_encrypt(struct skcipher_request *req)
 510 {
 511     struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 512     struct skcipher_walk walk;
 513     int err;
 514     unsigned int enc_bytes, nbytes;
 515
 516     err = skcipher_walk_virt(&walk, req, false);
 517
 518     while ((nbytes = enc_bytes = walk.nbytes)) {
 519             enc_bytes -= (nbytes % AES_BLOCK_SIZE);
 520         ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 521                        NULL, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);
 522                 nbytes &= AES_BLOCK_SIZE - 1;
 523         err = skcipher_walk_done(&walk, nbytes);
 524     }
 525
 526     return err;
 527 }
 528
 529 /*! \fn int ecb_aes_decrypt(struct skcipher_req *req)
 530  *  \ingroup IFX_AES_FUNCTIONS
 531  *  \brief ECB AES decrypt using linux crypto skcipher
 532  *  \param req skcipher request
 533  *  \return err
 534 */
 535 int ecb_aes_decrypt(struct skcipher_request *req)
 536 {
 537     struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 538     struct skcipher_walk walk;
 539     int err;
 540     unsigned int dec_bytes, nbytes;
 541
 542     err = skcipher_walk_virt(&walk, req, false);
 543
 544     while ((nbytes = dec_bytes = walk.nbytes)) {
 545             dec_bytes -= (nbytes % AES_BLOCK_SIZE);
 546         ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 547                        NULL, dec_bytes, CRYPTO_DIR_DECRYPT, 0);
 548         nbytes &= AES_BLOCK_SIZE - 1;
 549         err = skcipher_walk_done(&walk, nbytes);
 550     }
 551
 552     return err;
 553 }
 554
 555 /*
 556  * \brief AES function mappings
 557 */
 558 struct skcipher_alg ifxdeu_ecb_aes_alg = {
 559     .base.cra_name           =   "ecb(aes)",
 560     .base.cra_driver_name    =   "ifxdeu-ecb(aes)",
 561     .base.cra_priority       =   400,
 562     .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,
 563     .base.cra_blocksize      =   AES_BLOCK_SIZE,
 564     .base.cra_ctxsize        =   sizeof(struct aes_ctx),
 565     .base.cra_module         =   THIS_MODULE,
 566     .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_ecb_aes_alg.base.cra_list),
 567     .min_keysize             =   AES_MIN_KEY_SIZE,
 568     .max_keysize             =   AES_MAX_KEY_SIZE,
 569     .setkey                  =   aes_set_key_skcipher,
 570     .encrypt                 =   ecb_aes_encrypt,
 571     .decrypt                 =   ecb_aes_decrypt,
 572 };
 573
 574
 575 /*! \fn int ecb_aes_encrypt(struct skcipher_req *req)
 576  *  \ingroup IFX_AES_FUNCTIONS
 577  *  \brief CBC AES encrypt using linux crypto skcipher
 578  *  \param req skcipher request
 579  *  \return err
 580 */
 581 int cbc_aes_encrypt(struct skcipher_request *req)
 582 {
 583     struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 584     struct skcipher_walk walk;
 585     int err;
 586     unsigned int enc_bytes, nbytes;
 587
 588     err = skcipher_walk_virt(&walk, req, false);
 589
 590     while ((nbytes = enc_bytes = walk.nbytes)) {
 591             u8 *iv = walk.iv;
 592             enc_bytes -= (nbytes % AES_BLOCK_SIZE);
 593             ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 594                        iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);
 595         nbytes &= AES_BLOCK_SIZE - 1;
 596         err = skcipher_walk_done(&walk, nbytes);
 597     }
 598
 599     return err;
 600 }
 601
 602 /*! \fn int cbc_aes_decrypt(struct skcipher_req *req)
 603  *  \ingroup IFX_AES_FUNCTIONS
 604  *  \brief CBC AES decrypt using linux crypto skcipher
 605  *  \param req skcipher request
 606  *  \return err
 607 */
 608 int cbc_aes_decrypt(struct skcipher_request *req)
 609 {
 610     struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 611     struct skcipher_walk walk;
 612     int err;
 613     unsigned int dec_bytes, nbytes;
 614
 615     err = skcipher_walk_virt(&walk, req, false);
 616
 617     while ((nbytes = dec_bytes = walk.nbytes)) {
 618         u8 *iv = walk.iv;
 619             dec_bytes -= (nbytes % AES_BLOCK_SIZE);
 620             ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 621                        iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0);
 622         nbytes &= AES_BLOCK_SIZE - 1;
 623         err = skcipher_walk_done(&walk, nbytes);
 624     }
 625
 626     return err;
 627 }
 628
 629 /*
 630  * \brief AES function mappings
 631 */
 632 struct skcipher_alg ifxdeu_cbc_aes_alg = {
 633     .base.cra_name           =   "cbc(aes)",
 634     .base.cra_driver_name    =   "ifxdeu-cbc(aes)",
 635     .base.cra_priority       =   400,
 636     .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,
 637     .base.cra_blocksize      =   AES_BLOCK_SIZE,
 638     .base.cra_ctxsize        =   sizeof(struct aes_ctx),
 639     .base.cra_module         =   THIS_MODULE,
 640     .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_cbc_aes_alg.base.cra_list),
 641     .min_keysize             =   AES_MIN_KEY_SIZE,
 642     .max_keysize             =   AES_MAX_KEY_SIZE,
 643     .ivsize                  =   AES_BLOCK_SIZE,
 644     .setkey                  =   aes_set_key_skcipher,
 645     .encrypt                 =   cbc_aes_encrypt,
 646     .decrypt                 =   cbc_aes_decrypt,
 647 };
 648
 649
 650 /*! \fn int ctr_basic_aes_encrypt(struct skcipher_req *req)
 651  *  \ingroup IFX_AES_FUNCTIONS
 652  *  \brief Counter mode AES encrypt using linux crypto skcipher
 653  *  \param req skcipher request
 654  *  \return err
 655 */
 656 int ctr_basic_aes_encrypt(struct skcipher_request *req)
 657 {
 658     struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 659     struct skcipher_walk walk;
 660     unsigned int nbytes;
 661     int err;
 662
 663     err = skcipher_walk_virt(&walk, req, false);
 664
 665     while ((nbytes = walk.nbytes)) {
 666         ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 667                         walk.iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
 668         err = skcipher_walk_done(&walk, 0);
 669     }
 670     return err;
 671 }
 672
 673 /*! \fn int ctr_basic_aes_encrypt(struct skcipher_req *req)
 674  *  \ingroup IFX_AES_FUNCTIONS
 675  *  \brief Counter mode AES decrypt using linux crypto skcipher
 676  *  \param req skcipher request
 677  *  \return err
 678 */
 679 int ctr_basic_aes_decrypt(struct skcipher_request *req)
 680 {
 681     struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 682     struct skcipher_walk walk;
 683     unsigned int nbytes;
 684     int err;
 685
 686     err = skcipher_walk_virt(&walk, req, false);
 687
 688     while ((nbytes = walk.nbytes)) {
 689         ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 690                         walk.iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
 691         err = skcipher_walk_done(&walk, 0);
 692     }
 693
 694     return err;
 695 }
 696
 697 /*
 698  * \brief AES function mappings
 699 */
 700 struct skcipher_alg ifxdeu_ctr_basic_aes_alg = {
 701     .base.cra_name           =   "ctr(aes)",
 702     .base.cra_driver_name    =   "ifxdeu-ctr(aes)",
 703     .base.cra_priority       =   400,
 704     .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,
 705     .base.cra_blocksize      =   1,
 706     .base.cra_ctxsize        =   sizeof(struct aes_ctx),
 707     .base.cra_module         =   THIS_MODULE,
 708     .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_ctr_basic_aes_alg.base.cra_list),
 709     .min_keysize             =   AES_MIN_KEY_SIZE,
 710     .max_keysize             =   AES_MAX_KEY_SIZE,
 711     .ivsize                  =   AES_BLOCK_SIZE,
 712     .setkey                  =   aes_set_key_skcipher,
 713     .encrypt                 =   ctr_basic_aes_encrypt,
 714     .decrypt                 =   ctr_basic_aes_decrypt,
 715 };
 716
 717
 718 /*! \fn int ctr_rfc3686_aes_encrypt(struct skcipher_req *req)
 719  *  \ingroup IFX_AES_FUNCTIONS
 720  *  \brief Counter mode AES (rfc3686) encrypt using linux crypto skcipher
 721  *  \param req skcipher request
 722  *  \return err
 723 */
 724 int ctr_rfc3686_aes_encrypt(struct skcipher_request *req)
 725 {
 726     struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 727     struct skcipher_walk walk;
 728     unsigned int nbytes;
 729     int err, bsize;
 730     u8 rfc3686_iv[16];
 731
 732     err = skcipher_walk_virt(&walk, req, false);
 733     nbytes = walk.nbytes;
 734     bsize = nbytes;
 735
 736     /* set up counter block */
 737     memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
 738     memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);
 739
 740     /* initialize counter portion of counter block */
 741     *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
 742         cpu_to_be32(1);
 743
 744     /* scatterlist source is the same size as request size, just process once */
 745     if (nbytes == walk.nbytes) {
 746         ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 747                         rfc3686_iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
 748         nbytes -= walk.nbytes;
 749         err = skcipher_walk_done(&walk, nbytes);
 750         return err;
 751     }
 752
 753     while ((nbytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {
 754         ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 755                         rfc3686_iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
 756
 757         nbytes -= walk.nbytes;
 758         bsize -= walk.nbytes;
 759         err = skcipher_walk_done(&walk, nbytes);
 760     }
 761
 762     /* to handle remaining bytes < AES_BLOCK_SIZE */
 763     if (walk.nbytes) {
 764         ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 765                         rfc3686_iv, walk.nbytes, CRYPTO_DIR_ENCRYPT, 0);
 766         err = skcipher_walk_done(&walk, 0);
 767     }
 768
 769     return err;
 770 }
 771
 772 /*! \fn int ctr_rfc3686_aes_decrypt(struct skcipher_req *req)
 773  *  \ingroup IFX_AES_FUNCTIONS
 774  *  \brief Counter mode AES (rfc3686) decrypt using linux crypto skcipher
 775  *  \param req skcipher request
 776  *  \return err
 777 */
 778 int ctr_rfc3686_aes_decrypt(struct skcipher_request *req)
 779 {
 780     struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 781     struct skcipher_walk walk;
 782     unsigned int nbytes;
 783     int err, bsize;
 784     u8 rfc3686_iv[16];
 785
 786     err = skcipher_walk_virt(&walk, req, false);
 787     nbytes = walk.nbytes;
 788     bsize = nbytes;
 789
 790     /* set up counter block */
 791     memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
 792     memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);
 793
 794     /* initialize counter portion of counter block */
 795     *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
 796         cpu_to_be32(1);
 797
 798     /* scatterlist source is the same size as request size, just process once */
 799     if (nbytes == walk.nbytes) {
 800         ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 801                         rfc3686_iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
 802         nbytes -= walk.nbytes;
 803         err = skcipher_walk_done(&walk, nbytes);
 804         return err;
 805     }
 806
 807     while ((nbytes = walk.nbytes) % (walk.nbytes >= AES_BLOCK_SIZE)) {
 808         ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 809                         rfc3686_iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
 810
 811         nbytes -= walk.nbytes;
 812         bsize -= walk.nbytes;
 813         err = skcipher_walk_done(&walk, nbytes);
 814     }
 815
 816     /* to handle remaining bytes < AES_BLOCK_SIZE */
 817     if (walk.nbytes) {
 818         ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
 819                         rfc3686_iv, walk.nbytes, CRYPTO_DIR_ENCRYPT, 0);
 820         err = skcipher_walk_done(&walk, 0);
 821     }
 822
 823     return err;
 824 }
 825
 826 /*
 827  * \brief AES function mappings
 828 */
 829 struct skcipher_alg ifxdeu_ctr_rfc3686_aes_alg = {
 830     .base.cra_name           =   "rfc3686(ctr(aes))",
 831     .base.cra_driver_name    =   "ifxdeu-ctr-rfc3686(aes)",
 832     .base.cra_priority       =   400,
 833     .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,
 834     .base.cra_blocksize      =   1,
 835     .base.cra_ctxsize        =   sizeof(struct aes_ctx),
 836     .base.cra_module         =   THIS_MODULE,
 837     .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_ctr_rfc3686_aes_alg.base.cra_list),
 838     .min_keysize             =   AES_MIN_KEY_SIZE,
 839     .max_keysize             =   CTR_RFC3686_MAX_KEY_SIZE,
 840     .ivsize                  =   CTR_RFC3686_IV_SIZE,
 841     .setkey                  =   ctr_rfc3686_aes_set_key_skcipher,
 842     .encrypt                 =   ctr_rfc3686_aes_encrypt,
 843     .decrypt                 =   ctr_rfc3686_aes_decrypt,
 844 };
 845
 846
 847 /*! \fn int ifxdeu_init_aes (void)
 848  *  \ingroup IFX_AES_FUNCTIONS
 849  *  \brief function to initialize AES driver
 850  *  \return ret
 851 */
 852 int ifxdeu_init_aes (void)
 853 {
 854     int ret = -ENOSYS;
 855
 856     aes_chip_init();
 857
 858     if ((ret = crypto_register_alg(&ifxdeu_aes_alg)))
 859         goto aes_err;
 860
 861     if ((ret = crypto_register_skcipher(&ifxdeu_ecb_aes_alg)))
 862         goto ecb_aes_err;
 863
 864     if ((ret = crypto_register_skcipher(&ifxdeu_cbc_aes_alg)))
 865         goto cbc_aes_err;
 866
 867     if ((ret = crypto_register_skcipher(&ifxdeu_ctr_basic_aes_alg)))
 868         goto ctr_basic_aes_err;
 869
 870     if ((ret = crypto_register_skcipher(&ifxdeu_ctr_rfc3686_aes_alg)))
 871         goto ctr_rfc3686_aes_err;
 872
 873     CRTCL_SECT_INIT;
 874
 875
 876     printk (KERN_NOTICE "IFX DEU AES initialized%s%s.\n", disable_multiblock ? "" : " (multiblock)", disable_deudma ? "" : " (DMA)");
 877     return ret;
 878
 879 ctr_rfc3686_aes_err:
 880     crypto_unregister_skcipher(&ifxdeu_ctr_rfc3686_aes_alg);
 881     printk (KERN_ERR "IFX ctr_rfc3686_aes initialization failed!\n");
 882     return ret;
 883 ctr_basic_aes_err:
 884     crypto_unregister_skcipher(&ifxdeu_ctr_basic_aes_alg);
 885     printk (KERN_ERR "IFX ctr_basic_aes initialization failed!\n");
 886     return ret;
 887 cbc_aes_err:
 888     crypto_unregister_skcipher(&ifxdeu_cbc_aes_alg);
 889     printk (KERN_ERR "IFX cbc_aes initialization failed!\n");
 890     return ret;
 891 ecb_aes_err:
 892     crypto_unregister_skcipher(&ifxdeu_ecb_aes_alg);
 893     printk (KERN_ERR "IFX aes initialization failed!\n");
 894     return ret;
 895 aes_err:
 896     printk(KERN_ERR "IFX DEU AES initialization failed!\n");
 897
 898     return ret;
 899 }
 900
 901 /*! \fn void ifxdeu_fini_aes (void)
 902  *  \ingroup IFX_AES_FUNCTIONS
 903  *  \brief unregister aes driver
 904 */
 905 void ifxdeu_fini_aes (void)
 906 {
 907     crypto_unregister_alg (&ifxdeu_aes_alg);
 908     crypto_unregister_skcipher (&ifxdeu_ecb_aes_alg);
 909     crypto_unregister_skcipher (&ifxdeu_cbc_aes_alg);
 910     crypto_unregister_skcipher (&ifxdeu_ctr_basic_aes_alg);
 911     crypto_unregister_skcipher (&ifxdeu_ctr_rfc3686_aes_alg);
 912
 913 }