1 /******************************************************************************
3 ** FILE NAME : ifxmips_deu.h
4 ** DESCRIPTION : Data Encryption Unit Driver
5 ** COPYRIGHT : Copyright (c) 2009
6 ** Infineon Technologies AG
7 ** Am Campeon 1-12, 85579 Neubiberg, Germany
9 ** This program is free software; you can redistribute it and/or modify
10 ** it under the terms of the GNU General Public License as published by
11 ** the Free Software Foundation; either version 2 of the License, or
12 ** (at your option) any later version.
15 ** $Date $Author $Comment
16 ** 08,Sept 2009 Mohammad Firdaus Initial UEIP release
17 *******************************************************************************/
19 \defgroup IFX_DEU IFX_DEU_DRIVERS
21 \brief ifx deu driver module
26 \brief main deu driver header file
30 \defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS
32 \brief ifx deu definitions
39 #include <crypto/algapi.h>
40 #include <linux/interrupt.h>
42 #define IFXDEU_ALIGNMENT 16
44 #define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100)
45 #define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000))
46 #define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010))
47 #define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050))
48 #define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0))
49 #define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100))
51 #define PFX "ifxdeu: "
52 #define CLC_START IFX_DEU_CLK
53 #define IFXDEU_CRA_PRIORITY 300
54 #define IFXDEU_COMPOSITE_PRIORITY 400
55 //#define KSEG1 0xA0000000
56 #define IFX_PMU_ENABLE 1
57 #define IFX_PMU_DISABLE 0
59 #define CRYPTO_DIR_ENCRYPT 1
60 #define CRYPTO_DIR_DECRYPT 0
65 #define AES_COMPLETED 3
69 #define DES_COMPLETED 3
71 #define PROCESS_SCATTER 1
72 #define PROCESS_NEW_PACKET 2
74 #define PMU_DEU BIT(20)
75 #define START_DEU_POWER \
77 volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) CLC_START; \
78 ltq_pmu_enable(PMU_DEU); \
87 #define STOP_DEU_POWER \
89 volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) CLC_START; \
90 ltq_pmu_disable(PMU_DEU); \
100 * Not used anymore in UEIP (use IFX_DES_CON, IFX_AES_CON, etc instead)
101 * #define DEU_BASE (KSEG1+0x1E103100)
102 * #define DES_CON (DEU_BASE+0x10)
103 * #define AES_CON (DEU_BASE+0x50)
104 * #define HASH_CON (DEU_BASE+0xB0)
105 * #define DMA_CON (DEU_BASE+0xEC)
106 * #define INT_CON (DEU_BASE+0xF4)
107 * #define ARC4_CON (DEU_BASE+0x100)
111 int ifxdeu_init_des (void);
112 int ifxdeu_init_aes (void);
113 int ifxdeu_init_arc4 (void);
114 int ifxdeu_init_sha1 (void);
115 int ifxdeu_init_md5 (void);
116 int ifxdeu_init_sha1_hmac (void);
117 int ifxdeu_init_md5_hmac (void);
118 int __init
lqdeu_async_aes_init(void);
119 int __init
lqdeu_async_des_init(void);
121 void ifxdeu_fini_des (void);
122 void ifxdeu_fini_aes (void);
123 void ifxdeu_fini_arc4 (void);
124 void ifxdeu_fini_sha1 (void);
125 void ifxdeu_fini_md5 (void);
126 void ifxdeu_fini_sha1_hmac (void);
127 void ifxdeu_fini_md5_hmac (void);
128 void __exit
ifxdeu_fini_dma(void);
129 void __exit
lqdeu_fini_async_aes(void);
130 void __exit
lqdeu_fini_async_des(void);
131 void __exit
deu_fini (void);
132 int deu_dma_init (void);
134 extern spinlock_t ltq_deu_hash_lock
;
135 #define CRTCL_SECT_HASH_INIT spin_lock_init(<q_deu_hash_lock)
136 #define CRTCL_SECT_HASH_START spin_lock_irqsave(<q_deu_hash_lock, flag)
137 #define CRTCL_SECT_HASH_END spin_unlock_irqrestore(<q_deu_hash_lock, flag)
140 #define DEU_WAKELIST_INIT(queue) \
141 init_waitqueue_head(&queue)
143 #define DEU_WAIT_EVENT_TIMEOUT(queue, event, flags, timeout) \
145 wait_event_interruptible_timeout((queue), \
146 test_bit((event), &(flags)), (timeout)); \
147 clear_bit((event), &(flags)); \
151 #define DEU_WAKEUP_EVENT(queue, event, flags) \
153 set_bit((event), &(flags)); \
154 wake_up_interruptible(&(queue)); \
157 #define DEU_WAIT_EVENT(queue, event, flags) \
159 wait_event_interruptible(queue, \
160 test_bit((event), &(flags))); \
161 clear_bit((event), &(flags)); \
164 typedef struct deu_drv_priv
{
165 wait_queue_head_t deu_thread_wait
;
167 #define DES_ASYNC_EVENT 2
168 #define AES_ASYNC_EVENT 3
169 volatile long des_event_flags
;
170 volatile long aes_event_flags
;
171 volatile long deu_event_flags
;
177 struct aes_priv
*aes_dataptr
;
178 struct des_priv
*des_dataptr
;
183 * struct aes_priv_t - ASYNC AES
184 * @lock: spinlock lock
185 * @lock_flag: flag for spinlock activities
186 * @list: crypto queue API list
187 * @hw_status: DEU hw status flag
188 * @aes_wait_flag: flag for sleep queue
189 * @aes_wait_queue: queue attributes for aes
190 * @bytes_processed: number of bytes to process by DEU
191 * @aes_pid: pid number for AES thread
192 * @aes_sync: atomic wait sync for AES
198 struct crypto_queue list
;
199 unsigned int hw_status
;
200 volatile long aes_wait_flag
;
201 wait_queue_head_t aes_wait_queue
;
205 struct tasklet_struct aes_task
;
210 * struct des_priv_t - ASYNC DES
211 * @lock: spinlock lock
212 * @list: crypto queue API list
213 * @hw_status: DEU hw status flag
214 * @des_wait_flag: flag for sleep queue
215 * @des_wait_queue: queue attributes for des
216 * @des_pid: pid number for DES thread
217 * @des_sync: atomic wait sync for DES
223 struct crypto_queue list
;
224 unsigned int hw_status
;
225 volatile long des_wait_flag
;
226 wait_queue_head_t des_wait_queue
;
230 struct tasklet_struct des_task
;
234 #endif /* IFXMIPS_DEU_H */