1 /******************************************************************************
3 ** FILE NAME : ifxmips_ptm_adsl.c
9 ** DESCRIPTION : PTM driver common source file (core functions for Danube/
11 ** COPYRIGHT : Copyright (c) 2006
12 ** Infineon Technologies AG
13 ** Am Campeon 1-12, 85579 Neubiberg, Germany
15 ** This program is free software; you can redistribute it and/or modify
16 ** it under the terms of the GNU General Public License as published by
17 ** the Free Software Foundation; either version 2 of the License, or
18 ** (at your option) any later version.
21 ** $Date $Author $Comment
22 ** 07 JUL 2009 Xu Liang Init Version
23 *******************************************************************************/
28 * ####################################
30 * ####################################
36 #include <linux/version.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/errno.h>
41 #include <linux/proc_fs.h>
42 #include <linux/init.h>
43 #include <linux/ioctl.h>
44 #include <linux/etherdevice.h>
45 #include <linux/interrupt.h>
46 #include <linux/netdevice.h>
50 * Chip Specific Head File
52 #include "ifxmips_ptm_adsl.h"
55 #include <lantiq_soc.h>
58 * ####################################
59 * Kernel Version Adaption
60 * ####################################
62 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
63 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
64 #define MODULE_PARM(a, b) module_param(a, int, 0)
66 #define MODULE_PARM_ARRAY(a, b) MODULE_PARM(a, b)
72 * ####################################
73 * Parameters to Configure PPE
74 * ####################################
77 static int write_desc_delay
= 0x20; /* Write descriptor delay */
79 static int rx_max_packet_size
= ETH_MAX_FRAME_LENGTH
;
80 /* Max packet size for RX */
82 static int dma_rx_descriptor_length
= 24; /* Number of descriptors per DMA RX channel */
83 static int dma_tx_descriptor_length
= 24; /* Number of descriptors per DMA TX channel */
85 static int eth_efmtc_crc_cfg
= 0x03100710; /* default: tx_eth_crc_check: 1, tx_tc_crc_check: 1, tx_tc_crc_len = 16 */
86 /* rx_eth_crc_present: 1, rx_eth_crc_check: 1, rx_tc_crc_check: 1, rx_tc_crc_len = 16 */
88 MODULE_PARM(write_desc_delay
, "i");
89 MODULE_PARM_DESC(write_desc_delay
, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
91 MODULE_PARM(rx_max_packet_size
, "i");
92 MODULE_PARM_DESC(rx_max_packet_size
, "Max packet size in byte for downstream ethernet frames");
94 MODULE_PARM(dma_rx_descriptor_length
, "i");
95 MODULE_PARM_DESC(dma_rx_descriptor_length
, "Number of descriptor assigned to DMA RX channel (>16)");
96 MODULE_PARM(dma_tx_descriptor_length
, "i");
97 MODULE_PARM_DESC(dma_tx_descriptor_length
, "Number of descriptor assigned to DMA TX channel (>16)");
99 MODULE_PARM(eth_efmtc_crc_cfg
, "i");
100 MODULE_PARM_DESC(eth_efmtc_crc_cfg
, "Configuration for PTM TX/RX ethernet/efm-tc CRC");
105 * ####################################
107 * ####################################
111 #define DUMP_SKB_LEN ~0
116 * ####################################
118 * ####################################
124 static void ptm_setup(struct net_device
*, int);
125 static struct net_device_stats
*ptm_get_stats(struct net_device
*);
126 static int ptm_open(struct net_device
*);
127 static int ptm_stop(struct net_device
*);
128 static unsigned int ptm_poll(int, unsigned int);
129 static int ptm_napi_poll(struct napi_struct
*, int);
130 static int ptm_hard_start_xmit(struct sk_buff
*, struct net_device
*);
131 static int ptm_change_mtu(struct net_device
*, int);
132 static int ptm_ioctl(struct net_device
*, struct ifreq
*, int);
133 static void ptm_tx_timeout(struct net_device
*);
138 static INLINE
void adsl_led_flash(void);
141 * buffer manage functions
143 static INLINE
struct sk_buff
* alloc_skb_rx(void);
144 //static INLINE struct sk_buff* alloc_skb_tx(unsigned int);
145 static INLINE
struct sk_buff
*get_skb_rx_pointer(unsigned int);
146 static INLINE
int get_tx_desc(unsigned int, unsigned int *);
149 * Mailbox handler and signal function
151 static INLINE
int mailbox_rx_irq_handler(unsigned int);
152 static irqreturn_t
mailbox_irq_handler(int, void *);
153 static INLINE
void mailbox_signal(unsigned int, int);
154 #ifdef CONFIG_IFX_PTM_RX_TASKLET
155 static void do_ptm_tasklet(unsigned long);
161 #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
162 static void dump_skb(struct sk_buff
*, u32
, char *, int, int, int);
164 #define dump_skb(skb, len, title, port, ch, is_tx) do {} while (0)
166 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
167 static void skb_swap(struct sk_buff
*);
169 #define skb_swap(skb) do {} while (0)
173 * Proc File Functions
175 static INLINE
void proc_file_create(void);
176 static INLINE
void proc_file_delete(void);
177 static int proc_read_version(char *, char **, off_t
, int, int *, void *);
178 static int proc_read_wanmib(char *, char **, off_t
, int, int *, void *);
179 static int proc_write_wanmib(struct file
*, const char *, unsigned long, void *);
180 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
181 static int proc_read_genconf(char *, char **, off_t
, int, int *, void *);
183 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
184 static int proc_read_dbg(char *, char **, off_t
, int, int *, void *);
185 static int proc_write_dbg(struct file
*, const char *, unsigned long, void *);
189 * Proc Help Functions
191 static INLINE
int stricmp(const char *, const char *);
192 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
193 static INLINE
int strincmp(const char *, const char *, int);
195 static INLINE
int ifx_ptm_version(char *);
198 * Init & clean-up functions
200 static INLINE
void check_parameters(void);
201 static INLINE
int init_priv_data(void);
202 static INLINE
void clear_priv_data(void);
203 static INLINE
void init_tables(void);
208 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
209 extern int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
);
211 static inline int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
)
213 if ( is_showtime
!= NULL
)
222 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
223 extern int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *);
224 extern int (*ifx_mei_atm_showtime_exit
)(void);
226 int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *) = NULL
;
227 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter
);
228 int (*ifx_mei_atm_showtime_exit
)(void) = NULL
;
229 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit
);
235 * ####################################
237 * ####################################
240 static struct ptm_priv_data g_ptm_priv_data
;
242 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
243 static struct net_device_ops g_ptm_netdev_ops
= {
244 .ndo_get_stats
= ptm_get_stats
,
245 .ndo_open
= ptm_open
,
246 .ndo_stop
= ptm_stop
,
247 .ndo_start_xmit
= ptm_hard_start_xmit
,
248 .ndo_validate_addr
= eth_validate_addr
,
249 .ndo_set_mac_address
= eth_mac_addr
,
250 .ndo_change_mtu
= ptm_change_mtu
,
251 .ndo_do_ioctl
= ptm_ioctl
,
252 .ndo_tx_timeout
= ptm_tx_timeout
,
256 static struct net_device
*g_net_dev
[2] = {0};
257 static char *g_net_dev_name
[2] = {"ptm0", "ptmfast0"};
259 #ifdef CONFIG_IFX_PTM_RX_TASKLET
260 static struct tasklet_struct g_ptm_tasklet
[] = {
261 {NULL
, 0, ATOMIC_INIT(0), do_ptm_tasklet
, 0},
262 {NULL
, 0, ATOMIC_INIT(0), do_ptm_tasklet
, 1},
266 unsigned int ifx_ptm_dbg_enable
= DBG_ENABLE_MASK_ERR
;
268 static struct proc_dir_entry
* g_ptm_dir
= NULL
;
270 static int g_showtime
= 0;
275 * ####################################
277 * ####################################
280 static void ptm_setup(struct net_device
*dev
, int ndev
)
282 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
283 netif_carrier_off(dev
);
286 /* hook network operations */
287 dev
->netdev_ops
= &g_ptm_netdev_ops
;
288 netif_napi_add(dev
, &g_ptm_priv_data
.itf
[ndev
].napi
, ptm_napi_poll
, 25);
289 dev
->watchdog_timeo
= ETH_WATCHDOG_TIMEOUT
;
291 dev
->dev_addr
[0] = 0x00;
292 dev
->dev_addr
[1] = 0x20;
293 dev
->dev_addr
[2] = 0xda;
294 dev
->dev_addr
[3] = 0x86;
295 dev
->dev_addr
[4] = 0x23;
296 dev
->dev_addr
[5] = 0x75 + ndev
;
299 static struct net_device_stats
*ptm_get_stats(struct net_device
*dev
)
303 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
304 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
306 g_ptm_priv_data
.itf
[ndev
].stats
.rx_errors
= WAN_MIB_TABLE
[ndev
].wrx_tccrc_err_pdu
+ WAN_MIB_TABLE
[ndev
].wrx_ethcrc_err_pdu
;
307 g_ptm_priv_data
.itf
[ndev
].stats
.rx_dropped
= WAN_MIB_TABLE
[ndev
].wrx_nodesc_drop_pdu
+ WAN_MIB_TABLE
[ndev
].wrx_len_violation_drop_pdu
+ (WAN_MIB_TABLE
[ndev
].wrx_correct_pdu
- g_ptm_priv_data
.itf
[ndev
].stats
.rx_packets
);
309 return &g_ptm_priv_data
.itf
[ndev
].stats
;
312 static int ptm_open(struct net_device
*dev
)
316 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
317 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
319 napi_enable(&g_ptm_priv_data
.itf
[ndev
].napi
);
321 IFX_REG_W32_MASK(0, 1 << ndev
, MBOX_IGU1_IER
);
323 netif_start_queue(dev
);
328 static int ptm_stop(struct net_device
*dev
)
332 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
333 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
335 IFX_REG_W32_MASK((1 << ndev
) | (1 << (ndev
+ 16)), 0, MBOX_IGU1_IER
);
337 napi_disable(&g_ptm_priv_data
.itf
[ndev
].napi
);
339 netif_stop_queue(dev
);
344 static unsigned int ptm_poll(int ndev
, unsigned int work_to_do
)
346 unsigned int work_done
= 0;
348 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
350 while ( work_done
< work_to_do
&& WRX_DMA_CHANNEL_CONFIG(ndev
)->vlddes
> 0 ) {
351 if ( mailbox_rx_irq_handler(ndev
) < 0 )
359 static int ptm_napi_poll(struct napi_struct
*napi
, int budget
)
362 unsigned int work_done
;
364 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != napi
->dev
; ndev
++ );
366 work_done
= ptm_poll(ndev
, budget
);
369 if ( !netif_running(napi
->dev
) ) {
375 if ( WRX_DMA_CHANNEL_CONFIG(ndev
)->vlddes
== 0 ) {
377 IFX_REG_W32_MASK(0, 1 << ndev
, MBOX_IGU1_ISRC
);
379 if ( WRX_DMA_CHANNEL_CONFIG(ndev
)->vlddes
== 0 ) {
381 IFX_REG_W32_MASK(0, 1 << ndev
, MBOX_IGU1_IER
);
390 static int ptm_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
395 register struct tx_descriptor reg_desc
= {0};
397 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
398 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
401 err("not in showtime");
402 goto PTM_HARD_START_XMIT_FAIL
;
405 /* allocate descriptor */
406 desc_base
= get_tx_desc(ndev
, &f_full
);
408 dev
->trans_start
= jiffies
;
409 netif_stop_queue(dev
);
411 IFX_REG_W32_MASK(0, 1 << (ndev
+ 16), MBOX_IGU1_ISRC
);
412 IFX_REG_W32_MASK(0, 1 << (ndev
+ 16), MBOX_IGU1_IER
);
415 goto PTM_HARD_START_XMIT_FAIL
;
417 if ( g_ptm_priv_data
.itf
[ndev
].tx_skb
[desc_base
] != NULL
)
418 dev_kfree_skb_any(g_ptm_priv_data
.itf
[ndev
].tx_skb
[desc_base
]);
419 g_ptm_priv_data
.itf
[ndev
].tx_skb
[desc_base
] = skb
;
421 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
422 reg_desc
.datalen
= skb
->len
< ETH_ZLEN
? ETH_ZLEN
: skb
->len
;
423 reg_desc
.byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
426 reg_desc
.sop
= reg_desc
.eop
= 1;
428 /* write discriptor to memory and write back cache */
429 g_ptm_priv_data
.itf
[ndev
].tx_desc
[desc_base
] = reg_desc
;
430 dma_cache_wback((unsigned long)skb
->data
, skb
->len
);
433 dump_skb(skb
, DUMP_SKB_LEN
, (char *)__func__
, ndev
, ndev
, 1);
435 if ( (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_MAC_SWAP
) ) {
439 g_ptm_priv_data
.itf
[ndev
].stats
.tx_packets
++;
440 g_ptm_priv_data
.itf
[ndev
].stats
.tx_bytes
+= reg_desc
.datalen
;
442 dev
->trans_start
= jiffies
;
443 mailbox_signal(ndev
, 1);
449 PTM_HARD_START_XMIT_FAIL
:
450 dev_kfree_skb_any(skb
);
451 g_ptm_priv_data
.itf
[ndev
].stats
.tx_dropped
++;
455 static int ptm_change_mtu(struct net_device
*dev
, int mtu
)
457 /* Allow up to 1508 bytes, for RFC4638 */
458 if (mtu
< 68 || mtu
> ETH_DATA_LEN
+ 8)
464 static int ptm_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
468 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
469 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
473 case IFX_PTM_MIB_CW_GET
:
474 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxNoIdleCodewords
= WAN_MIB_TABLE
[ndev
].wrx_nonidle_cw
;
475 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxIdleCodewords
= WAN_MIB_TABLE
[ndev
].wrx_idle_cw
;
476 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxCodingViolation
= WAN_MIB_TABLE
[ndev
].wrx_err_cw
;
477 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifTxNoIdleCodewords
= 0;
478 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifTxIdleCodewords
= 0;
480 case IFX_PTM_MIB_FRAME_GET
:
481 ((PTM_FRAME_MIB_T
*)ifr
->ifr_data
)->RxCorrect
= WAN_MIB_TABLE
[ndev
].wrx_correct_pdu
;
482 ((PTM_FRAME_MIB_T
*)ifr
->ifr_data
)->TC_CrcError
= WAN_MIB_TABLE
[ndev
].wrx_tccrc_err_pdu
;
483 ((PTM_FRAME_MIB_T
*)ifr
->ifr_data
)->RxDropped
= WAN_MIB_TABLE
[ndev
].wrx_nodesc_drop_pdu
+ WAN_MIB_TABLE
[ndev
].wrx_len_violation_drop_pdu
;
484 ((PTM_FRAME_MIB_T
*)ifr
->ifr_data
)->TxSend
= WAN_MIB_TABLE
[ndev
].wtx_total_pdu
;
486 case IFX_PTM_CFG_GET
:
487 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcPresent
= CFG_ETH_EFMTC_CRC
->rx_eth_crc_present
;
488 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcCheck
= CFG_ETH_EFMTC_CRC
->rx_eth_crc_check
;
489 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcCheck
= CFG_ETH_EFMTC_CRC
->rx_tc_crc_check
;
490 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
= CFG_ETH_EFMTC_CRC
->rx_tc_crc_len
;
491 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxEthCrcGen
= CFG_ETH_EFMTC_CRC
->tx_eth_crc_gen
;
492 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcGen
= CFG_ETH_EFMTC_CRC
->tx_tc_crc_gen
;
493 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
= CFG_ETH_EFMTC_CRC
->tx_tc_crc_len
;
495 case IFX_PTM_CFG_SET
:
496 CFG_ETH_EFMTC_CRC
->rx_eth_crc_present
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcPresent
? 1 : 0;
497 CFG_ETH_EFMTC_CRC
->rx_eth_crc_check
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcCheck
? 1 : 0;
498 if ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcCheck
&& (((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
== 16 || ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
== 32) )
500 CFG_ETH_EFMTC_CRC
->rx_tc_crc_check
= 1;
501 CFG_ETH_EFMTC_CRC
->rx_tc_crc_len
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
;
505 CFG_ETH_EFMTC_CRC
->rx_tc_crc_check
= 0;
506 CFG_ETH_EFMTC_CRC
->rx_tc_crc_len
= 0;
508 CFG_ETH_EFMTC_CRC
->tx_eth_crc_gen
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxEthCrcGen
? 1 : 0;
509 if ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcGen
&& (((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
== 16 || ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
== 32) )
511 CFG_ETH_EFMTC_CRC
->tx_tc_crc_gen
= 1;
512 CFG_ETH_EFMTC_CRC
->tx_tc_crc_len
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
;
516 CFG_ETH_EFMTC_CRC
->tx_tc_crc_gen
= 0;
517 CFG_ETH_EFMTC_CRC
->tx_tc_crc_len
= 0;
527 static void ptm_tx_timeout(struct net_device
*dev
)
531 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
532 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
534 /* disable TX irq, release skb when sending new packet */
535 IFX_REG_W32_MASK(1 << (ndev
+ 16), 0, MBOX_IGU1_IER
);
537 /* wake up TX queue */
538 netif_wake_queue(dev
);
543 static INLINE
void adsl_led_flash(void)
547 static INLINE
struct sk_buff
* alloc_skb_rx(void)
551 /* allocate memroy including trailer and padding */
552 skb
= dev_alloc_skb(rx_max_packet_size
+ RX_HEAD_MAC_ADDR_ALIGNMENT
+ DATA_BUFFER_ALIGNMENT
);
554 /* must be burst length alignment and reserve two more bytes for MAC address alignment */
555 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 )
556 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
557 /* pub skb in reserved area "skb->data - 4" */
558 *((struct sk_buff
**)skb
->data
- 1) = skb
;
560 /* write back and invalidate cache */
561 dma_cache_wback_inv((unsigned long)skb
->data
- sizeof(skb
), sizeof(skb
));
562 /* invalidate cache */
563 dma_cache_inv((unsigned long)skb
->data
, (unsigned int)skb
->end
- (unsigned int)skb
->data
);
570 static INLINE
struct sk_buff
* alloc_skb_tx(unsigned int size
)
574 /* allocate memory including padding */
575 size
= (size
+ DATA_BUFFER_ALIGNMENT
- 1) & ~(DATA_BUFFER_ALIGNMENT
- 1);
576 skb
= dev_alloc_skb(size
+ DATA_BUFFER_ALIGNMENT
);
577 /* must be burst length alignment */
579 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
584 static INLINE
struct sk_buff
*get_skb_rx_pointer(unsigned int dataptr
)
586 unsigned int skb_dataptr
;
589 skb_dataptr
= ((dataptr
- 1) << 2) | KSEG1
;
590 skb
= *(struct sk_buff
**)skb_dataptr
;
592 ASSERT((unsigned int)skb
>= KSEG0
, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb
, dataptr
);
593 ASSERT(((unsigned int)skb
->data
| KSEG1
) == ((dataptr
<< 2) | KSEG1
), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb
, (unsigned int)skb
->data
, dataptr
);
598 static INLINE
int get_tx_desc(unsigned int itf
, unsigned int *f_full
)
601 struct ptm_itf
*p_itf
= &g_ptm_priv_data
.itf
[itf
];
603 // assume TX is serial operation
604 // no protection provided
608 if ( p_itf
->tx_desc
[p_itf
->tx_desc_pos
].own
== 0 ) {
609 desc_base
= p_itf
->tx_desc_pos
;
610 if ( ++(p_itf
->tx_desc_pos
) == dma_tx_descriptor_length
)
611 p_itf
->tx_desc_pos
= 0;
612 if ( p_itf
->tx_desc
[p_itf
->tx_desc_pos
].own
== 0 )
619 static INLINE
int mailbox_rx_irq_handler(unsigned int ch
) // return: < 0 - descriptor not available, 0 - received one packet
621 unsigned int ndev
= ch
;
623 struct sk_buff
*new_skb
;
624 volatile struct rx_descriptor
*desc
;
625 struct rx_descriptor reg_desc
;
628 desc
= &g_ptm_priv_data
.itf
[ndev
].rx_desc
[g_ptm_priv_data
.itf
[ndev
].rx_desc_pos
];
629 if ( desc
->own
|| !desc
->c
) // if PP32 hold descriptor or descriptor not completed
631 if ( ++g_ptm_priv_data
.itf
[ndev
].rx_desc_pos
== dma_rx_descriptor_length
)
632 g_ptm_priv_data
.itf
[ndev
].rx_desc_pos
= 0;
635 skb
= get_skb_rx_pointer(reg_desc
.dataptr
);
637 if ( !reg_desc
.err
) {
638 new_skb
= alloc_skb_rx();
639 if ( new_skb
!= NULL
) {
640 skb_reserve(skb
, reg_desc
.byteoff
);
641 skb_put(skb
, reg_desc
.datalen
);
643 dump_skb(skb
, DUMP_SKB_LEN
, (char *)__func__
, ndev
, ndev
, 0);
645 // parse protocol header
646 skb
->dev
= g_net_dev
[ndev
];
647 skb
->protocol
= eth_type_trans(skb
, skb
->dev
);
649 g_net_dev
[ndev
]->last_rx
= jiffies
;
651 netif_rx_ret
= netif_receive_skb(skb
);
653 if ( netif_rx_ret
!= NET_RX_DROP
) {
654 g_ptm_priv_data
.itf
[ndev
].stats
.rx_packets
++;
655 g_ptm_priv_data
.itf
[ndev
].stats
.rx_bytes
+= reg_desc
.datalen
;
658 reg_desc
.dataptr
= ((unsigned int)new_skb
->data
>> 2) & 0x0FFFFFFF;
659 reg_desc
.byteoff
= RX_HEAD_MAC_ADDR_ALIGNMENT
;
665 reg_desc
.datalen
= rx_max_packet_size
;
673 mailbox_signal(ndev
, 0);
680 static irqreturn_t
mailbox_irq_handler(int irq
, void *dev_id
)
685 isr
= IFX_REG_R32(MBOX_IGU1_ISR
);
686 IFX_REG_W32(isr
, MBOX_IGU1_ISRC
);
687 isr
&= IFX_REG_R32(MBOX_IGU1_IER
);
689 while ( (i
= __fls(isr
)) >= 0 ) {
694 IFX_REG_W32_MASK(1 << i
, 0, MBOX_IGU1_IER
);
696 if ( i
< MAX_ITF_NUMBER
)
697 netif_wake_queue(g_net_dev
[i
]);
701 #ifdef CONFIG_IFX_PTM_RX_INTERRUPT
702 while ( WRX_DMA_CHANNEL_CONFIG(i
)->vlddes
> 0 )
703 mailbox_rx_irq_handler(i
);
705 IFX_REG_W32_MASK(1 << i
, 0, MBOX_IGU1_IER
);
706 napi_schedule(&g_ptm_priv_data
.itf
[i
].napi
);
714 static INLINE
void mailbox_signal(unsigned int itf
, int is_tx
)
719 while ( MBOX_IGU3_ISR_ISR(itf
+ 16) && count
> 0 )
721 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf
+ 16), MBOX_IGU3_ISRS
);
724 while ( MBOX_IGU3_ISR_ISR(itf
) && count
> 0 )
726 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf
), MBOX_IGU3_ISRS
);
729 ASSERT(count
!= 0, "MBOX_IGU3_ISR = 0x%08x", IFX_REG_R32(MBOX_IGU3_ISR
));
732 #ifdef CONFIG_IFX_PTM_RX_TASKLET
733 static void do_ptm_tasklet(unsigned long arg
)
735 unsigned int work_to_do
= 25;
736 unsigned int work_done
= 0;
738 ASSERT(arg
>= 0 && arg
< ARRAY_SIZE(g_net_dev
), "arg = %lu (wrong value)", arg
);
740 while ( work_done
< work_to_do
&& WRX_DMA_CHANNEL_CONFIG(arg
)->vlddes
> 0 ) {
741 if ( mailbox_rx_irq_handler(arg
) < 0 )
748 if ( !netif_running(g_net_dev
[arg
]) )
752 if ( WRX_DMA_CHANNEL_CONFIG(arg
)->vlddes
== 0 ) {
754 IFX_REG_W32_MASK(0, 1 << arg
, MBOX_IGU1_ISRC
);
756 if ( WRX_DMA_CHANNEL_CONFIG(arg
)->vlddes
== 0 ) {
757 IFX_REG_W32_MASK(0, 1 << arg
, MBOX_IGU1_IER
);
763 tasklet_schedule(&g_ptm_tasklet
[arg
]);
767 #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
768 static void dump_skb(struct sk_buff
*skb
, u32 len
, char *title
, int port
, int ch
, int is_tx
)
772 if ( !(ifx_ptm_dbg_enable
& (is_tx
? DBG_ENABLE_MASK_DUMP_SKB_TX
: DBG_ENABLE_MASK_DUMP_SKB_RX
)) )
775 if ( skb
->len
< len
)
778 if ( len
> rx_max_packet_size
) {
779 printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (u32
)skb
, (u32
)skb
->data
, skb
->len
);
784 printk("%s (port %d, ch %d)\n", title
, port
, ch
);
786 printk("%s\n", title
);
787 printk(" skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (u32
)skb
->data
, (u32
)skb
->tail
, (int)skb
->len
);
788 for ( i
= 1; i
<= len
; i
++ ) {
790 printk(" %4d:", i
- 1);
791 printk(" %02X", (int)(*((char*)skb
->data
+ i
- 1) & 0xFF));
795 if ( (i
- 1) % 16 != 0 )
800 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
801 static void skb_swap(struct sk_buff
*skb
)
803 unsigned char tmp
[8];
804 unsigned char *p
= skb
->data
;
806 if ( !(p
[0] & 0x01) ) { // bypass broadcast/multicast
810 memcpy(p
+ 6, tmp
, 6);
814 while ( p
[0] == 0x81 && p
[1] == 0x00 )
818 if ( p
[0] == 0x08 && p
[1] == 0x00 ) {
822 memcpy(p
+ 4, tmp
, 4);
826 dma_cache_wback((unsigned long)skb
->data
, (unsigned long)p
- (unsigned long)skb
->data
);
831 static INLINE
void proc_file_create(void)
833 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
834 struct proc_dir_entry
*res
;
836 g_ptm_dir
= proc_mkdir("driver/ifx_ptm", NULL
);
838 create_proc_read_entry("version",
844 res
= create_proc_entry("wanmib",
848 res
->read_proc
= proc_read_wanmib
;
849 res
->write_proc
= proc_write_wanmib
;
852 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
853 create_proc_read_entry("genconf",
860 create_proc_read_entry("regs",
863 ifx_ptm_proc_read_regs
,
868 res
= create_proc_entry("dbg",
872 res
->read_proc
= proc_read_dbg
;
873 res
->write_proc
= proc_write_dbg
;
878 static INLINE
void proc_file_delete(void)
880 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
881 remove_proc_entry("dbg", g_ptm_dir
);
884 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
886 remove_proc_entry("regs", g_ptm_dir
);
889 remove_proc_entry("genconf", g_ptm_dir
);
892 remove_proc_entry("wanmib", g_ptm_dir
);
894 remove_proc_entry("version", g_ptm_dir
);
896 remove_proc_entry("driver/ifx_ptm", NULL
);
899 static int proc_read_version(char *buf
, char **start
, off_t offset
, int count
, int *eof
, void *data
)
903 len
+= ifx_ptm_version(buf
+ len
);
905 if ( offset
>= len
) {
910 *start
= buf
+ offset
;
911 if ( (len
-= offset
) > count
)
917 static int proc_read_wanmib(char *page
, char **start
, off_t off
, int count
, int *eof
, void *data
)
926 for ( i
= 0; i
< ARRAY_SIZE(title
); i
++ ) {
927 len
+= sprintf(page
+ off
+ len
, title
[i
]);
928 len
+= sprintf(page
+ off
+ len
, " wrx_correct_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_correct_pdu
);
929 len
+= sprintf(page
+ off
+ len
, " wrx_correct_pdu_bytes = %d\n", WAN_MIB_TABLE
[i
].wrx_correct_pdu_bytes
);
930 len
+= sprintf(page
+ off
+ len
, " wrx_tccrc_err_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_tccrc_err_pdu
);
931 len
+= sprintf(page
+ off
+ len
, " wrx_tccrc_err_pdu_bytes = %d\n", WAN_MIB_TABLE
[i
].wrx_tccrc_err_pdu_bytes
);
932 len
+= sprintf(page
+ off
+ len
, " wrx_ethcrc_err_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_ethcrc_err_pdu
);
933 len
+= sprintf(page
+ off
+ len
, " wrx_ethcrc_err_pdu_bytes = %d\n", WAN_MIB_TABLE
[i
].wrx_ethcrc_err_pdu_bytes
);
934 len
+= sprintf(page
+ off
+ len
, " wrx_nodesc_drop_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_nodesc_drop_pdu
);
935 len
+= sprintf(page
+ off
+ len
, " wrx_len_violation_drop_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_len_violation_drop_pdu
);
936 len
+= sprintf(page
+ off
+ len
, " wrx_idle_bytes = %d\n", WAN_MIB_TABLE
[i
].wrx_idle_bytes
);
937 len
+= sprintf(page
+ off
+ len
, " wrx_nonidle_cw = %d\n", WAN_MIB_TABLE
[i
].wrx_nonidle_cw
);
938 len
+= sprintf(page
+ off
+ len
, " wrx_idle_cw = %d\n", WAN_MIB_TABLE
[i
].wrx_idle_cw
);
939 len
+= sprintf(page
+ off
+ len
, " wrx_err_cw = %d\n", WAN_MIB_TABLE
[i
].wrx_err_cw
);
940 len
+= sprintf(page
+ off
+ len
, " wtx_total_pdu = %d\n", WAN_MIB_TABLE
[i
].wtx_total_pdu
);
941 len
+= sprintf(page
+ off
+ len
, " wtx_total_bytes = %d\n", WAN_MIB_TABLE
[i
].wtx_total_bytes
);
949 static int proc_write_wanmib(struct file
*file
, const char *buf
, unsigned long count
, void *data
)
957 len
= count
< sizeof(str
) ? count
: sizeof(str
) - 1;
958 rlen
= len
- copy_from_user(str
, buf
, len
);
959 while ( rlen
&& str
[rlen
- 1] <= ' ' )
962 for ( p
= str
; *p
&& *p
<= ' '; p
++, rlen
-- );
966 if ( stricmp(p
, "clear") == 0 || stricmp(p
, "clean") == 0 ) {
967 for ( i
= 0; i
< 2; i
++ )
968 memset((void*)&WAN_MIB_TABLE
[i
], 0, sizeof(WAN_MIB_TABLE
[i
]));
974 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
976 static int proc_read_genconf(char *page
, char **start
, off_t off
, int count
, int *eof
, void *data
)
979 int len_max
= off
+ count
;
986 pstr
= *start
= page
;
990 llen
+= sprintf(str
+ llen
, "CFG_WAN_WRDES_DELAY (0x%08X): %d\n", (unsigned int)CFG_WAN_WRDES_DELAY
, IFX_REG_R32(CFG_WAN_WRDES_DELAY
));
991 llen
+= sprintf(str
+ llen
, "CFG_WRX_DMACH_ON (0x%08X):", (unsigned int)CFG_WRX_DMACH_ON
);
992 for ( i
= 0, bit
= 1; i
< MAX_RX_DMA_CHANNEL_NUMBER
; i
++, bit
<<= 1 )
993 llen
+= sprintf(str
+ llen
, " %d - %s", i
, (IFX_REG_R32(CFG_WRX_DMACH_ON
) & bit
) ? "on " : "off");
994 llen
+= sprintf(str
+ llen
, "\n");
995 llen
+= sprintf(str
+ llen
, "CFG_WTX_DMACH_ON (0x%08X):", (unsigned int)CFG_WTX_DMACH_ON
);
996 for ( i
= 0, bit
= 1; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++, bit
<<= 1 )
997 llen
+= sprintf(str
+ llen
, " %d - %s", i
, (IFX_REG_R32(CFG_WTX_DMACH_ON
) & bit
) ? "on " : "off");
998 llen
+= sprintf(str
+ llen
, "\n");
999 llen
+= sprintf(str
+ llen
, "CFG_WRX_LOOK_BITTH (0x%08X): %d\n", (unsigned int)CFG_WRX_LOOK_BITTH
, IFX_REG_R32(CFG_WRX_LOOK_BITTH
));
1000 llen
+= sprintf(str
+ llen
, "CFG_ETH_EFMTC_CRC (0x%08X): rx_tc_crc_len - %2d, rx_tc_crc_check - %s\n", (unsigned int)CFG_ETH_EFMTC_CRC
, CFG_ETH_EFMTC_CRC
->rx_tc_crc_len
, CFG_ETH_EFMTC_CRC
->rx_tc_crc_check
? " on" : "off");
1001 llen
+= sprintf(str
+ llen
, " rx_eth_crc_check - %s, rx_eth_crc_present - %s\n", CFG_ETH_EFMTC_CRC
->rx_eth_crc_check
? " on" : "off", CFG_ETH_EFMTC_CRC
->rx_eth_crc_present
? " on" : "off");
1002 llen
+= sprintf(str
+ llen
, " tx_tc_crc_len - %2d, tx_tc_crc_gen - %s\n", CFG_ETH_EFMTC_CRC
->tx_tc_crc_len
, CFG_ETH_EFMTC_CRC
->tx_tc_crc_gen
? " on" : "off");
1003 llen
+= sprintf(str
+ llen
, " tx_eth_crc_gen - %s\n", CFG_ETH_EFMTC_CRC
->tx_eth_crc_gen
? " on" : "off");
1005 llen
+= sprintf(str
+ llen
, "RX Port:\n");
1006 for ( i
= 0; i
< MAX_RX_DMA_CHANNEL_NUMBER
; i
++ )
1007 llen
+= sprintf(str
+ llen
, " %d (0x%08X). mfs - %5d, dmach - %d, local_state - %d, partner_state - %d\n", i
, (unsigned int)WRX_PORT_CONFIG(i
), WRX_PORT_CONFIG(i
)->mfs
, WRX_PORT_CONFIG(i
)->dmach
, WRX_PORT_CONFIG(i
)->local_state
, WRX_PORT_CONFIG(i
)->partner_state
);
1008 llen
+= sprintf(str
+ llen
, "RX DMA Channel:\n");
1009 for ( i
= 0; i
< MAX_RX_DMA_CHANNEL_NUMBER
; i
++ )
1010 llen
+= sprintf(str
+ llen
, " %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\n", i
, (unsigned int)WRX_DMA_CHANNEL_CONFIG(i
), WRX_DMA_CHANNEL_CONFIG(i
)->desba
, ((unsigned int)WRX_DMA_CHANNEL_CONFIG(i
)->desba
<< 2) | KSEG1
, WRX_DMA_CHANNEL_CONFIG(i
)->deslen
, WRX_DMA_CHANNEL_CONFIG(i
)->vlddes
);
1012 llen
+= sprintf(str
+ llen
, "TX Port:\n");
1013 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ )
1014 llen
+= sprintf(str
+ llen
, " %d (0x%08X). tx_cwth2 - %d, tx_cwth1 - %d\n", i
, (unsigned int)WTX_PORT_CONFIG(i
), WTX_PORT_CONFIG(i
)->tx_cwth2
, WTX_PORT_CONFIG(i
)->tx_cwth1
);
1015 llen
+= sprintf(str
+ llen
, "TX DMA Channel:\n");
1016 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ )
1017 llen
+= sprintf(str
+ llen
, " %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\n", i
, (unsigned int)WTX_DMA_CHANNEL_CONFIG(i
), WTX_DMA_CHANNEL_CONFIG(i
)->desba
, ((unsigned int)WTX_DMA_CHANNEL_CONFIG(i
)->desba
<< 2) | KSEG1
, WTX_DMA_CHANNEL_CONFIG(i
)->deslen
, WTX_DMA_CHANNEL_CONFIG(i
)->vlddes
);
1019 if ( len
<= off
&& len
+ llen
> off
)
1021 memcpy(pstr
, str
+ off
- len
, len
+ llen
- off
);
1022 pstr
+= len
+ llen
- off
;
1024 else if ( len
> off
)
1026 memcpy(pstr
, str
, llen
);
1030 if ( len
>= len_max
)
1031 goto PROC_READ_GENCONF_OVERRUN_END
;
1037 PROC_READ_GENCONF_OVERRUN_END
:
1038 return len
- llen
- off
;
1041 #endif // defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
1043 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1045 static int proc_read_dbg(char *page
, char **start
, off_t off
, int count
, int *eof
, void *data
)
1049 len
+= sprintf(page
+ off
+ len
, "error print - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_ERR
) ? "enabled" : "disabled");
1050 len
+= sprintf(page
+ off
+ len
, "debug print - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_DEBUG_PRINT
) ? "enabled" : "disabled");
1051 len
+= sprintf(page
+ off
+ len
, "assert - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_ASSERT
) ? "enabled" : "disabled");
1052 len
+= sprintf(page
+ off
+ len
, "dump rx skb - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_DUMP_SKB_RX
) ? "enabled" : "disabled");
1053 len
+= sprintf(page
+ off
+ len
, "dump tx skb - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_DUMP_SKB_TX
) ? "enabled" : "disabled");
1054 len
+= sprintf(page
+ off
+ len
, "mac swap - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_MAC_SWAP
) ? "enabled" : "disabled");
1061 static int proc_write_dbg(struct file
*file
, const char *buf
, unsigned long count
, void *data
)
1063 static const char *dbg_enable_mask_str
[] = {
1082 static const int dbg_enable_mask_str_len
[] = {
1093 unsigned int dbg_enable_mask
[] = {
1094 DBG_ENABLE_MASK_ERR
,
1095 DBG_ENABLE_MASK_DEBUG_PRINT
,
1096 DBG_ENABLE_MASK_ASSERT
,
1097 DBG_ENABLE_MASK_DUMP_SKB_RX
,
1098 DBG_ENABLE_MASK_DUMP_SKB_TX
,
1099 DBG_ENABLE_MASK_DUMP_INIT
,
1100 DBG_ENABLE_MASK_DUMP_QOS
,
1101 DBG_ENABLE_MASK_MAC_SWAP
,
1113 len
= count
< sizeof(str
) ? count
: sizeof(str
) - 1;
1114 rlen
= len
- copy_from_user(str
, buf
, len
);
1115 while ( rlen
&& str
[rlen
- 1] <= ' ' )
1118 for ( p
= str
; *p
&& *p
<= ' '; p
++, rlen
-- );
1122 // debugging feature for enter/leave showtime
1123 if ( strincmp(p
, "enter", 5) == 0 && ifx_mei_atm_showtime_enter
!= NULL
)
1124 ifx_mei_atm_showtime_enter(NULL
, NULL
);
1125 else if ( strincmp(p
, "leave", 5) == 0 && ifx_mei_atm_showtime_exit
!= NULL
)
1126 ifx_mei_atm_showtime_exit();
1128 if ( strincmp(p
, "enable", 6) == 0 ) {
1132 else if ( strincmp(p
, "disable", 7) == 0 ) {
1136 else if ( strincmp(p
, "help", 4) == 0 || *p
== '?' ) {
1137 printk("echo <enable/disable> [err/dbg/assert/rx/tx/init/qos/swap/all] > /proc/driver/ifx_ptm/dbg\n");
1143 ifx_ptm_dbg_enable
|= DBG_ENABLE_MASK_ALL
& ~DBG_ENABLE_MASK_MAC_SWAP
;
1145 ifx_ptm_dbg_enable
&= ~DBG_ENABLE_MASK_ALL
| DBG_ENABLE_MASK_MAC_SWAP
;
1149 for ( i
= 0; i
< ARRAY_SIZE(dbg_enable_mask_str
); i
++ )
1150 if ( strincmp(p
, dbg_enable_mask_str
[i
], dbg_enable_mask_str_len
[i
]) == 0 ) {
1152 ifx_ptm_dbg_enable
|= dbg_enable_mask
[i
>> 1];
1154 ifx_ptm_dbg_enable
&= ~dbg_enable_mask
[i
>> 1];
1155 p
+= dbg_enable_mask_str_len
[i
];
1158 } while ( i
< ARRAY_SIZE(dbg_enable_mask_str
) );
1165 #endif // defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1167 static INLINE
int stricmp(const char *p1
, const char *p2
)
1171 while ( *p1
&& *p2
)
1173 c1
= *p1
>= 'A' && *p1
<= 'Z' ? *p1
+ 'a' - 'A' : *p1
;
1174 c2
= *p2
>= 'A' && *p2
<= 'Z' ? *p2
+ 'a' - 'A' : *p2
;
1184 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1185 static INLINE
int strincmp(const char *p1
, const char *p2
, int n
)
1189 while ( n
&& *p1
&& *p2
)
1191 c1
= *p1
>= 'A' && *p1
<= 'Z' ? *p1
+ 'a' - 'A' : *p1
;
1192 c2
= *p2
>= 'A' && *p2
<= 'Z' ? *p2
+ 'a' - 'A' : *p2
;
1200 return n
? *p1
- *p2
: c1
;
1204 static INLINE
int ifx_ptm_version(char *buf
)
1207 unsigned int major
, minor
;
1209 ifx_ptm_get_fw_ver(&major
, &minor
);
1211 len
+= sprintf(buf
+ len
, "PTM %d.%d.%d", IFX_PTM_VER_MAJOR
, IFX_PTM_VER_MID
, IFX_PTM_VER_MINOR
);
1212 len
+= sprintf(buf
+ len
, " PTM (E1) firmware version %d.%d\n", major
, minor
);
1217 static INLINE
void check_parameters(void)
1219 /* There is a delay between PPE write descriptor and descriptor is */
1220 /* really stored in memory. Host also has this delay when writing */
1221 /* descriptor. So PPE will use this value to determine if the write */
1222 /* operation makes effect. */
1223 if ( write_desc_delay
< 0 )
1224 write_desc_delay
= 0;
1226 /* Because of the limitation of length field in descriptors, the packet */
1227 /* size could not be larger than 64K minus overhead size. */
1228 if ( rx_max_packet_size
< ETH_MIN_FRAME_LENGTH
)
1229 rx_max_packet_size
= ETH_MIN_FRAME_LENGTH
;
1230 else if ( rx_max_packet_size
> 65536 - 1 )
1231 rx_max_packet_size
= 65536 - 1;
1233 if ( dma_rx_descriptor_length
< 2 )
1234 dma_rx_descriptor_length
= 2;
1235 if ( dma_tx_descriptor_length
< 2 )
1236 dma_tx_descriptor_length
= 2;
1239 static INLINE
int init_priv_data(void)
1243 struct rx_descriptor rx_desc
= {0};
1244 struct sk_buff
*skb
;
1245 volatile struct rx_descriptor
*p_rx_desc
;
1246 volatile struct tx_descriptor
*p_tx_desc
;
1247 struct sk_buff
**ppskb
;
1249 // clear ptm private data structure
1250 memset(&g_ptm_priv_data
, 0, sizeof(g_ptm_priv_data
));
1252 // allocate memory for RX descriptors
1253 p
= kzalloc(MAX_ITF_NUMBER
* dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1256 dma_cache_inv((unsigned long)p
, MAX_ITF_NUMBER
* dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1257 g_ptm_priv_data
.rx_desc_base
= p
;
1258 //p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1260 // allocate memory for TX descriptors
1261 p
= kzalloc(MAX_ITF_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1264 dma_cache_inv((unsigned long)p
, MAX_ITF_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
);
1265 g_ptm_priv_data
.tx_desc_base
= p
;
1267 // allocate memroy for TX skb pointers
1268 p
= kzalloc(MAX_ITF_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4, GFP_KERNEL
);
1271 dma_cache_wback_inv((unsigned long)p
, MAX_ITF_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4);
1272 g_ptm_priv_data
.tx_skb_base
= p
;
1274 p_rx_desc
= (volatile struct rx_descriptor
*)((((unsigned int)g_ptm_priv_data
.rx_desc_base
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1275 p_tx_desc
= (volatile struct tx_descriptor
*)((((unsigned int)g_ptm_priv_data
.tx_desc_base
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1276 ppskb
= (struct sk_buff
**)(((unsigned int)g_ptm_priv_data
.tx_skb_base
+ 3) & ~3);
1277 for ( i
= 0; i
< MAX_ITF_NUMBER
; i
++ ) {
1278 g_ptm_priv_data
.itf
[i
].rx_desc
= &p_rx_desc
[i
* dma_rx_descriptor_length
];
1279 g_ptm_priv_data
.itf
[i
].tx_desc
= &p_tx_desc
[i
* dma_tx_descriptor_length
];
1280 g_ptm_priv_data
.itf
[i
].tx_skb
= &ppskb
[i
* dma_tx_descriptor_length
];
1287 rx_desc
.byteoff
= RX_HEAD_MAC_ADDR_ALIGNMENT
;
1290 rx_desc
.datalen
= rx_max_packet_size
;
1291 for ( i
= 0; i
< MAX_ITF_NUMBER
* dma_rx_descriptor_length
; i
++ ) {
1292 skb
= alloc_skb_rx();
1295 rx_desc
.dataptr
= ((unsigned int)skb
->data
>> 2) & 0x0FFFFFFF;
1296 p_rx_desc
[i
] = rx_desc
;
1302 static INLINE
void clear_priv_data(void)
1305 struct sk_buff
*skb
;
1307 for ( i
= 0; i
< MAX_ITF_NUMBER
; i
++ ) {
1308 if ( g_ptm_priv_data
.itf
[i
].tx_skb
!= NULL
) {
1309 for ( j
= 0; j
< dma_tx_descriptor_length
; j
++ )
1310 if ( g_ptm_priv_data
.itf
[i
].tx_skb
[j
] != NULL
)
1311 dev_kfree_skb_any(g_ptm_priv_data
.itf
[i
].tx_skb
[j
]);
1313 if ( g_ptm_priv_data
.itf
[i
].rx_desc
!= NULL
) {
1314 for ( j
= 0; j
< dma_rx_descriptor_length
; j
++ ) {
1315 if ( g_ptm_priv_data
.itf
[i
].rx_desc
[j
].sop
|| g_ptm_priv_data
.itf
[i
].rx_desc
[j
].eop
) { // descriptor initialized
1316 skb
= get_skb_rx_pointer(g_ptm_priv_data
.itf
[i
].rx_desc
[j
].dataptr
);
1317 dev_kfree_skb_any(skb
);
1323 if ( g_ptm_priv_data
.rx_desc_base
!= NULL
)
1324 kfree(g_ptm_priv_data
.rx_desc_base
);
1326 if ( g_ptm_priv_data
.tx_desc_base
!= NULL
)
1327 kfree(g_ptm_priv_data
.tx_desc_base
);
1329 if ( g_ptm_priv_data
.tx_skb_base
!= NULL
)
1330 kfree(g_ptm_priv_data
.tx_skb_base
);
1333 static INLINE
void init_tables(void)
1336 volatile unsigned int *p
;
1337 struct wrx_dma_channel_config rx_config
= {0};
1338 struct wtx_dma_channel_config tx_config
= {0};
1339 struct wrx_port_cfg_status rx_port_cfg
= { 0 };
1340 struct wtx_port_cfg tx_port_cfg
= { 0 };
1345 IFX_REG_W32(CDM_CFG_RAM1_SET(0x00) | CDM_CFG_RAM0_SET(0x00), CDM_CFG
); // CDM block 1 must be data memory and mapped to 0x5000 (dword addr)
1346 p
= CDM_DATA_MEMORY(0, 0); // Clear CDM block 1
1347 for ( i
= 0; i
< CDM_DATA_MEMORY_DWLEN
; i
++, p
++ )
1353 IFX_REG_W32(write_desc_delay
, CFG_WAN_WRDES_DELAY
);
1354 IFX_REG_W32((1 << MAX_RX_DMA_CHANNEL_NUMBER
) - 1, CFG_WRX_DMACH_ON
);
1355 IFX_REG_W32((1 << MAX_TX_DMA_CHANNEL_NUMBER
) - 1, CFG_WTX_DMACH_ON
);
1357 IFX_REG_W32(8, CFG_WRX_LOOK_BITTH
); // WAN RX EFM-TC Looking Threshold
1359 IFX_REG_W32(eth_efmtc_crc_cfg
, CFG_ETH_EFMTC_CRC
);
1362 * WRX DMA Channel Configuration Table
1364 rx_config
.deslen
= dma_rx_descriptor_length
;
1365 rx_port_cfg
.mfs
= ETH_MAX_FRAME_LENGTH
;
1366 rx_port_cfg
.local_state
= 0; // looking for sync
1367 rx_port_cfg
.partner_state
= 0; // parter receiver is out of sync
1369 for ( i
= 0; i
< MAX_RX_DMA_CHANNEL_NUMBER
; i
++ ) {
1370 rx_config
.desba
= ((unsigned int)g_ptm_priv_data
.itf
[i
].rx_desc
>> 2) & 0x0FFFFFFF;
1371 *WRX_DMA_CHANNEL_CONFIG(i
) = rx_config
;
1373 rx_port_cfg
.dmach
= i
;
1374 *WRX_PORT_CONFIG(i
) = rx_port_cfg
;
1378 * WTX DMA Channel Configuration Table
1380 tx_config
.deslen
= dma_tx_descriptor_length
;
1381 tx_port_cfg
.tx_cwth1
= 5;
1382 tx_port_cfg
.tx_cwth2
= 4;
1384 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1385 tx_config
.desba
= ((unsigned int)g_ptm_priv_data
.itf
[i
].tx_desc
>> 2) & 0x0FFFFFFF;
1386 *WTX_DMA_CHANNEL_CONFIG(i
) = tx_config
;
1388 *WTX_PORT_CONFIG(i
) = tx_port_cfg
;
1395 * ####################################
1397 * ####################################
1400 static int ptm_showtime_enter(struct port_cell_info
*port_cell
, void *xdata_addr
)
1406 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
1407 netif_carrier_on(g_net_dev
[i
]);
1409 printk("enter showtime\n");
1414 static int ptm_showtime_exit(void)
1421 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
1422 netif_carrier_off(g_net_dev
[i
]);
1426 printk("leave showtime\n");
1434 * ####################################
1436 * ####################################
1441 * Initialize global variables, PP32, comunication structures, register IRQ
1442 * and register device.
1447 * else --- failure, usually it is negative value of error code
1449 static int ifx_ptm_init(void)
1452 struct port_cell_info port_cell
= {0};
1453 void *xdata_addr
= NULL
;
1459 ret
= init_priv_data();
1461 err("INIT_PRIV_DATA_FAIL");
1462 goto INIT_PRIV_DATA_FAIL
;
1465 ifx_ptm_init_chip();
1468 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1469 g_net_dev
[i
] = alloc_netdev(0, g_net_dev_name
[i
], NET_NAME_UNKNOWN
, ether_setup
);
1470 if ( g_net_dev
[i
] == NULL
)
1471 goto ALLOC_NETDEV_FAIL
;
1472 ptm_setup(g_net_dev
[i
], i
);
1475 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1476 ret
= register_netdev(g_net_dev
[i
]);
1478 goto REGISTER_NETDEV_FAIL
;
1481 /* register interrupt handler */
1482 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1483 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, 0, "ptm_mailbox_isr", &g_ptm_priv_data
);
1485 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, IRQF_DISABLED
, "ptm_mailbox_isr", &g_ptm_priv_data
);
1488 if ( ret
== -EBUSY
) {
1489 err("IRQ may be occupied by other driver, please reconfig to disable it.");
1492 err("request_irq fail");
1494 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
1496 disable_irq(PPE_MAILBOX_IGU1_INT
);
1498 ret
= ifx_pp32_start(0);
1500 err("ifx_pp32_start fail!");
1501 goto PP32_START_FAIL
;
1503 IFX_REG_W32(0, MBOX_IGU1_IER
);
1504 IFX_REG_W32(~0, MBOX_IGU1_ISRC
);
1506 enable_irq(PPE_MAILBOX_IGU1_INT
);
1511 port_cell
.port_num
= 1;
1512 ifx_mei_atm_showtime_check(&g_showtime
, &port_cell
, &xdata_addr
);
1514 ifx_mei_atm_showtime_enter
= ptm_showtime_enter
;
1515 ifx_mei_atm_showtime_exit
= ptm_showtime_exit
;
1517 ifx_ptm_version(ver_str
);
1518 printk(KERN_INFO
"%s", ver_str
);
1520 printk("ifxmips_ptm: PTM init succeed\n");
1525 free_irq(PPE_MAILBOX_IGU1_INT
, &g_ptm_priv_data
);
1526 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
:
1527 i
= ARRAY_SIZE(g_net_dev
);
1528 REGISTER_NETDEV_FAIL
:
1530 unregister_netdev(g_net_dev
[i
]);
1531 i
= ARRAY_SIZE(g_net_dev
);
1534 free_netdev(g_net_dev
[i
]);
1535 g_net_dev
[i
] = NULL
;
1537 INIT_PRIV_DATA_FAIL
:
1539 printk("ifxmips_ptm: PTM init failed\n");
1545 * Release memory, free IRQ, and deregister device.
1551 static void __exit
ifx_ptm_exit(void)
1555 ifx_mei_atm_showtime_enter
= NULL
;
1556 ifx_mei_atm_showtime_exit
= NULL
;
1563 free_irq(PPE_MAILBOX_IGU1_INT
, &g_ptm_priv_data
);
1565 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
1566 unregister_netdev(g_net_dev
[i
]);
1568 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1569 free_netdev(g_net_dev
[i
]);
1570 g_net_dev
[i
] = NULL
;
1573 ifx_ptm_uninit_chip();
1578 module_init(ifx_ptm_init
);
1579 module_exit(ifx_ptm_exit
);