1 /******************************************************************************
3 ** FILE NAME : ifxmips_ptm_vdsl.c
9 ** DESCRIPTION : PTM driver common source file (core functions for VR9)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
24 #include <linux/version.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/ctype.h>
29 #include <linux/errno.h>
30 #include <linux/proc_fs.h>
31 #include <linux/init.h>
32 #include <linux/ioctl.h>
33 #include <linux/etherdevice.h>
34 #include <linux/interrupt.h>
35 #include <linux/netdevice.h>
36 #include <linux/platform_device.h>
37 #include <linux/of_device.h>
39 #include "ifxmips_ptm_vdsl.h"
40 #include <lantiq_soc.h>
42 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
43 #define MODULE_PARM(a, b) module_param(a, int, 0)
45 static int wanqos_en
= 0;
46 static int queue_gamma_map
[4] = {0xFE, 0x01, 0x00, 0x00};
48 MODULE_PARM(wanqos_en
, "i");
49 MODULE_PARM_DESC(wanqos_en
, "WAN QoS support, 1 - enabled, 0 - disabled.");
51 MODULE_PARM_ARRAY(queue_gamma_map
, "4-4i");
52 MODULE_PARM_DESC(queue_gamma_map
, "TX QoS queues mapping to 4 TX Gamma interfaces.");
54 extern int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *);
55 extern int (*ifx_mei_atm_showtime_exit
)(void);
56 extern int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
);
58 static int g_showtime
= 0;
59 static void *g_xdata_addr
= NULL
;
62 #define ENABLE_TMP_DBG 0
64 unsigned long cgu_get_pp32_clock(void)
66 struct clk
*c
= clk_get_ppe();
67 unsigned long rate
= clk_get_rate(c
);
72 static void ptm_setup(struct net_device
*, int);
73 static struct net_device_stats
*ptm_get_stats(struct net_device
*);
74 static int ptm_open(struct net_device
*);
75 static int ptm_stop(struct net_device
*);
76 static unsigned int ptm_poll(int, unsigned int);
77 static int ptm_napi_poll(struct napi_struct
*, int);
78 static int ptm_hard_start_xmit(struct sk_buff
*, struct net_device
*);
79 static int ptm_ioctl(struct net_device
*, struct ifreq
*, int);
80 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)
81 static void ptm_tx_timeout(struct net_device
*);
83 static void ptm_tx_timeout(struct net_device
*, unsigned int txqueue
);
86 static inline struct sk_buff
* alloc_skb_rx(void);
87 static inline struct sk_buff
* alloc_skb_tx(unsigned int);
88 static inline struct sk_buff
*get_skb_pointer(unsigned int);
89 static inline int get_tx_desc(unsigned int, unsigned int *);
92 * Mailbox handler and signal function
94 static irqreturn_t
mailbox_irq_handler(int, void *);
97 * Tasklet to Handle Swap Descriptors
99 static void do_swap_desc_tasklet(unsigned long);
103 * Init & clean-up functions
105 static inline int init_priv_data(void);
106 static inline void clear_priv_data(void);
107 static inline int init_tables(void);
108 static inline void clear_tables(void);
110 static int g_wanqos_en
= 0;
112 static int g_queue_gamma_map
[4];
114 static struct ptm_priv_data g_ptm_priv_data
;
116 static struct net_device_ops g_ptm_netdev_ops
= {
117 .ndo_get_stats
= ptm_get_stats
,
118 .ndo_open
= ptm_open
,
119 .ndo_stop
= ptm_stop
,
120 .ndo_start_xmit
= ptm_hard_start_xmit
,
121 .ndo_validate_addr
= eth_validate_addr
,
122 .ndo_set_mac_address
= eth_mac_addr
,
123 .ndo_do_ioctl
= ptm_ioctl
,
124 .ndo_tx_timeout
= ptm_tx_timeout
,
127 static struct net_device
*g_net_dev
[1] = {0};
128 static char *g_net_dev_name
[1] = {"dsl0"};
130 static int g_ptm_prio_queue_map
[8];
132 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)
133 static DECLARE_TASKLET(g_swap_desc_tasklet
, do_swap_desc_tasklet
, 0);
135 static DECLARE_TASKLET_OLD(g_swap_desc_tasklet
, do_swap_desc_tasklet
);
139 unsigned int ifx_ptm_dbg_enable
= DBG_ENABLE_MASK_ERR
;
142 * ####################################
144 * ####################################
147 static void ptm_setup(struct net_device
*dev
, int ndev
)
149 netif_carrier_off(dev
);
151 dev
->netdev_ops
= &g_ptm_netdev_ops
;
152 /* Allow up to 1508 bytes, for RFC4638 */
153 dev
->max_mtu
= ETH_DATA_LEN
+ 8;
154 netif_napi_add(dev
, &g_ptm_priv_data
.itf
[ndev
].napi
, ptm_napi_poll
, 16);
155 dev
->watchdog_timeo
= ETH_WATCHDOG_TIMEOUT
;
157 dev
->dev_addr
[0] = 0x00;
158 dev
->dev_addr
[1] = 0x20;
159 dev
->dev_addr
[2] = 0xda;
160 dev
->dev_addr
[3] = 0x86;
161 dev
->dev_addr
[4] = 0x23;
162 dev
->dev_addr
[5] = 0x75 + ndev
;
165 static struct net_device_stats
*ptm_get_stats(struct net_device
*dev
)
167 struct net_device_stats
*s
;
169 if ( dev
!= g_net_dev
[0] )
171 s
= &g_ptm_priv_data
.itf
[0].stats
;
176 static int ptm_open(struct net_device
*dev
)
178 ASSERT(dev
== g_net_dev
[0], "incorrect device");
180 napi_enable(&g_ptm_priv_data
.itf
[0].napi
);
182 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER
);
184 netif_start_queue(dev
);
189 static int ptm_stop(struct net_device
*dev
)
191 ASSERT(dev
== g_net_dev
[0], "incorrect device");
193 IFX_REG_W32_MASK(1 | (1 << 17), 0, MBOX_IGU1_IER
);
195 napi_disable(&g_ptm_priv_data
.itf
[0].napi
);
197 netif_stop_queue(dev
);
202 static unsigned int ptm_poll(int ndev
, unsigned int work_to_do
)
204 unsigned int work_done
= 0;
205 volatile struct rx_descriptor
*desc
;
206 struct rx_descriptor reg_desc
;
207 struct sk_buff
*skb
, *new_skb
;
209 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
211 while ( work_done
< work_to_do
) {
212 desc
= &WAN_RX_DESC_BASE
[g_ptm_priv_data
.itf
[0].rx_desc_pos
];
213 if ( desc
->own
/* || !desc->c */ ) // if PP32 hold descriptor or descriptor not completed
215 if ( ++g_ptm_priv_data
.itf
[0].rx_desc_pos
== WAN_RX_DESC_NUM
)
216 g_ptm_priv_data
.itf
[0].rx_desc_pos
= 0;
219 skb
= get_skb_pointer(reg_desc
.dataptr
);
220 ASSERT(skb
!= NULL
, "invalid pointer skb == NULL");
222 new_skb
= alloc_skb_rx();
223 if ( new_skb
!= NULL
) {
224 skb_reserve(skb
, reg_desc
.byteoff
);
225 skb_put(skb
, reg_desc
.datalen
);
227 // parse protocol header
228 skb
->dev
= g_net_dev
[0];
229 skb
->protocol
= eth_type_trans(skb
, skb
->dev
);
231 netif_receive_skb(skb
);
233 g_ptm_priv_data
.itf
[0].stats
.rx_packets
++;
234 g_ptm_priv_data
.itf
[0].stats
.rx_bytes
+= reg_desc
.datalen
;
236 reg_desc
.dataptr
= (unsigned int)new_skb
->data
& 0x0FFFFFFF;
237 reg_desc
.byteoff
= RX_HEAD_MAC_ADDR_ALIGNMENT
;
240 reg_desc
.datalen
= RX_MAX_BUFFER_SIZE
- RX_HEAD_MAC_ADDR_ALIGNMENT
;
244 /* write discriptor to memory */
245 *((volatile unsigned int *)desc
+ 1) = *((unsigned int *)®_desc
+ 1);
247 *(volatile unsigned int *)desc
= *(unsigned int *)®_desc
;
255 static int ptm_napi_poll(struct napi_struct
*napi
, int budget
)
258 unsigned int work_done
;
260 work_done
= ptm_poll(ndev
, budget
);
263 if ( !netif_running(napi
->dev
) ) {
269 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_ISRC
);
271 if (work_done
< budget
) {
273 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER
);
281 static int ptm_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
285 volatile struct tx_descriptor
*desc
;
286 struct tx_descriptor reg_desc
= {0};
287 struct sk_buff
*skb_to_free
;
288 unsigned int byteoff
;
290 ASSERT(dev
== g_net_dev
[0], "incorrect device");
293 err("not in showtime");
294 goto PTM_HARD_START_XMIT_FAIL
;
297 /* allocate descriptor */
298 desc_base
= get_tx_desc(0, &f_full
);
300 netif_trans_update(dev
);
301 netif_stop_queue(dev
);
303 IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_ISRC
);
304 IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_IER
);
307 goto PTM_HARD_START_XMIT_FAIL
;
308 desc
= &CPU_TO_WAN_TX_DESC_BASE
[desc_base
];
310 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
311 if ( skb_headroom(skb
) < sizeof(struct sk_buff
*) + byteoff
|| skb_cloned(skb
) ) {
312 struct sk_buff
*new_skb
;
314 ASSERT(skb_headroom(skb
) >= sizeof(struct sk_buff
*) + byteoff
, "skb_headroom(skb) < sizeof(struct sk_buff *) + byteoff");
315 ASSERT(!skb_cloned(skb
), "skb is cloned");
317 new_skb
= alloc_skb_tx(skb
->len
);
318 if ( new_skb
== NULL
) {
320 goto ALLOC_SKB_TX_FAIL
;
322 skb_put(new_skb
, skb
->len
);
323 memcpy(new_skb
->data
, skb
->data
, skb
->len
);
324 dev_kfree_skb_any(skb
);
326 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
327 /* write back to physical memory */
328 dma_cache_wback((unsigned long)skb
->data
, skb
->len
);
331 /* make the skb unowned */
334 *(struct sk_buff
**)((unsigned int)skb
->data
- byteoff
- sizeof(struct sk_buff
*)) = skb
;
335 /* write back to physical memory */
336 dma_cache_wback((unsigned long)skb
->data
- byteoff
- sizeof(struct sk_buff
*), skb
->len
+ byteoff
+ sizeof(struct sk_buff
*));
338 /* free previous skb */
339 skb_to_free
= get_skb_pointer(desc
->dataptr
);
340 if ( skb_to_free
!= NULL
)
341 dev_kfree_skb_any(skb_to_free
);
343 /* update descriptor */
345 reg_desc
.dataptr
= (unsigned int)skb
->data
& (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT
- 1));
346 reg_desc
.datalen
= skb
->len
< ETH_ZLEN
? ETH_ZLEN
: skb
->len
;
347 reg_desc
.qid
= g_ptm_prio_queue_map
[skb
->priority
> 7 ? 7 : skb
->priority
];
348 reg_desc
.byteoff
= byteoff
;
351 reg_desc
.sop
= reg_desc
.eop
= 1;
354 g_ptm_priv_data
.itf
[0].stats
.tx_packets
++;
355 g_ptm_priv_data
.itf
[0].stats
.tx_bytes
+= reg_desc
.datalen
;
357 /* write discriptor to memory */
358 *((volatile unsigned int *)desc
+ 1) = *((unsigned int *)®_desc
+ 1);
360 *(volatile unsigned int *)desc
= *(unsigned int *)®_desc
;
362 netif_trans_update(dev
);
367 PTM_HARD_START_XMIT_FAIL
:
368 dev_kfree_skb_any(skb
);
369 g_ptm_priv_data
.itf
[0].stats
.tx_dropped
++;
373 static int ptm_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
375 ASSERT(dev
== g_net_dev
[0], "incorrect device");
379 case IFX_PTM_MIB_CW_GET
:
380 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxNoIdleCodewords
= IFX_REG_R32(DREG_AR_CELL0
) + IFX_REG_R32(DREG_AR_CELL1
);
381 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxIdleCodewords
= IFX_REG_R32(DREG_AR_IDLE_CNT0
) + IFX_REG_R32(DREG_AR_IDLE_CNT1
);
382 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxCodingViolation
= IFX_REG_R32(DREG_AR_CVN_CNT0
) + IFX_REG_R32(DREG_AR_CVN_CNT1
) + IFX_REG_R32(DREG_AR_CVNP_CNT0
) + IFX_REG_R32(DREG_AR_CVNP_CNT1
);
383 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifTxNoIdleCodewords
= IFX_REG_R32(DREG_AT_CELL0
) + IFX_REG_R32(DREG_AT_CELL1
);
384 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifTxIdleCodewords
= IFX_REG_R32(DREG_AT_IDLE_CNT0
) + IFX_REG_R32(DREG_AT_IDLE_CNT1
);
386 case IFX_PTM_MIB_FRAME_GET
:
388 PTM_FRAME_MIB_T data
= {0};
391 data
.RxCorrect
= IFX_REG_R32(DREG_AR_HEC_CNT0
) + IFX_REG_R32(DREG_AR_HEC_CNT1
) + IFX_REG_R32(DREG_AR_AIIDLE_CNT0
) + IFX_REG_R32(DREG_AR_AIIDLE_CNT1
);
392 for ( i
= 0; i
< 4; i
++ )
393 data
.RxDropped
+= WAN_RX_MIB_TABLE(i
)->wrx_dropdes_pdu
;
394 for ( i
= 0; i
< 8; i
++ )
395 data
.TxSend
+= WAN_TX_MIB_TABLE(i
)->wtx_total_pdu
;
397 *((PTM_FRAME_MIB_T
*)ifr
->ifr_data
) = data
;
400 case IFX_PTM_CFG_GET
:
401 // use bear channel 0 preemption gamma interface settings
402 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcPresent
= 1;
403 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcCheck
= RX_GAMMA_ITF_CFG(0)->rx_eth_fcs_ver_dis
== 0 ? 1 : 0;
404 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcCheck
= RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis
== 0 ? 1 : 0;;
405 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
= RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
== 0 ? 0 : (RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
* 16);
406 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxEthCrcGen
= TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis
== 0 ? 1 : 0;
407 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcGen
= TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
== 0 ? 0 : 1;
408 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
= TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
== 0 ? 0 : (TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
* 16);
410 case IFX_PTM_CFG_SET
:
414 for ( i
= 0; i
< 4; i
++ ) {
415 RX_GAMMA_ITF_CFG(i
)->rx_eth_fcs_ver_dis
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcCheck
? 0 : 1;
417 RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcCheck
? 0 : 1;
419 switch ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
) {
420 case 16: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
= 1; break;
421 case 32: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
= 2; break;
422 default: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size
= 0;
425 TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxEthCrcGen
? 0 : 1;
427 if ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcGen
) {
428 switch ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
) {
429 case 16: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
= 1; break;
430 case 32: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
= 2; break;
431 default: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
= 0;
435 TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size
= 0;
439 case IFX_PTM_MAP_PKT_PRIO_TO_Q
:
441 struct ppe_prio_q_map cmd
;
443 if ( copy_from_user(&cmd
, ifr
->ifr_data
, sizeof(cmd
)) )
446 if ( cmd
.pkt_prio
< 0 || cmd
.pkt_prio
>= ARRAY_SIZE(g_ptm_prio_queue_map
) )
449 if ( cmd
.qid
< 0 || cmd
.qid
>= g_wanqos_en
)
452 g_ptm_prio_queue_map
[cmd
.pkt_prio
] = cmd
.qid
;
462 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)
463 static void ptm_tx_timeout(struct net_device
*dev
)
465 static void ptm_tx_timeout(struct net_device
*dev
, unsigned int txqueue
)
468 ASSERT(dev
== g_net_dev
[0], "incorrect device");
470 /* disable TX irq, release skb when sending new packet */
471 IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER
);
473 /* wake up TX queue */
474 netif_wake_queue(dev
);
479 static inline struct sk_buff
* alloc_skb_rx(void)
483 /* allocate memroy including trailer and padding */
484 skb
= dev_alloc_skb(RX_MAX_BUFFER_SIZE
+ DATA_BUFFER_ALIGNMENT
);
486 /* must be burst length alignment and reserve two more bytes for MAC address alignment */
487 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 )
488 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
489 /* pub skb in reserved area "skb->data - 4" */
490 *((struct sk_buff
**)skb
->data
- 1) = skb
;
492 /* write back and invalidate cache */
493 dma_cache_wback_inv((unsigned long)skb
->data
- sizeof(skb
), sizeof(skb
));
494 /* invalidate cache */
495 dma_cache_inv((unsigned long)skb
->data
, (unsigned int)skb
->end
- (unsigned int)skb
->data
);
501 static inline struct sk_buff
* alloc_skb_tx(unsigned int size
)
505 /* allocate memory including padding */
506 size
= RX_MAX_BUFFER_SIZE
;
507 size
= (size
+ DATA_BUFFER_ALIGNMENT
- 1) & ~(DATA_BUFFER_ALIGNMENT
- 1);
508 skb
= dev_alloc_skb(size
+ DATA_BUFFER_ALIGNMENT
);
509 /* must be burst length alignment */
511 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
515 static inline struct sk_buff
*get_skb_pointer(unsigned int dataptr
)
517 unsigned int skb_dataptr
;
520 // usually, CPE memory is less than 256M bytes
521 // so NULL means invalid pointer
522 if ( dataptr
== 0 ) {
523 dbg("dataptr is 0, it's supposed to be invalid pointer");
527 skb_dataptr
= (dataptr
- 4) | KSEG1
;
528 skb
= *(struct sk_buff
**)skb_dataptr
;
530 ASSERT((unsigned int)skb
>= KSEG0
, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb
, dataptr
);
531 ASSERT((((unsigned int)skb
->data
& (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT
- 1))) | KSEG1
) == (dataptr
| KSEG1
), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb
, (unsigned int)skb
->data
, dataptr
);
536 static inline int get_tx_desc(unsigned int itf
, unsigned int *f_full
)
539 struct ptm_itf
*p_itf
= &g_ptm_priv_data
.itf
[0];
541 // assume TX is serial operation
542 // no protection provided
546 if ( CPU_TO_WAN_TX_DESC_BASE
[p_itf
->tx_desc_pos
].own
== 0 ) {
547 desc_base
= p_itf
->tx_desc_pos
;
548 if ( ++(p_itf
->tx_desc_pos
) == CPU_TO_WAN_TX_DESC_NUM
)
549 p_itf
->tx_desc_pos
= 0;
550 if ( CPU_TO_WAN_TX_DESC_BASE
[p_itf
->tx_desc_pos
].own
== 0 )
557 static irqreturn_t
mailbox_irq_handler(int irq
, void *dev_id
)
561 isr
= IFX_REG_R32(MBOX_IGU1_ISR
);
562 IFX_REG_W32(isr
, MBOX_IGU1_ISRC
);
563 isr
&= IFX_REG_R32(MBOX_IGU1_IER
);
566 IFX_REG_W32_MASK(1, 0, MBOX_IGU1_IER
);
567 napi_schedule(&g_ptm_priv_data
.itf
[0].napi
);
568 #if defined(ENABLE_TMP_DBG) && ENABLE_TMP_DBG
570 volatile struct rx_descriptor
*desc
= &WAN_RX_DESC_BASE
[g_ptm_priv_data
.itf
[0].rx_desc_pos
];
572 if ( desc
->own
) { // PP32 hold
573 err("invalid interrupt");
579 IFX_REG_W32_MASK(1 << 16, 0, MBOX_IGU1_IER
);
580 tasklet_hi_schedule(&g_swap_desc_tasklet
);
583 IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER
);
584 netif_wake_queue(g_net_dev
[0]);
590 static void do_swap_desc_tasklet(unsigned long arg
)
593 volatile struct tx_descriptor
*desc
;
595 unsigned int byteoff
;
597 while ( budget
-- > 0 ) {
598 if ( WAN_SWAP_DESC_BASE
[g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
].own
) // if PP32 hold descriptor
601 desc
= &WAN_SWAP_DESC_BASE
[g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
];
602 if ( ++g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
== WAN_SWAP_DESC_NUM
)
603 g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
= 0;
605 skb
= get_skb_pointer(desc
->dataptr
);
607 dev_kfree_skb_any(skb
);
609 skb
= alloc_skb_tx(RX_MAX_BUFFER_SIZE
);
611 panic("can't allocate swap buffer for PPE firmware use\n");
612 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
613 *(struct sk_buff
**)((unsigned int)skb
->data
- byteoff
- sizeof(struct sk_buff
*)) = skb
;
615 desc
->dataptr
= (unsigned int)skb
->data
& 0x0FFFFFFF;
620 IFX_REG_W32_MASK(0, 16, MBOX_IGU1_ISRC
);
621 // no more skb to be replaced
622 if ( WAN_SWAP_DESC_BASE
[g_ptm_priv_data
.itf
[0].tx_swap_desc_pos
].own
) { // if PP32 hold descriptor
623 IFX_REG_W32_MASK(0, 1 << 16, MBOX_IGU1_IER
);
627 tasklet_hi_schedule(&g_swap_desc_tasklet
);
632 static inline int ifx_ptm_version(char *buf
)
635 unsigned int major
, mid
, minor
;
637 ifx_ptm_get_fw_ver(&major
, &mid
, &minor
);
639 len
+= ifx_drv_ver(buf
+ len
, "PTM", IFX_PTM_VER_MAJOR
, IFX_PTM_VER_MID
, IFX_PTM_VER_MINOR
);
641 len
+= sprintf(buf
+ len
, " PTM (E1) firmware version %u.%u\n", major
, minor
);
643 len
+= sprintf(buf
+ len
, " PTM (E1) firmware version %u.%u.%u\n", major
, mid
, minor
);
648 static inline int init_priv_data(void)
652 g_wanqos_en
= wanqos_en
? wanqos_en
: 8;
653 if ( g_wanqos_en
> 8 )
656 for ( i
= 0; i
< ARRAY_SIZE(g_queue_gamma_map
); i
++ )
658 g_queue_gamma_map
[i
] = queue_gamma_map
[i
] & ((1 << g_wanqos_en
) - 1);
659 for ( j
= 0; j
< i
; j
++ )
660 g_queue_gamma_map
[i
] &= ~g_queue_gamma_map
[j
];
663 memset(&g_ptm_priv_data
, 0, sizeof(g_ptm_priv_data
));
666 int max_packet_priority
= ARRAY_SIZE(g_ptm_prio_queue_map
);
668 int q_step
, q_accum
, p_step
;
670 tx_num_q
= __ETH_WAN_TX_QUEUE_NUM
;
671 q_step
= tx_num_q
- 1;
672 p_step
= max_packet_priority
- 1;
673 for ( j
= 0, q_accum
= 0; j
< max_packet_priority
; j
++, q_accum
+= q_step
)
674 g_ptm_prio_queue_map
[j
] = q_step
- (q_accum
+ (p_step
>> 1)) / p_step
;
680 static inline void clear_priv_data(void)
684 static inline int init_tables(void)
686 struct sk_buff
*skb_pool
[WAN_RX_DESC_NUM
] = {0};
687 struct cfg_std_data_len cfg_std_data_len
= {0};
688 struct tx_qos_cfg tx_qos_cfg
= {0};
689 struct psave_cfg psave_cfg
= {0};
690 struct eg_bwctrl_cfg eg_bwctrl_cfg
= {0};
691 struct test_mode test_mode
= {0};
692 struct rx_bc_cfg rx_bc_cfg
= {0};
693 struct tx_bc_cfg tx_bc_cfg
= {0};
694 struct gpio_mode gpio_mode
= {0};
695 struct gpio_wm_cfg gpio_wm_cfg
= {0};
696 struct rx_gamma_itf_cfg rx_gamma_itf_cfg
= {0};
697 struct tx_gamma_itf_cfg tx_gamma_itf_cfg
= {0};
698 struct wtx_qos_q_desc_cfg wtx_qos_q_desc_cfg
= {0};
699 struct rx_descriptor rx_desc
= {0};
700 struct tx_descriptor tx_desc
= {0};
703 for ( i
= 0; i
< WAN_RX_DESC_NUM
; i
++ ) {
704 skb_pool
[i
] = alloc_skb_rx();
705 if ( skb_pool
[i
] == NULL
)
706 goto ALLOC_SKB_RX_FAIL
;
709 cfg_std_data_len
.byte_off
= RX_HEAD_MAC_ADDR_ALIGNMENT
; // this field replaces byte_off in rx descriptor of VDSL ingress
710 cfg_std_data_len
.data_len
= 1600;
711 *CFG_STD_DATA_LEN
= cfg_std_data_len
;
713 tx_qos_cfg
.time_tick
= cgu_get_pp32_clock() / 62500; // 16 * (cgu_get_pp32_clock() / 1000000)
714 tx_qos_cfg
.overhd_bytes
= 0;
715 tx_qos_cfg
.eth1_eg_qnum
= __ETH_WAN_TX_QUEUE_NUM
;
716 tx_qos_cfg
.eth1_burst_chk
= 1;
717 tx_qos_cfg
.eth1_qss
= 0;
718 tx_qos_cfg
.shape_en
= 0; // disable
719 tx_qos_cfg
.wfq_en
= 0; // strict priority
720 *TX_QOS_CFG
= tx_qos_cfg
;
722 psave_cfg
.start_state
= 0;
723 psave_cfg
.sleep_en
= 1; // enable sleep mode
724 *PSAVE_CFG
= psave_cfg
;
726 eg_bwctrl_cfg
.fdesc_wm
= 16;
727 eg_bwctrl_cfg
.class_len
= 128;
728 *EG_BWCTRL_CFG
= eg_bwctrl_cfg
;
730 //*GPIO_ADDR = (unsigned int)IFX_GPIO_P0_OUT;
731 *GPIO_ADDR
= (unsigned int)0x00000000; // disabled by default
733 gpio_mode
.gpio_bit_bc1
= 2;
734 gpio_mode
.gpio_bit_bc0
= 1;
735 gpio_mode
.gpio_bc1_en
= 0;
736 gpio_mode
.gpio_bc0_en
= 0;
737 *GPIO_MODE
= gpio_mode
;
739 gpio_wm_cfg
.stop_wm_bc1
= 2;
740 gpio_wm_cfg
.start_wm_bc1
= 4;
741 gpio_wm_cfg
.stop_wm_bc0
= 2;
742 gpio_wm_cfg
.start_wm_bc0
= 4;
743 *GPIO_WM_CFG
= gpio_wm_cfg
;
745 test_mode
.mib_clear_mode
= 0;
746 test_mode
.test_mode
= 0;
747 *TEST_MODE
= test_mode
;
749 rx_bc_cfg
.local_state
= 0;
750 rx_bc_cfg
.remote_state
= 0;
751 rx_bc_cfg
.to_false_th
= 7;
752 rx_bc_cfg
.to_looking_th
= 3;
753 *RX_BC_CFG(0) = rx_bc_cfg
;
754 *RX_BC_CFG(1) = rx_bc_cfg
;
756 tx_bc_cfg
.fill_wm
= 2;
757 tx_bc_cfg
.uflw_wm
= 2;
758 *TX_BC_CFG(0) = tx_bc_cfg
;
759 *TX_BC_CFG(1) = tx_bc_cfg
;
761 rx_gamma_itf_cfg
.receive_state
= 0;
762 rx_gamma_itf_cfg
.rx_min_len
= 60;
763 rx_gamma_itf_cfg
.rx_pad_en
= 1;
764 rx_gamma_itf_cfg
.rx_eth_fcs_ver_dis
= 0;
765 rx_gamma_itf_cfg
.rx_rm_eth_fcs
= 1;
766 rx_gamma_itf_cfg
.rx_tc_crc_ver_dis
= 0;
767 rx_gamma_itf_cfg
.rx_tc_crc_size
= 1;
768 rx_gamma_itf_cfg
.rx_eth_fcs_result
= 0xC704DD7B;
769 rx_gamma_itf_cfg
.rx_tc_crc_result
= 0x1D0F1D0F;
770 rx_gamma_itf_cfg
.rx_crc_cfg
= 0x2500;
771 rx_gamma_itf_cfg
.rx_eth_fcs_init_value
= 0xFFFFFFFF;
772 rx_gamma_itf_cfg
.rx_tc_crc_init_value
= 0x0000FFFF;
773 rx_gamma_itf_cfg
.rx_max_len_sel
= 0;
774 rx_gamma_itf_cfg
.rx_edit_num2
= 0;
775 rx_gamma_itf_cfg
.rx_edit_pos2
= 0;
776 rx_gamma_itf_cfg
.rx_edit_type2
= 0;
777 rx_gamma_itf_cfg
.rx_edit_en2
= 0;
778 rx_gamma_itf_cfg
.rx_edit_num1
= 0;
779 rx_gamma_itf_cfg
.rx_edit_pos1
= 0;
780 rx_gamma_itf_cfg
.rx_edit_type1
= 0;
781 rx_gamma_itf_cfg
.rx_edit_en1
= 0;
782 rx_gamma_itf_cfg
.rx_inserted_bytes_1l
= 0;
783 rx_gamma_itf_cfg
.rx_inserted_bytes_1h
= 0;
784 rx_gamma_itf_cfg
.rx_inserted_bytes_2l
= 0;
785 rx_gamma_itf_cfg
.rx_inserted_bytes_2h
= 0;
786 rx_gamma_itf_cfg
.rx_len_adj
= -6;
787 for ( i
= 0; i
< 4; i
++ )
788 *RX_GAMMA_ITF_CFG(i
) = rx_gamma_itf_cfg
;
790 tx_gamma_itf_cfg
.tx_len_adj
= 6;
791 tx_gamma_itf_cfg
.tx_crc_off_adj
= 6;
792 tx_gamma_itf_cfg
.tx_min_len
= 0;
793 tx_gamma_itf_cfg
.tx_eth_fcs_gen_dis
= 0;
794 tx_gamma_itf_cfg
.tx_tc_crc_size
= 1;
795 tx_gamma_itf_cfg
.tx_crc_cfg
= 0x2F00;
796 tx_gamma_itf_cfg
.tx_eth_fcs_init_value
= 0xFFFFFFFF;
797 tx_gamma_itf_cfg
.tx_tc_crc_init_value
= 0x0000FFFF;
798 for ( i
= 0; i
< ARRAY_SIZE(g_queue_gamma_map
); i
++ ) {
799 tx_gamma_itf_cfg
.queue_mapping
= g_queue_gamma_map
[i
];
800 *TX_GAMMA_ITF_CFG(i
) = tx_gamma_itf_cfg
;
803 for ( i
= 0; i
< __ETH_WAN_TX_QUEUE_NUM
; i
++ ) {
804 wtx_qos_q_desc_cfg
.length
= WAN_TX_DESC_NUM
;
805 wtx_qos_q_desc_cfg
.addr
= __ETH_WAN_TX_DESC_BASE(i
);
806 *WTX_QOS_Q_DESC_CFG(i
) = wtx_qos_q_desc_cfg
;
809 // default TX queue QoS config is all ZERO
812 IFX_REG_W32(0x90111293, TX_CTRL_K_TABLE(0));
813 IFX_REG_W32(0x14959617, TX_CTRL_K_TABLE(1));
814 IFX_REG_W32(0x18999A1B, TX_CTRL_K_TABLE(2));
815 IFX_REG_W32(0x9C1D1E9F, TX_CTRL_K_TABLE(3));
816 IFX_REG_W32(0xA02122A3, TX_CTRL_K_TABLE(4));
817 IFX_REG_W32(0x24A5A627, TX_CTRL_K_TABLE(5));
818 IFX_REG_W32(0x28A9AA2B, TX_CTRL_K_TABLE(6));
819 IFX_REG_W32(0xAC2D2EAF, TX_CTRL_K_TABLE(7));
820 IFX_REG_W32(0x30B1B233, TX_CTRL_K_TABLE(8));
821 IFX_REG_W32(0xB43536B7, TX_CTRL_K_TABLE(9));
822 IFX_REG_W32(0xB8393ABB, TX_CTRL_K_TABLE(10));
823 IFX_REG_W32(0x3CBDBE3F, TX_CTRL_K_TABLE(11));
824 IFX_REG_W32(0xC04142C3, TX_CTRL_K_TABLE(12));
825 IFX_REG_W32(0x44C5C647, TX_CTRL_K_TABLE(13));
826 IFX_REG_W32(0x48C9CA4B, TX_CTRL_K_TABLE(14));
827 IFX_REG_W32(0xCC4D4ECF, TX_CTRL_K_TABLE(15));
829 // init RX descriptor
834 rx_desc
.byteoff
= RX_HEAD_MAC_ADDR_ALIGNMENT
;
835 rx_desc
.datalen
= RX_MAX_BUFFER_SIZE
- RX_HEAD_MAC_ADDR_ALIGNMENT
;
836 for ( i
= 0; i
< WAN_RX_DESC_NUM
; i
++ ) {
837 rx_desc
.dataptr
= (unsigned int)skb_pool
[i
]->data
& 0x0FFFFFFF;
838 WAN_RX_DESC_BASE
[i
] = rx_desc
;
841 // init TX descriptor
851 for ( i
= 0; i
< CPU_TO_WAN_TX_DESC_NUM
; i
++ )
852 CPU_TO_WAN_TX_DESC_BASE
[i
] = tx_desc
;
853 for ( i
= 0; i
< WAN_TX_DESC_NUM_TOTAL
; i
++ )
854 WAN_TX_DESC_BASE(0)[i
] = tx_desc
;
856 // init Swap descriptor
857 for ( i
= 0; i
< WAN_SWAP_DESC_NUM
; i
++ )
858 WAN_SWAP_DESC_BASE
[i
] = tx_desc
;
860 // init fastpath TX descriptor
862 for ( i
= 0; i
< FASTPATH_TO_WAN_TX_DESC_NUM
; i
++ )
863 FASTPATH_TO_WAN_TX_DESC_BASE
[i
] = tx_desc
;
869 dev_kfree_skb_any(skb_pool
[i
]);
873 static inline void clear_tables(void)
878 for ( i
= 0; i
< WAN_RX_DESC_NUM
; i
++ ) {
879 skb
= get_skb_pointer(WAN_RX_DESC_BASE
[i
].dataptr
);
881 dev_kfree_skb_any(skb
);
884 for ( i
= 0; i
< CPU_TO_WAN_TX_DESC_NUM
; i
++ ) {
885 skb
= get_skb_pointer(CPU_TO_WAN_TX_DESC_BASE
[i
].dataptr
);
887 dev_kfree_skb_any(skb
);
890 for ( j
= 0; j
< 8; j
++ )
891 for ( i
= 0; i
< WAN_TX_DESC_NUM
; i
++ ) {
892 skb
= get_skb_pointer(WAN_TX_DESC_BASE(j
)[i
].dataptr
);
894 dev_kfree_skb_any(skb
);
897 for ( i
= 0; i
< WAN_SWAP_DESC_NUM
; i
++ ) {
898 skb
= get_skb_pointer(WAN_SWAP_DESC_BASE
[i
].dataptr
);
900 dev_kfree_skb_any(skb
);
903 for ( i
= 0; i
< FASTPATH_TO_WAN_TX_DESC_NUM
; i
++ ) {
904 skb
= get_skb_pointer(FASTPATH_TO_WAN_TX_DESC_BASE
[i
].dataptr
);
906 dev_kfree_skb_any(skb
);
910 static int ptm_showtime_enter(struct port_cell_info
*port_cell
, void *xdata_addr
)
914 ASSERT(port_cell
!= NULL
, "port_cell is NULL");
915 ASSERT(xdata_addr
!= NULL
, "xdata_addr is NULL");
917 // TODO: ReTX set xdata_addr
918 g_xdata_addr
= xdata_addr
;
922 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
923 netif_carrier_on(g_net_dev
[i
]);
925 IFX_REG_W32(0x0F, UTP_CFG
);
928 // IFX_REG_W32_MASK(1 << 17, 0, FFSM_CFG0);
931 printk("enter showtime\n");
936 static int ptm_showtime_exit(void)
944 // IFX_REG_W32_MASK(0, 1 << 17, FFSM_CFG0);
947 IFX_REG_W32(0x00, UTP_CFG
);
949 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
950 netif_carrier_off(g_net_dev
[i
]);
954 // TODO: ReTX clean state
957 printk("leave showtime\n");
962 static const struct of_device_id ltq_ptm_match
[] = {
964 { .compatible
= "lantiq,ppe-danube", .data
= NULL
},
965 #elif defined CONFIG_AMAZON_SE
966 { .compatible
= "lantiq,ppe-ase", .data
= NULL
},
967 #elif defined CONFIG_AR9
968 { .compatible
= "lantiq,ppe-arx100", .data
= NULL
},
969 #elif defined CONFIG_VR9
970 { .compatible
= "lantiq,ppe-xrx200", .data
= NULL
},
974 MODULE_DEVICE_TABLE(of
, ltq_ptm_match
);
976 static int ltq_ptm_probe(struct platform_device
*pdev
)
981 struct port_cell_info port_cell
= {0};
983 ret
= init_priv_data();
985 err("INIT_PRIV_DATA_FAIL");
986 goto INIT_PRIV_DATA_FAIL
;
989 ifx_ptm_init_chip(pdev
);
992 err("INIT_TABLES_FAIL");
993 goto INIT_TABLES_FAIL
;
996 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
997 g_net_dev
[i
] = alloc_netdev(0, g_net_dev_name
[i
], NET_NAME_UNKNOWN
, ether_setup
);
998 if ( g_net_dev
[i
] == NULL
)
999 goto ALLOC_NETDEV_FAIL
;
1000 ptm_setup(g_net_dev
[i
], i
);
1003 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1004 ret
= register_netdev(g_net_dev
[i
]);
1006 goto REGISTER_NETDEV_FAIL
;
1009 /* register interrupt handler */
1010 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, 0, "ptm_mailbox_isr", &g_ptm_priv_data
);
1012 if ( ret
== -EBUSY
) {
1013 err("IRQ may be occupied by other driver, please reconfig to disable it.");
1016 err("request_irq fail");
1018 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
1020 disable_irq(PPE_MAILBOX_IGU1_INT
);
1022 ret
= ifx_pp32_start(0);
1024 err("ifx_pp32_start fail!");
1025 goto PP32_START_FAIL
;
1027 IFX_REG_W32(1 << 16, MBOX_IGU1_IER
); // enable SWAP interrupt
1028 IFX_REG_W32(~0, MBOX_IGU1_ISRC
);
1030 enable_irq(PPE_MAILBOX_IGU1_INT
);
1032 ifx_mei_atm_showtime_check(&g_showtime
, &port_cell
, &g_xdata_addr
);
1034 ptm_showtime_enter(&port_cell
, &g_xdata_addr
);
1037 ifx_mei_atm_showtime_enter
= ptm_showtime_enter
;
1038 ifx_mei_atm_showtime_exit
= ptm_showtime_exit
;
1040 ifx_ptm_version(ver_str
);
1041 printk(KERN_INFO
"%s", ver_str
);
1043 printk("ifxmips_ptm: PTM init succeed\n");
1048 free_irq(PPE_MAILBOX_IGU1_INT
, &g_ptm_priv_data
);
1049 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
:
1050 i
= ARRAY_SIZE(g_net_dev
);
1051 REGISTER_NETDEV_FAIL
:
1053 unregister_netdev(g_net_dev
[i
]);
1054 i
= ARRAY_SIZE(g_net_dev
);
1057 free_netdev(g_net_dev
[i
]);
1058 g_net_dev
[i
] = NULL
;
1061 INIT_PRIV_DATA_FAIL
:
1063 printk("ifxmips_ptm: PTM init failed\n");
1067 static int ltq_ptm_remove(struct platform_device
*pdev
)
1070 ifx_mei_atm_showtime_enter
= NULL
;
1071 ifx_mei_atm_showtime_exit
= NULL
;
1076 free_irq(PPE_MAILBOX_IGU1_INT
, &g_ptm_priv_data
);
1078 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
1079 unregister_netdev(g_net_dev
[i
]);
1081 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1082 free_netdev(g_net_dev
[i
]);
1083 g_net_dev
[i
] = NULL
;
1088 ifx_ptm_uninit_chip();
1096 static int __init
wanqos_en_setup(char *line
)
1098 wanqos_en
= simple_strtoul(line
, NULL
, 0);
1100 if ( wanqos_en
< 1 || wanqos_en
> 8 )
1106 static int __init
queue_gamma_map_setup(char *line
)
1111 for ( i
= 0, p
= line
; i
< ARRAY_SIZE(queue_gamma_map
) && isxdigit(*p
); i
++ )
1113 queue_gamma_map
[i
] = simple_strtoul(p
, &p
, 0);
1114 if ( *p
== ',' || *p
== ';' || *p
== ':' )
1121 static struct platform_driver ltq_ptm_driver
= {
1122 .probe
= ltq_ptm_probe
,
1123 .remove
= ltq_ptm_remove
,
1126 .owner
= THIS_MODULE
,
1127 .of_match_table
= ltq_ptm_match
,
1131 module_platform_driver(ltq_ptm_driver
);
1133 __setup("wanqos_en=", wanqos_en_setup
);
1134 __setup("queue_gamma_map=", queue_gamma_map_setup
);
1137 MODULE_LICENSE("GPL");