1 /*******************************************************************************
3 Intel SmartPHY DSL PCIe Endpoint/ACA Linux driver
4 Copyright(c) 2016 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 *******************************************************************************/
27 #define HOST_IF_BASE 0x50000
28 #define ACA_CORE_BASE 0x50800
29 #define GENRISC_IRAM_BASE 0x58000
30 #define GENRISC_SPRAM_BASE 0x5C000
31 #define GENRISC_BASE 0x5D000
32 #define MAC_HT_EXT_BASE 0x5D400
33 #define ACA_SRAM_BASE 0x100000
34 #define ACA_SRAM_SIZE 0x2000 /* Project specific */
35 #define ACA_HOSTIF_ADDR_SHIFT 2
37 #define ACA_HOSTIF_ADDR(addr) ((addr) >> ACA_HOSTIF_ADDR_SHIFT)
39 #define ACA_HIF_LOC_POS 0x100060
40 #define ACA_HIF_PARAM_ADDR 0x100064
41 #define ACA_ACC_FW_SIZE 0x400
42 #define ACA_LOOP_CNT 1000
44 /* TODO: change name after karthik explained */
45 #define TXIN_DST_OWNBIT 0xC4
46 #define TXOUT_DST_OWNBIT 0x1C4
47 #define RXOUT_SRC_OWNBIT 0x3C4
48 #define RXIN_DST_OWNBIT 0x2C4
50 /* Genrisc Internal Host Descriptor(Ping/Pong) decided by ACA fw header */
52 #define ACA_CORE_REG(X) (ACA_CORE_BASE + (X))
53 #define TXIN_CFG1 ACA_CORE_REG(0x0)
54 #define TXIN_CFG2 ACA_CORE_REG(0x4)
55 #define TXIN_CFG3 ACA_CORE_REG(0x8)
56 #define TXIN_DST_OWWBIT_CFG4 ACA_CORE_REG(TXIN_DST_OWNBIT)
58 #define TXOUT_CFG1 ACA_CORE_REG(0x100)
59 #define TXOUT_CFG2 ACA_CORE_REG(0x104)
60 #define TXOUT_CFG3 ACA_CORE_REG(0x108)
61 #define TXOUT_DST_OWWBIT_CFG4 ACA_CORE_REG(TXOUT_DST_OWNBIT)
63 #define RXOUT_CFG1 ACA_CORE_REG(0x300)
64 #define RXOUT_CFG2 ACA_CORE_REG(0x304)
65 #define RXOUT_CFG3 ACA_CORE_REG(0x308)
66 #define RXOUT_SRC_OWNBIT_CFG3 ACA_CORE_REG(RXOUT_SRC_OWNBIT)
68 #define RXIN_CFG1 ACA_CORE_REG(0x200)
69 #define RXIN_CFG2 ACA_CORE_REG(0x204)
70 #define RXIN_CFG3 ACA_CORE_REG(0x208)
71 #define RXIN_SRC_OWNBIT_CFG3 ACA_CORE_REG(RXIN_DST_OWNBIT)
74 #define GNRC_REG(X) (GENRISC_BASE + (X))
75 #define GNRC_STOP_OP GNRC_REG(0x60)
76 #define GNRC_CONTINUE_OP GNRC_REG(0x64)
77 #define GNRC_START_OP GNRC_REG(0x90)
79 /* HOST Interface Register */
80 #define HOST_IF_REG(X) (HOST_IF_BASE + (X))
81 #define HD_DESC_IN_DW 0x7u
82 #define HD_DESC_IN_DW_S 0
83 #define PD_DESC_IN_DW 0x70u
84 #define PD_DESC_IN_DW_S 4
85 #define BYTE_SWAP_EN BIT(28)
87 #define TXIN_CONV_CFG HOST_IF_REG(0x14)
88 #define TXOUT_CONV_CFG HOST_IF_REG(0x18)
89 #define RXIN_CONV_CFG HOST_IF_REG(0x1C)
90 #define RXOUT_CONV_CFG HOST_IF_REG(0x20)
92 #define TXIN_COUNTERS HOST_IF_REG(0x44)
93 #define TXOUT_COUNTERS HOST_IF_REG(0x48)
94 #define RXIN_COUNTERS HOST_IF_REG(0x4c)
95 #define RXOUT_COUNTERS HOST_IF_REG(0x50)
97 #define TXOUT_RING_CFG HOST_IF_REG(0x98)
98 #define RXOUT_RING_CFG HOST_IF_REG(0x9C)
100 #define ACA_PENDING_JOB 0x00000300
101 #define ACA_PENDING_JOB_S 8
102 #define ACA_AVAIL_BUF 0x00030000
103 #define ACA_AVAIL_BUF_S 16
104 #define ACA_PP_BUFS 2
106 #define HOST_TYPE HOST_IF_REG(0xA0)
107 #define TXOUT_COUNTERS_UPDATE HOST_IF_REG(0xAC)
108 #define RXOUT_COUNTERS_UPDATE HOST_IF_REG(0xB4)
109 #define RXIN_HD_ACCUM_ADD HOST_IF_REG(0xC8) /* UMT Message trigger */
110 #define TXIN_HD_ACCUM_ADD HOST_IF_REG(0xCC) /* UMT Message trigger */
111 #define RXOUT_HD_ACCUM_ADD HOST_IF_REG(0xD0)
112 #define TXOUT_HD_ACCUM_ADD HOST_IF_REG(0xD4)
113 #define RXOUT_ACA_ACCUM_ADD HOST_IF_REG(0xE0) /* PPE FW tigger */
114 #define TXOUT_ACA_ACCUM_ADD HOST_IF_REG(0xE4) /* PPE FW tigger */
115 #define RXOUT_HD_ACCUM_SUB HOST_IF_REG(0xF8)
116 #define TXOUT_HD_ACCUM_SUB HOST_IF_REG(0xFC)
117 #define RXIN_ACA_ACCUM_SUB HOST_IF_REG(0x100)
118 #define TXIN_ACA_ACCUM_SUB HOST_IF_REG(0x104)
119 #define TXIN_ACA_HD_ACC_CNT HOST_IF_REG(0x11C)
120 #define UMT_ORDER_CFG HOST_IF_REG(0x234)
121 #define RXIN_HD_ACCUM_ADD_BE HOST_IF_REG(0x250)
122 #define TXIN_HD_ACCUM_ADD_BE HOST_IF_REG(0x254)
123 #define RXOUT_HD_ACCUM_SUB_BE HOST_IF_REG(0x268)
124 #define TXOUT_HD_ACCUM_SUB_BE HOST_IF_REG(0x26c)
126 /* MAC_HT_EXTENSION Register */
127 #define MAC_HT_EXT_REG(X) (MAC_HT_EXT_BASE + (X))
129 #define HT_GCLK_ENABLE MAC_HT_EXT_REG(0)
130 #define HT_SW_RST_RELEASE MAC_HT_EXT_REG(0x4)
131 #define HT_SW_RST_ASSRT MAC_HT_EXT_REG(0x1C)
132 #define SW_RST_GENRISC BIT(14)
133 #define SW_RST_RXOUT BIT(26)
134 #define SW_RST_RXIN BIT(27)
135 #define SW_RST_TXOUT BIT(28)
136 #define SW_RST_TXIN BIT(29)
137 #define SW_RST_HOSTIF_REG BIT(30)
138 #define OCP_ARB_ACC_PAGE_REG MAC_HT_EXT_REG(0x1C4)
139 #define AHB_ARB_HP_REG MAC_HT_EXT_REG(0x1C8)
141 /* Genrisc FW Configuration */
142 #define GNRC_SPRAM_REG(X) (GENRISC_SPRAM_BASE + (X))
145 #define GNRC_TXIN_TGT_STAT GNRC_SPRAM_REG(0x04)
146 #define GNRC_TXIN_TGT_PD_OFF GNRC_SPRAM_REG(0x08)
147 #define GNRC_TXIN_TGT_ACCM_CNT GNRC_SPRAM_REG(0x0C)
150 #define GNRC_TXOUT_TGT_STAT GNRC_SPRAM_REG(0x10)
151 #define GNRC_TXOUT_TGT_PD_OFF GNRC_SPRAM_REG(0x14)
152 #define GNRC_TXOUT_TGT_ACCM_CNT GNRC_SPRAM_REG(0x18)
155 #define GNRC_RXIN_TGT_STAT GNRC_SPRAM_REG(0x1C)
156 #define GNRC_RXIN_TGT_PD_OFF GNRC_SPRAM_REG(0x20)
157 #define GNRC_RXIN_TGT_ACCM_CNT GNRC_SPRAM_REG(0x24)
159 /* RX OUT XXX not consistent */
160 #define GNRC_RXOUT_TGT_STAT GNRC_SPRAM_REG(0x28)
161 #define GNRC_RXOUT_TGT_PD_OFF GNRC_SPRAM_REG(0x2C)
162 #define GNRC_RXOUT_TGT_ACCM_CNT GNRC_SPRAM_REG(0x30)
164 /* 4 Ring 8 UMT case SoC cumulative counter address configuration */
165 #define GNRC_TXIN_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x34)
166 #define GNRC_TXOUT_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x38)
167 #define GNRC_RXOUT_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x3C)
168 #define GNRC_RXIN_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x40)
171 #define GNRC_SOURCE_TXIN_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x54)
172 #define GNRC_SOURCE_TXOUT_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x58)
173 #define GNRC_SOURCE_RXOUT_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x5c)
174 #define GNRC_SOURCE_RXIN_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x60)
176 /* Txin index prefill */
177 #define GNRC_TXIN_BUF_PREFILL GNRC_SPRAM_REG(0x44)
178 /* Task enable bitmap */
179 #define GNRC_EN_TASK_BITMAP GNRC_SPRAM_REG(0x64)
181 #define ACA_SRAM_REG(X) (ACA_SRAM_BASE + (X))
182 #define ACA_TXOUT_PING_BUFFER_START ACA_SRAM_REG(0x1528)
186 #define ACA_SSX0_BASE 0x180000
187 #define ACA_SSX0_IA_BASE(id) (ACA_SSX0_BASE + (((id) - 1) << 10))
188 #define ACA_AGENT_CTRL(id) (ACA_SSX0_IA_BASE(id) + 0x20)
189 #define ACA_AGENT_STATUS(id) (ACA_SSX0_IA_BASE(id) + 0x28)
191 #define XBAR_CTRL_CORE_RESET BIT(0)
192 #define XBAR_CTRL_REJECT BIT(4)
194 #define XBAR_STAT_CORE_RESET BIT(0)
195 #define XBAR_STAT_REQ_ACTIVE BIT(4)
196 #define XBAR_STAT_RESP_WAITING BIT(5)
197 #define XBAR_STAT_BURST BIT(6)
198 #define XBAR_STAT_READEX BIT(7)
205 /* Should be passed from ACA FW header */
206 #define DESC_NUM_PER_CH 1
209 #define ACA_DMA_BASE 0x60000
211 #define ACA_DMA_REG(X) (ACA_DMA_BASE + (X))
212 #define ADMA_CLC ACA_DMA_REG(0x0)
213 #define ADMA_ID ACA_DMA_REG(0x8)
214 #define ADMA_CTRL ACA_DMA_REG(0x10)
215 #define ADMA_CPOLL ACA_DMA_REG(0x14)
217 #define ADMA_ID_REV 0x1Fu
218 #define ADMA_ID_REV_S 0
219 #define ADMA_ID_ID 0xFF00u
220 #define ADMA_ID_ID_S 8
221 #define ADMA_ID_PRTNR 0xF0000u
222 #define ADMA_ID_PRTNR_S 16
223 #define ADMA_ID_CHNR 0x7F00000u
224 #define ADMA_ID_CHNR_S 20
226 #define ADMA_CPOLL_EN BIT(31)
228 #define ADMA_CPOLL_CNT 0xFFF0u
229 #define ADMA_CPOLL_CNT_S 4
230 #define ADMA_DEFAULT_POLL 24
231 #define ADMA_CS ACA_DMA_REG(0x18)
232 #define ADMA_CCTRL ACA_DMA_REG(0x1C)
233 #define ADMA_CDBA ACA_DMA_REG(0x20)
234 #define ADMA_CDLEN ACA_DMA_REG(0x24)
235 #define ADMA_CIS ACA_DMA_REG(0x28)
236 #define ADMA_CIE ACA_DMA_REG(0x2C)
238 #define ADMA_CI_EOP BIT(1)
239 #define ADMA_CI_DUR BIT(2)
240 #define ADMA_CI_DESCPT BIT(3)
241 #define ADMA_CI_CHOFF BIT(4)
242 #define ADMA_CI_RDERR BIT(5)
243 #define ADMA_CI_ALL (ADMA_CI_EOP | ADMA_CI_DUR | ADMA_CI_DESCPT\
244 | ADMA_CI_CHOFF | ADMA_CI_RDERR)
246 #define ADMA_CDPTNRD ACA_DMA_REG(0x34)
247 #define ADMA_PS ACA_DMA_REG(0x40)
248 #define ADMA_PCTRL ACA_DMA_REG(0x44)
251 #define CCTRL_RST 1 /* Channel Reset */
252 #define CCTRL_ONOFF 0 /* Channel On/Off */
255 #define CTRL_PKTARB 31 /* Packet Arbitration */
256 #define CTRL_MDC 15 /* Meta data copy */
257 #define CTRL_DDBR 14 /* Dynamic Burst */
258 #define CTRL_DCNF 13 /* Descriptor Length CFG*/
259 #define CTRL_ENBE 9 /* Byte Enable */
260 #define CTRL_DRB 8 /* Descriptor read back */
261 #define CTRL_DSRAM 1 /* Dedicated Descriptor Access port Enable */
262 #define CTRL_RST 0 /* Global Reset */
265 #define PCTRL_FLUSH 16
266 #define PCTRL_TXENDI 10 /* TX DIR Endianess */
267 #define PCTRL_RXENDI 8 /* RX DIR Endianess */
268 #define PCTRL_TXBL 4 /* TX burst 2/4/8 */
269 #define PCTRL_RXBL 2 /* RX burst 2/4/8 */
270 #define PCTRL_TXBL16 1 /* TX burst of 16 */
271 #define PCTRL_RXBL16 0 /* RX burst of 16 */
274 #define ID_CHNR 20 /* Channel Number */
277 #define POLL_EN 31 /* Polling Enable */
278 #define POLL_CNT 4 /* Polling Counter */
280 #define ACA_DMA_CHAN_MAX 12
285 ACA_SEC_MAC_HT
= 0x3,
286 ACA_SEC_MEM_TXIN
= 0x4,
287 ACA_SEC_MEM_TXIN_PDRING
= 0x5,
288 ACA_SEC_MEM_TXOUT
= 0x6,
289 ACA_SEC_MEM_TXOUT_PDRING
= 0x7,
290 ACA_SEC_MEM_RXOUT
= 0x8,
291 ACA_SEC_MEM_RXOUT_PDRING
= 0x9,
292 ACA_SEC_MEM_RXIN
= 0xa,
293 ACA_SEC_MEM_RXIN_PDRING
= 0xb,
295 ACA_SEC_FW_INIT
= 0xd,
320 ACA_SOC_3RD_PARTY
= 8,
323 #define ACA_SOC_MASK 0xf
325 /* Common information element, len has different variants */
336 struct aca_sram_desc
{
346 /* ACA internal header part */
354 struct aca_fw_param
{
359 struct aca_mem_layout
{
360 u32 txin_host_desc_base
;
362 u32 txout_host_desc_base
;
364 u32 rxin_host_desc_base
;
366 u32 rxout_host_desc_base
;
370 struct aca_pdmem_layout
{
371 u32 txin_pd_desc_base
;
373 u32 txout_pd_desc_base
;
375 u32 rxin_pd_desc_base
;
377 u32 rxout_pd_desc_base
;
381 struct aca_fw_addr_tuple
{
388 struct aca_fw_dl_addr
{
390 struct aca_fw_addr_tuple fw_addr
[ACA_FW_MAX
];
394 const struct firmware
*fw
;
397 struct aca_mem_layout mem_layout
;
398 struct aca_pdmem_layout pdmem_layout
;
399 struct aca_fw_param fw_param
;
400 struct aca_fw_dl_addr fw_dl
;
402 u32 adma_desc_base
[ACA_DMA_CHAN_MAX
];
406 #ifdef CONFIG_CPU_BIG_ENDIAN
420 #endif /* CONFIG_CPU_BIG_ENDIAN */
425 #ifdef CONFIG_CPU_BIG_ENDIAN
435 #endif /* CONFIG_CPU_BIG_ENDIAN */
439 /* Fixed header part */
440 struct aca_fw_f_hdr
{
448 struct aca_hif_param
{
455 u32 pd_desc_threshold
;
458 struct aca_hif_params
{
460 struct aca_hif_param txin
;
461 struct aca_hif_param txout
;
462 struct aca_hif_param rxin
;
463 struct aca_hif_param rxout
;
469 #define ACA_MAGIC 0x25062016
475 struct mutex pin_lock
;
476 struct aca_fw_info fw_info
;
477 struct aca_hif_params
*hif_params
;