package/kernel/lantiq/vrx518_ep/src/ep.h

   1 /*******************************************************************************
   2
   3   Intel SmartPHY DSL PCIe Endpoint/ACA Linux driver
   4   Copyright(c) 2016 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22 *******************************************************************************/
  23
  24 #ifndef EP_H
  25 #define EP_H
  26
  27 #include <net/dc_ep.h>
  28
  29 #include "aca.h"
  30
  31 #define DC_EP_MAX_NUM           (DC_EP_MAX_PEER + 1)
  32 #define DC_EP_BAR_NUM           0
  33
  34 /* Maximum 8, if PCIe switch attached, 4 is used. 8 is also default one */
  35 #ifdef CONFIG_VRX518_PCIE_SWITCH_BONDING
  36 #define DC_PCIE_SWITCH_ATTACH           1
  37 #else
  38 #define DC_PCIE_SWITCH_ATTACH           0
  39 #endif /* CONFIG_VRX518_PCIE_SWITCH_BONDING */
  40
  41 #define DC_EP_DEFAULT_MSI_VECTOR        4
  42
  43 #define DC_EP_MAX_REFCNT        DC_EP_INT_MAX
  44
  45 #define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)
  46 #define SM(_v, _f)  (((_v) << _f##_S) & (_f))
  47
  48 enum dc_ep_msi_mode {
  49         DC_EP_8_MSI_MODE = 0,
  50         DC_EP_4_MSI_MODE,
  51         DC_EP_1_MSI_MODE,
  52 };
  53
  54 /* Structure used to extract attached EP detailed information for
  55  * PPE/DSL_MEI driver/Bonding
  56  */
  57 struct dc_ep_priv {
  58         struct pci_dev *pdev;
  59         struct device *dev;
  60         u32 ep_idx; /*!< EP logical index, the first found one will be 0
  61                         regardless of RC physical index
  62                         */
  63         u32 irq_base; /*!< The first MSI interrupt number */
  64         u32 irq_num; /*!< How many MSI interrupt supported */
  65         enum dc_ep_msi_mode msi_mode;
  66         u8 __iomem *mem;  /*!< The EP inbound memory base address
  67                                 derived from BAR0, SoC virtual address
  68                                 for PPE/DSL_MEI driver
  69                                 */
  70         u32 phymem; /*!< The EP inbound memory base address
  71                                 derived from BAR0, physical address for
  72                                 PPE FW
  73                                 */
  74         size_t memsize; /*!< The EP inbound memory window size */
  75         u32 peer_num;  /*!< Bonding peer number available */
  76         /*!< The bonding peer EP inbound memory base address derived from
  77          * its BAR0, SoC virtual address for PPE/DSL_MEI driver
  78          */
  79
  80         u8 __iomem *peer_mem[DC_EP_MAX_PEER];
  81
  82         /*!< The bonding peer EP inbound memory base address derived from
  83          * its BAR0, physical address for PPE FW
  84          */
  85         u32 peer_phymem[DC_EP_MAX_PEER];
  86
  87         /*!< The bonding peer inbound memory window size */
  88         size_t peer_memsize[DC_EP_MAX_PEER];
  89         atomic_t refcnt; /*!< The EP mapping driver referenced times
  90                                 by other modules
  91                                 */
  92         u16 device_id; /* Potential usage for different EP */
  93         bool switch_attached;
  94         struct dc_aca aca;
  95 };
  96
  97 struct dc_ep_info {
  98         int dev_num;
  99         int msi_mode;
 100         struct dc_ep_priv pcie_ep[DC_EP_MAX_NUM];
 101 };
 102
 103 static inline struct dc_aca *to_aca(struct dc_ep_priv *priv)
 104 {
 105         return &priv->aca;
 106 }
 107
 108 void dc_aca_shutdown(struct dc_ep_priv *priv);
 109 void dc_aca_info_init(struct dc_ep_priv *priv);
 110 int dc_aca_start(struct dc_ep_priv *priv, u32 func, int start);
 111 int dc_aca_stop(struct dc_ep_priv *priv, u32 *func, int reset);
 112 int dc_aca_init(struct dc_ep_priv *priv, struct aca_param *aca,
 113         struct aca_modem_param *mdm);
 114 void dc_aca_event_addr_get(struct dc_ep_priv *priv,
 115         struct aca_event_reg_addr *regs);
 116 void dc_aca_txin_sub_ack(struct dc_ep_priv *priv, u32 val);
 117 u32 aca_umt_msg_addr(struct dc_ep_priv *priv, u32 endian, u32 type);
 118 u32 dc_aca_txin_hd_cnt(struct dc_ep_priv *priv);
 119 void dc_aca_free_fw_file(struct dc_ep_priv *priv);
 120
 121 /* Card specific private data structure */
 122 struct pcie_ep_adapter {
 123         struct platform_device *mei_dev; /* the mei driver */
 124 };
 125
 126 #endif /* EP_H */
 127