package/kernel/lantiq/vrx518_ep/src/misc.c

   1 /*******************************************************************************
   2
   3   Intel SmartPHY DSL PCIe Endpoint/ACA Linux driver
   4   Copyright(c) 2016 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22 *******************************************************************************/
  23
  24 #include <linux/delay.h>
  25 #include <linux/mutex.h>
  26
  27 #include "regs.h"
  28 #include "ep.h"
  29 #include "misc.h"
  30
  31 #define padc_getbit(p, r)       (!!(rd32(r) & (1 << p)))
  32 #define padc_setbit(p, r)       wr32_mask(0, BIT(p), r)
  33 #define padc_clearbit(p, r)     wr32_mask(BIT(p), 0, r)
  34
  35 void dc_ep_clkod_disable(struct dc_ep_priv *priv)
  36 {
  37         wr32_mask(0, IF_CLKOD_ALL, IF_CLK);
  38 }
  39
  40 void dc_ep_icu_init(struct dc_ep_priv *priv)
  41 {
  42         /* Enable all interrupts in ICU level */
  43         wr32(ICU_DMA_TX_ALL, ICU_DMA_TX_IMER);
  44         wr32(ICU_DMA_RX_ALL, ICU_DMA_RX_IMER);
  45         wr32(ICU_TOP_ALL, ICU_IMER);
  46
  47         if (priv->msi_mode == DC_EP_4_MSI_MODE)
  48                 wr32(PCI_MSI_4_MODE, RCU_MSI);
  49         else
  50                 wr32(PCI_MSI_8_MODE, RCU_MSI);
  51
  52         /* PCIe app has to enable all MSI interrupts regardless of MSI mode */
  53         wr32(PCIE_MSI_EN_ALL, PCIE_APPL_MSI_EN);
  54 }
  55
  56 void dc_ep_icu_disable(struct dc_ep_priv *priv)
  57 {
  58         /* Disable all PCIe related interrupts */
  59         wr32(0, PCIE_APPL_MSI_EN);
  60
  61         wr32(PCI_MSI_8_MODE, RCU_MSI);
  62
  63         /* Disable all interrupts in ICU level */
  64         wr32(0, ICU_DMA_TX_IMER);
  65         wr32(0, ICU_DMA_RX_IMER);
  66         wr32(0, ICU_IMER);
  67 }
  68
  69 void dc_ep_icu_dis_intr(struct dc_ep_priv *priv, u32 bits)
  70 {
  71         wr32_mask(~bits, 0, ICU_IMER);
  72 }
  73
  74 void dc_ep_icu_en_intr(struct dc_ep_priv *priv, u32 bits)
  75 {
  76         wr32_mask(0, bits, ICU_IMER);
  77 }
  78
  79 void dc_ep_assert_device(struct dc_ep_priv *priv, u32 bits)
  80 {
  81         struct dc_aca *aca = to_aca(priv);
  82
  83         spin_lock(&aca->rcu_lock);
  84         wr32_mask(0, bits, RCU_REQ);
  85         spin_unlock(&aca->rcu_lock);
  86 }
  87
  88 void dc_ep_deassert_device(struct dc_ep_priv *priv, u32 bits)
  89 {
  90         struct dc_aca *aca = to_aca(priv);
  91
  92         spin_lock(&aca->rcu_lock);
  93         wr32_mask(bits, 0, RCU_REQ);
  94         spin_unlock(&aca->rcu_lock);
  95 }
  96
  97 int dc_ep_reset_device(struct dc_ep_priv *priv, u32 bits)
  98 {
  99         int retry = EP_TIMEOUT;
 100
 101         wr32(bits, RCU_REQ);
 102         do { } while (retry-- && (!(rd32(RCU_STAT) & bits)));
 103
 104         if (retry == 0) {
 105                 dev_err(priv->dev, "%s failed to reset\n", __func__);
 106                 return -ETIME;
 107         }
 108         return 0;
 109 }
 110
 111 int dc_ep_clk_on(struct dc_ep_priv *priv, u32 bits)
 112 {
 113         int retry = EP_TIMEOUT;
 114         struct dc_aca *aca = to_aca(priv);
 115
 116         spin_lock(&aca->clk_lock);
 117         wr32_mask(bits, 0, PMU_PWDCR);
 118         spin_unlock(&aca->clk_lock);
 119
 120         do { } while (--retry && (rd32(PMU_SR) & bits));
 121
 122         if (!retry) {
 123                 dev_err(priv->dev, "%s failed\n", __func__);
 124                 return -ETIME;
 125         }
 126         return 0;
 127 }
 128
 129 int dc_ep_clk_off(struct dc_ep_priv *priv, u32 bits)
 130 {
 131         int retry = EP_TIMEOUT;
 132         struct dc_aca *aca = to_aca(priv);
 133
 134         spin_lock(&aca->clk_lock);
 135         wr32_mask(0, bits, PMU_PWDCR);
 136         spin_unlock(&aca->clk_lock);
 137
 138         do {} while (--retry
 139                 && (!(rd32(PMU_SR) & bits)));
 140         if (!retry) {
 141                 dev_err(priv->dev, "%s failed\n", __func__);
 142                 return -ETIME;
 143         }
 144         return 0;
 145 }
 146
 147 int dc_ep_clk_set(struct dc_ep_priv *priv, u32 sysclk, u32 ppeclk)
 148 {
 149         struct dc_aca *aca = to_aca(priv);
 150
 151         if (sysclk > SYS_CLK_MAX || ppeclk > PPE_CLK_MAX)
 152                 return -EINVAL;
 153
 154         spin_lock(&aca->clk_lock);
 155         wr32_mask(PPE_CLK | SYS_CLK,
 156                 SM(sysclk, SYS_CLK) | SM(ppeclk, PPE_CLK), PLL_OMCFG);
 157         spin_unlock(&aca->clk_lock);
 158         return 0;
 159 }
 160
 161 int dc_ep_clk_get(struct dc_ep_priv *priv, u32 *sysclk, u32 *ppeclk)
 162 {
 163         u32 val;
 164
 165         val = rd32(PLL_OMCFG);
 166         *sysclk = MS(val, SYS_CLK);
 167         *ppeclk = MS(val, PPE_CLK);
 168         return 0;
 169 }
 170
 171 int dc_ep_gpio_dir(struct dc_ep_priv *priv, u32 gpio, int dir)
 172 {
 173         struct dc_aca *aca = to_aca(priv);
 174
 175         if (gpio > aca->max_gpio)
 176                 return -EINVAL;
 177
 178         if ((dir != GPIO_DIR_IN) && (dir != GPIO_DIR_OUT))
 179                 return -EINVAL;
 180
 181         if (dir == GPIO_DIR_IN)
 182                 wr32(BIT(gpio), GPIO_DIRCLR);
 183         else
 184                 wr32(BIT(gpio), GPIO_DIRSET);
 185         return 0;
 186 }
 187
 188 int dc_ep_gpio_set(struct dc_ep_priv *priv, u32 gpio, int val)
 189 {
 190         struct dc_aca *aca = to_aca(priv);
 191
 192         if (gpio > aca->max_gpio)
 193                 return -EINVAL;
 194
 195         dc_ep_gpio_dir(priv, gpio, GPIO_DIR_OUT);
 196
 197         if (val)
 198                 wr32(BIT(gpio), GPIO_OUTSET);
 199         else
 200                 wr32(BIT(gpio), GPIO_OUTCLR);
 201         return 0;
 202 }
 203
 204 int dc_ep_gpio_get(struct dc_ep_priv *priv, u32 gpio, int *val)
 205 {
 206         u32 dir;
 207         struct dc_aca *aca = to_aca(priv);
 208
 209         if (gpio > aca->max_gpio)
 210                 return -EINVAL;
 211
 212         dir = rd32(GPIO_DIR);
 213         if ((dir >> gpio) & 0x1)
 214                 *val = (rd32(GPIO_OUT) >> gpio) & 0x1;
 215         else
 216                 *val = (rd32(GPIO_IN) >> gpio) & 0x1;
 217         return 0;
 218 }
 219
 220 int dc_ep_pinmux_set(struct dc_ep_priv *priv, u32 gpio, int func)
 221 {
 222         struct dc_aca *aca = to_aca(priv);
 223
 224         if (gpio > aca->max_gpio)
 225                 return -EINVAL;
 226
 227         if (func >= MUX_FUNC_RES)
 228                 return -EINVAL;
 229
 230         mutex_lock(&aca->pin_lock);
 231         wr32_mask(PADC_MUX_M, func, PADC_MUX(gpio));
 232         mutex_unlock(&aca->pin_lock);
 233         return 0;
 234 }
 235
 236 int dc_ep_pinmux_get(struct dc_ep_priv *priv, u32 gpio, int *func)
 237 {
 238         struct dc_aca *aca = to_aca(priv);
 239
 240         if (gpio > aca->max_gpio)
 241                 return -EINVAL;
 242
 243         *func = rd32(PADC_MUX(gpio));
 244         return 0;
 245 }
 246
 247 int dc_ep_gpio_pupd_set(struct dc_ep_priv *priv, u32 gpio, u32 val)
 248 {
 249         struct dc_aca *aca = to_aca(priv);
 250
 251         if (gpio > aca->max_gpio)
 252                 return -EINVAL;
 253
 254         /* Not support for both enabled */
 255         if (val >= GPIO_PUPD_BOTH)
 256                 return -EINVAL;
 257
 258         mutex_lock(&aca->pin_lock);
 259         switch (val) {
 260         case GPIO_PUPD_DISABLE:
 261                 padc_clearbit(gpio, PADC_PUEN);
 262                 padc_clearbit(gpio, PADC_PDEN);
 263                 break;
 264         case GPIO_PULL_UP:
 265                 padc_setbit(gpio, PADC_PUEN);
 266                 padc_clearbit(gpio, PADC_PDEN);
 267                 break;
 268         case GPIO_PULL_DOWN:
 269                 padc_setbit(gpio, PADC_PDEN);
 270                 padc_clearbit(gpio, PADC_PUEN);
 271                 break;
 272         default:
 273                 break;
 274         }
 275         mutex_unlock(&aca->pin_lock);
 276         return 0;
 277 }
 278
 279 int dc_ep_gpio_od_set(struct dc_ep_priv *priv, u32 gpio, int val)
 280 {
 281         struct dc_aca *aca = to_aca(priv);
 282
 283         if (gpio > aca->max_gpio)
 284                 return -EINVAL;
 285
 286         mutex_lock(&aca->pin_lock);
 287         if (!!val)
 288                 padc_setbit(gpio, PADC_OD);
 289         else
 290                 padc_clearbit(gpio, PADC_OD);
 291         mutex_unlock(&aca->pin_lock);
 292         return 0;
 293 }
 294
 295 int dc_ep_gpio_src_set(struct dc_ep_priv *priv, u32 gpio, int val)
 296 {
 297         struct dc_aca *aca = to_aca(priv);
 298
 299         if (gpio > aca->max_gpio)
 300                 return -EINVAL;
 301
 302         mutex_lock(&aca->pin_lock);
 303         if (!!val)
 304                 padc_setbit(gpio, PADC_SRC);
 305         else
 306                 padc_clearbit(gpio, PADC_SRC);
 307         mutex_unlock(&aca->pin_lock);
 308         return 0;
 309 }
 310
 311 int dc_ep_gpio_dcc_set(struct dc_ep_priv *priv, u32 gpio, u32 val)
 312 {
 313         struct dc_aca *aca = to_aca(priv);
 314
 315         if (gpio > aca->max_gpio)
 316                 return -EINVAL;
 317
 318         if (val >= GPIO_DRV_CUR_MAX)
 319                 return -EINVAL;
 320
 321         mutex_lock(&aca->pin_lock);
 322         wr32_mask((0x3 << (gpio * 2)), (val << (gpio * 2)), PADC_DCC);
 323         mutex_unlock(&aca->pin_lock);
 324         return 0;
 325 }