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ath9k: merge initval updates
[openwrt/staging/lynxis/omap.git] / package / kernel / mac80211 / patches / 300-pending_work.patch
1 --- a/drivers/net/wireless/ath/ath10k/mac.c
2 +++ b/drivers/net/wireless/ath/ath10k/mac.c
3 @@ -1351,12 +1351,12 @@ static int ath10k_update_channel_list(st
4 ch->allow_vht = true;
5
6 ch->allow_ibss =
7 - !(channel->flags & IEEE80211_CHAN_NO_IBSS);
8 + !(channel->flags & IEEE80211_CHAN_NO_IR);
9
10 ch->ht40plus =
11 !(channel->flags & IEEE80211_CHAN_NO_HT40PLUS);
12
13 - passive = channel->flags & IEEE80211_CHAN_PASSIVE_SCAN;
14 + passive = channel->flags & IEEE80211_CHAN_NO_IR;
15 ch->passive = passive;
16
17 ch->freq = channel->center_freq;
18 --- a/drivers/net/wireless/ath/ath9k/Kconfig
19 +++ b/drivers/net/wireless/ath/ath9k/Kconfig
20 @@ -90,7 +90,7 @@ config ATH9K_DFS_CERTIFIED
21
22 config ATH9K_TX99
23 bool "Atheros ath9k TX99 testing support"
24 - depends on CFG80211_CERTIFICATION_ONUS
25 + depends on ATH9K_DEBUGFS && CFG80211_CERTIFICATION_ONUS
26 default n
27 ---help---
28 Say N. This should only be enabled on systems undergoing
29 @@ -108,6 +108,14 @@ config ATH9K_TX99
30 be evaluated to meet the RF exposure limits set forth in the
31 governmental SAR regulations.
32
33 +config ATH9K_WOW
34 + bool "Wake on Wireless LAN support (EXPERIMENTAL)"
35 + depends on ATH9K && PM
36 + default n
37 + ---help---
38 + This option enables Wake on Wireless LAN support for certain cards.
39 + Currently, AR9462 is supported.
40 +
41 config ATH9K_LEGACY_RATE_CONTROL
42 bool "Atheros ath9k rate control"
43 depends on ATH9K
44 --- a/drivers/net/wireless/ath/ath9k/Makefile
45 +++ b/drivers/net/wireless/ath/ath9k/Makefile
46 @@ -13,9 +13,9 @@ ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
47 ath9k-$(CPTCFG_ATH9K_AHB) += ahb.o
48 ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
49 ath9k-$(CPTCFG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
50 -ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += \
51 - dfs.o
52 -ath9k-$(CONFIG_PM_SLEEP) += wow.o
53 +ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += dfs.o
54 +ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o
55 +ath9k-$(CPTCFG_ATH9K_WOW) += wow.o
56
57 obj-$(CPTCFG_ATH9K) += ath9k.o
58
59 @@ -41,6 +41,8 @@ ath9k_hw-y:= \
60 ar9003_eeprom.o \
61 ar9003_paprd.o
62
63 +ath9k_hw-$(CPTCFG_ATH9K_WOW) += ar9003_wow.o
64 +
65 ath9k_hw-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) += btcoex.o \
66 ar9003_mci.o
67 obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o
68 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
69 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
70 @@ -26,6 +26,7 @@
71 #include "ar9462_2p0_initvals.h"
72 #include "ar9462_2p1_initvals.h"
73 #include "ar9565_1p0_initvals.h"
74 +#include "ar9565_1p1_initvals.h"
75
76 /* General hardware code for the AR9003 hadware family */
77
78 @@ -187,17 +188,17 @@ static void ar9003_hw_init_mode_regs(str
79 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
80 ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
81
82 - /* Load PCIE SERDES settings from INI */
83 -
84 - /* Awake Setting */
85 -
86 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
87 - ar9485_1_1_pcie_phy_clkreq_disable_L1);
88 -
89 - /* Sleep Setting */
90 -
91 - INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
92 - ar9485_1_1_pcie_phy_clkreq_disable_L1);
93 + if (ah->config.no_pll_pwrsave) {
94 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
95 + ar9485_1_1_pcie_phy_clkreq_disable_L1);
96 + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
97 + ar9485_1_1_pcie_phy_clkreq_disable_L1);
98 + } else {
99 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
100 + ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
101 + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
102 + ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
103 + }
104 } else if (AR_SREV_9462_21(ah)) {
105 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
106 ar9462_2p1_mac_core);
107 @@ -223,6 +224,10 @@ static void ar9003_hw_init_mode_regs(str
108 ar9462_2p1_modes_fast_clock);
109 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
110 ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
111 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
112 + ar9462_2p1_pciephy_clkreq_disable_L1);
113 + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
114 + ar9462_2p1_pciephy_clkreq_disable_L1);
115 } else if (AR_SREV_9462_20(ah)) {
116
117 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
118 @@ -247,18 +252,18 @@ static void ar9003_hw_init_mode_regs(str
119 ar9462_2p0_soc_postamble);
120
121 INIT_INI_ARRAY(&ah->iniModesRxGain,
122 - ar9462_common_rx_gain_table_2p0);
123 + ar9462_2p0_common_rx_gain);
124
125 /* Awake -> Sleep Setting */
126 INIT_INI_ARRAY(&ah->iniPcieSerdes,
127 - ar9462_pciephy_clkreq_disable_L1_2p0);
128 + ar9462_2p0_pciephy_clkreq_disable_L1);
129 /* Sleep -> Awake Setting */
130 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
131 - ar9462_pciephy_clkreq_disable_L1_2p0);
132 + ar9462_2p0_pciephy_clkreq_disable_L1);
133
134 /* Fast clock modal settings */
135 INIT_INI_ARRAY(&ah->iniModesFastClock,
136 - ar9462_modes_fast_clock_2p0);
137 + ar9462_2p0_modes_fast_clock);
138
139 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
140 ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
141 @@ -331,6 +336,41 @@ static void ar9003_hw_init_mode_regs(str
142
143 INIT_INI_ARRAY(&ah->iniModesFastClock,
144 ar9580_1p0_modes_fast_clock);
145 + } else if (AR_SREV_9565_11_OR_LATER(ah)) {
146 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
147 + ar9565_1p1_mac_core);
148 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
149 + ar9565_1p1_mac_postamble);
150 +
151 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
152 + ar9565_1p1_baseband_core);
153 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
154 + ar9565_1p1_baseband_postamble);
155 +
156 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
157 + ar9565_1p1_radio_core);
158 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
159 + ar9565_1p1_radio_postamble);
160 +
161 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
162 + ar9565_1p1_soc_preamble);
163 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
164 + ar9565_1p1_soc_postamble);
165 +
166 + INIT_INI_ARRAY(&ah->iniModesRxGain,
167 + ar9565_1p1_Common_rx_gain_table);
168 + INIT_INI_ARRAY(&ah->iniModesTxGain,
169 + ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
170 +
171 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
172 + ar9565_1p1_pciephy_clkreq_disable_L1);
173 + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
174 + ar9565_1p1_pciephy_clkreq_disable_L1);
175 +
176 + INIT_INI_ARRAY(&ah->iniModesFastClock,
177 + ar9565_1p1_modes_fast_clock);
178 + INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
179 + ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
180 } else if (AR_SREV_9565(ah)) {
181 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
182 ar9565_1p0_mac_core);
183 @@ -440,7 +480,10 @@ static void ar9003_tx_gain_table_mode0(s
184 ar9462_2p1_modes_low_ob_db_tx_gain);
185 else if (AR_SREV_9462_20(ah))
186 INIT_INI_ARRAY(&ah->iniModesTxGain,
187 - ar9462_modes_low_ob_db_tx_gain_table_2p0);
188 + ar9462_2p0_modes_low_ob_db_tx_gain);
189 + else if (AR_SREV_9565_11(ah))
190 + INIT_INI_ARRAY(&ah->iniModesTxGain,
191 + ar9565_1p1_modes_low_ob_db_tx_gain_table);
192 else if (AR_SREV_9565(ah))
193 INIT_INI_ARRAY(&ah->iniModesTxGain,
194 ar9565_1p0_modes_low_ob_db_tx_gain_table);
195 @@ -474,7 +517,10 @@ static void ar9003_tx_gain_table_mode1(s
196 ar9462_2p1_modes_high_ob_db_tx_gain);
197 else if (AR_SREV_9462_20(ah))
198 INIT_INI_ARRAY(&ah->iniModesTxGain,
199 - ar9462_modes_high_ob_db_tx_gain_table_2p0);
200 + ar9462_2p0_modes_high_ob_db_tx_gain);
201 + else if (AR_SREV_9565_11(ah))
202 + INIT_INI_ARRAY(&ah->iniModesTxGain,
203 + ar9565_1p1_modes_high_ob_db_tx_gain_table);
204 else if (AR_SREV_9565(ah))
205 INIT_INI_ARRAY(&ah->iniModesTxGain,
206 ar9565_1p0_modes_high_ob_db_tx_gain_table);
207 @@ -500,6 +546,9 @@ static void ar9003_tx_gain_table_mode2(s
208 else if (AR_SREV_9580(ah))
209 INIT_INI_ARRAY(&ah->iniModesTxGain,
210 ar9580_1p0_low_ob_db_tx_gain_table);
211 + else if (AR_SREV_9565_11(ah))
212 + INIT_INI_ARRAY(&ah->iniModesTxGain,
213 + ar9565_1p1_modes_low_ob_db_tx_gain_table);
214 else if (AR_SREV_9565(ah))
215 INIT_INI_ARRAY(&ah->iniModesTxGain,
216 ar9565_1p0_modes_low_ob_db_tx_gain_table);
217 @@ -525,6 +574,9 @@ static void ar9003_tx_gain_table_mode3(s
218 else if (AR_SREV_9580(ah))
219 INIT_INI_ARRAY(&ah->iniModesTxGain,
220 ar9580_1p0_high_power_tx_gain_table);
221 + else if (AR_SREV_9565_11(ah))
222 + INIT_INI_ARRAY(&ah->iniModesTxGain,
223 + ar9565_1p1_modes_high_power_tx_gain_table);
224 else if (AR_SREV_9565(ah))
225 INIT_INI_ARRAY(&ah->iniModesTxGain,
226 ar9565_1p0_modes_high_power_tx_gain_table);
227 @@ -546,7 +598,7 @@ static void ar9003_tx_gain_table_mode4(s
228 ar9462_2p1_modes_mix_ob_db_tx_gain);
229 else if (AR_SREV_9462_20(ah))
230 INIT_INI_ARRAY(&ah->iniModesTxGain,
231 - ar9462_modes_mix_ob_db_tx_gain_table_2p0);
232 + ar9462_2p0_modes_mix_ob_db_tx_gain);
233 else
234 INIT_INI_ARRAY(&ah->iniModesTxGain,
235 ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
236 @@ -581,6 +633,13 @@ static void ar9003_tx_gain_table_mode6(s
237 ar9580_1p0_type6_tx_gain_table);
238 }
239
240 +static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
241 +{
242 + if (AR_SREV_9340(ah))
243 + INIT_INI_ARRAY(&ah->iniModesTxGain,
244 + ar9340_cus227_tx_gain_table_1p0);
245 +}
246 +
247 typedef void (*ath_txgain_tab)(struct ath_hw *ah);
248
249 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
250 @@ -593,6 +652,7 @@ static void ar9003_tx_gain_table_apply(s
251 ar9003_tx_gain_table_mode4,
252 ar9003_tx_gain_table_mode5,
253 ar9003_tx_gain_table_mode6,
254 + ar9003_tx_gain_table_mode7,
255 };
256 int idx = ar9003_hw_get_tx_gain_idx(ah);
257
258 @@ -629,7 +689,10 @@ static void ar9003_rx_gain_table_mode0(s
259 ar9462_2p1_common_rx_gain);
260 else if (AR_SREV_9462_20(ah))
261 INIT_INI_ARRAY(&ah->iniModesRxGain,
262 - ar9462_common_rx_gain_table_2p0);
263 + ar9462_2p0_common_rx_gain);
264 + else if (AR_SREV_9565_11(ah))
265 + INIT_INI_ARRAY(&ah->iniModesRxGain,
266 + ar9565_1p1_Common_rx_gain_table);
267 else if (AR_SREV_9565(ah))
268 INIT_INI_ARRAY(&ah->iniModesRxGain,
269 ar9565_1p0_Common_rx_gain_table);
270 @@ -657,7 +720,7 @@ static void ar9003_rx_gain_table_mode1(s
271 ar9462_2p1_common_wo_xlna_rx_gain);
272 else if (AR_SREV_9462_20(ah))
273 INIT_INI_ARRAY(&ah->iniModesRxGain,
274 - ar9462_common_wo_xlna_rx_gain_table_2p0);
275 + ar9462_2p0_common_wo_xlna_rx_gain);
276 else if (AR_SREV_9550(ah)) {
277 INIT_INI_ARRAY(&ah->iniModesRxGain,
278 ar955x_1p0_common_wo_xlna_rx_gain_table);
279 @@ -666,6 +729,9 @@ static void ar9003_rx_gain_table_mode1(s
280 } else if (AR_SREV_9580(ah))
281 INIT_INI_ARRAY(&ah->iniModesRxGain,
282 ar9580_1p0_wo_xlna_rx_gain_table);
283 + else if (AR_SREV_9565_11(ah))
284 + INIT_INI_ARRAY(&ah->iniModesRxGain,
285 + ar9565_1p1_common_wo_xlna_rx_gain_table);
286 else if (AR_SREV_9565(ah))
287 INIT_INI_ARRAY(&ah->iniModesRxGain,
288 ar9565_1p0_common_wo_xlna_rx_gain_table);
289 @@ -687,7 +753,7 @@ static void ar9003_rx_gain_table_mode2(s
290 ar9462_2p1_baseband_postamble_5g_xlna);
291 } else if (AR_SREV_9462_20(ah)) {
292 INIT_INI_ARRAY(&ah->iniModesRxGain,
293 - ar9462_common_mixed_rx_gain_table_2p0);
294 + ar9462_2p0_common_mixed_rx_gain);
295 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
296 ar9462_2p0_baseband_core_mix_rxgain);
297 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
298 @@ -701,12 +767,12 @@ static void ar9003_rx_gain_table_mode3(s
299 {
300 if (AR_SREV_9462_21(ah)) {
301 INIT_INI_ARRAY(&ah->iniModesRxGain,
302 - ar9462_2p1_common_5g_xlna_only_rx_gain);
303 + ar9462_2p1_common_5g_xlna_only_rxgain);
304 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
305 ar9462_2p1_baseband_postamble_5g_xlna);
306 } else if (AR_SREV_9462_20(ah)) {
307 INIT_INI_ARRAY(&ah->iniModesRxGain,
308 - ar9462_2p0_5g_xlna_only_rxgain);
309 + ar9462_2p0_common_5g_xlna_only_rxgain);
310 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
311 ar9462_2p0_baseband_postamble_5g_xlna);
312 }
313 @@ -750,6 +816,9 @@ static void ar9003_hw_init_mode_gain_reg
314 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
315 bool power_off)
316 {
317 + unsigned int i;
318 + struct ar5416IniArray *array;
319 +
320 /*
321 * Increase L1 Entry Latency. Some WB222 boards don't have
322 * this change in eeprom/OTP.
323 @@ -775,18 +844,13 @@ static void ar9003_hw_configpcipowersave
324 * Configire PCIE after Ini init. SERDES values now come from ini file
325 * This enables PCIe low power mode.
326 */
327 - if (ah->config.pcieSerDesWrite) {
328 - unsigned int i;
329 - struct ar5416IniArray *array;
330 -
331 - array = power_off ? &ah->iniPcieSerdes :
332 - &ah->iniPcieSerdesLowPower;
333 -
334 - for (i = 0; i < array->ia_rows; i++) {
335 - REG_WRITE(ah,
336 - INI_RA(array, i, 0),
337 - INI_RA(array, i, 1));
338 - }
339 + array = power_off ? &ah->iniPcieSerdes :
340 + &ah->iniPcieSerdesLowPower;
341 +
342 + for (i = 0; i < array->ia_rows; i++) {
343 + REG_WRITE(ah,
344 + INI_RA(array, i, 0),
345 + INI_RA(array, i, 1));
346 }
347 }
348
349 --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
350 +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
351 @@ -1447,4 +1447,106 @@ static const u32 ar9340_1p0_soc_preamble
352 {0x00007038, 0x000004c2},
353 };
354
355 +static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = {
356 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
357 + {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
358 + {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
359 + {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
360 + {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
361 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
362 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
363 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
364 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
365 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
366 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
367 + {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
368 + {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
369 + {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
370 + {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603},
371 + {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02},
372 + {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04},
373 + {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20},
374 + {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20},
375 + {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
376 + {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
377 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
378 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
379 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
380 + {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
381 + {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
382 + {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
383 + {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
384 + {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
385 + {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
386 + {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
387 + {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
388 + {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
389 + {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
390 + {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
391 + {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
392 + {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
393 + {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
394 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
395 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
396 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
397 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
398 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
399 + {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
400 + {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
401 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
402 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
403 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
404 + {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
405 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
406 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
407 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
408 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
409 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
410 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
411 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
412 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
413 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
414 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
415 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
416 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
417 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
418 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
419 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
420 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
421 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
422 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
423 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
424 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
425 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
426 + {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
427 + {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
428 + {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
429 + {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
430 + {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
431 + {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
432 + {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
433 + {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
434 + {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
435 + {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
436 + {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
437 + {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
438 + {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
439 + {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
440 + {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
441 + {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
442 + {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
443 + {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
444 + {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
445 + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
446 + {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
447 + {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
448 + {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
449 + {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
450 + {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
451 + {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
452 + {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011},
453 + {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c},
454 + {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030},
455 +};
456 +
457 #endif /* INITVALS_9340_H */
458 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
459 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
460 @@ -459,6 +459,7 @@ void ath_check_ani(struct ath_softc *sc)
461 int ath_update_survey_stats(struct ath_softc *sc);
462 void ath_update_survey_nf(struct ath_softc *sc, int channel);
463 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
464 +void ath_ps_full_sleep(unsigned long data);
465
466 /**********/
467 /* BTCOEX */
468 @@ -570,6 +571,34 @@ static inline void ath_fill_led_pin(stru
469 }
470 #endif
471
472 +/************************/
473 +/* Wake on Wireless LAN */
474 +/************************/
475 +
476 +#ifdef CONFIG_ATH9K_WOW
477 +void ath9k_init_wow(struct ieee80211_hw *hw);
478 +int ath9k_suspend(struct ieee80211_hw *hw,
479 + struct cfg80211_wowlan *wowlan);
480 +int ath9k_resume(struct ieee80211_hw *hw);
481 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
482 +#else
483 +static inline void ath9k_init_wow(struct ieee80211_hw *hw)
484 +{
485 +}
486 +static inline int ath9k_suspend(struct ieee80211_hw *hw,
487 + struct cfg80211_wowlan *wowlan)
488 +{
489 + return 0;
490 +}
491 +static inline int ath9k_resume(struct ieee80211_hw *hw)
492 +{
493 + return 0;
494 +}
495 +static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
496 +{
497 +}
498 +#endif /* CONFIG_ATH9K_WOW */
499 +
500 /*******************************/
501 /* Antenna diversity/combining */
502 /*******************************/
503 @@ -632,15 +661,16 @@ void ath_ant_comb_scan(struct ath_softc
504 /* Main driver core */
505 /********************/
506
507 -#define ATH9K_PCI_CUS198 0x0001
508 -#define ATH9K_PCI_CUS230 0x0002
509 -#define ATH9K_PCI_CUS217 0x0004
510 -#define ATH9K_PCI_CUS252 0x0008
511 -#define ATH9K_PCI_WOW 0x0010
512 -#define ATH9K_PCI_BT_ANT_DIV 0x0020
513 -#define ATH9K_PCI_D3_L1_WAR 0x0040
514 -#define ATH9K_PCI_AR9565_1ANT 0x0080
515 -#define ATH9K_PCI_AR9565_2ANT 0x0100
516 +#define ATH9K_PCI_CUS198 0x0001
517 +#define ATH9K_PCI_CUS230 0x0002
518 +#define ATH9K_PCI_CUS217 0x0004
519 +#define ATH9K_PCI_CUS252 0x0008
520 +#define ATH9K_PCI_WOW 0x0010
521 +#define ATH9K_PCI_BT_ANT_DIV 0x0020
522 +#define ATH9K_PCI_D3_L1_WAR 0x0040
523 +#define ATH9K_PCI_AR9565_1ANT 0x0080
524 +#define ATH9K_PCI_AR9565_2ANT 0x0100
525 +#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
526
527 /*
528 * Default cache line size, in bytes.
529 @@ -723,6 +753,7 @@ struct ath_softc {
530 struct work_struct hw_check_work;
531 struct work_struct hw_reset_work;
532 struct completion paprd_complete;
533 + wait_queue_head_t tx_wait;
534
535 unsigned int hw_busy_count;
536 unsigned long sc_flags;
537 @@ -759,6 +790,7 @@ struct ath_softc {
538 struct delayed_work tx_complete_work;
539 struct delayed_work hw_pll_work;
540 struct timer_list rx_poll_timer;
541 + struct timer_list sleep_timer;
542
543 #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
544 struct ath_btcoex btcoex;
545 @@ -783,7 +815,7 @@ struct ath_softc {
546 bool tx99_state;
547 s16 tx99_power;
548
549 -#ifdef CONFIG_PM_SLEEP
550 +#ifdef CONFIG_ATH9K_WOW
551 atomic_t wow_got_bmiss_intr;
552 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
553 u32 wow_intr_before_sleep;
554 @@ -946,10 +978,25 @@ struct fft_sample_ht20_40 {
555 u8 data[SPECTRAL_HT20_40_NUM_BINS];
556 } __packed;
557
558 -int ath9k_tx99_init(struct ath_softc *sc);
559 -void ath9k_tx99_deinit(struct ath_softc *sc);
560 +/********/
561 +/* TX99 */
562 +/********/
563 +
564 +#ifdef CONFIG_ATH9K_TX99
565 +void ath9k_tx99_init_debug(struct ath_softc *sc);
566 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
567 struct ath_tx_control *txctl);
568 +#else
569 +static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
570 +{
571 +}
572 +static inline int ath9k_tx99_send(struct ath_softc *sc,
573 + struct sk_buff *skb,
574 + struct ath_tx_control *txctl)
575 +{
576 + return 0;
577 +}
578 +#endif /* CONFIG_ATH9K_TX99 */
579
580 void ath9k_tasklet(unsigned long data);
581 int ath_cabq_update(struct ath_softc *);
582 @@ -966,6 +1013,9 @@ extern bool is_ath9k_unloaded;
583
584 u8 ath9k_parse_mpdudensity(u8 mpdudensity);
585 irqreturn_t ath_isr(int irq, void *dev);
586 +int ath_reset(struct ath_softc *sc);
587 +void ath_cancel_work(struct ath_softc *sc);
588 +void ath_restart_work(struct ath_softc *sc);
589 int ath9k_init_device(u16 devid, struct ath_softc *sc,
590 const struct ath_bus_ops *bus_ops);
591 void ath9k_deinit_device(struct ath_softc *sc);
592 --- a/drivers/net/wireless/ath/ath9k/debug.c
593 +++ b/drivers/net/wireless/ath/ath9k/debug.c
594 @@ -1782,111 +1782,6 @@ void ath9k_deinit_debug(struct ath_softc
595 }
596 }
597
598 -static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
599 - size_t count, loff_t *ppos)
600 -{
601 - struct ath_softc *sc = file->private_data;
602 - char buf[3];
603 - unsigned int len;
604 -
605 - len = sprintf(buf, "%d\n", sc->tx99_state);
606 - return simple_read_from_buffer(user_buf, count, ppos, buf, len);
607 -}
608 -
609 -static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
610 - size_t count, loff_t *ppos)
611 -{
612 - struct ath_softc *sc = file->private_data;
613 - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
614 - char buf[32];
615 - bool start;
616 - ssize_t len;
617 - int r;
618 -
619 - if (sc->nvifs > 1)
620 - return -EOPNOTSUPP;
621 -
622 - len = min(count, sizeof(buf) - 1);
623 - if (copy_from_user(buf, user_buf, len))
624 - return -EFAULT;
625 -
626 - if (strtobool(buf, &start))
627 - return -EINVAL;
628 -
629 - if (start == sc->tx99_state) {
630 - if (!start)
631 - return count;
632 - ath_dbg(common, XMIT, "Resetting TX99\n");
633 - ath9k_tx99_deinit(sc);
634 - }
635 -
636 - if (!start) {
637 - ath9k_tx99_deinit(sc);
638 - return count;
639 - }
640 -
641 - r = ath9k_tx99_init(sc);
642 - if (r)
643 - return r;
644 -
645 - return count;
646 -}
647 -
648 -static const struct file_operations fops_tx99 = {
649 - .read = read_file_tx99,
650 - .write = write_file_tx99,
651 - .open = simple_open,
652 - .owner = THIS_MODULE,
653 - .llseek = default_llseek,
654 -};
655 -
656 -static ssize_t read_file_tx99_power(struct file *file,
657 - char __user *user_buf,
658 - size_t count, loff_t *ppos)
659 -{
660 - struct ath_softc *sc = file->private_data;
661 - char buf[32];
662 - unsigned int len;
663 -
664 - len = sprintf(buf, "%d (%d dBm)\n",
665 - sc->tx99_power,
666 - sc->tx99_power / 2);
667 -
668 - return simple_read_from_buffer(user_buf, count, ppos, buf, len);
669 -}
670 -
671 -static ssize_t write_file_tx99_power(struct file *file,
672 - const char __user *user_buf,
673 - size_t count, loff_t *ppos)
674 -{
675 - struct ath_softc *sc = file->private_data;
676 - int r;
677 - u8 tx_power;
678 -
679 - r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
680 - if (r)
681 - return r;
682 -
683 - if (tx_power > MAX_RATE_POWER)
684 - return -EINVAL;
685 -
686 - sc->tx99_power = tx_power;
687 -
688 - ath9k_ps_wakeup(sc);
689 - ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
690 - ath9k_ps_restore(sc);
691 -
692 - return count;
693 -}
694 -
695 -static const struct file_operations fops_tx99_power = {
696 - .read = read_file_tx99_power,
697 - .write = write_file_tx99_power,
698 - .open = simple_open,
699 - .owner = THIS_MODULE,
700 - .llseek = default_llseek,
701 -};
702 -
703 int ath9k_init_debug(struct ath_hw *ah)
704 {
705 struct ath_common *common = ath9k_hw_common(ah);
706 @@ -1903,6 +1798,7 @@ int ath9k_init_debug(struct ath_hw *ah)
707 #endif
708
709 ath9k_dfs_init_debug(sc);
710 + ath9k_tx99_init_debug(sc);
711
712 debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
713 &fops_dma);
714 @@ -1978,15 +1874,6 @@ int ath9k_init_debug(struct ath_hw *ah)
715 debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
716 &fops_btcoex);
717 #endif
718 - if (config_enabled(CPTCFG_ATH9K_TX99) &&
719 - AR_SREV_9300_20_OR_LATER(ah)) {
720 - debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
721 - sc->debug.debugfs_phy, sc,
722 - &fops_tx99);
723 - debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
724 - sc->debug.debugfs_phy, sc,
725 - &fops_tx99_power);
726 - }
727
728 return 0;
729 }
730 --- a/drivers/net/wireless/ath/ath9k/hw.c
731 +++ b/drivers/net/wireless/ath/ath9k/hw.c
732 @@ -17,6 +17,7 @@
733 #include <linux/io.h>
734 #include <linux/slab.h>
735 #include <linux/module.h>
736 +#include <linux/time.h>
737 #include <asm/unaligned.h>
738
739 #include "hw.h"
740 @@ -454,7 +455,6 @@ static void ath9k_hw_init_config(struct
741 }
742
743 ah->config.rx_intr_mitigation = true;
744 - ah->config.pcieSerDesWrite = true;
745
746 /*
747 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
748 @@ -1502,8 +1502,9 @@ static bool ath9k_hw_channel_change(stru
749 int r;
750
751 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
752 - band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
753 - mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
754 + u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
755 + band_switch = !!(flags_diff & CHANNEL_5GHZ);
756 + mode_diff = !!(flags_diff & ~CHANNEL_HT);
757 }
758
759 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
760 @@ -1815,7 +1816,7 @@ static int ath9k_hw_do_fastcc(struct ath
761 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
762 */
763 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
764 - chan->channelFlags != ah->curchan->channelFlags)
765 + ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
766 goto fail;
767
768 if (!ath9k_hw_check_alive(ah))
769 @@ -1856,10 +1857,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
770 struct ath9k_hw_cal_data *caldata, bool fastcc)
771 {
772 struct ath_common *common = ath9k_hw_common(ah);
773 + struct timespec ts;
774 u32 saveLedState;
775 u32 saveDefAntenna;
776 u32 macStaId1;
777 u64 tsf = 0;
778 + s64 usec = 0;
779 int r;
780 bool start_mci_reset = false;
781 bool save_fullsleep = ah->chip_fullsleep;
782 @@ -1902,10 +1905,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
783
784 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
785
786 - /* For chips on which RTC reset is done, save TSF before it gets cleared */
787 - if (AR_SREV_9100(ah) ||
788 - (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
789 - tsf = ath9k_hw_gettsf64(ah);
790 + /* Save TSF before chip reset, a cold reset clears it */
791 + tsf = ath9k_hw_gettsf64(ah);
792 + getrawmonotonic(&ts);
793 + usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
794
795 saveLedState = REG_READ(ah, AR_CFG_LED) &
796 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
797 @@ -1938,8 +1941,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
798 }
799
800 /* Restore TSF */
801 - if (tsf)
802 - ath9k_hw_settsf64(ah, tsf);
803 + getrawmonotonic(&ts);
804 + usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
805 + ath9k_hw_settsf64(ah, tsf + usec);
806
807 if (AR_SREV_9280_20_OR_LATER(ah))
808 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
809 --- a/drivers/net/wireless/ath/ath9k/hw.h
810 +++ b/drivers/net/wireless/ath/ath9k/hw.h
811 @@ -283,7 +283,6 @@ struct ath9k_ops_config {
812 int additional_swba_backoff;
813 int ack_6mb;
814 u32 cwm_ignore_extcca;
815 - bool pcieSerDesWrite;
816 u8 pcie_clock_req;
817 u32 pcie_waen;
818 u8 analog_shiftreg;
819 @@ -316,6 +315,7 @@ struct ath9k_ops_config {
820 u32 ant_ctrl_comm2g_switch_enable;
821 bool xatten_margin_cfg;
822 bool alt_mingainidx;
823 + bool no_pll_pwrsave;
824 };
825
826 enum ath9k_int {
827 @@ -920,7 +920,7 @@ struct ath_hw {
828 /* Enterprise mode cap */
829 u32 ent_mode;
830
831 -#ifdef CONFIG_PM_SLEEP
832 +#ifdef CONFIG_ATH9K_WOW
833 u32 wow_event_mask;
834 #endif
835 bool is_clk_25mhz;
836 @@ -1126,7 +1126,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
837 #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
838
839
840 -#ifdef CONFIG_PM_SLEEP
841 +#ifdef CONFIG_ATH9K_WOW
842 const char *ath9k_hw_wow_event_to_string(u32 wow_event);
843 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
844 u8 *user_mask, int pattern_count,
845 --- a/drivers/net/wireless/ath/ath9k/init.c
846 +++ b/drivers/net/wireless/ath/ath9k/init.c
847 @@ -609,6 +609,11 @@ static void ath9k_init_platform(struct a
848 ah->config.pcie_waen = 0x0040473b;
849 ath_info(common, "Enable WAR for ASPM D3/L1\n");
850 }
851 +
852 + if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
853 + ah->config.no_pll_pwrsave = true;
854 + ath_info(common, "Disable PLL PowerSave\n");
855 + }
856 }
857
858 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
859 @@ -683,6 +688,7 @@ static int ath9k_init_softc(u16 devid, s
860 common = ath9k_hw_common(ah);
861 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
862 sc->tx99_power = MAX_RATE_POWER + 1;
863 + init_waitqueue_head(&sc->tx_wait);
864
865 if (!pdata) {
866 ah->ah_flags |= AH_USE_EEPROM;
867 @@ -730,6 +736,7 @@ static int ath9k_init_softc(u16 devid, s
868 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
869 (unsigned long)sc);
870
871 + setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
872 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
873 INIT_WORK(&sc->hw_check_work, ath_hw_check);
874 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
875 @@ -845,7 +852,8 @@ static const struct ieee80211_iface_limi
876 };
877
878 static const struct ieee80211_iface_limit if_dfs_limits[] = {
879 - { .max = 1, .types = BIT(NL80211_IFTYPE_AP) },
880 + { .max = 1, .types = BIT(NL80211_IFTYPE_AP) |
881 + BIT(NL80211_IFTYPE_ADHOC) },
882 };
883
884 static const struct ieee80211_iface_combination if_comb[] = {
885 @@ -862,20 +870,11 @@ static const struct ieee80211_iface_comb
886 .max_interfaces = 1,
887 .num_different_channels = 1,
888 .beacon_int_infra_match = true,
889 - .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
890 - BIT(NL80211_CHAN_HT20),
891 + .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
892 + BIT(NL80211_CHAN_WIDTH_20),
893 }
894 };
895
896 -#ifdef CONFIG_PM
897 -static const struct wiphy_wowlan_support ath9k_wowlan_support = {
898 - .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
899 - .n_patterns = MAX_NUM_USER_PATTERN,
900 - .pattern_min_len = 1,
901 - .pattern_max_len = MAX_PATTERN_SIZE,
902 -};
903 -#endif
904 -
905 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
906 {
907 struct ath_hw *ah = sc->sc_ah;
908 @@ -925,16 +924,6 @@ void ath9k_set_hw_capab(struct ath_softc
909 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
910 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
911
912 -#ifdef CONFIG_PM_SLEEP
913 - if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
914 - (sc->driver_data & ATH9K_PCI_WOW) &&
915 - device_can_wakeup(sc->dev))
916 - hw->wiphy->wowlan = &ath9k_wowlan_support;
917 -
918 - atomic_set(&sc->wow_sleep_proc_intr, -1);
919 - atomic_set(&sc->wow_got_bmiss_intr, -1);
920 -#endif
921 -
922 hw->queues = 4;
923 hw->max_rates = 4;
924 hw->channel_change_time = 5000;
925 @@ -960,6 +949,7 @@ void ath9k_set_hw_capab(struct ath_softc
926 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
927 &sc->sbands[IEEE80211_BAND_5GHZ];
928
929 + ath9k_init_wow(hw);
930 ath9k_reload_chainmask_settings(sc);
931
932 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
933 @@ -1058,6 +1048,7 @@ static void ath9k_deinit_softc(struct at
934 if (ATH_TXQ_SETUP(sc, i))
935 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
936
937 + del_timer_sync(&sc->sleep_timer);
938 ath9k_hw_deinit(sc->sc_ah);
939 if (sc->dfs_detector != NULL)
940 sc->dfs_detector->exit(sc->dfs_detector);
941 --- a/drivers/net/wireless/ath/ath9k/main.c
942 +++ b/drivers/net/wireless/ath/ath9k/main.c
943 @@ -82,6 +82,22 @@ static bool ath9k_setpower(struct ath_so
944 return ret;
945 }
946
947 +void ath_ps_full_sleep(unsigned long data)
948 +{
949 + struct ath_softc *sc = (struct ath_softc *) data;
950 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
951 + bool reset;
952 +
953 + spin_lock(&common->cc_lock);
954 + ath_hw_cycle_counters_update(common);
955 + spin_unlock(&common->cc_lock);
956 +
957 + ath9k_hw_setrxabort(sc->sc_ah, 1);
958 + ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
959 +
960 + ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
961 +}
962 +
963 void ath9k_ps_wakeup(struct ath_softc *sc)
964 {
965 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
966 @@ -92,6 +108,7 @@ void ath9k_ps_wakeup(struct ath_softc *s
967 if (++sc->ps_usecount != 1)
968 goto unlock;
969
970 + del_timer_sync(&sc->sleep_timer);
971 power_mode = sc->sc_ah->power_mode;
972 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
973
974 @@ -117,17 +134,17 @@ void ath9k_ps_restore(struct ath_softc *
975 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
976 enum ath9k_power_mode mode;
977 unsigned long flags;
978 - bool reset;
979
980 spin_lock_irqsave(&sc->sc_pm_lock, flags);
981 if (--sc->ps_usecount != 0)
982 goto unlock;
983
984 if (sc->ps_idle) {
985 - ath9k_hw_setrxabort(sc->sc_ah, 1);
986 - ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
987 - mode = ATH9K_PM_FULL_SLEEP;
988 - } else if (sc->ps_enabled &&
989 + mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
990 + goto unlock;
991 + }
992 +
993 + if (sc->ps_enabled &&
994 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
995 PS_WAIT_FOR_CAB |
996 PS_WAIT_FOR_PSPOLL_DATA |
997 @@ -163,13 +180,13 @@ static void __ath_cancel_work(struct ath
998 #endif
999 }
1000
1001 -static void ath_cancel_work(struct ath_softc *sc)
1002 +void ath_cancel_work(struct ath_softc *sc)
1003 {
1004 __ath_cancel_work(sc);
1005 cancel_work_sync(&sc->hw_reset_work);
1006 }
1007
1008 -static void ath_restart_work(struct ath_softc *sc)
1009 +void ath_restart_work(struct ath_softc *sc)
1010 {
1011 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1012
1013 @@ -487,6 +504,8 @@ void ath9k_tasklet(unsigned long data)
1014 ath_tx_edma_tasklet(sc);
1015 else
1016 ath_tx_tasklet(sc);
1017 +
1018 + wake_up(&sc->tx_wait);
1019 }
1020
1021 ath9k_btcoex_handle_interrupt(sc, status);
1022 @@ -579,7 +598,8 @@ irqreturn_t ath_isr(int irq, void *dev)
1023
1024 goto chip_reset;
1025 }
1026 -#ifdef CONFIG_PM_SLEEP
1027 +
1028 +#ifdef CONFIG_ATH9K_WOW
1029 if (status & ATH9K_INT_BMISS) {
1030 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
1031 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
1032 @@ -588,6 +608,8 @@ irqreturn_t ath_isr(int irq, void *dev)
1033 }
1034 }
1035 #endif
1036 +
1037 +
1038 if (status & ATH9K_INT_SWBA)
1039 tasklet_schedule(&sc->bcon_tasklet);
1040
1041 @@ -627,7 +649,7 @@ chip_reset:
1042 #undef SCHED_INTR
1043 }
1044
1045 -static int ath_reset(struct ath_softc *sc)
1046 +int ath_reset(struct ath_softc *sc)
1047 {
1048 int r;
1049
1050 @@ -1817,13 +1839,31 @@ static void ath9k_set_coverage_class(str
1051 mutex_unlock(&sc->mutex);
1052 }
1053
1054 +static bool ath9k_has_tx_pending(struct ath_softc *sc)
1055 +{
1056 + int i, npend;
1057 +
1058 + for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1059 + if (!ATH_TXQ_SETUP(sc, i))
1060 + continue;
1061 +
1062 + if (!sc->tx.txq[i].axq_depth)
1063 + continue;
1064 +
1065 + npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1066 + if (npend)
1067 + break;
1068 + }
1069 +
1070 + return !!npend;
1071 +}
1072 +
1073 static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1074 {
1075 struct ath_softc *sc = hw->priv;
1076 struct ath_hw *ah = sc->sc_ah;
1077 struct ath_common *common = ath9k_hw_common(ah);
1078 - int timeout = 200; /* ms */
1079 - int i, j;
1080 + int timeout = HZ / 5; /* 200 ms */
1081 bool drain_txq;
1082
1083 mutex_lock(&sc->mutex);
1084 @@ -1841,25 +1881,9 @@ static void ath9k_flush(struct ieee80211
1085 return;
1086 }
1087
1088 - for (j = 0; j < timeout; j++) {
1089 - bool npend = false;
1090 -
1091 - if (j)
1092 - usleep_range(1000, 2000);
1093 -
1094 - for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1095 - if (!ATH_TXQ_SETUP(sc, i))
1096 - continue;
1097 -
1098 - npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1099 -
1100 - if (npend)
1101 - break;
1102 - }
1103 -
1104 - if (!npend)
1105 - break;
1106 - }
1107 + if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
1108 + timeout) > 0)
1109 + drop = false;
1110
1111 if (drop) {
1112 ath9k_ps_wakeup(sc);
1113 @@ -2021,333 +2045,6 @@ static int ath9k_get_antenna(struct ieee
1114 return 0;
1115 }
1116
1117 -#ifdef CONFIG_PM_SLEEP
1118 -
1119 -static void ath9k_wow_map_triggers(struct ath_softc *sc,
1120 - struct cfg80211_wowlan *wowlan,
1121 - u32 *wow_triggers)
1122 -{
1123 - if (wowlan->disconnect)
1124 - *wow_triggers |= AH_WOW_LINK_CHANGE |
1125 - AH_WOW_BEACON_MISS;
1126 - if (wowlan->magic_pkt)
1127 - *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
1128 -
1129 - if (wowlan->n_patterns)
1130 - *wow_triggers |= AH_WOW_USER_PATTERN_EN;
1131 -
1132 - sc->wow_enabled = *wow_triggers;
1133 -
1134 -}
1135 -
1136 -static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
1137 -{
1138 - struct ath_hw *ah = sc->sc_ah;
1139 - struct ath_common *common = ath9k_hw_common(ah);
1140 - int pattern_count = 0;
1141 - int i, byte_cnt;
1142 - u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
1143 - u8 dis_deauth_mask[MAX_PATTERN_SIZE];
1144 -
1145 - memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
1146 - memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
1147 -
1148 - /*
1149 - * Create Dissassociate / Deauthenticate packet filter
1150 - *
1151 - * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
1152 - * +--------------+----------+---------+--------+--------+----
1153 - * + Frame Control+ Duration + DA + SA + BSSID +
1154 - * +--------------+----------+---------+--------+--------+----
1155 - *
1156 - * The above is the management frame format for disassociate/
1157 - * deauthenticate pattern, from this we need to match the first byte
1158 - * of 'Frame Control' and DA, SA, and BSSID fields
1159 - * (skipping 2nd byte of FC and Duration feild.
1160 - *
1161 - * Disassociate pattern
1162 - * --------------------
1163 - * Frame control = 00 00 1010
1164 - * DA, SA, BSSID = x:x:x:x:x:x
1165 - * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
1166 - * | x:x:x:x:x:x -- 22 bytes
1167 - *
1168 - * Deauthenticate pattern
1169 - * ----------------------
1170 - * Frame control = 00 00 1100
1171 - * DA, SA, BSSID = x:x:x:x:x:x
1172 - * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
1173 - * | x:x:x:x:x:x -- 22 bytes
1174 - */
1175 -
1176 - /* Create Disassociate Pattern first */
1177 -
1178 - byte_cnt = 0;
1179 -
1180 - /* Fill out the mask with all FF's */
1181 -
1182 - for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
1183 - dis_deauth_mask[i] = 0xff;
1184 -
1185 - /* copy the first byte of frame control field */
1186 - dis_deauth_pattern[byte_cnt] = 0xa0;
1187 - byte_cnt++;
1188 -
1189 - /* skip 2nd byte of frame control and Duration field */
1190 - byte_cnt += 3;
1191 -
1192 - /*
1193 - * need not match the destination mac address, it can be a broadcast
1194 - * mac address or an unicast to this station
1195 - */
1196 - byte_cnt += 6;
1197 -
1198 - /* copy the source mac address */
1199 - memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
1200 -
1201 - byte_cnt += 6;
1202 -
1203 - /* copy the bssid, its same as the source mac address */
1204 -
1205 - memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
1206 -
1207 - /* Create Disassociate pattern mask */
1208 -
1209 - dis_deauth_mask[0] = 0xfe;
1210 - dis_deauth_mask[1] = 0x03;
1211 - dis_deauth_mask[2] = 0xc0;
1212 -
1213 - ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
1214 -
1215 - ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
1216 - pattern_count, byte_cnt);
1217 -
1218 - pattern_count++;
1219 - /*
1220 - * for de-authenticate pattern, only the first byte of the frame
1221 - * control field gets changed from 0xA0 to 0xC0
1222 - */
1223 - dis_deauth_pattern[0] = 0xC0;
1224 -
1225 - ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
1226 - pattern_count, byte_cnt);
1227 -
1228 -}
1229 -
1230 -static void ath9k_wow_add_pattern(struct ath_softc *sc,
1231 - struct cfg80211_wowlan *wowlan)
1232 -{
1233 - struct ath_hw *ah = sc->sc_ah;
1234 - struct ath9k_wow_pattern *wow_pattern = NULL;
1235 - struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
1236 - int mask_len;
1237 - s8 i = 0;
1238 -
1239 - if (!wowlan->n_patterns)
1240 - return;
1241 -
1242 - /*
1243 - * Add the new user configured patterns
1244 - */
1245 - for (i = 0; i < wowlan->n_patterns; i++) {
1246 -
1247 - wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
1248 -
1249 - if (!wow_pattern)
1250 - return;
1251 -
1252 - /*
1253 - * TODO: convert the generic user space pattern to
1254 - * appropriate chip specific/802.11 pattern.
1255 - */
1256 -
1257 - mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
1258 - memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
1259 - memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
1260 - memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
1261 - patterns[i].pattern_len);
1262 - memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
1263 - wow_pattern->pattern_len = patterns[i].pattern_len;
1264 -
1265 - /*
1266 - * just need to take care of deauth and disssoc pattern,
1267 - * make sure we don't overwrite them.
1268 - */
1269 -
1270 - ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
1271 - wow_pattern->mask_bytes,
1272 - i + 2,
1273 - wow_pattern->pattern_len);
1274 - kfree(wow_pattern);
1275 -
1276 - }
1277 -
1278 -}
1279 -
1280 -static int ath9k_suspend(struct ieee80211_hw *hw,
1281 - struct cfg80211_wowlan *wowlan)
1282 -{
1283 - struct ath_softc *sc = hw->priv;
1284 - struct ath_hw *ah = sc->sc_ah;
1285 - struct ath_common *common = ath9k_hw_common(ah);
1286 - u32 wow_triggers_enabled = 0;
1287 - int ret = 0;
1288 -
1289 - mutex_lock(&sc->mutex);
1290 -
1291 - ath_cancel_work(sc);
1292 - ath_stop_ani(sc);
1293 - del_timer_sync(&sc->rx_poll_timer);
1294 -
1295 - if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1296 - ath_dbg(common, ANY, "Device not present\n");
1297 - ret = -EINVAL;
1298 - goto fail_wow;
1299 - }
1300 -
1301 - if (WARN_ON(!wowlan)) {
1302 - ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
1303 - ret = -EINVAL;
1304 - goto fail_wow;
1305 - }
1306 -
1307 - if (!device_can_wakeup(sc->dev)) {
1308 - ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
1309 - ret = 1;
1310 - goto fail_wow;
1311 - }
1312 -
1313 - /*
1314 - * none of the sta vifs are associated
1315 - * and we are not currently handling multivif
1316 - * cases, for instance we have to seperately
1317 - * configure 'keep alive frame' for each
1318 - * STA.
1319 - */
1320 -
1321 - if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
1322 - ath_dbg(common, WOW, "None of the STA vifs are associated\n");
1323 - ret = 1;
1324 - goto fail_wow;
1325 - }
1326 -
1327 - if (sc->nvifs > 1) {
1328 - ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
1329 - ret = 1;
1330 - goto fail_wow;
1331 - }
1332 -
1333 - ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
1334 -
1335 - ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
1336 - wow_triggers_enabled);
1337 -
1338 - ath9k_ps_wakeup(sc);
1339 -
1340 - ath9k_stop_btcoex(sc);
1341 -
1342 - /*
1343 - * Enable wake up on recieving disassoc/deauth
1344 - * frame by default.
1345 - */
1346 - ath9k_wow_add_disassoc_deauth_pattern(sc);
1347 -
1348 - if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
1349 - ath9k_wow_add_pattern(sc, wowlan);
1350 -
1351 - spin_lock_bh(&sc->sc_pcu_lock);
1352 - /*
1353 - * To avoid false wake, we enable beacon miss interrupt only
1354 - * when we go to sleep. We save the current interrupt mask
1355 - * so we can restore it after the system wakes up
1356 - */
1357 - sc->wow_intr_before_sleep = ah->imask;
1358 - ah->imask &= ~ATH9K_INT_GLOBAL;
1359 - ath9k_hw_disable_interrupts(ah);
1360 - ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
1361 - ath9k_hw_set_interrupts(ah);
1362 - ath9k_hw_enable_interrupts(ah);
1363 -
1364 - spin_unlock_bh(&sc->sc_pcu_lock);
1365 -
1366 - /*
1367 - * we can now sync irq and kill any running tasklets, since we already
1368 - * disabled interrupts and not holding a spin lock
1369 - */
1370 - synchronize_irq(sc->irq);
1371 - tasklet_kill(&sc->intr_tq);
1372 -
1373 - ath9k_hw_wow_enable(ah, wow_triggers_enabled);
1374 -
1375 - ath9k_ps_restore(sc);
1376 - ath_dbg(common, ANY, "WoW enabled in ath9k\n");
1377 - atomic_inc(&sc->wow_sleep_proc_intr);
1378 -
1379 -fail_wow:
1380 - mutex_unlock(&sc->mutex);
1381 - return ret;
1382 -}
1383 -
1384 -static int ath9k_resume(struct ieee80211_hw *hw)
1385 -{
1386 - struct ath_softc *sc = hw->priv;
1387 - struct ath_hw *ah = sc->sc_ah;
1388 - struct ath_common *common = ath9k_hw_common(ah);
1389 - u32 wow_status;
1390 -
1391 - mutex_lock(&sc->mutex);
1392 -
1393 - ath9k_ps_wakeup(sc);
1394 -
1395 - spin_lock_bh(&sc->sc_pcu_lock);
1396 -
1397 - ath9k_hw_disable_interrupts(ah);
1398 - ah->imask = sc->wow_intr_before_sleep;
1399 - ath9k_hw_set_interrupts(ah);
1400 - ath9k_hw_enable_interrupts(ah);
1401 -
1402 - spin_unlock_bh(&sc->sc_pcu_lock);
1403 -
1404 - wow_status = ath9k_hw_wow_wakeup(ah);
1405 -
1406 - if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
1407 - /*
1408 - * some devices may not pick beacon miss
1409 - * as the reason they woke up so we add
1410 - * that here for that shortcoming.
1411 - */
1412 - wow_status |= AH_WOW_BEACON_MISS;
1413 - atomic_dec(&sc->wow_got_bmiss_intr);
1414 - ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
1415 - }
1416 -
1417 - atomic_dec(&sc->wow_sleep_proc_intr);
1418 -
1419 - if (wow_status) {
1420 - ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
1421 - ath9k_hw_wow_event_to_string(wow_status), wow_status);
1422 - }
1423 -
1424 - ath_restart_work(sc);
1425 - ath9k_start_btcoex(sc);
1426 -
1427 - ath9k_ps_restore(sc);
1428 - mutex_unlock(&sc->mutex);
1429 -
1430 - return 0;
1431 -}
1432 -
1433 -static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
1434 -{
1435 - struct ath_softc *sc = hw->priv;
1436 -
1437 - mutex_lock(&sc->mutex);
1438 - device_init_wakeup(sc->dev, 1);
1439 - device_set_wakeup_enable(sc->dev, enabled);
1440 - mutex_unlock(&sc->mutex);
1441 -}
1442 -
1443 -#endif
1444 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
1445 {
1446 struct ath_softc *sc = hw->priv;
1447 @@ -2373,134 +2070,6 @@ static void ath9k_channel_switch_beacon(
1448 sc->csa_vif = vif;
1449 }
1450
1451 -static void ath9k_tx99_stop(struct ath_softc *sc)
1452 -{
1453 - struct ath_hw *ah = sc->sc_ah;
1454 - struct ath_common *common = ath9k_hw_common(ah);
1455 -
1456 - ath_drain_all_txq(sc);
1457 - ath_startrecv(sc);
1458 -
1459 - ath9k_hw_set_interrupts(ah);
1460 - ath9k_hw_enable_interrupts(ah);
1461 -
1462 - ieee80211_wake_queues(sc->hw);
1463 -
1464 - kfree_skb(sc->tx99_skb);
1465 - sc->tx99_skb = NULL;
1466 - sc->tx99_state = false;
1467 -
1468 - ath9k_hw_tx99_stop(sc->sc_ah);
1469 - ath_dbg(common, XMIT, "TX99 stopped\n");
1470 -}
1471 -
1472 -static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
1473 -{
1474 - static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
1475 - 0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
1476 - 0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
1477 - 0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
1478 - 0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
1479 - 0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
1480 - 0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
1481 - 0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
1482 - u32 len = 1200;
1483 - struct ieee80211_hw *hw = sc->hw;
1484 - struct ieee80211_hdr *hdr;
1485 - struct ieee80211_tx_info *tx_info;
1486 - struct sk_buff *skb;
1487 -
1488 - skb = alloc_skb(len, GFP_KERNEL);
1489 - if (!skb)
1490 - return NULL;
1491 -
1492 - skb_put(skb, len);
1493 -
1494 - memset(skb->data, 0, len);
1495 -
1496 - hdr = (struct ieee80211_hdr *)skb->data;
1497 - hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
1498 - hdr->duration_id = 0;
1499 -
1500 - memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
1501 - memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
1502 - memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
1503 -
1504 - hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1505 -
1506 - tx_info = IEEE80211_SKB_CB(skb);
1507 - memset(tx_info, 0, sizeof(*tx_info));
1508 - tx_info->band = hw->conf.chandef.chan->band;
1509 - tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
1510 - tx_info->control.vif = sc->tx99_vif;
1511 -
1512 - memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
1513 -
1514 - return skb;
1515 -}
1516 -
1517 -void ath9k_tx99_deinit(struct ath_softc *sc)
1518 -{
1519 - ath_reset(sc);
1520 -
1521 - ath9k_ps_wakeup(sc);
1522 - ath9k_tx99_stop(sc);
1523 - ath9k_ps_restore(sc);
1524 -}
1525 -
1526 -int ath9k_tx99_init(struct ath_softc *sc)
1527 -{
1528 - struct ieee80211_hw *hw = sc->hw;
1529 - struct ath_hw *ah = sc->sc_ah;
1530 - struct ath_common *common = ath9k_hw_common(ah);
1531 - struct ath_tx_control txctl;
1532 - int r;
1533 -
1534 - if (sc->sc_flags & SC_OP_INVALID) {
1535 - ath_err(common,
1536 - "driver is in invalid state unable to use TX99");
1537 - return -EINVAL;
1538 - }
1539 -
1540 - sc->tx99_skb = ath9k_build_tx99_skb(sc);
1541 - if (!sc->tx99_skb)
1542 - return -ENOMEM;
1543 -
1544 - memset(&txctl, 0, sizeof(txctl));
1545 - txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
1546 -
1547 - ath_reset(sc);
1548 -
1549 - ath9k_ps_wakeup(sc);
1550 -
1551 - ath9k_hw_disable_interrupts(ah);
1552 - atomic_set(&ah->intr_ref_cnt, -1);
1553 - ath_drain_all_txq(sc);
1554 - ath_stoprecv(sc);
1555 -
1556 - sc->tx99_state = true;
1557 -
1558 - ieee80211_stop_queues(hw);
1559 -
1560 - if (sc->tx99_power == MAX_RATE_POWER + 1)
1561 - sc->tx99_power = MAX_RATE_POWER;
1562 -
1563 - ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
1564 - r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
1565 - if (r) {
1566 - ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
1567 - return r;
1568 - }
1569 -
1570 - ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
1571 - sc->tx99_power,
1572 - sc->tx99_power / 2);
1573 -
1574 - /* We leave the harware awake as it will be chugging on */
1575 -
1576 - return 0;
1577 -}
1578 -
1579 struct ieee80211_ops ath9k_ops = {
1580 .tx = ath9k_tx,
1581 .start = ath9k_start,
1582 @@ -2531,7 +2100,7 @@ struct ieee80211_ops ath9k_ops = {
1583 .set_antenna = ath9k_set_antenna,
1584 .get_antenna = ath9k_get_antenna,
1585
1586 -#ifdef CONFIG_PM_SLEEP
1587 +#ifdef CONFIG_ATH9K_WOW
1588 .suspend = ath9k_suspend,
1589 .resume = ath9k_resume,
1590 .set_wakeup = ath9k_set_wakeup,
1591 --- a/drivers/net/wireless/ath/ath9k/wow.c
1592 +++ b/drivers/net/wireless/ath/ath9k/wow.c
1593 @@ -1,5 +1,5 @@
1594 /*
1595 - * Copyright (c) 2012 Qualcomm Atheros, Inc.
1596 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
1597 *
1598 * Permission to use, copy, modify, and/or distribute this software for any
1599 * purpose with or without fee is hereby granted, provided that the above
1600 @@ -14,409 +14,348 @@
1601 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1602 */
1603
1604 -#include <linux/export.h>
1605 #include "ath9k.h"
1606 -#include "reg.h"
1607 -#include "hw-ops.h"
1608
1609 -const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1610 +static const struct wiphy_wowlan_support ath9k_wowlan_support = {
1611 + .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
1612 + .n_patterns = MAX_NUM_USER_PATTERN,
1613 + .pattern_min_len = 1,
1614 + .pattern_max_len = MAX_PATTERN_SIZE,
1615 +};
1616 +
1617 +static void ath9k_wow_map_triggers(struct ath_softc *sc,
1618 + struct cfg80211_wowlan *wowlan,
1619 + u32 *wow_triggers)
1620 {
1621 - if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
1622 - return "Magic pattern";
1623 - if (wow_event & AH_WOW_USER_PATTERN_EN)
1624 - return "User pattern";
1625 - if (wow_event & AH_WOW_LINK_CHANGE)
1626 - return "Link change";
1627 - if (wow_event & AH_WOW_BEACON_MISS)
1628 - return "Beacon miss";
1629 + if (wowlan->disconnect)
1630 + *wow_triggers |= AH_WOW_LINK_CHANGE |
1631 + AH_WOW_BEACON_MISS;
1632 + if (wowlan->magic_pkt)
1633 + *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
1634 +
1635 + if (wowlan->n_patterns)
1636 + *wow_triggers |= AH_WOW_USER_PATTERN_EN;
1637 +
1638 + sc->wow_enabled = *wow_triggers;
1639
1640 - return "unknown reason";
1641 }
1642 -EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
1643
1644 -static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
1645 +static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
1646 {
1647 + struct ath_hw *ah = sc->sc_ah;
1648 struct ath_common *common = ath9k_hw_common(ah);
1649 + int pattern_count = 0;
1650 + int i, byte_cnt;
1651 + u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
1652 + u8 dis_deauth_mask[MAX_PATTERN_SIZE];
1653
1654 - REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1655 + memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
1656 + memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
1657
1658 - /* set rx disable bit */
1659 - REG_WRITE(ah, AR_CR, AR_CR_RXD);
1660 + /*
1661 + * Create Dissassociate / Deauthenticate packet filter
1662 + *
1663 + * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
1664 + * +--------------+----------+---------+--------+--------+----
1665 + * + Frame Control+ Duration + DA + SA + BSSID +
1666 + * +--------------+----------+---------+--------+--------+----
1667 + *
1668 + * The above is the management frame format for disassociate/
1669 + * deauthenticate pattern, from this we need to match the first byte
1670 + * of 'Frame Control' and DA, SA, and BSSID fields
1671 + * (skipping 2nd byte of FC and Duration feild.
1672 + *
1673 + * Disassociate pattern
1674 + * --------------------
1675 + * Frame control = 00 00 1010
1676 + * DA, SA, BSSID = x:x:x:x:x:x
1677 + * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
1678 + * | x:x:x:x:x:x -- 22 bytes
1679 + *
1680 + * Deauthenticate pattern
1681 + * ----------------------
1682 + * Frame control = 00 00 1100
1683 + * DA, SA, BSSID = x:x:x:x:x:x
1684 + * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
1685 + * | x:x:x:x:x:x -- 22 bytes
1686 + */
1687
1688 - if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
1689 - ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
1690 - REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
1691 - return;
1692 - }
1693 + /* Create Disassociate Pattern first */
1694
1695 - REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
1696 -}
1697 + byte_cnt = 0;
1698
1699 -static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
1700 -{
1701 - struct ath_common *common = ath9k_hw_common(ah);
1702 - u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
1703 - u32 ctl[13] = {0};
1704 - u32 data_word[KAL_NUM_DATA_WORDS];
1705 - u8 i;
1706 - u32 wow_ka_data_word0;
1707 -
1708 - memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
1709 - memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
1710 -
1711 - /* set the transmit buffer */
1712 - ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
1713 - ctl[1] = 0;
1714 - ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */
1715 - ctl[4] = 0;
1716 - ctl[7] = (ah->txchainmask) << 2;
1717 - ctl[2] = 0xf << 16; /* tx_tries 0 */
1718 -
1719 - for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
1720 - REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
1721 -
1722 - REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
1723 -
1724 - data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
1725 - (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
1726 - data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
1727 - (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
1728 - data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
1729 - (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
1730 - data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
1731 - (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
1732 - data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
1733 - (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
1734 - data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
1735 -
1736 - if (AR_SREV_9462_20(ah)) {
1737 - /* AR9462 2.0 has an extra descriptor word (time based
1738 - * discard) compared to other chips */
1739 - REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
1740 - wow_ka_data_word0 = AR_WOW_TXBUF(13);
1741 - } else {
1742 - wow_ka_data_word0 = AR_WOW_TXBUF(12);
1743 - }
1744 + /* Fill out the mask with all FF's */
1745
1746 - for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
1747 - REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
1748 + for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
1749 + dis_deauth_mask[i] = 0xff;
1750
1751 -}
1752 + /* copy the first byte of frame control field */
1753 + dis_deauth_pattern[byte_cnt] = 0xa0;
1754 + byte_cnt++;
1755
1756 -void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1757 - u8 *user_mask, int pattern_count,
1758 - int pattern_len)
1759 -{
1760 - int i;
1761 - u32 pattern_val, mask_val;
1762 - u32 set, clr;
1763 + /* skip 2nd byte of frame control and Duration field */
1764 + byte_cnt += 3;
1765
1766 - /* FIXME: should check count by querying the hardware capability */
1767 - if (pattern_count >= MAX_NUM_PATTERN)
1768 - return;
1769 + /*
1770 + * need not match the destination mac address, it can be a broadcast
1771 + * mac address or an unicast to this station
1772 + */
1773 + byte_cnt += 6;
1774
1775 - REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
1776 + /* copy the source mac address */
1777 + memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
1778
1779 - /* set the registers for pattern */
1780 - for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
1781 - memcpy(&pattern_val, user_pattern, 4);
1782 - REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
1783 - pattern_val);
1784 - user_pattern += 4;
1785 - }
1786 + byte_cnt += 6;
1787
1788 - /* set the registers for mask */
1789 - for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
1790 - memcpy(&mask_val, user_mask, 4);
1791 - REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
1792 - user_mask += 4;
1793 - }
1794 + /* copy the bssid, its same as the source mac address */
1795
1796 - /* set the pattern length to be matched
1797 - *
1798 - * AR_WOW_LENGTH1_REG1
1799 - * bit 31:24 pattern 0 length
1800 - * bit 23:16 pattern 1 length
1801 - * bit 15:8 pattern 2 length
1802 - * bit 7:0 pattern 3 length
1803 - *
1804 - * AR_WOW_LENGTH1_REG2
1805 - * bit 31:24 pattern 4 length
1806 - * bit 23:16 pattern 5 length
1807 - * bit 15:8 pattern 6 length
1808 - * bit 7:0 pattern 7 length
1809 - *
1810 - * the below logic writes out the new
1811 - * pattern length for the corresponding
1812 - * pattern_count, while masking out the
1813 - * other fields
1814 - */
1815 + memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
1816
1817 - ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
1818 + /* Create Disassociate pattern mask */
1819
1820 - if (pattern_count < 4) {
1821 - /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
1822 - set = (pattern_len & AR_WOW_LENGTH_MAX) <<
1823 - AR_WOW_LEN1_SHIFT(pattern_count);
1824 - clr = AR_WOW_LENGTH1_MASK(pattern_count);
1825 - REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
1826 - } else {
1827 - /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
1828 - set = (pattern_len & AR_WOW_LENGTH_MAX) <<
1829 - AR_WOW_LEN2_SHIFT(pattern_count);
1830 - clr = AR_WOW_LENGTH2_MASK(pattern_count);
1831 - REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
1832 - }
1833 + dis_deauth_mask[0] = 0xfe;
1834 + dis_deauth_mask[1] = 0x03;
1835 + dis_deauth_mask[2] = 0xc0;
1836
1837 -}
1838 -EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
1839 + ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
1840
1841 -u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1842 -{
1843 - u32 wow_status = 0;
1844 - u32 val = 0, rval;
1845 + ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
1846 + pattern_count, byte_cnt);
1847
1848 + pattern_count++;
1849 /*
1850 - * read the WoW status register to know
1851 - * the wakeup reason
1852 + * for de-authenticate pattern, only the first byte of the frame
1853 + * control field gets changed from 0xA0 to 0xC0
1854 */
1855 - rval = REG_READ(ah, AR_WOW_PATTERN);
1856 - val = AR_WOW_STATUS(rval);
1857 + dis_deauth_pattern[0] = 0xC0;
1858
1859 - /*
1860 - * mask only the WoW events that we have enabled. Sometimes
1861 - * we have spurious WoW events from the AR_WOW_PATTERN
1862 - * register. This mask will clean it up.
1863 - */
1864 + ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
1865 + pattern_count, byte_cnt);
1866
1867 - val &= ah->wow_event_mask;
1868 +}
1869
1870 - if (val) {
1871 - if (val & AR_WOW_MAGIC_PAT_FOUND)
1872 - wow_status |= AH_WOW_MAGIC_PATTERN_EN;
1873 - if (AR_WOW_PATTERN_FOUND(val))
1874 - wow_status |= AH_WOW_USER_PATTERN_EN;
1875 - if (val & AR_WOW_KEEP_ALIVE_FAIL)
1876 - wow_status |= AH_WOW_LINK_CHANGE;
1877 - if (val & AR_WOW_BEACON_FAIL)
1878 - wow_status |= AH_WOW_BEACON_MISS;
1879 - }
1880 +static void ath9k_wow_add_pattern(struct ath_softc *sc,
1881 + struct cfg80211_wowlan *wowlan)
1882 +{
1883 + struct ath_hw *ah = sc->sc_ah;
1884 + struct ath9k_wow_pattern *wow_pattern = NULL;
1885 + struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
1886 + int mask_len;
1887 + s8 i = 0;
1888 +
1889 + if (!wowlan->n_patterns)
1890 + return;
1891
1892 /*
1893 - * set and clear WOW_PME_CLEAR registers for the chip to
1894 - * generate next wow signal.
1895 - * disable D3 before accessing other registers ?
1896 + * Add the new user configured patterns
1897 */
1898 + for (i = 0; i < wowlan->n_patterns; i++) {
1899
1900 - /* do we need to check the bit value 0x01000000 (7-10) ?? */
1901 - REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
1902 - AR_PMCTRL_PWR_STATE_D1D3);
1903 + wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
1904
1905 - /*
1906 - * clear all events
1907 - */
1908 - REG_WRITE(ah, AR_WOW_PATTERN,
1909 - AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
1910 + if (!wow_pattern)
1911 + return;
1912
1913 - /*
1914 - * restore the beacon threshold to init value
1915 - */
1916 - REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1917 + /*
1918 + * TODO: convert the generic user space pattern to
1919 + * appropriate chip specific/802.11 pattern.
1920 + */
1921
1922 - /*
1923 - * Restore the way the PCI-E reset, Power-On-Reset, external
1924 - * PCIE_POR_SHORT pins are tied to its original value.
1925 - * Previously just before WoW sleep, we untie the PCI-E
1926 - * reset to our Chip's Power On Reset so that any PCI-E
1927 - * reset from the bus will not reset our chip
1928 - */
1929 - if (ah->is_pciexpress)
1930 - ath9k_hw_configpcipowersave(ah, false);
1931 + mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
1932 + memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
1933 + memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
1934 + memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
1935 + patterns[i].pattern_len);
1936 + memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
1937 + wow_pattern->pattern_len = patterns[i].pattern_len;
1938 +
1939 + /*
1940 + * just need to take care of deauth and disssoc pattern,
1941 + * make sure we don't overwrite them.
1942 + */
1943 +
1944 + ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
1945 + wow_pattern->mask_bytes,
1946 + i + 2,
1947 + wow_pattern->pattern_len);
1948 + kfree(wow_pattern);
1949
1950 - ah->wow_event_mask = 0;
1951 + }
1952
1953 - return wow_status;
1954 }
1955 -EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
1956
1957 -void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1958 +int ath9k_suspend(struct ieee80211_hw *hw,
1959 + struct cfg80211_wowlan *wowlan)
1960 {
1961 - u32 wow_event_mask;
1962 - u32 set, clr;
1963 + struct ath_softc *sc = hw->priv;
1964 + struct ath_hw *ah = sc->sc_ah;
1965 + struct ath_common *common = ath9k_hw_common(ah);
1966 + u32 wow_triggers_enabled = 0;
1967 + int ret = 0;
1968
1969 - /*
1970 - * wow_event_mask is a mask to the AR_WOW_PATTERN register to
1971 - * indicate which WoW events we have enabled. The WoW events
1972 - * are from the 'pattern_enable' in this function and
1973 - * 'pattern_count' of ath9k_hw_wow_apply_pattern()
1974 - */
1975 - wow_event_mask = ah->wow_event_mask;
1976 + mutex_lock(&sc->mutex);
1977
1978 - /*
1979 - * Untie Power-on-Reset from the PCI-E-Reset. When we are in
1980 - * WOW sleep, we do want the Reset from the PCI-E to disturb
1981 - * our hw state
1982 - */
1983 - if (ah->is_pciexpress) {
1984 - /*
1985 - * we need to untie the internal POR (power-on-reset)
1986 - * to the external PCI-E reset. We also need to tie
1987 - * the PCI-E Phy reset to the PCI-E reset.
1988 - */
1989 - set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
1990 - clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
1991 - REG_RMW(ah, AR_WA, set, clr);
1992 + ath_cancel_work(sc);
1993 + ath_stop_ani(sc);
1994 + del_timer_sync(&sc->rx_poll_timer);
1995 +
1996 + if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1997 + ath_dbg(common, ANY, "Device not present\n");
1998 + ret = -EINVAL;
1999 + goto fail_wow;
2000 }
2001
2002 - /*
2003 - * set the power states appropriately and enable PME
2004 - */
2005 - set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
2006 - AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
2007 + if (WARN_ON(!wowlan)) {
2008 + ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2009 + ret = -EINVAL;
2010 + goto fail_wow;
2011 + }
2012
2013 - /*
2014 - * set and clear WOW_PME_CLEAR registers for the chip
2015 - * to generate next wow signal.
2016 - */
2017 - REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
2018 - clr = AR_PMCTRL_WOW_PME_CLR;
2019 - REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
2020 + if (!device_can_wakeup(sc->dev)) {
2021 + ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2022 + ret = 1;
2023 + goto fail_wow;
2024 + }
2025
2026 /*
2027 - * Setup for:
2028 - * - beacon misses
2029 - * - magic pattern
2030 - * - keep alive timeout
2031 - * - pattern matching
2032 + * none of the sta vifs are associated
2033 + * and we are not currently handling multivif
2034 + * cases, for instance we have to seperately
2035 + * configure 'keep alive frame' for each
2036 + * STA.
2037 */
2038
2039 - /*
2040 - * Program default values for pattern backoff, aifs/slot/KAL count,
2041 - * beacon miss timeout, KAL timeout, etc.
2042 - */
2043 - set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
2044 - REG_SET_BIT(ah, AR_WOW_PATTERN, set);
2045 + if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2046 + ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2047 + ret = 1;
2048 + goto fail_wow;
2049 + }
2050 +
2051 + if (sc->nvifs > 1) {
2052 + ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2053 + ret = 1;
2054 + goto fail_wow;
2055 + }
2056
2057 - set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
2058 - AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
2059 - AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
2060 - REG_SET_BIT(ah, AR_WOW_COUNT, set);
2061 -
2062 - if (pattern_enable & AH_WOW_BEACON_MISS)
2063 - set = AR_WOW_BEACON_TIMO;
2064 - /* We are not using beacon miss, program a large value */
2065 - else
2066 - set = AR_WOW_BEACON_TIMO_MAX;
2067 + ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2068
2069 - REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
2070 + ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2071 + wow_triggers_enabled);
2072
2073 - /*
2074 - * Keep alive timo in ms except AR9280
2075 - */
2076 - if (!pattern_enable)
2077 - set = AR_WOW_KEEP_ALIVE_NEVER;
2078 - else
2079 - set = KAL_TIMEOUT * 32;
2080 + ath9k_ps_wakeup(sc);
2081
2082 - REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
2083 + ath9k_stop_btcoex(sc);
2084
2085 /*
2086 - * Keep alive delay in us. based on 'power on clock',
2087 - * therefore in usec
2088 + * Enable wake up on recieving disassoc/deauth
2089 + * frame by default.
2090 */
2091 - set = KAL_DELAY * 1000;
2092 - REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
2093 + ath9k_wow_add_disassoc_deauth_pattern(sc);
2094
2095 - /*
2096 - * Create keep alive pattern to respond to beacons
2097 - */
2098 - ath9k_wow_create_keep_alive_pattern(ah);
2099 + if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2100 + ath9k_wow_add_pattern(sc, wowlan);
2101
2102 + spin_lock_bh(&sc->sc_pcu_lock);
2103 /*
2104 - * Configure MAC WoW Registers
2105 + * To avoid false wake, we enable beacon miss interrupt only
2106 + * when we go to sleep. We save the current interrupt mask
2107 + * so we can restore it after the system wakes up
2108 */
2109 - set = 0;
2110 - /* Send keep alive timeouts anyway */
2111 - clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
2112 -
2113 - if (pattern_enable & AH_WOW_LINK_CHANGE)
2114 - wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
2115 - else
2116 - set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
2117 + sc->wow_intr_before_sleep = ah->imask;
2118 + ah->imask &= ~ATH9K_INT_GLOBAL;
2119 + ath9k_hw_disable_interrupts(ah);
2120 + ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2121 + ath9k_hw_set_interrupts(ah);
2122 + ath9k_hw_enable_interrupts(ah);
2123
2124 - set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
2125 - REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
2126 + spin_unlock_bh(&sc->sc_pcu_lock);
2127
2128 /*
2129 - * we are relying on a bmiss failure. ensure we have
2130 - * enough threshold to prevent false positives
2131 + * we can now sync irq and kill any running tasklets, since we already
2132 + * disabled interrupts and not holding a spin lock
2133 */
2134 - REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
2135 - AR_WOW_BMISSTHRESHOLD);
2136 + synchronize_irq(sc->irq);
2137 + tasklet_kill(&sc->intr_tq);
2138 +
2139 + ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2140
2141 - set = 0;
2142 - clr = 0;
2143 + ath9k_ps_restore(sc);
2144 + ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2145 + atomic_inc(&sc->wow_sleep_proc_intr);
2146
2147 - if (pattern_enable & AH_WOW_BEACON_MISS) {
2148 - set = AR_WOW_BEACON_FAIL_EN;
2149 - wow_event_mask |= AR_WOW_BEACON_FAIL;
2150 - } else {
2151 - clr = AR_WOW_BEACON_FAIL_EN;
2152 +fail_wow:
2153 + mutex_unlock(&sc->mutex);
2154 + return ret;
2155 +}
2156 +
2157 +int ath9k_resume(struct ieee80211_hw *hw)
2158 +{
2159 + struct ath_softc *sc = hw->priv;
2160 + struct ath_hw *ah = sc->sc_ah;
2161 + struct ath_common *common = ath9k_hw_common(ah);
2162 + u32 wow_status;
2163 +
2164 + mutex_lock(&sc->mutex);
2165 +
2166 + ath9k_ps_wakeup(sc);
2167 +
2168 + spin_lock_bh(&sc->sc_pcu_lock);
2169 +
2170 + ath9k_hw_disable_interrupts(ah);
2171 + ah->imask = sc->wow_intr_before_sleep;
2172 + ath9k_hw_set_interrupts(ah);
2173 + ath9k_hw_enable_interrupts(ah);
2174 +
2175 + spin_unlock_bh(&sc->sc_pcu_lock);
2176 +
2177 + wow_status = ath9k_hw_wow_wakeup(ah);
2178 +
2179 + if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2180 + /*
2181 + * some devices may not pick beacon miss
2182 + * as the reason they woke up so we add
2183 + * that here for that shortcoming.
2184 + */
2185 + wow_status |= AH_WOW_BEACON_MISS;
2186 + atomic_dec(&sc->wow_got_bmiss_intr);
2187 + ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2188 }
2189
2190 - REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
2191 + atomic_dec(&sc->wow_sleep_proc_intr);
2192
2193 - set = 0;
2194 - clr = 0;
2195 - /*
2196 - * Enable the magic packet registers
2197 - */
2198 - if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
2199 - set = AR_WOW_MAGIC_EN;
2200 - wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
2201 - } else {
2202 - clr = AR_WOW_MAGIC_EN;
2203 + if (wow_status) {
2204 + ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2205 + ath9k_hw_wow_event_to_string(wow_status), wow_status);
2206 }
2207 - set |= AR_WOW_MAC_INTR_EN;
2208 - REG_RMW(ah, AR_WOW_PATTERN, set, clr);
2209
2210 - REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
2211 - AR_WOW_PATTERN_SUPPORTED);
2212 + ath_restart_work(sc);
2213 + ath9k_start_btcoex(sc);
2214
2215 - /*
2216 - * Set the power states appropriately and enable PME
2217 - */
2218 - clr = 0;
2219 - set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
2220 - AR_PMCTRL_PWR_PM_CTRL_ENA;
2221 + ath9k_ps_restore(sc);
2222 + mutex_unlock(&sc->mutex);
2223
2224 - clr = AR_PCIE_PM_CTRL_ENA;
2225 - REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
2226 + return 0;
2227 +}
2228
2229 - /*
2230 - * this is needed to prevent the chip waking up
2231 - * the host within 3-4 seconds with certain
2232 - * platform/BIOS. The fix is to enable
2233 - * D1 & D3 to match original definition and
2234 - * also match the OTP value. Anyway this
2235 - * is more related to SW WOW.
2236 - */
2237 - clr = AR_PMCTRL_PWR_STATE_D1D3;
2238 - REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
2239 +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2240 +{
2241 + struct ath_softc *sc = hw->priv;
2242
2243 - set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
2244 - REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
2245 + mutex_lock(&sc->mutex);
2246 + device_init_wakeup(sc->dev, 1);
2247 + device_set_wakeup_enable(sc->dev, enabled);
2248 + mutex_unlock(&sc->mutex);
2249 +}
2250
2251 - REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2252 +void ath9k_init_wow(struct ieee80211_hw *hw)
2253 +{
2254 + struct ath_softc *sc = hw->priv;
2255
2256 - /* to bring down WOW power low margin */
2257 - set = BIT(13);
2258 - REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
2259 - /* HW WoW */
2260 - clr = BIT(5);
2261 - REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
2262 + if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
2263 + (sc->driver_data & ATH9K_PCI_WOW) &&
2264 + device_can_wakeup(sc->dev))
2265 + hw->wiphy->wowlan = &ath9k_wowlan_support;
2266
2267 - ath9k_hw_set_powermode_wow_sleep(ah);
2268 - ah->wow_event_mask = wow_event_mask;
2269 + atomic_set(&sc->wow_sleep_proc_intr, -1);
2270 + atomic_set(&sc->wow_got_bmiss_intr, -1);
2271 }
2272 -EXPORT_SYMBOL(ath9k_hw_wow_enable);
2273 --- a/drivers/net/wireless/ath/ath9k/xmit.c
2274 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
2275 @@ -1786,6 +1786,9 @@ bool ath_drain_all_txq(struct ath_softc
2276 if (!ATH_TXQ_SETUP(sc, i))
2277 continue;
2278
2279 + if (!sc->tx.txq[i].axq_depth)
2280 + continue;
2281 +
2282 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
2283 npend |= BIT(i);
2284 }
2285 @@ -2749,6 +2752,8 @@ void ath_tx_node_cleanup(struct ath_soft
2286 }
2287 }
2288
2289 +#ifdef CONFIG_ATH9K_TX99
2290 +
2291 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2292 struct ath_tx_control *txctl)
2293 {
2294 @@ -2791,3 +2796,5 @@ int ath9k_tx99_send(struct ath_softc *sc
2295
2296 return 0;
2297 }
2298 +
2299 +#endif /* CONFIG_ATH9K_TX99 */
2300 --- a/drivers/net/wireless/ath/regd.c
2301 +++ b/drivers/net/wireless/ath/regd.c
2302 @@ -37,17 +37,17 @@ static int __ath_regd_init(struct ath_re
2303
2304 /* We enable active scan on these a case by case basis by regulatory domain */
2305 #define ATH9K_2GHZ_CH12_13 REG_RULE(2467-10, 2472+10, 40, 0, 20,\
2306 - NL80211_RRF_PASSIVE_SCAN)
2307 + NL80211_RRF_NO_IR)
2308 #define ATH9K_2GHZ_CH14 REG_RULE(2484-10, 2484+10, 40, 0, 20,\
2309 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
2310 + NL80211_RRF_NO_IR | NL80211_RRF_NO_OFDM)
2311
2312 /* We allow IBSS on these on a case by case basis by regulatory domain */
2313 #define ATH9K_5GHZ_5150_5350 REG_RULE(5150-10, 5350+10, 80, 0, 30,\
2314 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
2315 + NL80211_RRF_NO_IR)
2316 #define ATH9K_5GHZ_5470_5850 REG_RULE(5470-10, 5850+10, 80, 0, 30,\
2317 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
2318 + NL80211_RRF_NO_IR)
2319 #define ATH9K_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 80, 0, 30,\
2320 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
2321 + NL80211_RRF_NO_IR)
2322
2323 #define ATH9K_2GHZ_ALL ATH9K_2GHZ_CH01_11, \
2324 ATH9K_2GHZ_CH12_13, \
2325 @@ -224,17 +224,16 @@ ath_reg_apply_beaconing_flags(struct wip
2326 * regulatory_hint().
2327 */
2328 if (!(reg_rule->flags &
2329 - NL80211_RRF_NO_IBSS))
2330 + NL80211_RRF_NO_IR))
2331 ch->flags &=
2332 - ~IEEE80211_CHAN_NO_IBSS;
2333 + ~IEEE80211_CHAN_NO_IR;
2334 if (!(reg_rule->flags &
2335 - NL80211_RRF_PASSIVE_SCAN))
2336 + NL80211_RRF_NO_IR))
2337 ch->flags &=
2338 - ~IEEE80211_CHAN_PASSIVE_SCAN;
2339 + ~IEEE80211_CHAN_NO_IR;
2340 } else {
2341 if (ch->beacon_found)
2342 - ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
2343 - IEEE80211_CHAN_PASSIVE_SCAN);
2344 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
2345 }
2346 }
2347 }
2348 @@ -260,11 +259,11 @@ ath_reg_apply_active_scan_flags(struct w
2349 */
2350 if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
2351 ch = &sband->channels[11]; /* CH 12 */
2352 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
2353 - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
2354 + if (ch->flags & IEEE80211_CHAN_NO_IR)
2355 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
2356 ch = &sband->channels[12]; /* CH 13 */
2357 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
2358 - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
2359 + if (ch->flags & IEEE80211_CHAN_NO_IR)
2360 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
2361 return;
2362 }
2363
2364 @@ -278,17 +277,17 @@ ath_reg_apply_active_scan_flags(struct w
2365 ch = &sband->channels[11]; /* CH 12 */
2366 reg_rule = freq_reg_info(wiphy, ch->center_freq);
2367 if (!IS_ERR(reg_rule)) {
2368 - if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
2369 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
2370 - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
2371 + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
2372 + if (ch->flags & IEEE80211_CHAN_NO_IR)
2373 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
2374 }
2375
2376 ch = &sband->channels[12]; /* CH 13 */
2377 reg_rule = freq_reg_info(wiphy, ch->center_freq);
2378 if (!IS_ERR(reg_rule)) {
2379 - if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
2380 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
2381 - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
2382 + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
2383 + if (ch->flags & IEEE80211_CHAN_NO_IR)
2384 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
2385 }
2386 }
2387
2388 @@ -320,8 +319,8 @@ static void ath_reg_apply_radar_flags(st
2389 */
2390 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
2391 ch->flags |= IEEE80211_CHAN_RADAR |
2392 - IEEE80211_CHAN_NO_IBSS |
2393 - IEEE80211_CHAN_PASSIVE_SCAN;
2394 + IEEE80211_CHAN_NO_IR |
2395 + IEEE80211_CHAN_NO_IR;
2396 }
2397 }
2398
2399 --- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
2400 +++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
2401 @@ -812,7 +812,7 @@ static s32 brcmf_p2p_run_escan(struct br
2402 struct ieee80211_channel *chan = request->channels[i];
2403
2404 if (chan->flags & (IEEE80211_CHAN_RADAR |
2405 - IEEE80211_CHAN_PASSIVE_SCAN))
2406 + IEEE80211_CHAN_NO_IR))
2407 continue;
2408
2409 chanspecs[i] = channel_to_chanspec(&p2p->cfg->d11inf,
2410 --- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
2411 +++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
2412 @@ -202,9 +202,9 @@ static struct ieee80211_supported_band _
2413
2414 /* This is to override regulatory domains defined in cfg80211 module (reg.c)
2415 * By default world regulatory domain defined in reg.c puts the flags
2416 - * NL80211_RRF_PASSIVE_SCAN and NL80211_RRF_NO_IBSS for 5GHz channels (for
2417 - * 36..48 and 149..165). With respect to these flags, wpa_supplicant doesn't
2418 - * start p2p operations on 5GHz channels. All the changes in world regulatory
2419 + * NL80211_RRF_NO_IR for 5GHz channels (for * 36..48 and 149..165).
2420 + * With respect to these flags, wpa_supplicant doesn't * start p2p
2421 + * operations on 5GHz channels. All the changes in world regulatory
2422 * domain are to be done here.
2423 */
2424 static const struct ieee80211_regdomain brcmf_regdom = {
2425 @@ -5197,10 +5197,10 @@ static s32 brcmf_construct_reginfo(struc
2426 if (channel & WL_CHAN_RADAR)
2427 band_chan_arr[index].flags |=
2428 (IEEE80211_CHAN_RADAR |
2429 - IEEE80211_CHAN_NO_IBSS);
2430 + IEEE80211_CHAN_NO_IR);
2431 if (channel & WL_CHAN_PASSIVE)
2432 band_chan_arr[index].flags |=
2433 - IEEE80211_CHAN_PASSIVE_SCAN;
2434 + IEEE80211_CHAN_NO_IR;
2435 }
2436 }
2437 if (!update)
2438 --- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
2439 +++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
2440 @@ -59,23 +59,20 @@
2441
2442 #define BRCM_2GHZ_2412_2462 REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
2443 #define BRCM_2GHZ_2467_2472 REG_RULE(2467-10, 2472+10, 20, 0, 19, \
2444 - NL80211_RRF_PASSIVE_SCAN | \
2445 - NL80211_RRF_NO_IBSS)
2446 + NL80211_RRF_NO_IR)
2447
2448 #define BRCM_5GHZ_5180_5240 REG_RULE(5180-10, 5240+10, 40, 0, 21, \
2449 - NL80211_RRF_PASSIVE_SCAN | \
2450 - NL80211_RRF_NO_IBSS)
2451 + NL80211_RRF_NO_IR)
2452 #define BRCM_5GHZ_5260_5320 REG_RULE(5260-10, 5320+10, 40, 0, 21, \
2453 - NL80211_RRF_PASSIVE_SCAN | \
2454 + NL80211_RRF_NO_IR | \
2455 NL80211_RRF_DFS | \
2456 - NL80211_RRF_NO_IBSS)
2457 + NL80211_RRF_NO_IR)
2458 #define BRCM_5GHZ_5500_5700 REG_RULE(5500-10, 5700+10, 40, 0, 21, \
2459 - NL80211_RRF_PASSIVE_SCAN | \
2460 + NL80211_RRF_NO_IR | \
2461 NL80211_RRF_DFS | \
2462 - NL80211_RRF_NO_IBSS)
2463 + NL80211_RRF_NO_IR)
2464 #define BRCM_5GHZ_5745_5825 REG_RULE(5745-10, 5825+10, 40, 0, 21, \
2465 - NL80211_RRF_PASSIVE_SCAN | \
2466 - NL80211_RRF_NO_IBSS)
2467 + NL80211_RRF_NO_IR)
2468
2469 static const struct ieee80211_regdomain brcms_regdom_x2 = {
2470 .n_reg_rules = 6,
2471 @@ -395,7 +392,7 @@ brcms_c_channel_set_chanspec(struct brcm
2472 brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
2473
2474 brcms_b_set_chanspec(wlc->hw, chanspec,
2475 - !!(ch->flags & IEEE80211_CHAN_PASSIVE_SCAN),
2476 + !!(ch->flags & IEEE80211_CHAN_NO_IR),
2477 &txpwr);
2478 }
2479
2480 @@ -657,8 +654,8 @@ static void brcms_reg_apply_radar_flags(
2481 */
2482 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
2483 ch->flags |= IEEE80211_CHAN_RADAR |
2484 - IEEE80211_CHAN_NO_IBSS |
2485 - IEEE80211_CHAN_PASSIVE_SCAN;
2486 + IEEE80211_CHAN_NO_IR |
2487 + IEEE80211_CHAN_NO_IR;
2488 }
2489 }
2490
2491 @@ -688,14 +685,13 @@ brcms_reg_apply_beaconing_flags(struct w
2492 if (IS_ERR(rule))
2493 continue;
2494
2495 - if (!(rule->flags & NL80211_RRF_NO_IBSS))
2496 - ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
2497 - if (!(rule->flags & NL80211_RRF_PASSIVE_SCAN))
2498 + if (!(rule->flags & NL80211_RRF_NO_IR))
2499 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
2500 + if (!(rule->flags & NL80211_RRF_NO_IR))
2501 ch->flags &=
2502 - ~IEEE80211_CHAN_PASSIVE_SCAN;
2503 + ~IEEE80211_CHAN_NO_IR;
2504 } else if (ch->beacon_found) {
2505 - ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
2506 - IEEE80211_CHAN_PASSIVE_SCAN);
2507 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
2508 }
2509 }
2510 }
2511 --- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
2512 +++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
2513 @@ -125,13 +125,13 @@ static struct ieee80211_channel brcms_2g
2514 CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
2515 CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
2516 CHAN2GHZ(12, 2467,
2517 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
2518 + IEEE80211_CHAN_NO_IR |
2519 IEEE80211_CHAN_NO_HT40PLUS),
2520 CHAN2GHZ(13, 2472,
2521 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
2522 + IEEE80211_CHAN_NO_IR |
2523 IEEE80211_CHAN_NO_HT40PLUS),
2524 CHAN2GHZ(14, 2484,
2525 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
2526 + IEEE80211_CHAN_NO_IR |
2527 IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS |
2528 IEEE80211_CHAN_NO_OFDM)
2529 };
2530 @@ -144,51 +144,51 @@ static struct ieee80211_channel brcms_5g
2531 CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
2532 /* UNII-2 */
2533 CHAN5GHZ(52,
2534 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2535 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
2536 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2537 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
2538 CHAN5GHZ(56,
2539 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2540 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
2541 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2542 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
2543 CHAN5GHZ(60,
2544 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2545 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
2546 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2547 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
2548 CHAN5GHZ(64,
2549 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2550 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
2551 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2552 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
2553 /* MID */
2554 CHAN5GHZ(100,
2555 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2556 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
2557 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2558 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
2559 CHAN5GHZ(104,
2560 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2561 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
2562 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2563 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
2564 CHAN5GHZ(108,
2565 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2566 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
2567 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2568 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
2569 CHAN5GHZ(112,
2570 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2571 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
2572 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2573 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
2574 CHAN5GHZ(116,
2575 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2576 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
2577 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2578 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
2579 CHAN5GHZ(120,
2580 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2581 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
2582 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2583 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
2584 CHAN5GHZ(124,
2585 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2586 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
2587 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2588 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
2589 CHAN5GHZ(128,
2590 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2591 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
2592 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2593 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
2594 CHAN5GHZ(132,
2595 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2596 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
2597 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2598 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
2599 CHAN5GHZ(136,
2600 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2601 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
2602 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2603 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
2604 CHAN5GHZ(140,
2605 - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
2606 - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
2607 + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
2608 + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS |
2609 IEEE80211_CHAN_NO_HT40MINUS),
2610 /* UNII-3 */
2611 CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
2612 --- a/drivers/net/wireless/cw1200/scan.c
2613 +++ b/drivers/net/wireless/cw1200/scan.c
2614 @@ -197,9 +197,9 @@ void cw1200_scan_work(struct work_struct
2615 if ((*it)->band != first->band)
2616 break;
2617 if (((*it)->flags ^ first->flags) &
2618 - IEEE80211_CHAN_PASSIVE_SCAN)
2619 + IEEE80211_CHAN_NO_IR)
2620 break;
2621 - if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
2622 + if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
2623 (*it)->max_power != first->max_power)
2624 break;
2625 }
2626 @@ -210,7 +210,7 @@ void cw1200_scan_work(struct work_struct
2627 else
2628 scan.max_tx_rate = WSM_TRANSMIT_RATE_1;
2629 scan.num_probes =
2630 - (first->flags & IEEE80211_CHAN_PASSIVE_SCAN) ? 0 : 2;
2631 + (first->flags & IEEE80211_CHAN_NO_IR) ? 0 : 2;
2632 scan.num_ssids = priv->scan.n_ssids;
2633 scan.ssids = &priv->scan.ssids[0];
2634 scan.num_channels = it - priv->scan.curr;
2635 @@ -233,7 +233,7 @@ void cw1200_scan_work(struct work_struct
2636 }
2637 for (i = 0; i < scan.num_channels; ++i) {
2638 scan.ch[i].number = priv->scan.curr[i]->hw_value;
2639 - if (priv->scan.curr[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
2640 + if (priv->scan.curr[i]->flags & IEEE80211_CHAN_NO_IR) {
2641 scan.ch[i].min_chan_time = 50;
2642 scan.ch[i].max_chan_time = 100;
2643 } else {
2644 @@ -241,7 +241,7 @@ void cw1200_scan_work(struct work_struct
2645 scan.ch[i].max_chan_time = 25;
2646 }
2647 }
2648 - if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
2649 + if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
2650 priv->scan.output_power != first->max_power) {
2651 priv->scan.output_power = first->max_power;
2652 wsm_set_output_power(priv,
2653 --- a/drivers/net/wireless/ipw2x00/ipw2100.c
2654 +++ b/drivers/net/wireless/ipw2x00/ipw2100.c
2655 @@ -1934,10 +1934,10 @@ static int ipw2100_wdev_init(struct net_
2656 bg_band->channels[i].max_power = geo->bg[i].max_power;
2657 if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
2658 bg_band->channels[i].flags |=
2659 - IEEE80211_CHAN_PASSIVE_SCAN;
2660 + IEEE80211_CHAN_NO_IR;
2661 if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
2662 bg_band->channels[i].flags |=
2663 - IEEE80211_CHAN_NO_IBSS;
2664 + IEEE80211_CHAN_NO_IR;
2665 if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
2666 bg_band->channels[i].flags |=
2667 IEEE80211_CHAN_RADAR;
2668 --- a/drivers/net/wireless/ipw2x00/ipw2200.c
2669 +++ b/drivers/net/wireless/ipw2x00/ipw2200.c
2670 @@ -11472,10 +11472,10 @@ static int ipw_wdev_init(struct net_devi
2671 bg_band->channels[i].max_power = geo->bg[i].max_power;
2672 if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
2673 bg_band->channels[i].flags |=
2674 - IEEE80211_CHAN_PASSIVE_SCAN;
2675 + IEEE80211_CHAN_NO_IR;
2676 if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
2677 bg_band->channels[i].flags |=
2678 - IEEE80211_CHAN_NO_IBSS;
2679 + IEEE80211_CHAN_NO_IR;
2680 if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
2681 bg_band->channels[i].flags |=
2682 IEEE80211_CHAN_RADAR;
2683 @@ -11511,10 +11511,10 @@ static int ipw_wdev_init(struct net_devi
2684 a_band->channels[i].max_power = geo->a[i].max_power;
2685 if (geo->a[i].flags & LIBIPW_CH_PASSIVE_ONLY)
2686 a_band->channels[i].flags |=
2687 - IEEE80211_CHAN_PASSIVE_SCAN;
2688 + IEEE80211_CHAN_NO_IR;
2689 if (geo->a[i].flags & LIBIPW_CH_NO_IBSS)
2690 a_band->channels[i].flags |=
2691 - IEEE80211_CHAN_NO_IBSS;
2692 + IEEE80211_CHAN_NO_IR;
2693 if (geo->a[i].flags & LIBIPW_CH_RADAR_DETECT)
2694 a_band->channels[i].flags |=
2695 IEEE80211_CHAN_RADAR;
2696 --- a/drivers/net/wireless/iwlegacy/3945-mac.c
2697 +++ b/drivers/net/wireless/iwlegacy/3945-mac.c
2698 @@ -1595,7 +1595,7 @@ il3945_get_channels_for_scan(struct il_p
2699 * and use long active_dwell time.
2700 */
2701 if (!is_active || il_is_channel_passive(ch_info) ||
2702 - (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
2703 + (chan->flags & IEEE80211_CHAN_NO_IR)) {
2704 scan_ch->type = 0; /* passive */
2705 if (IL_UCODE_API(il->ucode_ver) == 1)
2706 scan_ch->active_dwell =
2707 --- a/drivers/net/wireless/iwlegacy/4965-mac.c
2708 +++ b/drivers/net/wireless/iwlegacy/4965-mac.c
2709 @@ -805,7 +805,7 @@ il4965_get_channels_for_scan(struct il_p
2710 }
2711
2712 if (!is_active || il_is_channel_passive(ch_info) ||
2713 - (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
2714 + (chan->flags & IEEE80211_CHAN_NO_IR))
2715 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
2716 else
2717 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
2718 --- a/drivers/net/wireless/iwlegacy/common.c
2719 +++ b/drivers/net/wireless/iwlegacy/common.c
2720 @@ -3447,10 +3447,10 @@ il_init_geos(struct il_priv *il)
2721
2722 if (il_is_channel_valid(ch)) {
2723 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
2724 - geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
2725 + geo_ch->flags |= IEEE80211_CHAN_NO_IR;
2726
2727 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
2728 - geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
2729 + geo_ch->flags |= IEEE80211_CHAN_NO_IR;
2730
2731 if (ch->flags & EEPROM_CHANNEL_RADAR)
2732 geo_ch->flags |= IEEE80211_CHAN_RADAR;
2733 --- a/drivers/net/wireless/iwlegacy/debug.c
2734 +++ b/drivers/net/wireless/iwlegacy/debug.c
2735 @@ -567,12 +567,12 @@ il_dbgfs_channels_read(struct file *file
2736 flags & IEEE80211_CHAN_RADAR ?
2737 " (IEEE 802.11h required)" : "",
2738 ((channels[i].
2739 - flags & IEEE80211_CHAN_NO_IBSS) ||
2740 + flags & IEEE80211_CHAN_NO_IR) ||
2741 (channels[i].
2742 flags & IEEE80211_CHAN_RADAR)) ? "" :
2743 ", IBSS",
2744 channels[i].
2745 - flags & IEEE80211_CHAN_PASSIVE_SCAN ?
2746 + flags & IEEE80211_CHAN_NO_IR ?
2747 "passive only" : "active/passive");
2748 }
2749 supp_band = il_get_hw_mode(il, IEEE80211_BAND_5GHZ);
2750 @@ -594,12 +594,12 @@ il_dbgfs_channels_read(struct file *file
2751 flags & IEEE80211_CHAN_RADAR ?
2752 " (IEEE 802.11h required)" : "",
2753 ((channels[i].
2754 - flags & IEEE80211_CHAN_NO_IBSS) ||
2755 + flags & IEEE80211_CHAN_NO_IR) ||
2756 (channels[i].
2757 flags & IEEE80211_CHAN_RADAR)) ? "" :
2758 ", IBSS",
2759 channels[i].
2760 - flags & IEEE80211_CHAN_PASSIVE_SCAN ?
2761 + flags & IEEE80211_CHAN_NO_IR ?
2762 "passive only" : "active/passive");
2763 }
2764 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2765 --- a/drivers/net/wireless/iwlwifi/dvm/debugfs.c
2766 +++ b/drivers/net/wireless/iwlwifi/dvm/debugfs.c
2767 @@ -352,12 +352,12 @@ static ssize_t iwl_dbgfs_channels_read(s
2768 channels[i].max_power,
2769 channels[i].flags & IEEE80211_CHAN_RADAR ?
2770 " (IEEE 802.11h required)" : "",
2771 - ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
2772 + ((channels[i].flags & IEEE80211_CHAN_NO_IR)
2773 || (channels[i].flags &
2774 IEEE80211_CHAN_RADAR)) ? "" :
2775 ", IBSS",
2776 channels[i].flags &
2777 - IEEE80211_CHAN_PASSIVE_SCAN ?
2778 + IEEE80211_CHAN_NO_IR ?
2779 "passive only" : "active/passive");
2780 }
2781 supp_band = iwl_get_hw_mode(priv, IEEE80211_BAND_5GHZ);
2782 @@ -375,12 +375,12 @@ static ssize_t iwl_dbgfs_channels_read(s
2783 channels[i].max_power,
2784 channels[i].flags & IEEE80211_CHAN_RADAR ?
2785 " (IEEE 802.11h required)" : "",
2786 - ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
2787 + ((channels[i].flags & IEEE80211_CHAN_NO_IR)
2788 || (channels[i].flags &
2789 IEEE80211_CHAN_RADAR)) ? "" :
2790 ", IBSS",
2791 channels[i].flags &
2792 - IEEE80211_CHAN_PASSIVE_SCAN ?
2793 + IEEE80211_CHAN_NO_IR ?
2794 "passive only" : "active/passive");
2795 }
2796 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2797 --- a/drivers/net/wireless/iwlwifi/dvm/scan.c
2798 +++ b/drivers/net/wireless/iwlwifi/dvm/scan.c
2799 @@ -544,7 +544,7 @@ static int iwl_get_channels_for_scan(str
2800 channel = chan->hw_value;
2801 scan_ch->channel = cpu_to_le16(channel);
2802
2803 - if (!is_active || (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
2804 + if (!is_active || (chan->flags & IEEE80211_CHAN_NO_IR))
2805 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
2806 else
2807 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
2808 --- a/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
2809 +++ b/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
2810 @@ -614,10 +614,10 @@ static int iwl_init_channel_map(struct d
2811 channel->flags = IEEE80211_CHAN_NO_HT40;
2812
2813 if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS))
2814 - channel->flags |= IEEE80211_CHAN_NO_IBSS;
2815 + channel->flags |= IEEE80211_CHAN_NO_IR;
2816
2817 if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE))
2818 - channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
2819 + channel->flags |= IEEE80211_CHAN_NO_IR;
2820
2821 if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR)
2822 channel->flags |= IEEE80211_CHAN_RADAR;
2823 --- a/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
2824 +++ b/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
2825 @@ -223,10 +223,10 @@ static int iwl_init_channel_map(struct d
2826 channel->flags |= IEEE80211_CHAN_NO_160MHZ;
2827
2828 if (!(ch_flags & NVM_CHANNEL_IBSS))
2829 - channel->flags |= IEEE80211_CHAN_NO_IBSS;
2830 + channel->flags |= IEEE80211_CHAN_NO_IR;
2831
2832 if (!(ch_flags & NVM_CHANNEL_ACTIVE))
2833 - channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
2834 + channel->flags |= IEEE80211_CHAN_NO_IR;
2835
2836 if (ch_flags & NVM_CHANNEL_RADAR)
2837 channel->flags |= IEEE80211_CHAN_RADAR;
2838 --- a/drivers/net/wireless/iwlwifi/mvm/scan.c
2839 +++ b/drivers/net/wireless/iwlwifi/mvm/scan.c
2840 @@ -192,7 +192,7 @@ static void iwl_mvm_scan_fill_channels(s
2841 for (i = 0; i < cmd->channel_count; i++) {
2842 chan->channel = cpu_to_le16(req->channels[i]->hw_value);
2843 chan->type = cpu_to_le32(type);
2844 - if (req->channels[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN)
2845 + if (req->channels[i]->flags & IEEE80211_CHAN_NO_IR)
2846 chan->type &= cpu_to_le32(~SCAN_CHANNEL_TYPE_ACTIVE);
2847 chan->active_dwell = cpu_to_le16(active_dwell);
2848 chan->passive_dwell = cpu_to_le16(passive_dwell);
2849 @@ -642,7 +642,7 @@ static void iwl_build_channel_cfg(struct
2850 channels->iter_count[index] = cpu_to_le16(1);
2851 channels->iter_interval[index] = 0;
2852
2853 - if (!(s_band->channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
2854 + if (!(s_band->channels[i].flags & IEEE80211_CHAN_NO_IR))
2855 channels->type[index] |=
2856 cpu_to_le32(IWL_SCAN_OFFLOAD_CHANNEL_ACTIVE);
2857
2858 --- a/drivers/net/wireless/mac80211_hwsim.c
2859 +++ b/drivers/net/wireless/mac80211_hwsim.c
2860 @@ -159,7 +159,7 @@ static const struct ieee80211_regdomain
2861 .reg_rules = {
2862 REG_RULE(2412-10, 2462+10, 40, 0, 20, 0),
2863 REG_RULE(5725-10, 5850+10, 40, 0, 30,
2864 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
2865 + NL80211_RRF_NO_IR),
2866 }
2867 };
2868
2869 @@ -1485,7 +1485,7 @@ static void hw_scan_work(struct work_str
2870 req->channels[hwsim->scan_chan_idx]->center_freq);
2871
2872 hwsim->tmp_chan = req->channels[hwsim->scan_chan_idx];
2873 - if (hwsim->tmp_chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
2874 + if (hwsim->tmp_chan->flags & IEEE80211_CHAN_NO_IR ||
2875 !req->n_ssids) {
2876 dwell = 120;
2877 } else {
2878 --- a/drivers/net/wireless/mwifiex/cfg80211.c
2879 +++ b/drivers/net/wireless/mwifiex/cfg80211.c
2880 @@ -50,24 +50,24 @@ static const struct ieee80211_regdomain
2881 REG_RULE(2412-10, 2462+10, 40, 3, 20, 0),
2882 /* Channel 12 - 13 */
2883 REG_RULE(2467-10, 2472+10, 20, 3, 20,
2884 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
2885 + NL80211_RRF_NO_IR),
2886 /* Channel 14 */
2887 REG_RULE(2484-10, 2484+10, 20, 3, 20,
2888 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
2889 + NL80211_RRF_NO_IR |
2890 NL80211_RRF_NO_OFDM),
2891 /* Channel 36 - 48 */
2892 REG_RULE(5180-10, 5240+10, 40, 3, 20,
2893 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
2894 + NL80211_RRF_NO_IR),
2895 /* Channel 149 - 165 */
2896 REG_RULE(5745-10, 5825+10, 40, 3, 20,
2897 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
2898 + NL80211_RRF_NO_IR),
2899 /* Channel 52 - 64 */
2900 REG_RULE(5260-10, 5320+10, 40, 3, 30,
2901 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
2902 + NL80211_RRF_NO_IR |
2903 NL80211_RRF_DFS),
2904 /* Channel 100 - 140 */
2905 REG_RULE(5500-10, 5700+10, 40, 3, 30,
2906 - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
2907 + NL80211_RRF_NO_IR |
2908 NL80211_RRF_DFS),
2909 }
2910 };
2911 @@ -1968,7 +1968,7 @@ mwifiex_cfg80211_scan(struct wiphy *wiph
2912 user_scan_cfg->chan_list[i].chan_number = chan->hw_value;
2913 user_scan_cfg->chan_list[i].radio_type = chan->band;
2914
2915 - if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
2916 + if (chan->flags & IEEE80211_CHAN_NO_IR)
2917 user_scan_cfg->chan_list[i].scan_type =
2918 MWIFIEX_SCAN_TYPE_PASSIVE;
2919 else
2920 --- a/drivers/net/wireless/mwifiex/scan.c
2921 +++ b/drivers/net/wireless/mwifiex/scan.c
2922 @@ -515,14 +515,14 @@ mwifiex_scan_create_channel_list(struct
2923 scan_chan_list[chan_idx].max_scan_time =
2924 cpu_to_le16((u16) user_scan_in->
2925 chan_list[0].scan_time);
2926 - else if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
2927 + else if (ch->flags & IEEE80211_CHAN_NO_IR)
2928 scan_chan_list[chan_idx].max_scan_time =
2929 cpu_to_le16(adapter->passive_scan_time);
2930 else
2931 scan_chan_list[chan_idx].max_scan_time =
2932 cpu_to_le16(adapter->active_scan_time);
2933
2934 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
2935 + if (ch->flags & IEEE80211_CHAN_NO_IR)
2936 scan_chan_list[chan_idx].chan_scan_mode_bitmap
2937 |= MWIFIEX_PASSIVE_SCAN;
2938 else
2939 --- a/drivers/net/wireless/rt2x00/rt2x00lib.h
2940 +++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
2941 @@ -146,7 +146,7 @@ void rt2x00queue_remove_l2pad(struct sk_
2942 * @local: frame is not from mac80211
2943 */
2944 int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
2945 - bool local);
2946 + struct ieee80211_sta *sta, bool local);
2947
2948 /**
2949 * rt2x00queue_update_beacon - Send new beacon from mac80211
2950 --- a/drivers/net/wireless/rt2x00/rt2x00mac.c
2951 +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
2952 @@ -90,7 +90,7 @@ static int rt2x00mac_tx_rts_cts(struct r
2953 frag_skb->data, data_length, tx_info,
2954 (struct ieee80211_rts *)(skb->data));
2955
2956 - retval = rt2x00queue_write_tx_frame(queue, skb, true);
2957 + retval = rt2x00queue_write_tx_frame(queue, skb, NULL, true);
2958 if (retval) {
2959 dev_kfree_skb_any(skb);
2960 rt2x00_warn(rt2x00dev, "Failed to send RTS/CTS frame\n");
2961 @@ -151,7 +151,7 @@ void rt2x00mac_tx(struct ieee80211_hw *h
2962 goto exit_fail;
2963 }
2964
2965 - if (unlikely(rt2x00queue_write_tx_frame(queue, skb, false)))
2966 + if (unlikely(rt2x00queue_write_tx_frame(queue, skb, control->sta, false)))
2967 goto exit_fail;
2968
2969 /*
2970 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c
2971 +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
2972 @@ -635,7 +635,7 @@ static void rt2x00queue_bar_check(struct
2973 }
2974
2975 int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
2976 - bool local)
2977 + struct ieee80211_sta *sta, bool local)
2978 {
2979 struct ieee80211_tx_info *tx_info;
2980 struct queue_entry *entry;
2981 @@ -649,7 +649,7 @@ int rt2x00queue_write_tx_frame(struct da
2982 * after that we are free to use the skb->cb array
2983 * for our information.
2984 */
2985 - rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, NULL);
2986 + rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, sta);
2987
2988 /*
2989 * All information is retrieved from the skb->cb array,
2990 --- a/drivers/net/wireless/rtl818x/rtl8187/dev.c
2991 +++ b/drivers/net/wireless/rtl818x/rtl8187/dev.c
2992 @@ -416,7 +416,7 @@ static int rtl8187_init_urbs(struct ieee
2993 struct rtl8187_rx_info *info;
2994 int ret = 0;
2995
2996 - while (skb_queue_len(&priv->rx_queue) < 16) {
2997 + while (skb_queue_len(&priv->rx_queue) < 32) {
2998 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
2999 if (!skb) {
3000 ret = -ENOMEM;
3001 --- a/drivers/net/wireless/rtlwifi/base.c
3002 +++ b/drivers/net/wireless/rtlwifi/base.c
3003 @@ -1078,8 +1078,8 @@ u8 rtl_is_special_data(struct ieee80211_
3004
3005 ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
3006 SNAP_SIZE + PROTOC_TYPE_SIZE);
3007 - ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
3008 - /* ether_type = ntohs(ether_type); */
3009 + ether_type = be16_to_cpu(*(__be16 *)((u8 *)skb->data + mac_hdr_len +
3010 + SNAP_SIZE));
3011
3012 if (ETH_P_IP == ether_type) {
3013 if (IPPROTO_UDP == ip->protocol) {
3014 --- a/drivers/net/wireless/rtlwifi/regd.c
3015 +++ b/drivers/net/wireless/rtlwifi/regd.c
3016 @@ -59,30 +59,27 @@ static struct country_code_to_enum_rd al
3017 */
3018 #define RTL819x_2GHZ_CH12_13 \
3019 REG_RULE(2467-10, 2472+10, 40, 0, 20,\
3020 - NL80211_RRF_PASSIVE_SCAN)
3021 + NL80211_RRF_NO_IR)
3022
3023 #define RTL819x_2GHZ_CH14 \
3024 REG_RULE(2484-10, 2484+10, 40, 0, 20, \
3025 - NL80211_RRF_PASSIVE_SCAN | \
3026 + NL80211_RRF_NO_IR | \
3027 NL80211_RRF_NO_OFDM)
3028
3029 /* 5G chan 36 - chan 64*/
3030 #define RTL819x_5GHZ_5150_5350 \
3031 REG_RULE(5150-10, 5350+10, 40, 0, 30, \
3032 - NL80211_RRF_PASSIVE_SCAN | \
3033 - NL80211_RRF_NO_IBSS)
3034 + NL80211_RRF_NO_IR)
3035
3036 /* 5G chan 100 - chan 165*/
3037 #define RTL819x_5GHZ_5470_5850 \
3038 REG_RULE(5470-10, 5850+10, 40, 0, 30, \
3039 - NL80211_RRF_PASSIVE_SCAN | \
3040 - NL80211_RRF_NO_IBSS)
3041 + NL80211_RRF_NO_IR)
3042
3043 /* 5G chan 149 - chan 165*/
3044 #define RTL819x_5GHZ_5725_5850 \
3045 REG_RULE(5725-10, 5850+10, 40, 0, 30, \
3046 - NL80211_RRF_PASSIVE_SCAN | \
3047 - NL80211_RRF_NO_IBSS)
3048 + NL80211_RRF_NO_IR)
3049
3050 #define RTL819x_5GHZ_ALL \
3051 (RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850)
3052 @@ -185,16 +182,15 @@ static void _rtl_reg_apply_beaconing_fla
3053 *regulatory_hint().
3054 */
3055
3056 - if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
3057 - ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
3058 + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3059 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
3060 if (!(reg_rule->
3061 - flags & NL80211_RRF_PASSIVE_SCAN))
3062 + flags & NL80211_RRF_NO_IR))
3063 ch->flags &=
3064 - ~IEEE80211_CHAN_PASSIVE_SCAN;
3065 + ~IEEE80211_CHAN_NO_IR;
3066 } else {
3067 if (ch->beacon_found)
3068 - ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
3069 - IEEE80211_CHAN_PASSIVE_SCAN);
3070 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
3071 }
3072 }
3073 }
3074 @@ -219,11 +215,11 @@ static void _rtl_reg_apply_active_scan_f
3075 */
3076 if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
3077 ch = &sband->channels[11]; /* CH 12 */
3078 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3079 - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3080 + if (ch->flags & IEEE80211_CHAN_NO_IR)
3081 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
3082 ch = &sband->channels[12]; /* CH 13 */
3083 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3084 - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3085 + if (ch->flags & IEEE80211_CHAN_NO_IR)
3086 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
3087 return;
3088 }
3089
3090 @@ -237,17 +233,17 @@ static void _rtl_reg_apply_active_scan_f
3091 ch = &sband->channels[11]; /* CH 12 */
3092 reg_rule = freq_reg_info(wiphy, ch->center_freq);
3093 if (!IS_ERR(reg_rule)) {
3094 - if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
3095 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3096 - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3097 + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3098 + if (ch->flags & IEEE80211_CHAN_NO_IR)
3099 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
3100 }
3101
3102 ch = &sband->channels[12]; /* CH 13 */
3103 reg_rule = freq_reg_info(wiphy, ch->center_freq);
3104 if (!IS_ERR(reg_rule)) {
3105 - if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
3106 - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3107 - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
3108 + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
3109 + if (ch->flags & IEEE80211_CHAN_NO_IR)
3110 + ch->flags &= ~IEEE80211_CHAN_NO_IR;
3111 }
3112 }
3113
3114 @@ -284,8 +280,8 @@ static void _rtl_reg_apply_radar_flags(s
3115 */
3116 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
3117 ch->flags |= IEEE80211_CHAN_RADAR |
3118 - IEEE80211_CHAN_NO_IBSS |
3119 - IEEE80211_CHAN_PASSIVE_SCAN;
3120 + IEEE80211_CHAN_NO_IR |
3121 + IEEE80211_CHAN_NO_IR;
3122 }
3123 }
3124
3125 --- a/drivers/net/wireless/ti/wl12xx/scan.c
3126 +++ b/drivers/net/wireless/ti/wl12xx/scan.c
3127 @@ -47,7 +47,7 @@ static int wl1271_get_scan_channels(stru
3128 * In active scans, we only scan channels not
3129 * marked as passive.
3130 */
3131 - (passive || !(flags & IEEE80211_CHAN_PASSIVE_SCAN))) {
3132 + (passive || !(flags & IEEE80211_CHAN_NO_IR))) {
3133 wl1271_debug(DEBUG_SCAN, "band %d, center_freq %d ",
3134 req->channels[i]->band,
3135 req->channels[i]->center_freq);
3136 --- a/drivers/net/wireless/ti/wlcore/cmd.c
3137 +++ b/drivers/net/wireless/ti/wlcore/cmd.c
3138 @@ -1688,7 +1688,7 @@ int wlcore_cmd_regdomain_config_locked(s
3139
3140 if (channel->flags & (IEEE80211_CHAN_DISABLED |
3141 IEEE80211_CHAN_RADAR |
3142 - IEEE80211_CHAN_PASSIVE_SCAN))
3143 + IEEE80211_CHAN_NO_IR))
3144 continue;
3145
3146 ch_bit_idx = wlcore_get_reg_conf_ch_idx(b, ch);
3147 --- a/drivers/net/wireless/ti/wlcore/main.c
3148 +++ b/drivers/net/wireless/ti/wlcore/main.c
3149 @@ -91,8 +91,7 @@ static void wl1271_reg_notify(struct wip
3150 continue;
3151
3152 if (ch->flags & IEEE80211_CHAN_RADAR)
3153 - ch->flags |= IEEE80211_CHAN_NO_IBSS |
3154 - IEEE80211_CHAN_PASSIVE_SCAN;
3155 + ch->flags |= IEEE80211_CHAN_NO_IR;
3156
3157 }
3158
3159 --- a/drivers/net/wireless/ti/wlcore/scan.c
3160 +++ b/drivers/net/wireless/ti/wlcore/scan.c
3161 @@ -189,14 +189,14 @@ wlcore_scan_get_channels(struct wl1271 *
3162 flags = req_channels[i]->flags;
3163
3164 if (force_passive)
3165 - flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3166 + flags |= IEEE80211_CHAN_NO_IR;
3167
3168 if ((req_channels[i]->band == band) &&
3169 !(flags & IEEE80211_CHAN_DISABLED) &&
3170 (!!(flags & IEEE80211_CHAN_RADAR) == radar) &&
3171 /* if radar is set, we ignore the passive flag */
3172 (radar ||
3173 - !!(flags & IEEE80211_CHAN_PASSIVE_SCAN) == passive)) {
3174 + !!(flags & IEEE80211_CHAN_NO_IR) == passive)) {
3175
3176
3177 if (flags & IEEE80211_CHAN_RADAR) {
3178 @@ -221,7 +221,7 @@ wlcore_scan_get_channels(struct wl1271 *
3179 (band == IEEE80211_BAND_2GHZ) &&
3180 (channels[j].channel >= 12) &&
3181 (channels[j].channel <= 14) &&
3182 - (flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
3183 + (flags & IEEE80211_CHAN_NO_IR) &&
3184 !force_passive) {
3185 /* pactive channels treated as DFS */
3186 channels[j].flags = SCAN_CHANNEL_FLAGS_DFS;
3187 @@ -244,7 +244,7 @@ wlcore_scan_get_channels(struct wl1271 *
3188 max_dwell_time_active,
3189 flags & IEEE80211_CHAN_RADAR ?
3190 ", DFS" : "",
3191 - flags & IEEE80211_CHAN_PASSIVE_SCAN ?
3192 + flags & IEEE80211_CHAN_NO_IR ?
3193 ", PASSIVE" : "");
3194 j++;
3195 }
3196 --- a/include/net/cfg80211.h
3197 +++ b/include/net/cfg80211.h
3198 @@ -91,9 +91,8 @@ enum ieee80211_band {
3199 * Channel flags set by the regulatory control code.
3200 *
3201 * @IEEE80211_CHAN_DISABLED: This channel is disabled.
3202 - * @IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
3203 - * on this channel.
3204 - * @IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
3205 + * @IEEE80211_CHAN_NO_IR: do not initiate radiation, this includes
3206 + * sending probe requests or beaconing.
3207 * @IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
3208 * @IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
3209 * is not permitted.
3210 @@ -113,8 +112,8 @@ enum ieee80211_band {
3211 */
3212 enum ieee80211_channel_flags {
3213 IEEE80211_CHAN_DISABLED = 1<<0,
3214 - IEEE80211_CHAN_PASSIVE_SCAN = 1<<1,
3215 - IEEE80211_CHAN_NO_IBSS = 1<<2,
3216 + IEEE80211_CHAN_NO_IR = 1<<1,
3217 + /* hole at 1<<2 */
3218 IEEE80211_CHAN_RADAR = 1<<3,
3219 IEEE80211_CHAN_NO_HT40PLUS = 1<<4,
3220 IEEE80211_CHAN_NO_HT40MINUS = 1<<5,
3221 @@ -4149,6 +4148,7 @@ void cfg80211_radar_event(struct wiphy *
3222 /**
3223 * cfg80211_cac_event - Channel availability check (CAC) event
3224 * @netdev: network device
3225 + * @chandef: chandef for the current channel
3226 * @event: type of event
3227 * @gfp: context flags
3228 *
3229 @@ -4157,6 +4157,7 @@ void cfg80211_radar_event(struct wiphy *
3230 * also by full-MAC drivers.
3231 */
3232 void cfg80211_cac_event(struct net_device *netdev,
3233 + const struct cfg80211_chan_def *chandef,
3234 enum nl80211_radar_event event, gfp_t gfp);
3235
3236
3237 @@ -4282,7 +4283,8 @@ bool cfg80211_reg_can_beacon(struct wiph
3238 * @dev: the device which switched channels
3239 * @chandef: the new channel definition
3240 *
3241 - * Acquires wdev_lock, so must only be called from sleepable driver context!
3242 + * Caller must acquire wdev_lock, therefore must only be called from sleepable
3243 + * driver context!
3244 */
3245 void cfg80211_ch_switch_notify(struct net_device *dev,
3246 struct cfg80211_chan_def *chandef);
3247 --- a/include/uapi/linux/nl80211.h
3248 +++ b/include/uapi/linux/nl80211.h
3249 @@ -1508,6 +1508,12 @@ enum nl80211_commands {
3250 * to react to radar events, e.g. initiate a channel switch or leave the
3251 * IBSS network.
3252 *
3253 + * @NL80211_ATTR_SUPPORT_5_MHZ: A flag indicating that the device supports
3254 + * 5 MHz channel bandwidth.
3255 + *
3256 + * @NL80211_ATTR_SUPPORT_10_MHZ: A flag indicating that the device supports
3257 + * 10 MHz channel bandwidth.
3258 + *
3259 * @NL80211_ATTR_MAX: highest attribute number currently defined
3260 * @__NL80211_ATTR_AFTER_LAST: internal use
3261 */
3262 @@ -1824,6 +1830,9 @@ enum nl80211_attrs {
3263
3264 NL80211_ATTR_HANDLE_DFS,
3265
3266 + NL80211_ATTR_SUPPORT_5_MHZ,
3267 + NL80211_ATTR_SUPPORT_10_MHZ,
3268 +
3269 /* add attributes here, update the policy in nl80211.c */
3270
3271 __NL80211_ATTR_AFTER_LAST,
3272 @@ -2224,10 +2233,9 @@ enum nl80211_band_attr {
3273 * @NL80211_FREQUENCY_ATTR_FREQ: Frequency in MHz
3274 * @NL80211_FREQUENCY_ATTR_DISABLED: Channel is disabled in current
3275 * regulatory domain.
3276 - * @NL80211_FREQUENCY_ATTR_PASSIVE_SCAN: Only passive scanning is
3277 - * permitted on this channel in current regulatory domain.
3278 - * @NL80211_FREQUENCY_ATTR_NO_IBSS: IBSS networks are not permitted
3279 - * on this channel in current regulatory domain.
3280 + * @NL80211_FREQUENCY_ATTR_NO_IR: no mechanisms that initiate radiation
3281 + * are permitted on this channel, this includes sending probe
3282 + * requests, or modes of operation that require beaconing.
3283 * @NL80211_FREQUENCY_ATTR_RADAR: Radar detection is mandatory
3284 * on this channel in current regulatory domain.
3285 * @NL80211_FREQUENCY_ATTR_MAX_TX_POWER: Maximum transmission power in mBm
3286 @@ -2254,8 +2262,8 @@ enum nl80211_frequency_attr {
3287 __NL80211_FREQUENCY_ATTR_INVALID,
3288 NL80211_FREQUENCY_ATTR_FREQ,
3289 NL80211_FREQUENCY_ATTR_DISABLED,
3290 - NL80211_FREQUENCY_ATTR_PASSIVE_SCAN,
3291 - NL80211_FREQUENCY_ATTR_NO_IBSS,
3292 + NL80211_FREQUENCY_ATTR_NO_IR,
3293 + __NL80211_FREQUENCY_ATTR_NO_IBSS,
3294 NL80211_FREQUENCY_ATTR_RADAR,
3295 NL80211_FREQUENCY_ATTR_MAX_TX_POWER,
3296 NL80211_FREQUENCY_ATTR_DFS_STATE,
3297 @@ -2271,6 +2279,9 @@ enum nl80211_frequency_attr {
3298 };
3299
3300 #define NL80211_FREQUENCY_ATTR_MAX_TX_POWER NL80211_FREQUENCY_ATTR_MAX_TX_POWER
3301 +#define NL80211_FREQUENCY_ATTR_PASSIVE_SCAN NL80211_FREQUENCY_ATTR_NO_IR
3302 +#define NL80211_FREQUENCY_ATTR_NO_IBSS NL80211_FREQUENCY_ATTR_NO_IR
3303 +#define NL80211_FREQUENCY_ATTR_NO_IR NL80211_FREQUENCY_ATTR_NO_IR
3304
3305 /**
3306 * enum nl80211_bitrate_attr - bitrate attributes
3307 @@ -2413,8 +2424,9 @@ enum nl80211_sched_scan_match_attr {
3308 * @NL80211_RRF_DFS: DFS support is required to be used
3309 * @NL80211_RRF_PTP_ONLY: this is only for Point To Point links
3310 * @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links
3311 - * @NL80211_RRF_PASSIVE_SCAN: passive scan is required
3312 - * @NL80211_RRF_NO_IBSS: no IBSS is allowed
3313 + * @NL80211_RRF_NO_IR: no mechanisms that initiate radiation are allowed,
3314 + * this includes probe requests or modes of operation that require
3315 + * beaconing.
3316 */
3317 enum nl80211_reg_rule_flags {
3318 NL80211_RRF_NO_OFDM = 1<<0,
3319 @@ -2424,10 +2436,17 @@ enum nl80211_reg_rule_flags {
3320 NL80211_RRF_DFS = 1<<4,
3321 NL80211_RRF_PTP_ONLY = 1<<5,
3322 NL80211_RRF_PTMP_ONLY = 1<<6,
3323 - NL80211_RRF_PASSIVE_SCAN = 1<<7,
3324 - NL80211_RRF_NO_IBSS = 1<<8,
3325 + NL80211_RRF_NO_IR = 1<<7,
3326 + __NL80211_RRF_NO_IBSS = 1<<8,
3327 };
3328
3329 +#define NL80211_RRF_PASSIVE_SCAN NL80211_RRF_NO_IR
3330 +#define NL80211_RRF_NO_IBSS NL80211_RRF_NO_IR
3331 +#define NL80211_RRF_NO_IR NL80211_RRF_NO_IR
3332 +
3333 +/* For backport compatibility with older userspace */
3334 +#define NL80211_RRF_NO_IR_ALL (NL80211_RRF_NO_IR | __NL80211_RRF_NO_IBSS)
3335 +
3336 /**
3337 * enum nl80211_dfs_regions - regulatory DFS regions
3338 *
3339 --- a/net/mac80211/cfg.c
3340 +++ b/net/mac80211/cfg.c
3341 @@ -846,7 +846,7 @@ static int ieee80211_set_probe_resp(stru
3342 if (!resp || !resp_len)
3343 return 1;
3344
3345 - old = rtnl_dereference(sdata->u.ap.probe_resp);
3346 + old = sdata_dereference(sdata->u.ap.probe_resp, sdata);
3347
3348 new = kzalloc(sizeof(struct probe_resp) + resp_len, GFP_KERNEL);
3349 if (!new)
3350 @@ -870,7 +870,8 @@ int ieee80211_assign_beacon(struct ieee8
3351 int size, err;
3352 u32 changed = BSS_CHANGED_BEACON;
3353
3354 - old = rtnl_dereference(sdata->u.ap.beacon);
3355 + old = sdata_dereference(sdata->u.ap.beacon, sdata);
3356 +
3357
3358 /* Need to have a beacon head if we don't have one yet */
3359 if (!params->head && !old)
3360 @@ -947,7 +948,7 @@ static int ieee80211_start_ap(struct wip
3361 BSS_CHANGED_P2P_PS;
3362 int err;
3363
3364 - old = rtnl_dereference(sdata->u.ap.beacon);
3365 + old = sdata_dereference(sdata->u.ap.beacon, sdata);
3366 if (old)
3367 return -EALREADY;
3368
3369 @@ -1001,7 +1002,8 @@ static int ieee80211_start_ap(struct wip
3370
3371 err = drv_start_ap(sdata->local, sdata);
3372 if (err) {
3373 - old = rtnl_dereference(sdata->u.ap.beacon);
3374 + old = sdata_dereference(sdata->u.ap.beacon, sdata);
3375 +
3376 if (old)
3377 kfree_rcu(old, rcu_head);
3378 RCU_INIT_POINTER(sdata->u.ap.beacon, NULL);
3379 @@ -1032,7 +1034,7 @@ static int ieee80211_change_beacon(struc
3380 if (sdata->vif.csa_active)
3381 return -EBUSY;
3382
3383 - old = rtnl_dereference(sdata->u.ap.beacon);
3384 + old = sdata_dereference(sdata->u.ap.beacon, sdata);
3385 if (!old)
3386 return -ENOENT;
3387
3388 @@ -1050,15 +1052,18 @@ static int ieee80211_stop_ap(struct wiph
3389 struct ieee80211_local *local = sdata->local;
3390 struct beacon_data *old_beacon;
3391 struct probe_resp *old_probe_resp;
3392 + struct cfg80211_chan_def chandef;
3393
3394 - old_beacon = rtnl_dereference(sdata->u.ap.beacon);
3395 + old_beacon = sdata_dereference(sdata->u.ap.beacon, sdata);
3396 if (!old_beacon)
3397 return -ENOENT;
3398 - old_probe_resp = rtnl_dereference(sdata->u.ap.probe_resp);
3399 + old_probe_resp = sdata_dereference(sdata->u.ap.probe_resp, sdata);
3400
3401 /* abort any running channel switch */
3402 sdata->vif.csa_active = false;
3403 - cancel_work_sync(&sdata->csa_finalize_work);
3404 + kfree(sdata->u.ap.next_beacon);
3405 + sdata->u.ap.next_beacon = NULL;
3406 +
3407 cancel_work_sync(&sdata->u.ap.request_smps_work);
3408
3409 /* turn off carrier for this interface and dependent VLANs */
3410 @@ -1091,8 +1096,10 @@ static int ieee80211_stop_ap(struct wiph
3411 ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON_ENABLED);
3412
3413 if (sdata->wdev.cac_started) {
3414 + chandef = sdata->vif.bss_conf.chandef;
3415 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
3416 - cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
3417 + cfg80211_cac_event(sdata->dev, &chandef,
3418 + NL80211_RADAR_CAC_ABORTED,
3419 GFP_KERNEL);
3420 }
3421
3422 @@ -1368,7 +1375,7 @@ static int sta_apply_parameters(struct i
3423 changed |=
3424 ieee80211_mps_set_sta_local_pm(sta,
3425 params->local_pm);
3426 - ieee80211_bss_info_change_notify(sdata, changed);
3427 + ieee80211_mbss_info_change_notify(sdata, changed);
3428 #endif
3429 }
3430
3431 @@ -1953,7 +1960,7 @@ static int ieee80211_change_bss(struct w
3432 enum ieee80211_band band;
3433 u32 changed = 0;
3434
3435 - if (!rtnl_dereference(sdata->u.ap.beacon))
3436 + if (!sdata_dereference(sdata->u.ap.beacon, sdata))
3437 return -ENOENT;
3438
3439 band = ieee80211_get_sdata_band(sdata);
3440 @@ -2964,27 +2971,33 @@ void ieee80211_csa_finalize_work(struct
3441 struct ieee80211_local *local = sdata->local;
3442 int err, changed = 0;
3443
3444 + sdata_lock(sdata);
3445 + /* AP might have been stopped while waiting for the lock. */
3446 + if (!sdata->vif.csa_active)
3447 + goto unlock;
3448 +
3449 if (!ieee80211_sdata_running(sdata))
3450 - return;
3451 + goto unlock;
3452
3453 sdata->radar_required = sdata->csa_radar_required;
3454 - err = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
3455 - &changed);
3456 + err = ieee80211_vif_change_channel(sdata, &changed);
3457 if (WARN_ON(err < 0))
3458 - return;
3459 + goto unlock;
3460
3461 if (!local->use_chanctx) {
3462 - local->_oper_chandef = local->csa_chandef;
3463 + local->_oper_chandef = sdata->csa_chandef;
3464 ieee80211_hw_config(local, 0);
3465 }
3466
3467 ieee80211_bss_info_change_notify(sdata, changed);
3468
3469 + sdata->vif.csa_active = false;
3470 switch (sdata->vif.type) {
3471 case NL80211_IFTYPE_AP:
3472 err = ieee80211_assign_beacon(sdata, sdata->u.ap.next_beacon);
3473 if (err < 0)
3474 - return;
3475 + goto unlock;
3476 +
3477 changed |= err;
3478 kfree(sdata->u.ap.next_beacon);
3479 sdata->u.ap.next_beacon = NULL;
3480 @@ -2998,20 +3011,22 @@ void ieee80211_csa_finalize_work(struct
3481 case NL80211_IFTYPE_MESH_POINT:
3482 err = ieee80211_mesh_finish_csa(sdata);
3483 if (err < 0)
3484 - return;
3485 + goto unlock;
3486 break;
3487 #endif
3488 default:
3489 WARN_ON(1);
3490 - return;
3491 + goto unlock;
3492 }
3493 - sdata->vif.csa_active = false;
3494
3495 ieee80211_wake_queues_by_reason(&sdata->local->hw,
3496 IEEE80211_MAX_QUEUE_MAP,
3497 IEEE80211_QUEUE_STOP_REASON_CSA);
3498
3499 - cfg80211_ch_switch_notify(sdata->dev, &local->csa_chandef);
3500 + cfg80211_ch_switch_notify(sdata->dev, &sdata->csa_chandef);
3501 +
3502 +unlock:
3503 + sdata_unlock(sdata);
3504 }
3505
3506 static int ieee80211_channel_switch(struct wiphy *wiphy, struct net_device *dev,
3507 @@ -3024,6 +3039,8 @@ static int ieee80211_channel_switch(stru
3508 struct ieee80211_if_mesh __maybe_unused *ifmsh;
3509 int err, num_chanctx;
3510
3511 + lockdep_assert_held(&sdata->wdev.mtx);
3512 +
3513 if (!list_empty(&local->roc_list) || local->scanning)
3514 return -EBUSY;
3515
3516 @@ -3120,9 +3137,17 @@ static int ieee80211_channel_switch(stru
3517 params->chandef.chan->band)
3518 return -EINVAL;
3519
3520 + ifmsh->chsw_init = true;
3521 + if (!ifmsh->pre_value)
3522 + ifmsh->pre_value = 1;
3523 + else
3524 + ifmsh->pre_value++;
3525 +
3526 err = ieee80211_mesh_csa_beacon(sdata, params, true);
3527 - if (err < 0)
3528 + if (err < 0) {
3529 + ifmsh->chsw_init = false;
3530 return err;
3531 + }
3532 break;
3533 #endif
3534 default:
3535 @@ -3136,7 +3161,7 @@ static int ieee80211_channel_switch(stru
3536 IEEE80211_MAX_QUEUE_MAP,
3537 IEEE80211_QUEUE_STOP_REASON_CSA);
3538
3539 - local->csa_chandef = params->chandef;
3540 + sdata->csa_chandef = params->chandef;
3541 sdata->vif.csa_active = true;
3542
3543 ieee80211_bss_info_change_notify(sdata, err);
3544 --- a/net/mac80211/iface.c
3545 +++ b/net/mac80211/iface.c
3546 @@ -749,6 +749,7 @@ static void ieee80211_do_stop(struct iee
3547 u32 hw_reconf_flags = 0;
3548 int i, flushed;
3549 struct ps_data *ps;
3550 + struct cfg80211_chan_def chandef;
3551
3552 clear_bit(SDATA_STATE_RUNNING, &sdata->state);
3553
3554 @@ -828,11 +829,13 @@ static void ieee80211_do_stop(struct iee
3555 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
3556
3557 if (sdata->wdev.cac_started) {
3558 + chandef = sdata->vif.bss_conf.chandef;
3559 WARN_ON(local->suspended);
3560 mutex_lock(&local->iflist_mtx);
3561 ieee80211_vif_release_channel(sdata);
3562 mutex_unlock(&local->iflist_mtx);
3563 - cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
3564 + cfg80211_cac_event(sdata->dev, &chandef,
3565 + NL80211_RADAR_CAC_ABORTED,
3566 GFP_KERNEL);
3567 }
3568
3569 @@ -1340,7 +1343,6 @@ static void ieee80211_setup_sdata(struct
3570 sdata->vif.bss_conf.bssid = NULL;
3571 break;
3572 case NL80211_IFTYPE_AP_VLAN:
3573 - break;
3574 case NL80211_IFTYPE_P2P_DEVICE:
3575 sdata->vif.bss_conf.bssid = sdata->vif.addr;
3576 break;
3577 --- a/net/mac80211/mlme.c
3578 +++ b/net/mac80211/mlme.c
3579 @@ -886,8 +886,7 @@ static void ieee80211_chswitch_work(stru
3580 if (!ifmgd->associated)
3581 goto out;
3582
3583 - ret = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
3584 - &changed);
3585 + ret = ieee80211_vif_change_channel(sdata, &changed);
3586 if (ret) {
3587 sdata_info(sdata,
3588 "vif channel switch failed, disconnecting\n");
3589 @@ -897,7 +896,7 @@ static void ieee80211_chswitch_work(stru
3590 }
3591
3592 if (!local->use_chanctx) {
3593 - local->_oper_chandef = local->csa_chandef;
3594 + local->_oper_chandef = sdata->csa_chandef;
3595 /* Call "hw_config" only if doing sw channel switch.
3596 * Otherwise update the channel directly
3597 */
3598 @@ -908,7 +907,7 @@ static void ieee80211_chswitch_work(stru
3599 }
3600
3601 /* XXX: shouldn't really modify cfg80211-owned data! */
3602 - ifmgd->associated->channel = local->csa_chandef.chan;
3603 + ifmgd->associated->channel = sdata->csa_chandef.chan;
3604
3605 /* XXX: wait for a beacon first? */
3606 ieee80211_wake_queues_by_reason(&local->hw,
3607 @@ -1035,7 +1034,7 @@ ieee80211_sta_process_chanswitch(struct
3608 }
3609 mutex_unlock(&local->chanctx_mtx);
3610
3611 - local->csa_chandef = csa_ie.chandef;
3612 + sdata->csa_chandef = csa_ie.chandef;
3613
3614 if (csa_ie.mode)
3615 ieee80211_stop_queues_by_reason(&local->hw,
3616 @@ -1398,10 +1397,12 @@ void ieee80211_dfs_cac_timer_work(struct
3617 struct ieee80211_sub_if_data *sdata =
3618 container_of(delayed_work, struct ieee80211_sub_if_data,
3619 dfs_cac_timer_work);
3620 + struct cfg80211_chan_def chandef = sdata->vif.bss_conf.chandef;
3621
3622 ieee80211_vif_release_channel(sdata);
3623 -
3624 - cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_FINISHED, GFP_KERNEL);
3625 + cfg80211_cac_event(sdata->dev, &chandef,
3626 + NL80211_RADAR_CAC_FINISHED,
3627 + GFP_KERNEL);
3628 }
3629
3630 /* MLME */
3631 --- a/net/mac80211/rx.c
3632 +++ b/net/mac80211/rx.c
3633 @@ -729,9 +729,7 @@ static void ieee80211_release_reorder_fr
3634 lockdep_assert_held(&tid_agg_rx->reorder_lock);
3635
3636 while (ieee80211_sn_less(tid_agg_rx->head_seq_num, head_seq_num)) {
3637 - index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
3638 - tid_agg_rx->ssn) %
3639 - tid_agg_rx->buf_size;
3640 + index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
3641 ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
3642 frames);
3643 }
3644 @@ -757,8 +755,7 @@ static void ieee80211_sta_reorder_releas
3645 lockdep_assert_held(&tid_agg_rx->reorder_lock);
3646
3647 /* release the buffer until next missing frame */
3648 - index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
3649 - tid_agg_rx->ssn) % tid_agg_rx->buf_size;
3650 + index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
3651 if (!tid_agg_rx->reorder_buf[index] &&
3652 tid_agg_rx->stored_mpdu_num) {
3653 /*
3654 @@ -793,15 +790,11 @@ static void ieee80211_sta_reorder_releas
3655 } else while (tid_agg_rx->reorder_buf[index]) {
3656 ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
3657 frames);
3658 - index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
3659 - tid_agg_rx->ssn) %
3660 - tid_agg_rx->buf_size;
3661 + index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
3662 }
3663
3664 if (tid_agg_rx->stored_mpdu_num) {
3665 - j = index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
3666 - tid_agg_rx->ssn) %
3667 - tid_agg_rx->buf_size;
3668 + j = index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
3669
3670 for (; j != (index - 1) % tid_agg_rx->buf_size;
3671 j = (j + 1) % tid_agg_rx->buf_size) {
3672 @@ -861,8 +854,7 @@ static bool ieee80211_sta_manage_reorder
3673
3674 /* Now the new frame is always in the range of the reordering buffer */
3675
3676 - index = ieee80211_sn_sub(mpdu_seq_num,
3677 - tid_agg_rx->ssn) % tid_agg_rx->buf_size;
3678 + index = mpdu_seq_num % tid_agg_rx->buf_size;
3679
3680 /* check if we already stored this frame */
3681 if (tid_agg_rx->reorder_buf[index]) {
3682 @@ -911,7 +903,8 @@ static void ieee80211_rx_reorder_ampdu(s
3683 u16 sc;
3684 u8 tid, ack_policy;
3685
3686 - if (!ieee80211_is_data_qos(hdr->frame_control))
3687 + if (!ieee80211_is_data_qos(hdr->frame_control) ||
3688 + is_multicast_ether_addr(hdr->addr1))
3689 goto dont_reorder;
3690
3691 /*
3692 --- a/net/mac80211/scan.c
3693 +++ b/net/mac80211/scan.c
3694 @@ -526,7 +526,7 @@ static int __ieee80211_start_scan(struct
3695 ieee80211_hw_config(local, 0);
3696
3697 if ((req->channels[0]->flags &
3698 - IEEE80211_CHAN_PASSIVE_SCAN) ||
3699 + IEEE80211_CHAN_NO_IR) ||
3700 !local->scan_req->n_ssids) {
3701 next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
3702 } else {
3703 @@ -572,7 +572,7 @@ ieee80211_scan_get_channel_time(struct i
3704 * TODO: channel switching also consumes quite some time,
3705 * add that delay as well to get a better estimation
3706 */
3707 - if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
3708 + if (chan->flags & IEEE80211_CHAN_NO_IR)
3709 return IEEE80211_PASSIVE_CHANNEL_TIME;
3710 return IEEE80211_PROBE_DELAY + IEEE80211_CHANNEL_TIME;
3711 }
3712 @@ -696,7 +696,7 @@ static void ieee80211_scan_state_set_cha
3713 *
3714 * In any case, it is not necessary for a passive scan.
3715 */
3716 - if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
3717 + if (chan->flags & IEEE80211_CHAN_NO_IR ||
3718 !local->scan_req->n_ssids) {
3719 *next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
3720 local->next_scan_state = SCAN_DECISION;
3721 @@ -881,7 +881,7 @@ int ieee80211_request_ibss_scan(struct i
3722 struct ieee80211_channel *tmp_ch =
3723 &local->hw.wiphy->bands[band]->channels[i];
3724
3725 - if (tmp_ch->flags & (IEEE80211_CHAN_NO_IBSS |
3726 + if (tmp_ch->flags & (IEEE80211_CHAN_NO_IR |
3727 IEEE80211_CHAN_DISABLED))
3728 continue;
3729
3730 @@ -895,7 +895,7 @@ int ieee80211_request_ibss_scan(struct i
3731
3732 local->int_scan_req->n_channels = n_ch;
3733 } else {
3734 - if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IBSS |
3735 + if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IR |
3736 IEEE80211_CHAN_DISABLED)))
3737 goto unlock;
3738
3739 --- a/net/mac80211/tx.c
3740 +++ b/net/mac80211/tx.c
3741 @@ -1728,8 +1728,7 @@ netdev_tx_t ieee80211_monitor_start_xmit
3742 * radar detection by itself. We can do that later by adding a
3743 * monitor flag interfaces used for AP support.
3744 */
3745 - if ((chan->flags & (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_RADAR |
3746 - IEEE80211_CHAN_PASSIVE_SCAN)))
3747 + if ((chan->flags & (IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_RADAR)))
3748 goto fail_rcu;
3749
3750 ieee80211_xmit(sdata, skb, chan->band);
3751 --- a/net/mac80211/util.c
3752 +++ b/net/mac80211/util.c
3753 @@ -2259,14 +2259,17 @@ u64 ieee80211_calculate_rx_timestamp(str
3754 void ieee80211_dfs_cac_cancel(struct ieee80211_local *local)
3755 {
3756 struct ieee80211_sub_if_data *sdata;
3757 + struct cfg80211_chan_def chandef;
3758
3759 mutex_lock(&local->iflist_mtx);
3760 list_for_each_entry(sdata, &local->interfaces, list) {
3761 cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
3762
3763 if (sdata->wdev.cac_started) {
3764 + chandef = sdata->vif.bss_conf.chandef;
3765 ieee80211_vif_release_channel(sdata);
3766 cfg80211_cac_event(sdata->dev,
3767 + &chandef,
3768 NL80211_RADAR_CAC_ABORTED,
3769 GFP_KERNEL);
3770 }
3771 @@ -2459,14 +2462,9 @@ int ieee80211_send_action_csa(struct iee
3772 WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT : 0x00;
3773 put_unaligned_le16(WLAN_REASON_MESH_CHAN, pos); /* Reason Cd */
3774 pos += 2;
3775 - if (!ifmsh->pre_value)
3776 - ifmsh->pre_value = 1;
3777 - else
3778 - ifmsh->pre_value++;
3779 pre_value = cpu_to_le16(ifmsh->pre_value);
3780 memcpy(pos, &pre_value, 2); /* Precedence Value */
3781 pos += 2;
3782 - ifmsh->chsw_init = true;
3783 }
3784
3785 ieee80211_tx_skb(sdata, skb);
3786 --- a/net/wireless/chan.c
3787 +++ b/net/wireless/chan.c
3788 @@ -277,6 +277,32 @@ void cfg80211_set_dfs_state(struct wiphy
3789 width, dfs_state);
3790 }
3791
3792 +static u32 cfg80211_get_start_freq(u32 center_freq,
3793 + u32 bandwidth)
3794 +{
3795 + u32 start_freq;
3796 +
3797 + if (bandwidth <= 20)
3798 + start_freq = center_freq;
3799 + else
3800 + start_freq = center_freq - bandwidth/2 + 10;
3801 +
3802 + return start_freq;
3803 +}
3804 +
3805 +static u32 cfg80211_get_end_freq(u32 center_freq,
3806 + u32 bandwidth)
3807 +{
3808 + u32 end_freq;
3809 +
3810 + if (bandwidth <= 20)
3811 + end_freq = center_freq;
3812 + else
3813 + end_freq = center_freq + bandwidth/2 - 10;
3814 +
3815 + return end_freq;
3816 +}
3817 +
3818 static int cfg80211_get_chans_dfs_required(struct wiphy *wiphy,
3819 u32 center_freq,
3820 u32 bandwidth)
3821 @@ -284,13 +310,8 @@ static int cfg80211_get_chans_dfs_requir
3822 struct ieee80211_channel *c;
3823 u32 freq, start_freq, end_freq;
3824
3825 - if (bandwidth <= 20) {
3826 - start_freq = center_freq;
3827 - end_freq = center_freq;
3828 - } else {
3829 - start_freq = center_freq - bandwidth/2 + 10;
3830 - end_freq = center_freq + bandwidth/2 - 10;
3831 - }
3832 + start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
3833 + end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
3834
3835 for (freq = start_freq; freq <= end_freq; freq += 20) {
3836 c = ieee80211_get_channel(wiphy, freq);
3837 @@ -330,33 +351,159 @@ int cfg80211_chandef_dfs_required(struct
3838 }
3839 EXPORT_SYMBOL(cfg80211_chandef_dfs_required);
3840
3841 -static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
3842 - u32 center_freq, u32 bandwidth,
3843 - u32 prohibited_flags)
3844 +static int cfg80211_get_chans_dfs_usable(struct wiphy *wiphy,
3845 + u32 center_freq,
3846 + u32 bandwidth)
3847 {
3848 struct ieee80211_channel *c;
3849 u32 freq, start_freq, end_freq;
3850 + int count = 0;
3851
3852 - if (bandwidth <= 20) {
3853 - start_freq = center_freq;
3854 - end_freq = center_freq;
3855 - } else {
3856 - start_freq = center_freq - bandwidth/2 + 10;
3857 - end_freq = center_freq + bandwidth/2 - 10;
3858 + start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
3859 + end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
3860 +
3861 + /*
3862 + * Check entire range of channels for the bandwidth.
3863 + * Check all channels are DFS channels (DFS_USABLE or
3864 + * DFS_AVAILABLE). Return number of usable channels
3865 + * (require CAC). Allow DFS and non-DFS channel mix.
3866 + */
3867 + for (freq = start_freq; freq <= end_freq; freq += 20) {
3868 + c = ieee80211_get_channel(wiphy, freq);
3869 + if (!c)
3870 + return -EINVAL;
3871 +
3872 + if (c->flags & IEEE80211_CHAN_DISABLED)
3873 + return -EINVAL;
3874 +
3875 + if (c->flags & IEEE80211_CHAN_RADAR) {
3876 + if (c->dfs_state == NL80211_DFS_UNAVAILABLE)
3877 + return -EINVAL;
3878 +
3879 + if (c->dfs_state == NL80211_DFS_USABLE)
3880 + count++;
3881 + }
3882 + }
3883 +
3884 + return count;
3885 +}
3886 +
3887 +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
3888 + const struct cfg80211_chan_def *chandef)
3889 +{
3890 + int width;
3891 + int r1, r2 = 0;
3892 +
3893 + if (WARN_ON(!cfg80211_chandef_valid(chandef)))
3894 + return false;
3895 +
3896 + width = cfg80211_chandef_get_width(chandef);
3897 + if (width < 0)
3898 + return false;
3899 +
3900 + r1 = cfg80211_get_chans_dfs_usable(wiphy, chandef->center_freq1,
3901 + width);
3902 +
3903 + if (r1 < 0)
3904 + return false;
3905 +
3906 + switch (chandef->width) {
3907 + case NL80211_CHAN_WIDTH_80P80:
3908 + WARN_ON(!chandef->center_freq2);
3909 + r2 = cfg80211_get_chans_dfs_usable(wiphy,
3910 + chandef->center_freq2,
3911 + width);
3912 + if (r2 < 0)
3913 + return false;
3914 + break;
3915 + default:
3916 + WARN_ON(chandef->center_freq2);
3917 + break;
3918 }
3919
3920 + return (r1 + r2 > 0);
3921 +}
3922 +
3923 +
3924 +static bool cfg80211_get_chans_dfs_available(struct wiphy *wiphy,
3925 + u32 center_freq,
3926 + u32 bandwidth)
3927 +{
3928 + struct ieee80211_channel *c;
3929 + u32 freq, start_freq, end_freq;
3930 +
3931 + start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
3932 + end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
3933 +
3934 + /*
3935 + * Check entire range of channels for the bandwidth.
3936 + * If any channel in between is disabled or has not
3937 + * had gone through CAC return false
3938 + */
3939 for (freq = start_freq; freq <= end_freq; freq += 20) {
3940 c = ieee80211_get_channel(wiphy, freq);
3941 if (!c)
3942 return false;
3943
3944 - /* check for radar flags */
3945 - if ((prohibited_flags & c->flags & IEEE80211_CHAN_RADAR) &&
3946 + if (c->flags & IEEE80211_CHAN_DISABLED)
3947 + return false;
3948 +
3949 + if ((c->flags & IEEE80211_CHAN_RADAR) &&
3950 (c->dfs_state != NL80211_DFS_AVAILABLE))
3951 return false;
3952 + }
3953 +
3954 + return true;
3955 +}
3956 +
3957 +static bool cfg80211_chandef_dfs_available(struct wiphy *wiphy,
3958 + const struct cfg80211_chan_def *chandef)
3959 +{
3960 + int width;
3961 + int r;
3962 +
3963 + if (WARN_ON(!cfg80211_chandef_valid(chandef)))
3964 + return false;
3965
3966 - /* check for the other flags */
3967 - if (c->flags & prohibited_flags & ~IEEE80211_CHAN_RADAR)
3968 + width = cfg80211_chandef_get_width(chandef);
3969 + if (width < 0)
3970 + return false;
3971 +
3972 + r = cfg80211_get_chans_dfs_available(wiphy, chandef->center_freq1,
3973 + width);
3974 +
3975 + /* If any of channels unavailable for cf1 just return */
3976 + if (!r)
3977 + return r;
3978 +
3979 + switch (chandef->width) {
3980 + case NL80211_CHAN_WIDTH_80P80:
3981 + WARN_ON(!chandef->center_freq2);
3982 + r = cfg80211_get_chans_dfs_available(wiphy,
3983 + chandef->center_freq2,
3984 + width);
3985 + default:
3986 + WARN_ON(chandef->center_freq2);
3987 + break;
3988 + }
3989 +
3990 + return r;
3991 +}
3992 +
3993 +
3994 +static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
3995 + u32 center_freq, u32 bandwidth,
3996 + u32 prohibited_flags)
3997 +{
3998 + struct ieee80211_channel *c;
3999 + u32 freq, start_freq, end_freq;
4000 +
4001 + start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
4002 + end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
4003 +
4004 + for (freq = start_freq; freq <= end_freq; freq += 20) {
4005 + c = ieee80211_get_channel(wiphy, freq);
4006 + if (!c || c->flags & prohibited_flags)
4007 return false;
4008 }
4009
4010 @@ -462,14 +609,19 @@ bool cfg80211_reg_can_beacon(struct wiph
4011 struct cfg80211_chan_def *chandef)
4012 {
4013 bool res;
4014 + u32 prohibited_flags = IEEE80211_CHAN_DISABLED |
4015 + IEEE80211_CHAN_NO_IR |
4016 + IEEE80211_CHAN_RADAR;
4017
4018 trace_cfg80211_reg_can_beacon(wiphy, chandef);
4019
4020 - res = cfg80211_chandef_usable(wiphy, chandef,
4021 - IEEE80211_CHAN_DISABLED |
4022 - IEEE80211_CHAN_PASSIVE_SCAN |
4023 - IEEE80211_CHAN_NO_IBSS |
4024 - IEEE80211_CHAN_RADAR);
4025 + if (cfg80211_chandef_dfs_required(wiphy, chandef) > 0 &&
4026 + cfg80211_chandef_dfs_available(wiphy, chandef)) {
4027 + /* We can skip IEEE80211_CHAN_NO_IR if chandef dfs available */
4028 + prohibited_flags = IEEE80211_CHAN_DISABLED;
4029 + }
4030 +
4031 + res = cfg80211_chandef_usable(wiphy, chandef, prohibited_flags);
4032
4033 trace_cfg80211_return_bool(res);
4034 return res;
4035 --- a/net/wireless/core.h
4036 +++ b/net/wireless/core.h
4037 @@ -382,6 +382,19 @@ int cfg80211_can_use_iftype_chan(struct
4038 enum cfg80211_chan_mode chanmode,
4039 u8 radar_detect);
4040
4041 +/**
4042 + * cfg80211_chandef_dfs_usable - checks if chandef is DFS usable
4043 + * @wiphy: the wiphy to validate against
4044 + * @chandef: the channel definition to check
4045 + *
4046 + * Checks if chandef is usable and we can/need start CAC on such channel.
4047 + *
4048 + * Return: Return true if all channels available and at least
4049 + * one channel require CAC (NL80211_DFS_USABLE)
4050 + */
4051 +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
4052 + const struct cfg80211_chan_def *chandef);
4053 +
4054 void cfg80211_set_dfs_state(struct wiphy *wiphy,
4055 const struct cfg80211_chan_def *chandef,
4056 enum nl80211_dfs_state dfs_state);
4057 --- a/net/wireless/genregdb.awk
4058 +++ b/net/wireless/genregdb.awk
4059 @@ -107,10 +107,13 @@ active && /^[ \t]*\(/ {
4060 } else if (flagarray[arg] == "PTMP-ONLY") {
4061 flags = flags "\n\t\t\tNL80211_RRF_PTMP_ONLY | "
4062 } else if (flagarray[arg] == "PASSIVE-SCAN") {
4063 - flags = flags "\n\t\t\tNL80211_RRF_PASSIVE_SCAN | "
4064 + flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
4065 } else if (flagarray[arg] == "NO-IBSS") {
4066 - flags = flags "\n\t\t\tNL80211_RRF_NO_IBSS | "
4067 + flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
4068 + } else if (flagarray[arg] == "NO-IR") {
4069 + flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
4070 }
4071 +
4072 }
4073 flags = flags "0"
4074 printf "\t\tREG_RULE(%d, %d, %d, %d, %d, %s),\n", start, end, bw, gain, power, flags
4075 --- a/net/wireless/ibss.c
4076 +++ b/net/wireless/ibss.c
4077 @@ -274,7 +274,7 @@ int cfg80211_ibss_wext_join(struct cfg80
4078
4079 for (i = 0; i < sband->n_channels; i++) {
4080 chan = &sband->channels[i];
4081 - if (chan->flags & IEEE80211_CHAN_NO_IBSS)
4082 + if (chan->flags & IEEE80211_CHAN_NO_IR)
4083 continue;
4084 if (chan->flags & IEEE80211_CHAN_DISABLED)
4085 continue;
4086 @@ -345,7 +345,7 @@ int cfg80211_ibss_wext_siwfreq(struct ne
4087 chan = ieee80211_get_channel(wdev->wiphy, freq);
4088 if (!chan)
4089 return -EINVAL;
4090 - if (chan->flags & IEEE80211_CHAN_NO_IBSS ||
4091 + if (chan->flags & IEEE80211_CHAN_NO_IR ||
4092 chan->flags & IEEE80211_CHAN_DISABLED)
4093 return -EINVAL;
4094 }
4095 --- a/net/wireless/mesh.c
4096 +++ b/net/wireless/mesh.c
4097 @@ -141,8 +141,7 @@ int __cfg80211_join_mesh(struct cfg80211
4098
4099 for (i = 0; i < sband->n_channels; i++) {
4100 chan = &sband->channels[i];
4101 - if (chan->flags & (IEEE80211_CHAN_NO_IBSS |
4102 - IEEE80211_CHAN_PASSIVE_SCAN |
4103 + if (chan->flags & (IEEE80211_CHAN_NO_IR |
4104 IEEE80211_CHAN_DISABLED |
4105 IEEE80211_CHAN_RADAR))
4106 continue;
4107 --- a/net/wireless/mlme.c
4108 +++ b/net/wireless/mlme.c
4109 @@ -763,12 +763,12 @@ void cfg80211_radar_event(struct wiphy *
4110 EXPORT_SYMBOL(cfg80211_radar_event);
4111
4112 void cfg80211_cac_event(struct net_device *netdev,
4113 + const struct cfg80211_chan_def *chandef,
4114 enum nl80211_radar_event event, gfp_t gfp)
4115 {
4116 struct wireless_dev *wdev = netdev->ieee80211_ptr;
4117 struct wiphy *wiphy = wdev->wiphy;
4118 struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
4119 - struct cfg80211_chan_def chandef;
4120 unsigned long timeout;
4121
4122 trace_cfg80211_cac_event(netdev, event);
4123 @@ -779,14 +779,12 @@ void cfg80211_cac_event(struct net_devic
4124 if (WARN_ON(!wdev->channel))
4125 return;
4126
4127 - cfg80211_chandef_create(&chandef, wdev->channel, NL80211_CHAN_NO_HT);
4128 -
4129 switch (event) {
4130 case NL80211_RADAR_CAC_FINISHED:
4131 timeout = wdev->cac_start_time +
4132 msecs_to_jiffies(IEEE80211_DFS_MIN_CAC_TIME_MS);
4133 WARN_ON(!time_after_eq(jiffies, timeout));
4134 - cfg80211_set_dfs_state(wiphy, &chandef, NL80211_DFS_AVAILABLE);
4135 + cfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_AVAILABLE);
4136 break;
4137 case NL80211_RADAR_CAC_ABORTED:
4138 break;
4139 @@ -796,6 +794,6 @@ void cfg80211_cac_event(struct net_devic
4140 }
4141 wdev->cac_started = false;
4142
4143 - nl80211_radar_notify(rdev, &chandef, event, netdev, gfp);
4144 + nl80211_radar_notify(rdev, chandef, event, netdev, gfp);
4145 }
4146 EXPORT_SYMBOL(cfg80211_cac_event);
4147 --- a/net/wireless/nl80211.c
4148 +++ b/net/wireless/nl80211.c
4149 @@ -545,12 +545,12 @@ static int nl80211_msg_put_channel(struc
4150 if ((chan->flags & IEEE80211_CHAN_DISABLED) &&
4151 nla_put_flag(msg, NL80211_FREQUENCY_ATTR_DISABLED))
4152 goto nla_put_failure;
4153 - if ((chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
4154 - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_PASSIVE_SCAN))
4155 - goto nla_put_failure;
4156 - if ((chan->flags & IEEE80211_CHAN_NO_IBSS) &&
4157 - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IBSS))
4158 - goto nla_put_failure;
4159 + if (chan->flags & IEEE80211_CHAN_NO_IR) {
4160 + if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IR))
4161 + goto nla_put_failure;
4162 + if (nla_put_flag(msg, __NL80211_FREQUENCY_ATTR_NO_IBSS))
4163 + goto nla_put_failure;
4164 + }
4165 if (chan->flags & IEEE80211_CHAN_RADAR) {
4166 if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_RADAR))
4167 goto nla_put_failure;
4168 @@ -1229,7 +1229,8 @@ static int nl80211_send_wiphy(struct cfg
4169 nla_put_flag(msg, NL80211_ATTR_TDLS_EXTERNAL_SETUP))
4170 goto nla_put_failure;
4171 if ((dev->wiphy.flags & WIPHY_FLAG_SUPPORTS_5_10_MHZ) &&
4172 - nla_put_flag(msg, WIPHY_FLAG_SUPPORTS_5_10_MHZ))
4173 + (nla_put_flag(msg, NL80211_ATTR_SUPPORT_5_MHZ) ||
4174 + nla_put_flag(msg, NL80211_ATTR_SUPPORT_10_MHZ)))
4175 goto nla_put_failure;
4176
4177 state->split_start++;
4178 @@ -2170,7 +2171,7 @@ static inline u64 wdev_id(struct wireles
4179 }
4180
4181 static int nl80211_send_chandef(struct sk_buff *msg,
4182 - struct cfg80211_chan_def *chandef)
4183 + const struct cfg80211_chan_def *chandef)
4184 {
4185 WARN_ON(!cfg80211_chandef_valid(chandef));
4186
4187 @@ -3219,6 +3220,7 @@ static int nl80211_start_ap(struct sk_bu
4188 return PTR_ERR(params.acl);
4189 }
4190
4191 + wdev_lock(wdev);
4192 err = rdev_start_ap(rdev, dev, &params);
4193 if (!err) {
4194 wdev->preset_chandef = params.chandef;
4195 @@ -3227,6 +3229,7 @@ static int nl80211_start_ap(struct sk_bu
4196 wdev->ssid_len = params.ssid_len;
4197 memcpy(wdev->ssid, params.ssid, wdev->ssid_len);
4198 }
4199 + wdev_unlock(wdev);
4200
4201 kfree(params.acl);
4202
4203 @@ -3255,7 +3258,11 @@ static int nl80211_set_beacon(struct sk_
4204 if (err)
4205 return err;
4206
4207 - return rdev_change_beacon(rdev, dev, &params);
4208 + wdev_lock(wdev);
4209 + err = rdev_change_beacon(rdev, dev, &params);
4210 + wdev_unlock(wdev);
4211 +
4212 + return err;
4213 }
4214
4215 static int nl80211_stop_ap(struct sk_buff *skb, struct genl_info *info)
4216 @@ -4461,7 +4468,9 @@ static int nl80211_set_bss(struct sk_buf
4217 {
4218 struct cfg80211_registered_device *rdev = info->user_ptr[0];
4219 struct net_device *dev = info->user_ptr[1];
4220 + struct wireless_dev *wdev = dev->ieee80211_ptr;
4221 struct bss_parameters params;
4222 + int err;
4223
4224 memset(&params, 0, sizeof(params));
4225 /* default to not changing parameters */
4226 @@ -4527,7 +4536,11 @@ static int nl80211_set_bss(struct sk_buf
4227 dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO)
4228 return -EOPNOTSUPP;
4229
4230 - return rdev_change_bss(rdev, dev, &params);
4231 + wdev_lock(wdev);
4232 + err = rdev_change_bss(rdev, dev, &params);
4233 + wdev_unlock(wdev);
4234 +
4235 + return err;
4236 }
4237
4238 static const struct nla_policy reg_rule_policy[NL80211_REG_RULE_ATTR_MAX + 1] = {
4239 @@ -5653,7 +5666,7 @@ static int nl80211_start_radar_detection
4240 if (err == 0)
4241 return -EINVAL;
4242
4243 - if (chandef.chan->dfs_state != NL80211_DFS_USABLE)
4244 + if (!cfg80211_chandef_dfs_usable(wdev->wiphy, &chandef))
4245 return -EINVAL;
4246
4247 if (!rdev->ops->start_radar_detection)
4248 @@ -5793,7 +5806,11 @@ skip_beacons:
4249 if (info->attrs[NL80211_ATTR_CH_SWITCH_BLOCK_TX])
4250 params.block_tx = true;
4251
4252 - return rdev_channel_switch(rdev, dev, &params);
4253 + wdev_lock(wdev);
4254 + err = rdev_channel_switch(rdev, dev, &params);
4255 + wdev_unlock(wdev);
4256 +
4257 + return err;
4258 }
4259
4260 static int nl80211_send_bss(struct sk_buff *msg, struct netlink_callback *cb,
4261 @@ -10809,21 +10826,18 @@ void cfg80211_ch_switch_notify(struct ne
4262 struct wiphy *wiphy = wdev->wiphy;
4263 struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
4264
4265 - trace_cfg80211_ch_switch_notify(dev, chandef);
4266 + ASSERT_WDEV_LOCK(wdev);
4267
4268 - wdev_lock(wdev);
4269 + trace_cfg80211_ch_switch_notify(dev, chandef);
4270
4271 if (WARN_ON(wdev->iftype != NL80211_IFTYPE_AP &&
4272 wdev->iftype != NL80211_IFTYPE_P2P_GO &&
4273 wdev->iftype != NL80211_IFTYPE_ADHOC &&
4274 wdev->iftype != NL80211_IFTYPE_MESH_POINT))
4275 - goto out;
4276 + return;
4277
4278 wdev->channel = chandef->chan;
4279 nl80211_ch_switch_notify(rdev, dev, chandef, GFP_KERNEL);
4280 -out:
4281 - wdev_unlock(wdev);
4282 - return;
4283 }
4284 EXPORT_SYMBOL(cfg80211_ch_switch_notify);
4285
4286 @@ -10882,7 +10896,7 @@ EXPORT_SYMBOL(cfg80211_cqm_txe_notify);
4287
4288 void
4289 nl80211_radar_notify(struct cfg80211_registered_device *rdev,
4290 - struct cfg80211_chan_def *chandef,
4291 + const struct cfg80211_chan_def *chandef,
4292 enum nl80211_radar_event event,
4293 struct net_device *netdev, gfp_t gfp)
4294 {
4295 --- a/net/wireless/nl80211.h
4296 +++ b/net/wireless/nl80211.h
4297 @@ -70,7 +70,7 @@ int nl80211_send_mgmt(struct cfg80211_re
4298
4299 void
4300 nl80211_radar_notify(struct cfg80211_registered_device *rdev,
4301 - struct cfg80211_chan_def *chandef,
4302 + const struct cfg80211_chan_def *chandef,
4303 enum nl80211_radar_event event,
4304 struct net_device *netdev, gfp_t gfp);
4305
4306 --- a/net/wireless/reg.c
4307 +++ b/net/wireless/reg.c
4308 @@ -163,35 +163,29 @@ static const struct ieee80211_regdomain
4309 REG_RULE(2412-10, 2462+10, 40, 6, 20, 0),
4310 /* IEEE 802.11b/g, channels 12..13. */
4311 REG_RULE(2467-10, 2472+10, 40, 6, 20,
4312 - NL80211_RRF_PASSIVE_SCAN |
4313 - NL80211_RRF_NO_IBSS),
4314 + NL80211_RRF_NO_IR),
4315 /* IEEE 802.11 channel 14 - Only JP enables
4316 * this and for 802.11b only */
4317 REG_RULE(2484-10, 2484+10, 20, 6, 20,
4318 - NL80211_RRF_PASSIVE_SCAN |
4319 - NL80211_RRF_NO_IBSS |
4320 + NL80211_RRF_NO_IR |
4321 NL80211_RRF_NO_OFDM),
4322 /* IEEE 802.11a, channel 36..48 */
4323 REG_RULE(5180-10, 5240+10, 160, 6, 20,
4324 - NL80211_RRF_PASSIVE_SCAN |
4325 - NL80211_RRF_NO_IBSS),
4326 + NL80211_RRF_NO_IR),
4327
4328 /* IEEE 802.11a, channel 52..64 - DFS required */
4329 REG_RULE(5260-10, 5320+10, 160, 6, 20,
4330 - NL80211_RRF_PASSIVE_SCAN |
4331 - NL80211_RRF_NO_IBSS |
4332 + NL80211_RRF_NO_IR |
4333 NL80211_RRF_DFS),
4334
4335 /* IEEE 802.11a, channel 100..144 - DFS required */
4336 REG_RULE(5500-10, 5720+10, 160, 6, 20,
4337 - NL80211_RRF_PASSIVE_SCAN |
4338 - NL80211_RRF_NO_IBSS |
4339 + NL80211_RRF_NO_IR |
4340 NL80211_RRF_DFS),
4341
4342 /* IEEE 802.11a, channel 149..165 */
4343 REG_RULE(5745-10, 5825+10, 80, 6, 20,
4344 - NL80211_RRF_PASSIVE_SCAN |
4345 - NL80211_RRF_NO_IBSS),
4346 + NL80211_RRF_NO_IR),
4347
4348 /* IEEE 802.11ad (60gHz), channels 1..3 */
4349 REG_RULE(56160+2160*1-1080, 56160+2160*3+1080, 2160, 0, 0, 0),
4350 @@ -698,10 +692,8 @@ regdom_intersect(const struct ieee80211_
4351 static u32 map_regdom_flags(u32 rd_flags)
4352 {
4353 u32 channel_flags = 0;
4354 - if (rd_flags & NL80211_RRF_PASSIVE_SCAN)
4355 - channel_flags |= IEEE80211_CHAN_PASSIVE_SCAN;
4356 - if (rd_flags & NL80211_RRF_NO_IBSS)
4357 - channel_flags |= IEEE80211_CHAN_NO_IBSS;
4358 + if (rd_flags & NL80211_RRF_NO_IR_ALL)
4359 + channel_flags |= IEEE80211_CHAN_NO_IR;
4360 if (rd_flags & NL80211_RRF_DFS)
4361 channel_flags |= IEEE80211_CHAN_RADAR;
4362 if (rd_flags & NL80211_RRF_NO_OFDM)
4363 @@ -1066,13 +1058,8 @@ static void handle_reg_beacon(struct wip
4364 chan_before.center_freq = chan->center_freq;
4365 chan_before.flags = chan->flags;
4366
4367 - if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
4368 - chan->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
4369 - channel_changed = true;
4370 - }
4371 -
4372 - if (chan->flags & IEEE80211_CHAN_NO_IBSS) {
4373 - chan->flags &= ~IEEE80211_CHAN_NO_IBSS;
4374 + if (chan->flags & IEEE80211_CHAN_NO_IR) {
4375 + chan->flags &= ~IEEE80211_CHAN_NO_IR;
4376 channel_changed = true;
4377 }
4378
4379 --- /dev/null
4380 +++ b/drivers/net/wireless/ath/ath9k/ar9003_wow.c
4381 @@ -0,0 +1,422 @@
4382 +/*
4383 + * Copyright (c) 2012 Qualcomm Atheros, Inc.
4384 + *
4385 + * Permission to use, copy, modify, and/or distribute this software for any
4386 + * purpose with or without fee is hereby granted, provided that the above
4387 + * copyright notice and this permission notice appear in all copies.
4388 + *
4389 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
4390 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
4391 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
4392 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
4393 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
4394 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
4395 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
4396 + */
4397 +
4398 +#include <linux/export.h>
4399 +#include "ath9k.h"
4400 +#include "reg.h"
4401 +#include "hw-ops.h"
4402 +
4403 +const char *ath9k_hw_wow_event_to_string(u32 wow_event)
4404 +{
4405 + if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
4406 + return "Magic pattern";
4407 + if (wow_event & AH_WOW_USER_PATTERN_EN)
4408 + return "User pattern";
4409 + if (wow_event & AH_WOW_LINK_CHANGE)
4410 + return "Link change";
4411 + if (wow_event & AH_WOW_BEACON_MISS)
4412 + return "Beacon miss";
4413 +
4414 + return "unknown reason";
4415 +}
4416 +EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
4417 +
4418 +static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
4419 +{
4420 + struct ath_common *common = ath9k_hw_common(ah);
4421 +
4422 + REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
4423 +
4424 + /* set rx disable bit */
4425 + REG_WRITE(ah, AR_CR, AR_CR_RXD);
4426 +
4427 + if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
4428 + ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
4429 + REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
4430 + return;
4431 + }
4432 +
4433 + REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
4434 +}
4435 +
4436 +static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
4437 +{
4438 + struct ath_common *common = ath9k_hw_common(ah);
4439 + u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
4440 + u32 ctl[13] = {0};
4441 + u32 data_word[KAL_NUM_DATA_WORDS];
4442 + u8 i;
4443 + u32 wow_ka_data_word0;
4444 +
4445 + memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
4446 + memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
4447 +
4448 + /* set the transmit buffer */
4449 + ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
4450 + ctl[1] = 0;
4451 + ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */
4452 + ctl[4] = 0;
4453 + ctl[7] = (ah->txchainmask) << 2;
4454 + ctl[2] = 0xf << 16; /* tx_tries 0 */
4455 +
4456 + for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
4457 + REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
4458 +
4459 + REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
4460 +
4461 + data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
4462 + (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
4463 + data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
4464 + (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
4465 + data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
4466 + (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
4467 + data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
4468 + (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
4469 + data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
4470 + (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
4471 + data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
4472 +
4473 + if (AR_SREV_9462_20(ah)) {
4474 + /* AR9462 2.0 has an extra descriptor word (time based
4475 + * discard) compared to other chips */
4476 + REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
4477 + wow_ka_data_word0 = AR_WOW_TXBUF(13);
4478 + } else {
4479 + wow_ka_data_word0 = AR_WOW_TXBUF(12);
4480 + }
4481 +
4482 + for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
4483 + REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
4484 +
4485 +}
4486 +
4487 +void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
4488 + u8 *user_mask, int pattern_count,
4489 + int pattern_len)
4490 +{
4491 + int i;
4492 + u32 pattern_val, mask_val;
4493 + u32 set, clr;
4494 +
4495 + /* FIXME: should check count by querying the hardware capability */
4496 + if (pattern_count >= MAX_NUM_PATTERN)
4497 + return;
4498 +
4499 + REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
4500 +
4501 + /* set the registers for pattern */
4502 + for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
4503 + memcpy(&pattern_val, user_pattern, 4);
4504 + REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
4505 + pattern_val);
4506 + user_pattern += 4;
4507 + }
4508 +
4509 + /* set the registers for mask */
4510 + for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
4511 + memcpy(&mask_val, user_mask, 4);
4512 + REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
4513 + user_mask += 4;
4514 + }
4515 +
4516 + /* set the pattern length to be matched
4517 + *
4518 + * AR_WOW_LENGTH1_REG1
4519 + * bit 31:24 pattern 0 length
4520 + * bit 23:16 pattern 1 length
4521 + * bit 15:8 pattern 2 length
4522 + * bit 7:0 pattern 3 length
4523 + *
4524 + * AR_WOW_LENGTH1_REG2
4525 + * bit 31:24 pattern 4 length
4526 + * bit 23:16 pattern 5 length
4527 + * bit 15:8 pattern 6 length
4528 + * bit 7:0 pattern 7 length
4529 + *
4530 + * the below logic writes out the new
4531 + * pattern length for the corresponding
4532 + * pattern_count, while masking out the
4533 + * other fields
4534 + */
4535 +
4536 + ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
4537 +
4538 + if (pattern_count < 4) {
4539 + /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
4540 + set = (pattern_len & AR_WOW_LENGTH_MAX) <<
4541 + AR_WOW_LEN1_SHIFT(pattern_count);
4542 + clr = AR_WOW_LENGTH1_MASK(pattern_count);
4543 + REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
4544 + } else {
4545 + /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
4546 + set = (pattern_len & AR_WOW_LENGTH_MAX) <<
4547 + AR_WOW_LEN2_SHIFT(pattern_count);
4548 + clr = AR_WOW_LENGTH2_MASK(pattern_count);
4549 + REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
4550 + }
4551 +
4552 +}
4553 +EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
4554 +
4555 +u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
4556 +{
4557 + u32 wow_status = 0;
4558 + u32 val = 0, rval;
4559 +
4560 + /*
4561 + * read the WoW status register to know
4562 + * the wakeup reason
4563 + */
4564 + rval = REG_READ(ah, AR_WOW_PATTERN);
4565 + val = AR_WOW_STATUS(rval);
4566 +
4567 + /*
4568 + * mask only the WoW events that we have enabled. Sometimes
4569 + * we have spurious WoW events from the AR_WOW_PATTERN
4570 + * register. This mask will clean it up.
4571 + */
4572 +
4573 + val &= ah->wow_event_mask;
4574 +
4575 + if (val) {
4576 + if (val & AR_WOW_MAGIC_PAT_FOUND)
4577 + wow_status |= AH_WOW_MAGIC_PATTERN_EN;
4578 + if (AR_WOW_PATTERN_FOUND(val))
4579 + wow_status |= AH_WOW_USER_PATTERN_EN;
4580 + if (val & AR_WOW_KEEP_ALIVE_FAIL)
4581 + wow_status |= AH_WOW_LINK_CHANGE;
4582 + if (val & AR_WOW_BEACON_FAIL)
4583 + wow_status |= AH_WOW_BEACON_MISS;
4584 + }
4585 +
4586 + /*
4587 + * set and clear WOW_PME_CLEAR registers for the chip to
4588 + * generate next wow signal.
4589 + * disable D3 before accessing other registers ?
4590 + */
4591 +
4592 + /* do we need to check the bit value 0x01000000 (7-10) ?? */
4593 + REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
4594 + AR_PMCTRL_PWR_STATE_D1D3);
4595 +
4596 + /*
4597 + * clear all events
4598 + */
4599 + REG_WRITE(ah, AR_WOW_PATTERN,
4600 + AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
4601 +
4602 + /*
4603 + * restore the beacon threshold to init value
4604 + */
4605 + REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
4606 +
4607 + /*
4608 + * Restore the way the PCI-E reset, Power-On-Reset, external
4609 + * PCIE_POR_SHORT pins are tied to its original value.
4610 + * Previously just before WoW sleep, we untie the PCI-E
4611 + * reset to our Chip's Power On Reset so that any PCI-E
4612 + * reset from the bus will not reset our chip
4613 + */
4614 + if (ah->is_pciexpress)
4615 + ath9k_hw_configpcipowersave(ah, false);
4616 +
4617 + ah->wow_event_mask = 0;
4618 +
4619 + return wow_status;
4620 +}
4621 +EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
4622 +
4623 +void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
4624 +{
4625 + u32 wow_event_mask;
4626 + u32 set, clr;
4627 +
4628 + /*
4629 + * wow_event_mask is a mask to the AR_WOW_PATTERN register to
4630 + * indicate which WoW events we have enabled. The WoW events
4631 + * are from the 'pattern_enable' in this function and
4632 + * 'pattern_count' of ath9k_hw_wow_apply_pattern()
4633 + */
4634 + wow_event_mask = ah->wow_event_mask;
4635 +
4636 + /*
4637 + * Untie Power-on-Reset from the PCI-E-Reset. When we are in
4638 + * WOW sleep, we do want the Reset from the PCI-E to disturb
4639 + * our hw state
4640 + */
4641 + if (ah->is_pciexpress) {
4642 + /*
4643 + * we need to untie the internal POR (power-on-reset)
4644 + * to the external PCI-E reset. We also need to tie
4645 + * the PCI-E Phy reset to the PCI-E reset.
4646 + */
4647 + set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
4648 + clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
4649 + REG_RMW(ah, AR_WA, set, clr);
4650 + }
4651 +
4652 + /*
4653 + * set the power states appropriately and enable PME
4654 + */
4655 + set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
4656 + AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
4657 +
4658 + /*
4659 + * set and clear WOW_PME_CLEAR registers for the chip
4660 + * to generate next wow signal.
4661 + */
4662 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
4663 + clr = AR_PMCTRL_WOW_PME_CLR;
4664 + REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
4665 +
4666 + /*
4667 + * Setup for:
4668 + * - beacon misses
4669 + * - magic pattern
4670 + * - keep alive timeout
4671 + * - pattern matching
4672 + */
4673 +
4674 + /*
4675 + * Program default values for pattern backoff, aifs/slot/KAL count,
4676 + * beacon miss timeout, KAL timeout, etc.
4677 + */
4678 + set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
4679 + REG_SET_BIT(ah, AR_WOW_PATTERN, set);
4680 +
4681 + set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
4682 + AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
4683 + AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
4684 + REG_SET_BIT(ah, AR_WOW_COUNT, set);
4685 +
4686 + if (pattern_enable & AH_WOW_BEACON_MISS)
4687 + set = AR_WOW_BEACON_TIMO;
4688 + /* We are not using beacon miss, program a large value */
4689 + else
4690 + set = AR_WOW_BEACON_TIMO_MAX;
4691 +
4692 + REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
4693 +
4694 + /*
4695 + * Keep alive timo in ms except AR9280
4696 + */
4697 + if (!pattern_enable)
4698 + set = AR_WOW_KEEP_ALIVE_NEVER;
4699 + else
4700 + set = KAL_TIMEOUT * 32;
4701 +
4702 + REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
4703 +
4704 + /*
4705 + * Keep alive delay in us. based on 'power on clock',
4706 + * therefore in usec
4707 + */
4708 + set = KAL_DELAY * 1000;
4709 + REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
4710 +
4711 + /*
4712 + * Create keep alive pattern to respond to beacons
4713 + */
4714 + ath9k_wow_create_keep_alive_pattern(ah);
4715 +
4716 + /*
4717 + * Configure MAC WoW Registers
4718 + */
4719 + set = 0;
4720 + /* Send keep alive timeouts anyway */
4721 + clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
4722 +
4723 + if (pattern_enable & AH_WOW_LINK_CHANGE)
4724 + wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
4725 + else
4726 + set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
4727 +
4728 + set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
4729 + REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
4730 +
4731 + /*
4732 + * we are relying on a bmiss failure. ensure we have
4733 + * enough threshold to prevent false positives
4734 + */
4735 + REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
4736 + AR_WOW_BMISSTHRESHOLD);
4737 +
4738 + set = 0;
4739 + clr = 0;
4740 +
4741 + if (pattern_enable & AH_WOW_BEACON_MISS) {
4742 + set = AR_WOW_BEACON_FAIL_EN;
4743 + wow_event_mask |= AR_WOW_BEACON_FAIL;
4744 + } else {
4745 + clr = AR_WOW_BEACON_FAIL_EN;
4746 + }
4747 +
4748 + REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
4749 +
4750 + set = 0;
4751 + clr = 0;
4752 + /*
4753 + * Enable the magic packet registers
4754 + */
4755 + if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
4756 + set = AR_WOW_MAGIC_EN;
4757 + wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
4758 + } else {
4759 + clr = AR_WOW_MAGIC_EN;
4760 + }
4761 + set |= AR_WOW_MAC_INTR_EN;
4762 + REG_RMW(ah, AR_WOW_PATTERN, set, clr);
4763 +
4764 + REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
4765 + AR_WOW_PATTERN_SUPPORTED);
4766 +
4767 + /*
4768 + * Set the power states appropriately and enable PME
4769 + */
4770 + clr = 0;
4771 + set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
4772 + AR_PMCTRL_PWR_PM_CTRL_ENA;
4773 +
4774 + clr = AR_PCIE_PM_CTRL_ENA;
4775 + REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
4776 +
4777 + /*
4778 + * this is needed to prevent the chip waking up
4779 + * the host within 3-4 seconds with certain
4780 + * platform/BIOS. The fix is to enable
4781 + * D1 & D3 to match original definition and
4782 + * also match the OTP value. Anyway this
4783 + * is more related to SW WOW.
4784 + */
4785 + clr = AR_PMCTRL_PWR_STATE_D1D3;
4786 + REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
4787 +
4788 + set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
4789 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
4790 +
4791 + REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
4792 +
4793 + /* to bring down WOW power low margin */
4794 + set = BIT(13);
4795 + REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
4796 + /* HW WoW */
4797 + clr = BIT(5);
4798 + REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
4799 +
4800 + ath9k_hw_set_powermode_wow_sleep(ah);
4801 + ah->wow_event_mask = wow_event_mask;
4802 +}
4803 +EXPORT_SYMBOL(ath9k_hw_wow_enable);
4804 --- /dev/null
4805 +++ b/drivers/net/wireless/ath/ath9k/tx99.c
4806 @@ -0,0 +1,263 @@
4807 +/*
4808 + * Copyright (c) 2013 Qualcomm Atheros, Inc.
4809 + *
4810 + * Permission to use, copy, modify, and/or distribute this software for any
4811 + * purpose with or without fee is hereby granted, provided that the above
4812 + * copyright notice and this permission notice appear in all copies.
4813 + *
4814 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
4815 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
4816 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
4817 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
4818 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
4819 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
4820 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
4821 + */
4822 +
4823 +#include "ath9k.h"
4824 +
4825 +static void ath9k_tx99_stop(struct ath_softc *sc)
4826 +{
4827 + struct ath_hw *ah = sc->sc_ah;
4828 + struct ath_common *common = ath9k_hw_common(ah);
4829 +
4830 + ath_drain_all_txq(sc);
4831 + ath_startrecv(sc);
4832 +
4833 + ath9k_hw_set_interrupts(ah);
4834 + ath9k_hw_enable_interrupts(ah);
4835 +
4836 + ieee80211_wake_queues(sc->hw);
4837 +
4838 + kfree_skb(sc->tx99_skb);
4839 + sc->tx99_skb = NULL;
4840 + sc->tx99_state = false;
4841 +
4842 + ath9k_hw_tx99_stop(sc->sc_ah);
4843 + ath_dbg(common, XMIT, "TX99 stopped\n");
4844 +}
4845 +
4846 +static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
4847 +{
4848 + static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
4849 + 0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
4850 + 0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
4851 + 0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
4852 + 0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
4853 + 0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
4854 + 0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
4855 + 0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
4856 + u32 len = 1200;
4857 + struct ieee80211_hw *hw = sc->hw;
4858 + struct ieee80211_hdr *hdr;
4859 + struct ieee80211_tx_info *tx_info;
4860 + struct sk_buff *skb;
4861 +
4862 + skb = alloc_skb(len, GFP_KERNEL);
4863 + if (!skb)
4864 + return NULL;
4865 +
4866 + skb_put(skb, len);
4867 +
4868 + memset(skb->data, 0, len);
4869 +
4870 + hdr = (struct ieee80211_hdr *)skb->data;
4871 + hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
4872 + hdr->duration_id = 0;
4873 +
4874 + memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
4875 + memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
4876 + memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
4877 +
4878 + hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
4879 +
4880 + tx_info = IEEE80211_SKB_CB(skb);
4881 + memset(tx_info, 0, sizeof(*tx_info));
4882 + tx_info->band = hw->conf.chandef.chan->band;
4883 + tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
4884 + tx_info->control.vif = sc->tx99_vif;
4885 +
4886 + memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
4887 +
4888 + return skb;
4889 +}
4890 +
4891 +static void ath9k_tx99_deinit(struct ath_softc *sc)
4892 +{
4893 + ath_reset(sc);
4894 +
4895 + ath9k_ps_wakeup(sc);
4896 + ath9k_tx99_stop(sc);
4897 + ath9k_ps_restore(sc);
4898 +}
4899 +
4900 +static int ath9k_tx99_init(struct ath_softc *sc)
4901 +{
4902 + struct ieee80211_hw *hw = sc->hw;
4903 + struct ath_hw *ah = sc->sc_ah;
4904 + struct ath_common *common = ath9k_hw_common(ah);
4905 + struct ath_tx_control txctl;
4906 + int r;
4907 +
4908 + if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
4909 + ath_err(common,
4910 + "driver is in invalid state unable to use TX99");
4911 + return -EINVAL;
4912 + }
4913 +
4914 + sc->tx99_skb = ath9k_build_tx99_skb(sc);
4915 + if (!sc->tx99_skb)
4916 + return -ENOMEM;
4917 +
4918 + memset(&txctl, 0, sizeof(txctl));
4919 + txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
4920 +
4921 + ath_reset(sc);
4922 +
4923 + ath9k_ps_wakeup(sc);
4924 +
4925 + ath9k_hw_disable_interrupts(ah);
4926 + atomic_set(&ah->intr_ref_cnt, -1);
4927 + ath_drain_all_txq(sc);
4928 + ath_stoprecv(sc);
4929 +
4930 + sc->tx99_state = true;
4931 +
4932 + ieee80211_stop_queues(hw);
4933 +
4934 + if (sc->tx99_power == MAX_RATE_POWER + 1)
4935 + sc->tx99_power = MAX_RATE_POWER;
4936 +
4937 + ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
4938 + r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
4939 + if (r) {
4940 + ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
4941 + return r;
4942 + }
4943 +
4944 + ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
4945 + sc->tx99_power,
4946 + sc->tx99_power / 2);
4947 +
4948 + /* We leave the harware awake as it will be chugging on */
4949 +
4950 + return 0;
4951 +}
4952 +
4953 +static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
4954 + size_t count, loff_t *ppos)
4955 +{
4956 + struct ath_softc *sc = file->private_data;
4957 + char buf[3];
4958 + unsigned int len;
4959 +
4960 + len = sprintf(buf, "%d\n", sc->tx99_state);
4961 + return simple_read_from_buffer(user_buf, count, ppos, buf, len);
4962 +}
4963 +
4964 +static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
4965 + size_t count, loff_t *ppos)
4966 +{
4967 + struct ath_softc *sc = file->private_data;
4968 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4969 + char buf[32];
4970 + bool start;
4971 + ssize_t len;
4972 + int r;
4973 +
4974 + if (sc->nvifs > 1)
4975 + return -EOPNOTSUPP;
4976 +
4977 + len = min(count, sizeof(buf) - 1);
4978 + if (copy_from_user(buf, user_buf, len))
4979 + return -EFAULT;
4980 +
4981 + if (strtobool(buf, &start))
4982 + return -EINVAL;
4983 +
4984 + if (start == sc->tx99_state) {
4985 + if (!start)
4986 + return count;
4987 + ath_dbg(common, XMIT, "Resetting TX99\n");
4988 + ath9k_tx99_deinit(sc);
4989 + }
4990 +
4991 + if (!start) {
4992 + ath9k_tx99_deinit(sc);
4993 + return count;
4994 + }
4995 +
4996 + r = ath9k_tx99_init(sc);
4997 + if (r)
4998 + return r;
4999 +
5000 + return count;
5001 +}
5002 +
5003 +static const struct file_operations fops_tx99 = {
5004 + .read = read_file_tx99,
5005 + .write = write_file_tx99,
5006 + .open = simple_open,
5007 + .owner = THIS_MODULE,
5008 + .llseek = default_llseek,
5009 +};
5010 +
5011 +static ssize_t read_file_tx99_power(struct file *file,
5012 + char __user *user_buf,
5013 + size_t count, loff_t *ppos)
5014 +{
5015 + struct ath_softc *sc = file->private_data;
5016 + char buf[32];
5017 + unsigned int len;
5018 +
5019 + len = sprintf(buf, "%d (%d dBm)\n",
5020 + sc->tx99_power,
5021 + sc->tx99_power / 2);
5022 +
5023 + return simple_read_from_buffer(user_buf, count, ppos, buf, len);
5024 +}
5025 +
5026 +static ssize_t write_file_tx99_power(struct file *file,
5027 + const char __user *user_buf,
5028 + size_t count, loff_t *ppos)
5029 +{
5030 + struct ath_softc *sc = file->private_data;
5031 + int r;
5032 + u8 tx_power;
5033 +
5034 + r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
5035 + if (r)
5036 + return r;
5037 +
5038 + if (tx_power > MAX_RATE_POWER)
5039 + return -EINVAL;
5040 +
5041 + sc->tx99_power = tx_power;
5042 +
5043 + ath9k_ps_wakeup(sc);
5044 + ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
5045 + ath9k_ps_restore(sc);
5046 +
5047 + return count;
5048 +}
5049 +
5050 +static const struct file_operations fops_tx99_power = {
5051 + .read = read_file_tx99_power,
5052 + .write = write_file_tx99_power,
5053 + .open = simple_open,
5054 + .owner = THIS_MODULE,
5055 + .llseek = default_llseek,
5056 +};
5057 +
5058 +void ath9k_tx99_init_debug(struct ath_softc *sc)
5059 +{
5060 + if (!AR_SREV_9300_20_OR_LATER(sc->sc_ah))
5061 + return;
5062 +
5063 + debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
5064 + sc->debug.debugfs_phy, sc,
5065 + &fops_tx99);
5066 + debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
5067 + sc->debug.debugfs_phy, sc,
5068 + &fops_tx99_power);
5069 +}
5070 --- a/drivers/net/wireless/ath/ath9k/dfs_debug.c
5071 +++ b/drivers/net/wireless/ath/ath9k/dfs_debug.c
5072 @@ -44,14 +44,20 @@ static ssize_t read_file_dfs(struct file
5073 if (buf == NULL)
5074 return -ENOMEM;
5075
5076 - if (sc->dfs_detector)
5077 - dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
5078 -
5079 len += scnprintf(buf + len, size - len, "DFS support for "
5080 "macVersion = 0x%x, macRev = 0x%x: %s\n",
5081 hw_ver->macVersion, hw_ver->macRev,
5082 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
5083 "enabled" : "disabled");
5084 +
5085 + if (!sc->dfs_detector) {
5086 + len += scnprintf(buf + len, size - len,
5087 + "DFS detector not enabled\n");
5088 + goto exit;
5089 + }
5090 +
5091 + dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
5092 +
5093 len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
5094 ATH9K_DFS_STAT("pulse events reported ", pulses_total);
5095 ATH9K_DFS_STAT("invalid pulse events ", pulses_no_dfs);
5096 @@ -76,6 +82,7 @@ static ssize_t read_file_dfs(struct file
5097 ATH9K_DFS_POOL_STAT("Seqs. alloc error ", pseq_alloc_error);
5098 ATH9K_DFS_POOL_STAT("Seqs. in use ", pseq_used);
5099
5100 +exit:
5101 if (len > size)
5102 len = size;
5103
5104 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
5105 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
5106 @@ -641,11 +641,12 @@ static void ar9003_hw_override_ini(struc
5107 else
5108 ah->enabled_cals &= ~TX_IQ_CAL;
5109
5110 - if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
5111 - ah->enabled_cals |= TX_CL_CAL;
5112 - else
5113 - ah->enabled_cals &= ~TX_CL_CAL;
5114 }
5115 +
5116 + if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
5117 + ah->enabled_cals |= TX_CL_CAL;
5118 + else
5119 + ah->enabled_cals &= ~TX_CL_CAL;
5120 }
5121
5122 static void ar9003_hw_prog_ini(struct ath_hw *ah,
5123 @@ -701,6 +702,54 @@ static int ar9550_hw_get_modes_txgain_in
5124 return ret;
5125 }
5126
5127 +static void ar9003_doubler_fix(struct ath_hw *ah)
5128 +{
5129 + if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
5130 + REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
5131 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5132 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
5133 + REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
5134 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5135 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
5136 + REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
5137 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5138 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
5139 +
5140 + udelay(200);
5141 +
5142 + REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
5143 + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
5144 + REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
5145 + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
5146 + REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
5147 + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
5148 +
5149 + udelay(1);
5150 +
5151 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
5152 + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
5153 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
5154 + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
5155 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
5156 + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
5157 +
5158 + udelay(200);
5159 +
5160 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
5161 + AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
5162 +
5163 + REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
5164 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5165 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
5166 + REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
5167 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5168 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
5169 + REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
5170 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
5171 + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
5172 + }
5173 +}
5174 +
5175 static int ar9003_hw_process_ini(struct ath_hw *ah,
5176 struct ath9k_channel *chan)
5177 {
5178 @@ -726,6 +775,8 @@ static int ar9003_hw_process_ini(struct
5179 modesIndex);
5180 }
5181
5182 + ar9003_doubler_fix(ah);
5183 +
5184 /*
5185 * RXGAIN initvals.
5186 */
5187 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
5188 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
5189 @@ -656,13 +656,24 @@
5190 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
5191 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
5192 #define AR_PHY_65NM_CH0_SYNTH7 0x16098
5193 +#define AR_PHY_65NM_CH0_SYNTH12 0x160ac
5194 #define AR_PHY_65NM_CH0_BIAS1 0x160c0
5195 #define AR_PHY_65NM_CH0_BIAS2 0x160c4
5196 #define AR_PHY_65NM_CH0_BIAS4 0x160cc
5197 +#define AR_PHY_65NM_CH0_RXTX2 0x16104
5198 +#define AR_PHY_65NM_CH1_RXTX2 0x16504
5199 +#define AR_PHY_65NM_CH2_RXTX2 0x16904
5200 #define AR_PHY_65NM_CH0_RXTX4 0x1610c
5201 #define AR_PHY_65NM_CH1_RXTX4 0x1650c
5202 #define AR_PHY_65NM_CH2_RXTX4 0x1690c
5203
5204 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000
5205 +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19
5206 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004
5207 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2
5208 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008
5209 +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3
5210 +
5211 #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
5212 (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
5213 #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
5214 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c
5215 +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
5216 @@ -181,6 +181,7 @@ static void rt2x00lib_autowakeup(struct
5217 static void rt2x00lib_bc_buffer_iter(void *data, u8 *mac,
5218 struct ieee80211_vif *vif)
5219 {
5220 + struct ieee80211_tx_control control = {};
5221 struct rt2x00_dev *rt2x00dev = data;
5222 struct sk_buff *skb;
5223
5224 @@ -195,7 +196,7 @@ static void rt2x00lib_bc_buffer_iter(voi
5225 */
5226 skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
5227 while (skb) {
5228 - rt2x00mac_tx(rt2x00dev->hw, NULL, skb);
5229 + rt2x00mac_tx(rt2x00dev->hw, &control, skb);
5230 skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
5231 }
5232 }
5233 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
5234 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
5235 @@ -1040,14 +1040,14 @@ static void ar9003_hw_cl_cal_post_proc(s
5236 }
5237 }
5238
5239 -static bool ar9003_hw_init_cal(struct ath_hw *ah,
5240 - struct ath9k_channel *chan)
5241 +static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
5242 + struct ath9k_channel *chan)
5243 {
5244 struct ath_common *common = ath9k_hw_common(ah);
5245 struct ath9k_hw_cal_data *caldata = ah->caldata;
5246 bool txiqcal_done = false;
5247 bool is_reusable = true, status = true;
5248 - bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
5249 + bool run_rtt_cal = false, run_agc_cal;
5250 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
5251 u32 rx_delay = 0;
5252 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
5253 @@ -1119,22 +1119,12 @@ static bool ar9003_hw_init_cal(struct at
5254 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
5255 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
5256 txiqcal_done = run_agc_cal = true;
5257 - } else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
5258 - run_agc_cal = true;
5259 - sep_iq_cal = true;
5260 }
5261
5262 skip_tx_iqcal:
5263 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
5264 ar9003_mci_init_cal_req(ah, &is_reusable);
5265
5266 - if (sep_iq_cal) {
5267 - txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
5268 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
5269 - udelay(5);
5270 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
5271 - }
5272 -
5273 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
5274 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
5275 /* Disable BB_active */
5276 @@ -1228,13 +1218,109 @@ skip_tx_iqcal:
5277 return true;
5278 }
5279
5280 +static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
5281 + struct ath9k_channel *chan)
5282 +{
5283 + struct ath_common *common = ath9k_hw_common(ah);
5284 + struct ath9k_hw_cal_data *caldata = ah->caldata;
5285 + bool txiqcal_done = false;
5286 + bool is_reusable = true, status = true;
5287 + bool run_agc_cal = false, sep_iq_cal = false;
5288 +
5289 + /* Use chip chainmask only for calibration */
5290 + ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
5291 +
5292 + if (ah->enabled_cals & TX_CL_CAL) {
5293 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
5294 + run_agc_cal = true;
5295 + }
5296 +
5297 + if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
5298 + goto skip_tx_iqcal;
5299 +
5300 + /* Do Tx IQ Calibration */
5301 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
5302 + AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
5303 + DELPT);
5304 +
5305 + /*
5306 + * For AR9485 or later chips, TxIQ cal runs as part of
5307 + * AGC calibration. Specifically, AR9550 in SoC chips.
5308 + */
5309 + if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
5310 + txiqcal_done = true;
5311 + run_agc_cal = true;
5312 + } else {
5313 + sep_iq_cal = true;
5314 + run_agc_cal = true;
5315 + }
5316 +
5317 + /*
5318 + * In the SoC family, this will run for AR9300, AR9331 and AR9340.
5319 + */
5320 + if (sep_iq_cal) {
5321 + txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
5322 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
5323 + udelay(5);
5324 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
5325 + }
5326 +
5327 +skip_tx_iqcal:
5328 + if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
5329 + /* Calibrate the AGC */
5330 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5331 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
5332 + AR_PHY_AGC_CONTROL_CAL);
5333 +
5334 + /* Poll for offset calibration complete */
5335 + status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
5336 + AR_PHY_AGC_CONTROL_CAL,
5337 + 0, AH_WAIT_TIMEOUT);
5338 + }
5339 +
5340 + if (!status) {
5341 + ath_dbg(common, CALIBRATE,
5342 + "offset calibration failed to complete in %d ms; noisy environment?\n",
5343 + AH_WAIT_TIMEOUT / 1000);
5344 + return false;
5345 + }
5346 +
5347 + if (txiqcal_done)
5348 + ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
5349 +
5350 + /* Revert chainmask to runtime parameters */
5351 + ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
5352 +
5353 + /* Initialize list pointers */
5354 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
5355 +
5356 + INIT_CAL(&ah->iq_caldata);
5357 + INSERT_CAL(ah, &ah->iq_caldata);
5358 + ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
5359 +
5360 + /* Initialize current pointer to first element in list */
5361 + ah->cal_list_curr = ah->cal_list;
5362 +
5363 + if (ah->cal_list_curr)
5364 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
5365 +
5366 + if (caldata)
5367 + caldata->CalValid = 0;
5368 +
5369 + return true;
5370 +}
5371 +
5372 void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
5373 {
5374 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
5375 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
5376
5377 + if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
5378 + priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
5379 + else
5380 + priv_ops->init_cal = ar9003_hw_init_cal_soc;
5381 +
5382 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
5383 - priv_ops->init_cal = ar9003_hw_init_cal;
5384 priv_ops->setup_calibration = ar9003_hw_setup_calibration;
5385
5386 ops->calibrate = ar9003_hw_calibrate;
5387 --- a/drivers/net/wireless/ath/ath9k/common.c
5388 +++ b/drivers/net/wireless/ath/ath9k/common.c
5389 @@ -98,10 +98,8 @@ struct ath9k_channel *ath9k_cmn_get_chan
5390 {
5391 struct ieee80211_channel *curchan = chandef->chan;
5392 struct ath9k_channel *channel;
5393 - u8 chan_idx;
5394
5395 - chan_idx = curchan->hw_value;
5396 - channel = &ah->channels[chan_idx];
5397 + channel = &ah->channels[curchan->hw_value];
5398 ath9k_cmn_update_ichannel(channel, chandef);
5399
5400 return channel;
5401 --- a/net/mac80211/rc80211_minstrel_ht.c
5402 +++ b/net/mac80211/rc80211_minstrel_ht.c
5403 @@ -226,7 +226,7 @@ minstrel_ht_calc_tp(struct minstrel_ht_s
5404 nsecs = 1000 * mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
5405
5406 nsecs += minstrel_mcs_groups[group].duration[rate];
5407 - tp = 1000000 * ((mr->probability * 1000) / nsecs);
5408 + tp = 1000000 * ((prob * 1000) / nsecs);
5409
5410 mr->cur_tp = MINSTREL_TRUNC(tp);
5411 }
5412 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
5413 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
5414 @@ -3984,18 +3984,20 @@ static void ar9003_hw_quick_drop_apply(s
5415 int quick_drop;
5416 s32 t[3], f[3] = {5180, 5500, 5785};
5417
5418 - if (!(pBase->miscConfiguration & BIT(1)))
5419 + if (!(pBase->miscConfiguration & BIT(4)))
5420 return;
5421
5422 - if (freq < 4000)
5423 - quick_drop = eep->modalHeader2G.quick_drop;
5424 - else {
5425 - t[0] = eep->base_ext1.quick_drop_low;
5426 - t[1] = eep->modalHeader5G.quick_drop;
5427 - t[2] = eep->base_ext1.quick_drop_high;
5428 - quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
5429 + if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {
5430 + if (freq < 4000) {
5431 + quick_drop = eep->modalHeader2G.quick_drop;
5432 + } else {
5433 + t[0] = eep->base_ext1.quick_drop_low;
5434 + t[1] = eep->modalHeader5G.quick_drop;
5435 + t[2] = eep->base_ext1.quick_drop_high;
5436 + quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
5437 + }
5438 + REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
5439 }
5440 - REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
5441 }
5442
5443 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
5444 @@ -4035,7 +4037,7 @@ static void ar9003_hw_xlna_bias_strength
5445 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5446 u8 bias;
5447
5448 - if (!(eep->baseEepHeader.featureEnable & 0x40))
5449 + if (!(eep->baseEepHeader.miscConfiguration & 0x40))
5450 return;
5451
5452 if (!AR_SREV_9300(ah))
5453 --- a/net/mac80211/ieee80211_i.h
5454 +++ b/net/mac80211/ieee80211_i.h
5455 @@ -735,6 +735,7 @@ struct ieee80211_sub_if_data {
5456 int csa_counter_offset_beacon;
5457 int csa_counter_offset_presp;
5458 bool csa_radar_required;
5459 + struct cfg80211_chan_def csa_chandef;
5460
5461 /* used to reconfigure hardware SM PS */
5462 struct work_struct recalc_smps;
5463 @@ -811,6 +812,9 @@ static inline void sdata_unlock(struct i
5464 __release(&sdata->wdev.mtx);
5465 }
5466
5467 +#define sdata_dereference(p, sdata) \
5468 + rcu_dereference_protected(p, lockdep_is_held(&sdata->wdev.mtx))
5469 +
5470 static inline void
5471 sdata_assert_lock(struct ieee80211_sub_if_data *sdata)
5472 {
5473 @@ -1098,7 +1102,6 @@ struct ieee80211_local {
5474 enum mac80211_scan_state next_scan_state;
5475 struct delayed_work scan_work;
5476 struct ieee80211_sub_if_data __rcu *scan_sdata;
5477 - struct cfg80211_chan_def csa_chandef;
5478 /* For backward compatibility only -- do not use */
5479 struct cfg80211_chan_def _oper_chandef;
5480
5481 @@ -1236,6 +1239,7 @@ struct ieee80211_csa_ie {
5482 u8 mode;
5483 u8 count;
5484 u8 ttl;
5485 + u16 pre_value;
5486 };
5487
5488 /* Parsed Information Elements */
5489 @@ -1738,7 +1742,6 @@ ieee80211_vif_change_bandwidth(struct ie
5490 /* NOTE: only use ieee80211_vif_change_channel() for channel switch */
5491 int __must_check
5492 ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
5493 - const struct cfg80211_chan_def *chandef,
5494 u32 *changed);
5495 void ieee80211_vif_release_channel(struct ieee80211_sub_if_data *sdata);
5496 void ieee80211_vif_vlan_copy_chanctx(struct ieee80211_sub_if_data *sdata);
5497 --- a/net/mac80211/chan.c
5498 +++ b/net/mac80211/chan.c
5499 @@ -411,12 +411,12 @@ int ieee80211_vif_use_channel(struct iee
5500 }
5501
5502 int ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
5503 - const struct cfg80211_chan_def *chandef,
5504 u32 *changed)
5505 {
5506 struct ieee80211_local *local = sdata->local;
5507 struct ieee80211_chanctx_conf *conf;
5508 struct ieee80211_chanctx *ctx;
5509 + const struct cfg80211_chan_def *chandef = &sdata->csa_chandef;
5510 int ret;
5511 u32 chanctx_changed = 0;
5512
5513 --- a/net/mac80211/ibss.c
5514 +++ b/net/mac80211/ibss.c
5515 @@ -550,12 +550,12 @@ int ieee80211_ibss_finish_csa(struct iee
5516 capability);
5517 /* XXX: should not really modify cfg80211 data */
5518 if (cbss) {
5519 - cbss->channel = sdata->local->csa_chandef.chan;
5520 + cbss->channel = sdata->csa_chandef.chan;
5521 cfg80211_put_bss(sdata->local->hw.wiphy, cbss);
5522 }
5523 }
5524
5525 - ifibss->chandef = sdata->local->csa_chandef;
5526 + ifibss->chandef = sdata->csa_chandef;
5527
5528 /* generate the beacon */
5529 err = ieee80211_ibss_csa_beacon(sdata, NULL);
5530 @@ -922,7 +922,7 @@ ieee80211_ibss_process_chanswitch(struct
5531 IEEE80211_MAX_QUEUE_MAP,
5532 IEEE80211_QUEUE_STOP_REASON_CSA);
5533
5534 - sdata->local->csa_chandef = params.chandef;
5535 + sdata->csa_chandef = params.chandef;
5536 sdata->vif.csa_active = true;
5537
5538 ieee80211_bss_info_change_notify(sdata, err);
5539 --- a/net/mac80211/mesh.c
5540 +++ b/net/mac80211/mesh.c
5541 @@ -943,14 +943,19 @@ ieee80211_mesh_process_chnswitch(struct
5542 params.chandef.chan->center_freq);
5543
5544 params.block_tx = csa_ie.mode & WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT;
5545 - if (beacon)
5546 + if (beacon) {
5547 ifmsh->chsw_ttl = csa_ie.ttl - 1;
5548 - else
5549 - ifmsh->chsw_ttl = 0;
5550 + if (ifmsh->pre_value >= csa_ie.pre_value)
5551 + return false;
5552 + ifmsh->pre_value = csa_ie.pre_value;
5553 + }
5554
5555 - if (ifmsh->chsw_ttl > 0)
5556 + if (ifmsh->chsw_ttl < ifmsh->mshcfg.dot11MeshTTL) {
5557 if (ieee80211_mesh_csa_beacon(sdata, &params, false) < 0)
5558 return false;
5559 + } else {
5560 + return false;
5561 + }
5562
5563 sdata->csa_radar_required = params.radar_required;
5564
5565 @@ -959,7 +964,7 @@ ieee80211_mesh_process_chnswitch(struct
5566 IEEE80211_MAX_QUEUE_MAP,
5567 IEEE80211_QUEUE_STOP_REASON_CSA);
5568
5569 - sdata->local->csa_chandef = params.chandef;
5570 + sdata->csa_chandef = params.chandef;
5571 sdata->vif.csa_active = true;
5572
5573 ieee80211_bss_info_change_notify(sdata, err);
5574 @@ -1163,7 +1168,6 @@ static int mesh_fwd_csa_frame(struct iee
5575 offset_ttl = (len < 42) ? 7 : 10;
5576 *(pos + offset_ttl) -= 1;
5577 *(pos + offset_ttl + 1) &= ~WLAN_EID_CHAN_SWITCH_PARAM_INITIATOR;
5578 - sdata->u.mesh.chsw_ttl = *(pos + offset_ttl);
5579
5580 memcpy(mgmt_fwd, mgmt, len);
5581 eth_broadcast_addr(mgmt_fwd->da);
5582 @@ -1182,7 +1186,7 @@ static void mesh_rx_csa_frame(struct iee
5583 u16 pre_value;
5584 bool fwd_csa = true;
5585 size_t baselen;
5586 - u8 *pos, ttl;
5587 + u8 *pos;
5588
5589 if (mgmt->u.action.u.measurement.action_code !=
5590 WLAN_ACTION_SPCT_CHL_SWITCH)
5591 @@ -1193,8 +1197,8 @@ static void mesh_rx_csa_frame(struct iee
5592 u.action.u.chan_switch.variable);
5593 ieee802_11_parse_elems(pos, len - baselen, false, &elems);
5594
5595 - ttl = elems.mesh_chansw_params_ie->mesh_ttl;
5596 - if (!--ttl)
5597 + ifmsh->chsw_ttl = elems.mesh_chansw_params_ie->mesh_ttl;
5598 + if (!--ifmsh->chsw_ttl)
5599 fwd_csa = false;
5600
5601 pre_value = le16_to_cpu(elems.mesh_chansw_params_ie->mesh_pre_value);
5602 --- a/net/mac80211/spectmgmt.c
5603 +++ b/net/mac80211/spectmgmt.c
5604 @@ -78,6 +78,8 @@ int ieee80211_parse_ch_switch_ie(struct
5605 if (elems->mesh_chansw_params_ie) {
5606 csa_ie->ttl = elems->mesh_chansw_params_ie->mesh_ttl;
5607 csa_ie->mode = elems->mesh_chansw_params_ie->mesh_flags;
5608 + csa_ie->pre_value = le16_to_cpu(
5609 + elems->mesh_chansw_params_ie->mesh_pre_value);
5610 }
5611
5612 new_freq = ieee80211_channel_to_frequency(new_chan_no, new_band);
5613 --- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
5614 +++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
5615 @@ -1109,7 +1109,9 @@ void ath6kl_cfg80211_ch_switch_notify(st
5616 (mode == WMI_11G_HT20) ?
5617 NL80211_CHAN_HT20 : NL80211_CHAN_NO_HT);
5618
5619 + mutex_lock(vif->wdev->mtx);
5620 cfg80211_ch_switch_notify(vif->ndev, &chandef);
5621 + mutex_unlock(vif->wdev->mtx);
5622 }
5623
5624 static int ath6kl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
5625 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
5626 +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
5627 @@ -20,6 +20,44 @@
5628
5629 /* AR9462 2.1 */
5630
5631 +#define ar9462_2p1_mac_postamble ar9462_2p0_mac_postamble
5632 +
5633 +#define ar9462_2p1_baseband_core ar9462_2p0_baseband_core
5634 +
5635 +#define ar9462_2p1_radio_core ar9462_2p0_radio_core
5636 +
5637 +#define ar9462_2p1_radio_postamble ar9462_2p0_radio_postamble
5638 +
5639 +#define ar9462_2p1_soc_postamble ar9462_2p0_soc_postamble
5640 +
5641 +#define ar9462_2p1_radio_postamble_sys2ant ar9462_2p0_radio_postamble_sys2ant
5642 +
5643 +#define ar9462_2p1_common_rx_gain ar9462_2p0_common_rx_gain
5644 +
5645 +#define ar9462_2p1_common_mixed_rx_gain ar9462_2p0_common_mixed_rx_gain
5646 +
5647 +#define ar9462_2p1_common_5g_xlna_only_rxgain ar9462_2p0_common_5g_xlna_only_rxgain
5648 +
5649 +#define ar9462_2p1_baseband_core_mix_rxgain ar9462_2p0_baseband_core_mix_rxgain
5650 +
5651 +#define ar9462_2p1_baseband_postamble_mix_rxgain ar9462_2p0_baseband_postamble_mix_rxgain
5652 +
5653 +#define ar9462_2p1_baseband_postamble_5g_xlna ar9462_2p0_baseband_postamble_5g_xlna
5654 +
5655 +#define ar9462_2p1_common_wo_xlna_rx_gain ar9462_2p0_common_wo_xlna_rx_gain
5656 +
5657 +#define ar9462_2p1_modes_low_ob_db_tx_gain ar9462_2p0_modes_low_ob_db_tx_gain
5658 +
5659 +#define ar9462_2p1_modes_high_ob_db_tx_gain ar9462_2p0_modes_high_ob_db_tx_gain
5660 +
5661 +#define ar9462_2p1_modes_mix_ob_db_tx_gain ar9462_2p0_modes_mix_ob_db_tx_gain
5662 +
5663 +#define ar9462_2p1_modes_fast_clock ar9462_2p0_modes_fast_clock
5664 +
5665 +#define ar9462_2p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
5666 +
5667 +#define ar9462_2p1_pciephy_clkreq_disable_L1 ar9462_2p0_pciephy_clkreq_disable_L1
5668 +
5669 static const u32 ar9462_2p1_mac_core[][2] = {
5670 /* Addr allmodes */
5671 {0x00000008, 0x00000000},
5672 @@ -183,168 +221,6 @@ static const u32 ar9462_2p1_mac_core[][2
5673 {0x000083d0, 0x000301ff},
5674 };
5675
5676 -static const u32 ar9462_2p1_mac_postamble[][5] = {
5677 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
5678 - {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
5679 - {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
5680 - {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
5681 - {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
5682 - {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
5683 - {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
5684 - {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
5685 - {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
5686 -};
5687 -
5688 -static const u32 ar9462_2p1_baseband_core[][2] = {
5689 - /* Addr allmodes */
5690 - {0x00009800, 0xafe68e30},
5691 - {0x00009804, 0xfd14e000},
5692 - {0x00009808, 0x9c0a9f6b},
5693 - {0x0000980c, 0x04900000},
5694 - {0x00009814, 0x9280c00a},
5695 - {0x00009818, 0x00000000},
5696 - {0x0000981c, 0x00020028},
5697 - {0x00009834, 0x6400a290},
5698 - {0x00009838, 0x0108ecff},
5699 - {0x0000983c, 0x0d000600},
5700 - {0x00009880, 0x201fff00},
5701 - {0x00009884, 0x00001042},
5702 - {0x000098a4, 0x00200400},
5703 - {0x000098b0, 0x32440bbe},
5704 - {0x000098d0, 0x004b6a8e},
5705 - {0x000098d4, 0x00000820},
5706 - {0x000098dc, 0x00000000},
5707 - {0x000098e4, 0x01ffffff},
5708 - {0x000098e8, 0x01ffffff},
5709 - {0x000098ec, 0x01ffffff},
5710 - {0x000098f0, 0x00000000},
5711 - {0x000098f4, 0x00000000},
5712 - {0x00009bf0, 0x80000000},
5713 - {0x00009c04, 0xff55ff55},
5714 - {0x00009c08, 0x0320ff55},
5715 - {0x00009c0c, 0x00000000},
5716 - {0x00009c10, 0x00000000},
5717 - {0x00009c14, 0x00046384},
5718 - {0x00009c18, 0x05b6b440},
5719 - {0x00009c1c, 0x00b6b440},
5720 - {0x00009d00, 0xc080a333},
5721 - {0x00009d04, 0x40206c10},
5722 - {0x00009d08, 0x009c4060},
5723 - {0x00009d0c, 0x9883800a},
5724 - {0x00009d10, 0x01834061},
5725 - {0x00009d14, 0x00c0040b},
5726 - {0x00009d18, 0x00000000},
5727 - {0x00009e08, 0x0038230c},
5728 - {0x00009e24, 0x990bb515},
5729 - {0x00009e28, 0x0c6f0000},
5730 - {0x00009e30, 0x06336f77},
5731 - {0x00009e34, 0x6af6532f},
5732 - {0x00009e38, 0x0cc80c00},
5733 - {0x00009e40, 0x15262820},
5734 - {0x00009e4c, 0x00001004},
5735 - {0x00009e50, 0x00ff03f1},
5736 - {0x00009e54, 0xe4c555c2},
5737 - {0x00009e58, 0xfd857722},
5738 - {0x00009e5c, 0xe9198724},
5739 - {0x00009fc0, 0x803e4788},
5740 - {0x00009fc4, 0x0001efb5},
5741 - {0x00009fcc, 0x40000014},
5742 - {0x00009fd0, 0x0a193b93},
5743 - {0x0000a20c, 0x00000000},
5744 - {0x0000a220, 0x00000000},
5745 - {0x0000a224, 0x00000000},
5746 - {0x0000a228, 0x10002310},
5747 - {0x0000a23c, 0x00000000},
5748 - {0x0000a244, 0x0c000000},
5749 - {0x0000a2a0, 0x00000001},
5750 - {0x0000a2c0, 0x00000001},
5751 - {0x0000a2c8, 0x00000000},
5752 - {0x0000a2cc, 0x18c43433},
5753 - {0x0000a2d4, 0x00000000},
5754 - {0x0000a2ec, 0x00000000},
5755 - {0x0000a2f0, 0x00000000},
5756 - {0x0000a2f4, 0x00000000},
5757 - {0x0000a2f8, 0x00000000},
5758 - {0x0000a344, 0x00000000},
5759 - {0x0000a34c, 0x00000000},
5760 - {0x0000a350, 0x0000a000},
5761 - {0x0000a364, 0x00000000},
5762 - {0x0000a370, 0x00000000},
5763 - {0x0000a390, 0x00000001},
5764 - {0x0000a394, 0x00000444},
5765 - {0x0000a398, 0x001f0e0f},
5766 - {0x0000a39c, 0x0075393f},
5767 - {0x0000a3a0, 0xb79f6427},
5768 - {0x0000a3c0, 0x20202020},
5769 - {0x0000a3c4, 0x22222220},
5770 - {0x0000a3c8, 0x20200020},
5771 - {0x0000a3cc, 0x20202020},
5772 - {0x0000a3d0, 0x20202020},
5773 - {0x0000a3d4, 0x20202020},
5774 - {0x0000a3d8, 0x20202020},
5775 - {0x0000a3dc, 0x20202020},
5776 - {0x0000a3e0, 0x20202020},
5777 - {0x0000a3e4, 0x20202020},
5778 - {0x0000a3e8, 0x20202020},
5779 - {0x0000a3ec, 0x20202020},
5780 - {0x0000a3f0, 0x00000000},
5781 - {0x0000a3f4, 0x00000006},
5782 - {0x0000a3f8, 0x0c9bd380},
5783 - {0x0000a3fc, 0x000f0f01},
5784 - {0x0000a400, 0x8fa91f01},
5785 - {0x0000a404, 0x00000000},
5786 - {0x0000a408, 0x0e79e5c6},
5787 - {0x0000a40c, 0x00820820},
5788 - {0x0000a414, 0x1ce739ce},
5789 - {0x0000a418, 0x2d001dce},
5790 - {0x0000a434, 0x00000000},
5791 - {0x0000a438, 0x00001801},
5792 - {0x0000a43c, 0x00100000},
5793 - {0x0000a444, 0x00000000},
5794 - {0x0000a448, 0x05000080},
5795 - {0x0000a44c, 0x00000001},
5796 - {0x0000a450, 0x00010000},
5797 - {0x0000a454, 0x07000000},
5798 - {0x0000a644, 0xbfad9d74},
5799 - {0x0000a648, 0x0048060a},
5800 - {0x0000a64c, 0x00002037},
5801 - {0x0000a670, 0x03020100},
5802 - {0x0000a674, 0x09080504},
5803 - {0x0000a678, 0x0d0c0b0a},
5804 - {0x0000a67c, 0x13121110},
5805 - {0x0000a680, 0x31301514},
5806 - {0x0000a684, 0x35343332},
5807 - {0x0000a688, 0x00000036},
5808 - {0x0000a690, 0x00000838},
5809 - {0x0000a6b0, 0x0000000a},
5810 - {0x0000a6b4, 0x00512c01},
5811 - {0x0000a7c0, 0x00000000},
5812 - {0x0000a7c4, 0xfffffffc},
5813 - {0x0000a7c8, 0x00000000},
5814 - {0x0000a7cc, 0x00000000},
5815 - {0x0000a7d0, 0x00000000},
5816 - {0x0000a7d4, 0x00000004},
5817 - {0x0000a7dc, 0x00000000},
5818 - {0x0000a7f0, 0x80000000},
5819 - {0x0000a8d0, 0x004b6a8e},
5820 - {0x0000a8d4, 0x00000820},
5821 - {0x0000a8dc, 0x00000000},
5822 - {0x0000a8f0, 0x00000000},
5823 - {0x0000a8f4, 0x00000000},
5824 - {0x0000abf0, 0x80000000},
5825 - {0x0000b2d0, 0x00000080},
5826 - {0x0000b2d4, 0x00000000},
5827 - {0x0000b2ec, 0x00000000},
5828 - {0x0000b2f0, 0x00000000},
5829 - {0x0000b2f4, 0x00000000},
5830 - {0x0000b2f8, 0x00000000},
5831 - {0x0000b408, 0x0e79e5c0},
5832 - {0x0000b40c, 0x00820820},
5833 - {0x0000b420, 0x00000000},
5834 - {0x0000b6b0, 0x0000000a},
5835 - {0x0000b6b4, 0x00000001},
5836 -};
5837 -
5838 static const u32 ar9462_2p1_baseband_postamble[][5] = {
5839 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
5840 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
5841 @@ -361,7 +237,7 @@ static const u32 ar9462_2p1_baseband_pos
5842 {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e},
5843 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
5844 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
5845 - {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
5846 + {0x00009e20, 0x000003a5, 0x000003a5, 0x000003a5, 0x000003a5},
5847 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
5848 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
5849 {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
5850 @@ -400,1375 +276,16 @@ static const u32 ar9462_2p1_baseband_pos
5851 {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000},
5852 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
5853 {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
5854 - {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
5855 + {0x0000ae20, 0x000001a6, 0x000001a6, 0x000001aa, 0x000001aa},
5856 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
5857 };
5858
5859 -static const u32 ar9462_2p1_radio_core[][2] = {
5860 - /* Addr allmodes */
5861 - {0x00016000, 0x36db6db6},
5862 - {0x00016004, 0x6db6db40},
5863 - {0x00016008, 0x73f00000},
5864 - {0x0001600c, 0x00000000},
5865 - {0x00016010, 0x6d820001},
5866 - {0x00016040, 0x7f80fff8},
5867 - {0x0001604c, 0x2699e04f},
5868 - {0x00016050, 0x6db6db6c},
5869 - {0x00016058, 0x6c200000},
5870 - {0x00016080, 0x000c0000},
5871 - {0x00016084, 0x9a68048c},
5872 - {0x00016088, 0x54214514},
5873 - {0x0001608c, 0x1203040b},
5874 - {0x00016090, 0x24926490},
5875 - {0x00016098, 0xd2888888},
5876 - {0x000160a0, 0x0a108ffe},
5877 - {0x000160a4, 0x812fc491},
5878 - {0x000160a8, 0x423c8000},
5879 - {0x000160b4, 0x92000000},
5880 - {0x000160b8, 0x0285dddc},
5881 - {0x000160bc, 0x02908888},
5882 - {0x000160c0, 0x00adb6d0},
5883 - {0x000160c4, 0x6db6db60},
5884 - {0x000160c8, 0x6db6db6c},
5885 - {0x000160cc, 0x0de6c1b0},
5886 - {0x00016100, 0x3fffbe04},
5887 - {0x00016104, 0xfff80000},
5888 - {0x00016108, 0x00200400},
5889 - {0x00016110, 0x00000000},
5890 - {0x00016144, 0x02084080},
5891 - {0x00016148, 0x000080c0},
5892 - {0x00016280, 0x050a0001},
5893 - {0x00016284, 0x3d841418},
5894 - {0x00016288, 0x00000000},
5895 - {0x0001628c, 0xe3000000},
5896 - {0x00016290, 0xa1005080},
5897 - {0x00016294, 0x00000020},
5898 - {0x00016298, 0x54a82900},
5899 - {0x00016340, 0x121e4276},
5900 - {0x00016344, 0x00300000},
5901 - {0x00016400, 0x36db6db6},
5902 - {0x00016404, 0x6db6db40},
5903 - {0x00016408, 0x73f00000},
5904 - {0x0001640c, 0x00000000},
5905 - {0x00016410, 0x6c800001},
5906 - {0x00016440, 0x7f80fff8},
5907 - {0x0001644c, 0x4699e04f},
5908 - {0x00016450, 0x6db6db6c},
5909 - {0x00016500, 0x3fffbe04},
5910 - {0x00016504, 0xfff80000},
5911 - {0x00016508, 0x00200400},
5912 - {0x00016510, 0x00000000},
5913 - {0x00016544, 0x02084080},
5914 - {0x00016548, 0x000080c0},
5915 -};
5916 -
5917 -static const u32 ar9462_2p1_radio_postamble[][5] = {
5918 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
5919 - {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
5920 - {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
5921 - {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
5922 - {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
5923 -};
5924 -
5925 static const u32 ar9462_2p1_soc_preamble[][2] = {
5926 /* Addr allmodes */
5927 - {0x000040a4, 0x00a0c1c9},
5928 + {0x000040a4, 0x00a0c9c9},
5929 {0x00007020, 0x00000000},
5930 {0x00007034, 0x00000002},
5931 {0x00007038, 0x000004c2},
5932 };
5933
5934 -static const u32 ar9462_2p1_soc_postamble[][5] = {
5935 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
5936 - {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
5937 -};
5938 -
5939 -static const u32 ar9462_2p1_radio_postamble_sys2ant[][5] = {
5940 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
5941 - {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
5942 - {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
5943 - {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
5944 -};
5945 -
5946 -static const u32 ar9462_2p1_common_rx_gain[][2] = {
5947 - /* Addr allmodes */
5948 - {0x0000a000, 0x00010000},
5949 - {0x0000a004, 0x00030002},
5950 - {0x0000a008, 0x00050004},
5951 - {0x0000a00c, 0x00810080},
5952 - {0x0000a010, 0x00830082},
5953 - {0x0000a014, 0x01810180},
5954 - {0x0000a018, 0x01830182},
5955 - {0x0000a01c, 0x01850184},
5956 - {0x0000a020, 0x01890188},
5957 - {0x0000a024, 0x018b018a},
5958 - {0x0000a028, 0x018d018c},
5959 - {0x0000a02c, 0x01910190},
5960 - {0x0000a030, 0x01930192},
5961 - {0x0000a034, 0x01950194},
5962 - {0x0000a038, 0x038a0196},
5963 - {0x0000a03c, 0x038c038b},
5964 - {0x0000a040, 0x0390038d},
5965 - {0x0000a044, 0x03920391},
5966 - {0x0000a048, 0x03940393},
5967 - {0x0000a04c, 0x03960395},
5968 - {0x0000a050, 0x00000000},
5969 - {0x0000a054, 0x00000000},
5970 - {0x0000a058, 0x00000000},
5971 - {0x0000a05c, 0x00000000},
5972 - {0x0000a060, 0x00000000},
5973 - {0x0000a064, 0x00000000},
5974 - {0x0000a068, 0x00000000},
5975 - {0x0000a06c, 0x00000000},
5976 - {0x0000a070, 0x00000000},
5977 - {0x0000a074, 0x00000000},
5978 - {0x0000a078, 0x00000000},
5979 - {0x0000a07c, 0x00000000},
5980 - {0x0000a080, 0x22222229},
5981 - {0x0000a084, 0x1d1d1d1d},
5982 - {0x0000a088, 0x1d1d1d1d},
5983 - {0x0000a08c, 0x1d1d1d1d},
5984 - {0x0000a090, 0x171d1d1d},
5985 - {0x0000a094, 0x11111717},
5986 - {0x0000a098, 0x00030311},
5987 - {0x0000a09c, 0x00000000},
5988 - {0x0000a0a0, 0x00000000},
5989 - {0x0000a0a4, 0x00000000},
5990 - {0x0000a0a8, 0x00000000},
5991 - {0x0000a0ac, 0x00000000},
5992 - {0x0000a0b0, 0x00000000},
5993 - {0x0000a0b4, 0x00000000},
5994 - {0x0000a0b8, 0x00000000},
5995 - {0x0000a0bc, 0x00000000},
5996 - {0x0000a0c0, 0x001f0000},
5997 - {0x0000a0c4, 0x01000101},
5998 - {0x0000a0c8, 0x011e011f},
5999 - {0x0000a0cc, 0x011c011d},
6000 - {0x0000a0d0, 0x02030204},
6001 - {0x0000a0d4, 0x02010202},
6002 - {0x0000a0d8, 0x021f0200},
6003 - {0x0000a0dc, 0x0302021e},
6004 - {0x0000a0e0, 0x03000301},
6005 - {0x0000a0e4, 0x031e031f},
6006 - {0x0000a0e8, 0x0402031d},
6007 - {0x0000a0ec, 0x04000401},
6008 - {0x0000a0f0, 0x041e041f},
6009 - {0x0000a0f4, 0x0502041d},
6010 - {0x0000a0f8, 0x05000501},
6011 - {0x0000a0fc, 0x051e051f},
6012 - {0x0000a100, 0x06010602},
6013 - {0x0000a104, 0x061f0600},
6014 - {0x0000a108, 0x061d061e},
6015 - {0x0000a10c, 0x07020703},
6016 - {0x0000a110, 0x07000701},
6017 - {0x0000a114, 0x00000000},
6018 - {0x0000a118, 0x00000000},
6019 - {0x0000a11c, 0x00000000},
6020 - {0x0000a120, 0x00000000},
6021 - {0x0000a124, 0x00000000},
6022 - {0x0000a128, 0x00000000},
6023 - {0x0000a12c, 0x00000000},
6024 - {0x0000a130, 0x00000000},
6025 - {0x0000a134, 0x00000000},
6026 - {0x0000a138, 0x00000000},
6027 - {0x0000a13c, 0x00000000},
6028 - {0x0000a140, 0x001f0000},
6029 - {0x0000a144, 0x01000101},
6030 - {0x0000a148, 0x011e011f},
6031 - {0x0000a14c, 0x011c011d},
6032 - {0x0000a150, 0x02030204},
6033 - {0x0000a154, 0x02010202},
6034 - {0x0000a158, 0x021f0200},
6035 - {0x0000a15c, 0x0302021e},
6036 - {0x0000a160, 0x03000301},
6037 - {0x0000a164, 0x031e031f},
6038 - {0x0000a168, 0x0402031d},
6039 - {0x0000a16c, 0x04000401},
6040 - {0x0000a170, 0x041e041f},
6041 - {0x0000a174, 0x0502041d},
6042 - {0x0000a178, 0x05000501},
6043 - {0x0000a17c, 0x051e051f},
6044 - {0x0000a180, 0x06010602},
6045 - {0x0000a184, 0x061f0600},
6046 - {0x0000a188, 0x061d061e},
6047 - {0x0000a18c, 0x07020703},
6048 - {0x0000a190, 0x07000701},
6049 - {0x0000a194, 0x00000000},
6050 - {0x0000a198, 0x00000000},
6051 - {0x0000a19c, 0x00000000},
6052 - {0x0000a1a0, 0x00000000},
6053 - {0x0000a1a4, 0x00000000},
6054 - {0x0000a1a8, 0x00000000},
6055 - {0x0000a1ac, 0x00000000},
6056 - {0x0000a1b0, 0x00000000},
6057 - {0x0000a1b4, 0x00000000},
6058 - {0x0000a1b8, 0x00000000},
6059 - {0x0000a1bc, 0x00000000},
6060 - {0x0000a1c0, 0x00000000},
6061 - {0x0000a1c4, 0x00000000},
6062 - {0x0000a1c8, 0x00000000},
6063 - {0x0000a1cc, 0x00000000},
6064 - {0x0000a1d0, 0x00000000},
6065 - {0x0000a1d4, 0x00000000},
6066 - {0x0000a1d8, 0x00000000},
6067 - {0x0000a1dc, 0x00000000},
6068 - {0x0000a1e0, 0x00000000},
6069 - {0x0000a1e4, 0x00000000},
6070 - {0x0000a1e8, 0x00000000},
6071 - {0x0000a1ec, 0x00000000},
6072 - {0x0000a1f0, 0x00000396},
6073 - {0x0000a1f4, 0x00000396},
6074 - {0x0000a1f8, 0x00000396},
6075 - {0x0000a1fc, 0x00000196},
6076 - {0x0000b000, 0x00010000},
6077 - {0x0000b004, 0x00030002},
6078 - {0x0000b008, 0x00050004},
6079 - {0x0000b00c, 0x00810080},
6080 - {0x0000b010, 0x00830082},
6081 - {0x0000b014, 0x01810180},
6082 - {0x0000b018, 0x01830182},
6083 - {0x0000b01c, 0x01850184},
6084 - {0x0000b020, 0x02810280},
6085 - {0x0000b024, 0x02830282},
6086 - {0x0000b028, 0x02850284},
6087 - {0x0000b02c, 0x02890288},
6088 - {0x0000b030, 0x028b028a},
6089 - {0x0000b034, 0x0388028c},
6090 - {0x0000b038, 0x038a0389},
6091 - {0x0000b03c, 0x038c038b},
6092 - {0x0000b040, 0x0390038d},
6093 - {0x0000b044, 0x03920391},
6094 - {0x0000b048, 0x03940393},
6095 - {0x0000b04c, 0x03960395},
6096 - {0x0000b050, 0x00000000},
6097 - {0x0000b054, 0x00000000},
6098 - {0x0000b058, 0x00000000},
6099 - {0x0000b05c, 0x00000000},
6100 - {0x0000b060, 0x00000000},
6101 - {0x0000b064, 0x00000000},
6102 - {0x0000b068, 0x00000000},
6103 - {0x0000b06c, 0x00000000},
6104 - {0x0000b070, 0x00000000},
6105 - {0x0000b074, 0x00000000},
6106 - {0x0000b078, 0x00000000},
6107 - {0x0000b07c, 0x00000000},
6108 - {0x0000b080, 0x2a2d2f32},
6109 - {0x0000b084, 0x21232328},
6110 - {0x0000b088, 0x19191c1e},
6111 - {0x0000b08c, 0x12141417},
6112 - {0x0000b090, 0x07070e0e},
6113 - {0x0000b094, 0x03030305},
6114 - {0x0000b098, 0x00000003},
6115 - {0x0000b09c, 0x00000000},
6116 - {0x0000b0a0, 0x00000000},
6117 - {0x0000b0a4, 0x00000000},
6118 - {0x0000b0a8, 0x00000000},
6119 - {0x0000b0ac, 0x00000000},
6120 - {0x0000b0b0, 0x00000000},
6121 - {0x0000b0b4, 0x00000000},
6122 - {0x0000b0b8, 0x00000000},
6123 - {0x0000b0bc, 0x00000000},
6124 - {0x0000b0c0, 0x003f0020},
6125 - {0x0000b0c4, 0x00400041},
6126 - {0x0000b0c8, 0x0140005f},
6127 - {0x0000b0cc, 0x0160015f},
6128 - {0x0000b0d0, 0x017e017f},
6129 - {0x0000b0d4, 0x02410242},
6130 - {0x0000b0d8, 0x025f0240},
6131 - {0x0000b0dc, 0x027f0260},
6132 - {0x0000b0e0, 0x0341027e},
6133 - {0x0000b0e4, 0x035f0340},
6134 - {0x0000b0e8, 0x037f0360},
6135 - {0x0000b0ec, 0x04400441},
6136 - {0x0000b0f0, 0x0460045f},
6137 - {0x0000b0f4, 0x0541047f},
6138 - {0x0000b0f8, 0x055f0540},
6139 - {0x0000b0fc, 0x057f0560},
6140 - {0x0000b100, 0x06400641},
6141 - {0x0000b104, 0x0660065f},
6142 - {0x0000b108, 0x067e067f},
6143 - {0x0000b10c, 0x07410742},
6144 - {0x0000b110, 0x075f0740},
6145 - {0x0000b114, 0x077f0760},
6146 - {0x0000b118, 0x07800781},
6147 - {0x0000b11c, 0x07a0079f},
6148 - {0x0000b120, 0x07c107bf},
6149 - {0x0000b124, 0x000007c0},
6150 - {0x0000b128, 0x00000000},
6151 - {0x0000b12c, 0x00000000},
6152 - {0x0000b130, 0x00000000},
6153 - {0x0000b134, 0x00000000},
6154 - {0x0000b138, 0x00000000},
6155 - {0x0000b13c, 0x00000000},
6156 - {0x0000b140, 0x003f0020},
6157 - {0x0000b144, 0x00400041},
6158 - {0x0000b148, 0x0140005f},
6159 - {0x0000b14c, 0x0160015f},
6160 - {0x0000b150, 0x017e017f},
6161 - {0x0000b154, 0x02410242},
6162 - {0x0000b158, 0x025f0240},
6163 - {0x0000b15c, 0x027f0260},
6164 - {0x0000b160, 0x0341027e},
6165 - {0x0000b164, 0x035f0340},
6166 - {0x0000b168, 0x037f0360},
6167 - {0x0000b16c, 0x04400441},
6168 - {0x0000b170, 0x0460045f},
6169 - {0x0000b174, 0x0541047f},
6170 - {0x0000b178, 0x055f0540},
6171 - {0x0000b17c, 0x057f0560},
6172 - {0x0000b180, 0x06400641},
6173 - {0x0000b184, 0x0660065f},
6174 - {0x0000b188, 0x067e067f},
6175 - {0x0000b18c, 0x07410742},
6176 - {0x0000b190, 0x075f0740},
6177 - {0x0000b194, 0x077f0760},
6178 - {0x0000b198, 0x07800781},
6179 - {0x0000b19c, 0x07a0079f},
6180 - {0x0000b1a0, 0x07c107bf},
6181 - {0x0000b1a4, 0x000007c0},
6182 - {0x0000b1a8, 0x00000000},
6183 - {0x0000b1ac, 0x00000000},
6184 - {0x0000b1b0, 0x00000000},
6185 - {0x0000b1b4, 0x00000000},
6186 - {0x0000b1b8, 0x00000000},
6187 - {0x0000b1bc, 0x00000000},
6188 - {0x0000b1c0, 0x00000000},
6189 - {0x0000b1c4, 0x00000000},
6190 - {0x0000b1c8, 0x00000000},
6191 - {0x0000b1cc, 0x00000000},
6192 - {0x0000b1d0, 0x00000000},
6193 - {0x0000b1d4, 0x00000000},
6194 - {0x0000b1d8, 0x00000000},
6195 - {0x0000b1dc, 0x00000000},
6196 - {0x0000b1e0, 0x00000000},
6197 - {0x0000b1e4, 0x00000000},
6198 - {0x0000b1e8, 0x00000000},
6199 - {0x0000b1ec, 0x00000000},
6200 - {0x0000b1f0, 0x00000396},
6201 - {0x0000b1f4, 0x00000396},
6202 - {0x0000b1f8, 0x00000396},
6203 - {0x0000b1fc, 0x00000196},
6204 -};
6205 -
6206 -static const u32 ar9462_2p1_common_mixed_rx_gain[][2] = {
6207 - /* Addr allmodes */
6208 - {0x0000a000, 0x00010000},
6209 - {0x0000a004, 0x00030002},
6210 - {0x0000a008, 0x00050004},
6211 - {0x0000a00c, 0x00810080},
6212 - {0x0000a010, 0x00830082},
6213 - {0x0000a014, 0x01810180},
6214 - {0x0000a018, 0x01830182},
6215 - {0x0000a01c, 0x01850184},
6216 - {0x0000a020, 0x01890188},
6217 - {0x0000a024, 0x018b018a},
6218 - {0x0000a028, 0x018d018c},
6219 - {0x0000a02c, 0x03820190},
6220 - {0x0000a030, 0x03840383},
6221 - {0x0000a034, 0x03880385},
6222 - {0x0000a038, 0x038a0389},
6223 - {0x0000a03c, 0x038c038b},
6224 - {0x0000a040, 0x0390038d},
6225 - {0x0000a044, 0x03920391},
6226 - {0x0000a048, 0x03940393},
6227 - {0x0000a04c, 0x03960395},
6228 - {0x0000a050, 0x00000000},
6229 - {0x0000a054, 0x00000000},
6230 - {0x0000a058, 0x00000000},
6231 - {0x0000a05c, 0x00000000},
6232 - {0x0000a060, 0x00000000},
6233 - {0x0000a064, 0x00000000},
6234 - {0x0000a068, 0x00000000},
6235 - {0x0000a06c, 0x00000000},
6236 - {0x0000a070, 0x00000000},
6237 - {0x0000a074, 0x00000000},
6238 - {0x0000a078, 0x00000000},
6239 - {0x0000a07c, 0x00000000},
6240 - {0x0000a080, 0x29292929},
6241 - {0x0000a084, 0x29292929},
6242 - {0x0000a088, 0x29292929},
6243 - {0x0000a08c, 0x29292929},
6244 - {0x0000a090, 0x22292929},
6245 - {0x0000a094, 0x1d1d2222},
6246 - {0x0000a098, 0x0c111117},
6247 - {0x0000a09c, 0x00030303},
6248 - {0x0000a0a0, 0x00000000},
6249 - {0x0000a0a4, 0x00000000},
6250 - {0x0000a0a8, 0x00000000},
6251 - {0x0000a0ac, 0x00000000},
6252 - {0x0000a0b0, 0x00000000},
6253 - {0x0000a0b4, 0x00000000},
6254 - {0x0000a0b8, 0x00000000},
6255 - {0x0000a0bc, 0x00000000},
6256 - {0x0000a0c0, 0x001f0000},
6257 - {0x0000a0c4, 0x01000101},
6258 - {0x0000a0c8, 0x011e011f},
6259 - {0x0000a0cc, 0x011c011d},
6260 - {0x0000a0d0, 0x02030204},
6261 - {0x0000a0d4, 0x02010202},
6262 - {0x0000a0d8, 0x021f0200},
6263 - {0x0000a0dc, 0x0302021e},
6264 - {0x0000a0e0, 0x03000301},
6265 - {0x0000a0e4, 0x031e031f},
6266 - {0x0000a0e8, 0x0402031d},
6267 - {0x0000a0ec, 0x04000401},
6268 - {0x0000a0f0, 0x041e041f},
6269 - {0x0000a0f4, 0x0502041d},
6270 - {0x0000a0f8, 0x05000501},
6271 - {0x0000a0fc, 0x051e051f},
6272 - {0x0000a100, 0x06010602},
6273 - {0x0000a104, 0x061f0600},
6274 - {0x0000a108, 0x061d061e},
6275 - {0x0000a10c, 0x07020703},
6276 - {0x0000a110, 0x07000701},
6277 - {0x0000a114, 0x00000000},
6278 - {0x0000a118, 0x00000000},
6279 - {0x0000a11c, 0x00000000},
6280 - {0x0000a120, 0x00000000},
6281 - {0x0000a124, 0x00000000},
6282 - {0x0000a128, 0x00000000},
6283 - {0x0000a12c, 0x00000000},
6284 - {0x0000a130, 0x00000000},
6285 - {0x0000a134, 0x00000000},
6286 - {0x0000a138, 0x00000000},
6287 - {0x0000a13c, 0x00000000},
6288 - {0x0000a140, 0x001f0000},
6289 - {0x0000a144, 0x01000101},
6290 - {0x0000a148, 0x011e011f},
6291 - {0x0000a14c, 0x011c011d},
6292 - {0x0000a150, 0x02030204},
6293 - {0x0000a154, 0x02010202},
6294 - {0x0000a158, 0x021f0200},
6295 - {0x0000a15c, 0x0302021e},
6296 - {0x0000a160, 0x03000301},
6297 - {0x0000a164, 0x031e031f},
6298 - {0x0000a168, 0x0402031d},
6299 - {0x0000a16c, 0x04000401},
6300 - {0x0000a170, 0x041e041f},
6301 - {0x0000a174, 0x0502041d},
6302 - {0x0000a178, 0x05000501},
6303 - {0x0000a17c, 0x051e051f},
6304 - {0x0000a180, 0x06010602},
6305 - {0x0000a184, 0x061f0600},
6306 - {0x0000a188, 0x061d061e},
6307 - {0x0000a18c, 0x07020703},
6308 - {0x0000a190, 0x07000701},
6309 - {0x0000a194, 0x00000000},
6310 - {0x0000a198, 0x00000000},
6311 - {0x0000a19c, 0x00000000},
6312 - {0x0000a1a0, 0x00000000},
6313 - {0x0000a1a4, 0x00000000},
6314 - {0x0000a1a8, 0x00000000},
6315 - {0x0000a1ac, 0x00000000},
6316 - {0x0000a1b0, 0x00000000},
6317 - {0x0000a1b4, 0x00000000},
6318 - {0x0000a1b8, 0x00000000},
6319 - {0x0000a1bc, 0x00000000},
6320 - {0x0000a1c0, 0x00000000},
6321 - {0x0000a1c4, 0x00000000},
6322 - {0x0000a1c8, 0x00000000},
6323 - {0x0000a1cc, 0x00000000},
6324 - {0x0000a1d0, 0x00000000},
6325 - {0x0000a1d4, 0x00000000},
6326 - {0x0000a1d8, 0x00000000},
6327 - {0x0000a1dc, 0x00000000},
6328 - {0x0000a1e0, 0x00000000},
6329 - {0x0000a1e4, 0x00000000},
6330 - {0x0000a1e8, 0x00000000},
6331 - {0x0000a1ec, 0x00000000},
6332 - {0x0000a1f0, 0x00000396},
6333 - {0x0000a1f4, 0x00000396},
6334 - {0x0000a1f8, 0x00000396},
6335 - {0x0000a1fc, 0x00000196},
6336 - {0x0000b000, 0x00010000},
6337 - {0x0000b004, 0x00030002},
6338 - {0x0000b008, 0x00050004},
6339 - {0x0000b00c, 0x00810080},
6340 - {0x0000b010, 0x00830082},
6341 - {0x0000b014, 0x01810180},
6342 - {0x0000b018, 0x01830182},
6343 - {0x0000b01c, 0x01850184},
6344 - {0x0000b020, 0x02810280},
6345 - {0x0000b024, 0x02830282},
6346 - {0x0000b028, 0x02850284},
6347 - {0x0000b02c, 0x02890288},
6348 - {0x0000b030, 0x028b028a},
6349 - {0x0000b034, 0x0388028c},
6350 - {0x0000b038, 0x038a0389},
6351 - {0x0000b03c, 0x038c038b},
6352 - {0x0000b040, 0x0390038d},
6353 - {0x0000b044, 0x03920391},
6354 - {0x0000b048, 0x03940393},
6355 - {0x0000b04c, 0x03960395},
6356 - {0x0000b050, 0x00000000},
6357 - {0x0000b054, 0x00000000},
6358 - {0x0000b058, 0x00000000},
6359 - {0x0000b05c, 0x00000000},
6360 - {0x0000b060, 0x00000000},
6361 - {0x0000b064, 0x00000000},
6362 - {0x0000b068, 0x00000000},
6363 - {0x0000b06c, 0x00000000},
6364 - {0x0000b070, 0x00000000},
6365 - {0x0000b074, 0x00000000},
6366 - {0x0000b078, 0x00000000},
6367 - {0x0000b07c, 0x00000000},
6368 - {0x0000b080, 0x2a2d2f32},
6369 - {0x0000b084, 0x21232328},
6370 - {0x0000b088, 0x19191c1e},
6371 - {0x0000b08c, 0x12141417},
6372 - {0x0000b090, 0x07070e0e},
6373 - {0x0000b094, 0x03030305},
6374 - {0x0000b098, 0x00000003},
6375 - {0x0000b09c, 0x00000000},
6376 - {0x0000b0a0, 0x00000000},
6377 - {0x0000b0a4, 0x00000000},
6378 - {0x0000b0a8, 0x00000000},
6379 - {0x0000b0ac, 0x00000000},
6380 - {0x0000b0b0, 0x00000000},
6381 - {0x0000b0b4, 0x00000000},
6382 - {0x0000b0b8, 0x00000000},
6383 - {0x0000b0bc, 0x00000000},
6384 - {0x0000b0c0, 0x003f0020},
6385 - {0x0000b0c4, 0x00400041},
6386 - {0x0000b0c8, 0x0140005f},
6387 - {0x0000b0cc, 0x0160015f},
6388 - {0x0000b0d0, 0x017e017f},
6389 - {0x0000b0d4, 0x02410242},
6390 - {0x0000b0d8, 0x025f0240},
6391 - {0x0000b0dc, 0x027f0260},
6392 - {0x0000b0e0, 0x0341027e},
6393 - {0x0000b0e4, 0x035f0340},
6394 - {0x0000b0e8, 0x037f0360},
6395 - {0x0000b0ec, 0x04400441},
6396 - {0x0000b0f0, 0x0460045f},
6397 - {0x0000b0f4, 0x0541047f},
6398 - {0x0000b0f8, 0x055f0540},
6399 - {0x0000b0fc, 0x057f0560},
6400 - {0x0000b100, 0x06400641},
6401 - {0x0000b104, 0x0660065f},
6402 - {0x0000b108, 0x067e067f},
6403 - {0x0000b10c, 0x07410742},
6404 - {0x0000b110, 0x075f0740},
6405 - {0x0000b114, 0x077f0760},
6406 - {0x0000b118, 0x07800781},
6407 - {0x0000b11c, 0x07a0079f},
6408 - {0x0000b120, 0x07c107bf},
6409 - {0x0000b124, 0x000007c0},
6410 - {0x0000b128, 0x00000000},
6411 - {0x0000b12c, 0x00000000},
6412 - {0x0000b130, 0x00000000},
6413 - {0x0000b134, 0x00000000},
6414 - {0x0000b138, 0x00000000},
6415 - {0x0000b13c, 0x00000000},
6416 - {0x0000b140, 0x003f0020},
6417 - {0x0000b144, 0x00400041},
6418 - {0x0000b148, 0x0140005f},
6419 - {0x0000b14c, 0x0160015f},
6420 - {0x0000b150, 0x017e017f},
6421 - {0x0000b154, 0x02410242},
6422 - {0x0000b158, 0x025f0240},
6423 - {0x0000b15c, 0x027f0260},
6424 - {0x0000b160, 0x0341027e},
6425 - {0x0000b164, 0x035f0340},
6426 - {0x0000b168, 0x037f0360},
6427 - {0x0000b16c, 0x04400441},
6428 - {0x0000b170, 0x0460045f},
6429 - {0x0000b174, 0x0541047f},
6430 - {0x0000b178, 0x055f0540},
6431 - {0x0000b17c, 0x057f0560},
6432 - {0x0000b180, 0x06400641},
6433 - {0x0000b184, 0x0660065f},
6434 - {0x0000b188, 0x067e067f},
6435 - {0x0000b18c, 0x07410742},
6436 - {0x0000b190, 0x075f0740},
6437 - {0x0000b194, 0x077f0760},
6438 - {0x0000b198, 0x07800781},
6439 - {0x0000b19c, 0x07a0079f},
6440 - {0x0000b1a0, 0x07c107bf},
6441 - {0x0000b1a4, 0x000007c0},
6442 - {0x0000b1a8, 0x00000000},
6443 - {0x0000b1ac, 0x00000000},
6444 - {0x0000b1b0, 0x00000000},
6445 - {0x0000b1b4, 0x00000000},
6446 - {0x0000b1b8, 0x00000000},
6447 - {0x0000b1bc, 0x00000000},
6448 - {0x0000b1c0, 0x00000000},
6449 - {0x0000b1c4, 0x00000000},
6450 - {0x0000b1c8, 0x00000000},
6451 - {0x0000b1cc, 0x00000000},
6452 - {0x0000b1d0, 0x00000000},
6453 - {0x0000b1d4, 0x00000000},
6454 - {0x0000b1d8, 0x00000000},
6455 - {0x0000b1dc, 0x00000000},
6456 - {0x0000b1e0, 0x00000000},
6457 - {0x0000b1e4, 0x00000000},
6458 - {0x0000b1e8, 0x00000000},
6459 - {0x0000b1ec, 0x00000000},
6460 - {0x0000b1f0, 0x00000396},
6461 - {0x0000b1f4, 0x00000396},
6462 - {0x0000b1f8, 0x00000396},
6463 - {0x0000b1fc, 0x00000196},
6464 -};
6465 -
6466 -static const u32 ar9462_2p1_baseband_core_mix_rxgain[][2] = {
6467 - /* Addr allmodes */
6468 - {0x00009fd0, 0x0a2d6b93},
6469 -};
6470 -
6471 -static const u32 ar9462_2p1_baseband_postamble_mix_rxgain[][5] = {
6472 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
6473 - {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae},
6474 - {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da},
6475 - {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81},
6476 - {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8},
6477 - {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e},
6478 - {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e},
6479 -};
6480 -
6481 -static const u32 ar9462_2p1_baseband_postamble_5g_xlna[][5] = {
6482 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
6483 - {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
6484 -};
6485 -
6486 -static const u32 ar9462_2p1_common_wo_xlna_rx_gain[][2] = {
6487 - /* Addr allmodes */
6488 - {0x0000a000, 0x00010000},
6489 - {0x0000a004, 0x00030002},
6490 - {0x0000a008, 0x00050004},
6491 - {0x0000a00c, 0x00810080},
6492 - {0x0000a010, 0x00830082},
6493 - {0x0000a014, 0x01810180},
6494 - {0x0000a018, 0x01830182},
6495 - {0x0000a01c, 0x01850184},
6496 - {0x0000a020, 0x01890188},
6497 - {0x0000a024, 0x018b018a},
6498 - {0x0000a028, 0x018d018c},
6499 - {0x0000a02c, 0x03820190},
6500 - {0x0000a030, 0x03840383},
6501 - {0x0000a034, 0x03880385},
6502 - {0x0000a038, 0x038a0389},
6503 - {0x0000a03c, 0x038c038b},
6504 - {0x0000a040, 0x0390038d},
6505 - {0x0000a044, 0x03920391},
6506 - {0x0000a048, 0x03940393},
6507 - {0x0000a04c, 0x03960395},
6508 - {0x0000a050, 0x00000000},
6509 - {0x0000a054, 0x00000000},
6510 - {0x0000a058, 0x00000000},
6511 - {0x0000a05c, 0x00000000},
6512 - {0x0000a060, 0x00000000},
6513 - {0x0000a064, 0x00000000},
6514 - {0x0000a068, 0x00000000},
6515 - {0x0000a06c, 0x00000000},
6516 - {0x0000a070, 0x00000000},
6517 - {0x0000a074, 0x00000000},
6518 - {0x0000a078, 0x00000000},
6519 - {0x0000a07c, 0x00000000},
6520 - {0x0000a080, 0x29292929},
6521 - {0x0000a084, 0x29292929},
6522 - {0x0000a088, 0x29292929},
6523 - {0x0000a08c, 0x29292929},
6524 - {0x0000a090, 0x22292929},
6525 - {0x0000a094, 0x1d1d2222},
6526 - {0x0000a098, 0x0c111117},
6527 - {0x0000a09c, 0x00030303},
6528 - {0x0000a0a0, 0x00000000},
6529 - {0x0000a0a4, 0x00000000},
6530 - {0x0000a0a8, 0x00000000},
6531 - {0x0000a0ac, 0x00000000},
6532 - {0x0000a0b0, 0x00000000},
6533 - {0x0000a0b4, 0x00000000},
6534 - {0x0000a0b8, 0x00000000},
6535 - {0x0000a0bc, 0x00000000},
6536 - {0x0000a0c0, 0x001f0000},
6537 - {0x0000a0c4, 0x01000101},
6538 - {0x0000a0c8, 0x011e011f},
6539 - {0x0000a0cc, 0x011c011d},
6540 - {0x0000a0d0, 0x02030204},
6541 - {0x0000a0d4, 0x02010202},
6542 - {0x0000a0d8, 0x021f0200},
6543 - {0x0000a0dc, 0x0302021e},
6544 - {0x0000a0e0, 0x03000301},
6545 - {0x0000a0e4, 0x031e031f},
6546 - {0x0000a0e8, 0x0402031d},
6547 - {0x0000a0ec, 0x04000401},
6548 - {0x0000a0f0, 0x041e041f},
6549 - {0x0000a0f4, 0x0502041d},
6550 - {0x0000a0f8, 0x05000501},
6551 - {0x0000a0fc, 0x051e051f},
6552 - {0x0000a100, 0x06010602},
6553 - {0x0000a104, 0x061f0600},
6554 - {0x0000a108, 0x061d061e},
6555 - {0x0000a10c, 0x07020703},
6556 - {0x0000a110, 0x07000701},
6557 - {0x0000a114, 0x00000000},
6558 - {0x0000a118, 0x00000000},
6559 - {0x0000a11c, 0x00000000},
6560 - {0x0000a120, 0x00000000},
6561 - {0x0000a124, 0x00000000},
6562 - {0x0000a128, 0x00000000},
6563 - {0x0000a12c, 0x00000000},
6564 - {0x0000a130, 0x00000000},
6565 - {0x0000a134, 0x00000000},
6566 - {0x0000a138, 0x00000000},
6567 - {0x0000a13c, 0x00000000},
6568 - {0x0000a140, 0x001f0000},
6569 - {0x0000a144, 0x01000101},
6570 - {0x0000a148, 0x011e011f},
6571 - {0x0000a14c, 0x011c011d},
6572 - {0x0000a150, 0x02030204},
6573 - {0x0000a154, 0x02010202},
6574 - {0x0000a158, 0x021f0200},
6575 - {0x0000a15c, 0x0302021e},
6576 - {0x0000a160, 0x03000301},
6577 - {0x0000a164, 0x031e031f},
6578 - {0x0000a168, 0x0402031d},
6579 - {0x0000a16c, 0x04000401},
6580 - {0x0000a170, 0x041e041f},
6581 - {0x0000a174, 0x0502041d},
6582 - {0x0000a178, 0x05000501},
6583 - {0x0000a17c, 0x051e051f},
6584 - {0x0000a180, 0x06010602},
6585 - {0x0000a184, 0x061f0600},
6586 - {0x0000a188, 0x061d061e},
6587 - {0x0000a18c, 0x07020703},
6588 - {0x0000a190, 0x07000701},
6589 - {0x0000a194, 0x00000000},
6590 - {0x0000a198, 0x00000000},
6591 - {0x0000a19c, 0x00000000},
6592 - {0x0000a1a0, 0x00000000},
6593 - {0x0000a1a4, 0x00000000},
6594 - {0x0000a1a8, 0x00000000},
6595 - {0x0000a1ac, 0x00000000},
6596 - {0x0000a1b0, 0x00000000},
6597 - {0x0000a1b4, 0x00000000},
6598 - {0x0000a1b8, 0x00000000},
6599 - {0x0000a1bc, 0x00000000},
6600 - {0x0000a1c0, 0x00000000},
6601 - {0x0000a1c4, 0x00000000},
6602 - {0x0000a1c8, 0x00000000},
6603 - {0x0000a1cc, 0x00000000},
6604 - {0x0000a1d0, 0x00000000},
6605 - {0x0000a1d4, 0x00000000},
6606 - {0x0000a1d8, 0x00000000},
6607 - {0x0000a1dc, 0x00000000},
6608 - {0x0000a1e0, 0x00000000},
6609 - {0x0000a1e4, 0x00000000},
6610 - {0x0000a1e8, 0x00000000},
6611 - {0x0000a1ec, 0x00000000},
6612 - {0x0000a1f0, 0x00000396},
6613 - {0x0000a1f4, 0x00000396},
6614 - {0x0000a1f8, 0x00000396},
6615 - {0x0000a1fc, 0x00000196},
6616 - {0x0000b000, 0x00010000},
6617 - {0x0000b004, 0x00030002},
6618 - {0x0000b008, 0x00050004},
6619 - {0x0000b00c, 0x00810080},
6620 - {0x0000b010, 0x00830082},
6621 - {0x0000b014, 0x01810180},
6622 - {0x0000b018, 0x01830182},
6623 - {0x0000b01c, 0x01850184},
6624 - {0x0000b020, 0x02810280},
6625 - {0x0000b024, 0x02830282},
6626 - {0x0000b028, 0x02850284},
6627 - {0x0000b02c, 0x02890288},
6628 - {0x0000b030, 0x028b028a},
6629 - {0x0000b034, 0x0388028c},
6630 - {0x0000b038, 0x038a0389},
6631 - {0x0000b03c, 0x038c038b},
6632 - {0x0000b040, 0x0390038d},
6633 - {0x0000b044, 0x03920391},
6634 - {0x0000b048, 0x03940393},
6635 - {0x0000b04c, 0x03960395},
6636 - {0x0000b050, 0x00000000},
6637 - {0x0000b054, 0x00000000},
6638 - {0x0000b058, 0x00000000},
6639 - {0x0000b05c, 0x00000000},
6640 - {0x0000b060, 0x00000000},
6641 - {0x0000b064, 0x00000000},
6642 - {0x0000b068, 0x00000000},
6643 - {0x0000b06c, 0x00000000},
6644 - {0x0000b070, 0x00000000},
6645 - {0x0000b074, 0x00000000},
6646 - {0x0000b078, 0x00000000},
6647 - {0x0000b07c, 0x00000000},
6648 - {0x0000b080, 0x32323232},
6649 - {0x0000b084, 0x2f2f3232},
6650 - {0x0000b088, 0x23282a2d},
6651 - {0x0000b08c, 0x1c1e2123},
6652 - {0x0000b090, 0x14171919},
6653 - {0x0000b094, 0x0e0e1214},
6654 - {0x0000b098, 0x03050707},
6655 - {0x0000b09c, 0x00030303},
6656 - {0x0000b0a0, 0x00000000},
6657 - {0x0000b0a4, 0x00000000},
6658 - {0x0000b0a8, 0x00000000},
6659 - {0x0000b0ac, 0x00000000},
6660 - {0x0000b0b0, 0x00000000},
6661 - {0x0000b0b4, 0x00000000},
6662 - {0x0000b0b8, 0x00000000},
6663 - {0x0000b0bc, 0x00000000},
6664 - {0x0000b0c0, 0x003f0020},
6665 - {0x0000b0c4, 0x00400041},
6666 - {0x0000b0c8, 0x0140005f},
6667 - {0x0000b0cc, 0x0160015f},
6668 - {0x0000b0d0, 0x017e017f},
6669 - {0x0000b0d4, 0x02410242},
6670 - {0x0000b0d8, 0x025f0240},
6671 - {0x0000b0dc, 0x027f0260},
6672 - {0x0000b0e0, 0x0341027e},
6673 - {0x0000b0e4, 0x035f0340},
6674 - {0x0000b0e8, 0x037f0360},
6675 - {0x0000b0ec, 0x04400441},
6676 - {0x0000b0f0, 0x0460045f},
6677 - {0x0000b0f4, 0x0541047f},
6678 - {0x0000b0f8, 0x055f0540},
6679 - {0x0000b0fc, 0x057f0560},
6680 - {0x0000b100, 0x06400641},
6681 - {0x0000b104, 0x0660065f},
6682 - {0x0000b108, 0x067e067f},
6683 - {0x0000b10c, 0x07410742},
6684 - {0x0000b110, 0x075f0740},
6685 - {0x0000b114, 0x077f0760},
6686 - {0x0000b118, 0x07800781},
6687 - {0x0000b11c, 0x07a0079f},
6688 - {0x0000b120, 0x07c107bf},
6689 - {0x0000b124, 0x000007c0},
6690 - {0x0000b128, 0x00000000},
6691 - {0x0000b12c, 0x00000000},
6692 - {0x0000b130, 0x00000000},
6693 - {0x0000b134, 0x00000000},
6694 - {0x0000b138, 0x00000000},
6695 - {0x0000b13c, 0x00000000},
6696 - {0x0000b140, 0x003f0020},
6697 - {0x0000b144, 0x00400041},
6698 - {0x0000b148, 0x0140005f},
6699 - {0x0000b14c, 0x0160015f},
6700 - {0x0000b150, 0x017e017f},
6701 - {0x0000b154, 0x02410242},
6702 - {0x0000b158, 0x025f0240},
6703 - {0x0000b15c, 0x027f0260},
6704 - {0x0000b160, 0x0341027e},
6705 - {0x0000b164, 0x035f0340},
6706 - {0x0000b168, 0x037f0360},
6707 - {0x0000b16c, 0x04400441},
6708 - {0x0000b170, 0x0460045f},
6709 - {0x0000b174, 0x0541047f},
6710 - {0x0000b178, 0x055f0540},
6711 - {0x0000b17c, 0x057f0560},
6712 - {0x0000b180, 0x06400641},
6713 - {0x0000b184, 0x0660065f},
6714 - {0x0000b188, 0x067e067f},
6715 - {0x0000b18c, 0x07410742},
6716 - {0x0000b190, 0x075f0740},
6717 - {0x0000b194, 0x077f0760},
6718 - {0x0000b198, 0x07800781},
6719 - {0x0000b19c, 0x07a0079f},
6720 - {0x0000b1a0, 0x07c107bf},
6721 - {0x0000b1a4, 0x000007c0},
6722 - {0x0000b1a8, 0x00000000},
6723 - {0x0000b1ac, 0x00000000},
6724 - {0x0000b1b0, 0x00000000},
6725 - {0x0000b1b4, 0x00000000},
6726 - {0x0000b1b8, 0x00000000},
6727 - {0x0000b1bc, 0x00000000},
6728 - {0x0000b1c0, 0x00000000},
6729 - {0x0000b1c4, 0x00000000},
6730 - {0x0000b1c8, 0x00000000},
6731 - {0x0000b1cc, 0x00000000},
6732 - {0x0000b1d0, 0x00000000},
6733 - {0x0000b1d4, 0x00000000},
6734 - {0x0000b1d8, 0x00000000},
6735 - {0x0000b1dc, 0x00000000},
6736 - {0x0000b1e0, 0x00000000},
6737 - {0x0000b1e4, 0x00000000},
6738 - {0x0000b1e8, 0x00000000},
6739 - {0x0000b1ec, 0x00000000},
6740 - {0x0000b1f0, 0x00000396},
6741 - {0x0000b1f4, 0x00000396},
6742 - {0x0000b1f8, 0x00000396},
6743 - {0x0000b1fc, 0x00000196},
6744 -};
6745 -
6746 -static const u32 ar9462_2p1_common_5g_xlna_only_rx_gain[][2] = {
6747 - /* Addr allmodes */
6748 - {0x0000a000, 0x00010000},
6749 - {0x0000a004, 0x00030002},
6750 - {0x0000a008, 0x00050004},
6751 - {0x0000a00c, 0x00810080},
6752 - {0x0000a010, 0x00830082},
6753 - {0x0000a014, 0x01810180},
6754 - {0x0000a018, 0x01830182},
6755 - {0x0000a01c, 0x01850184},
6756 - {0x0000a020, 0x01890188},
6757 - {0x0000a024, 0x018b018a},
6758 - {0x0000a028, 0x018d018c},
6759 - {0x0000a02c, 0x03820190},
6760 - {0x0000a030, 0x03840383},
6761 - {0x0000a034, 0x03880385},
6762 - {0x0000a038, 0x038a0389},
6763 - {0x0000a03c, 0x038c038b},
6764 - {0x0000a040, 0x0390038d},
6765 - {0x0000a044, 0x03920391},
6766 - {0x0000a048, 0x03940393},
6767 - {0x0000a04c, 0x03960395},
6768 - {0x0000a050, 0x00000000},
6769 - {0x0000a054, 0x00000000},
6770 - {0x0000a058, 0x00000000},
6771 - {0x0000a05c, 0x00000000},
6772 - {0x0000a060, 0x00000000},
6773 - {0x0000a064, 0x00000000},
6774 - {0x0000a068, 0x00000000},
6775 - {0x0000a06c, 0x00000000},
6776 - {0x0000a070, 0x00000000},
6777 - {0x0000a074, 0x00000000},
6778 - {0x0000a078, 0x00000000},
6779 - {0x0000a07c, 0x00000000},
6780 - {0x0000a080, 0x29292929},
6781 - {0x0000a084, 0x29292929},
6782 - {0x0000a088, 0x29292929},
6783 - {0x0000a08c, 0x29292929},
6784 - {0x0000a090, 0x22292929},
6785 - {0x0000a094, 0x1d1d2222},
6786 - {0x0000a098, 0x0c111117},
6787 - {0x0000a09c, 0x00030303},
6788 - {0x0000a0a0, 0x00000000},
6789 - {0x0000a0a4, 0x00000000},
6790 - {0x0000a0a8, 0x00000000},
6791 - {0x0000a0ac, 0x00000000},
6792 - {0x0000a0b0, 0x00000000},
6793 - {0x0000a0b4, 0x00000000},
6794 - {0x0000a0b8, 0x00000000},
6795 - {0x0000a0bc, 0x00000000},
6796 - {0x0000a0c0, 0x001f0000},
6797 - {0x0000a0c4, 0x01000101},
6798 - {0x0000a0c8, 0x011e011f},
6799 - {0x0000a0cc, 0x011c011d},
6800 - {0x0000a0d0, 0x02030204},
6801 - {0x0000a0d4, 0x02010202},
6802 - {0x0000a0d8, 0x021f0200},
6803 - {0x0000a0dc, 0x0302021e},
6804 - {0x0000a0e0, 0x03000301},
6805 - {0x0000a0e4, 0x031e031f},
6806 - {0x0000a0e8, 0x0402031d},
6807 - {0x0000a0ec, 0x04000401},
6808 - {0x0000a0f0, 0x041e041f},
6809 - {0x0000a0f4, 0x0502041d},
6810 - {0x0000a0f8, 0x05000501},
6811 - {0x0000a0fc, 0x051e051f},
6812 - {0x0000a100, 0x06010602},
6813 - {0x0000a104, 0x061f0600},
6814 - {0x0000a108, 0x061d061e},
6815 - {0x0000a10c, 0x07020703},
6816 - {0x0000a110, 0x07000701},
6817 - {0x0000a114, 0x00000000},
6818 - {0x0000a118, 0x00000000},
6819 - {0x0000a11c, 0x00000000},
6820 - {0x0000a120, 0x00000000},
6821 - {0x0000a124, 0x00000000},
6822 - {0x0000a128, 0x00000000},
6823 - {0x0000a12c, 0x00000000},
6824 - {0x0000a130, 0x00000000},
6825 - {0x0000a134, 0x00000000},
6826 - {0x0000a138, 0x00000000},
6827 - {0x0000a13c, 0x00000000},
6828 - {0x0000a140, 0x001f0000},
6829 - {0x0000a144, 0x01000101},
6830 - {0x0000a148, 0x011e011f},
6831 - {0x0000a14c, 0x011c011d},
6832 - {0x0000a150, 0x02030204},
6833 - {0x0000a154, 0x02010202},
6834 - {0x0000a158, 0x021f0200},
6835 - {0x0000a15c, 0x0302021e},
6836 - {0x0000a160, 0x03000301},
6837 - {0x0000a164, 0x031e031f},
6838 - {0x0000a168, 0x0402031d},
6839 - {0x0000a16c, 0x04000401},
6840 - {0x0000a170, 0x041e041f},
6841 - {0x0000a174, 0x0502041d},
6842 - {0x0000a178, 0x05000501},
6843 - {0x0000a17c, 0x051e051f},
6844 - {0x0000a180, 0x06010602},
6845 - {0x0000a184, 0x061f0600},
6846 - {0x0000a188, 0x061d061e},
6847 - {0x0000a18c, 0x07020703},
6848 - {0x0000a190, 0x07000701},
6849 - {0x0000a194, 0x00000000},
6850 - {0x0000a198, 0x00000000},
6851 - {0x0000a19c, 0x00000000},
6852 - {0x0000a1a0, 0x00000000},
6853 - {0x0000a1a4, 0x00000000},
6854 - {0x0000a1a8, 0x00000000},
6855 - {0x0000a1ac, 0x00000000},
6856 - {0x0000a1b0, 0x00000000},
6857 - {0x0000a1b4, 0x00000000},
6858 - {0x0000a1b8, 0x00000000},
6859 - {0x0000a1bc, 0x00000000},
6860 - {0x0000a1c0, 0x00000000},
6861 - {0x0000a1c4, 0x00000000},
6862 - {0x0000a1c8, 0x00000000},
6863 - {0x0000a1cc, 0x00000000},
6864 - {0x0000a1d0, 0x00000000},
6865 - {0x0000a1d4, 0x00000000},
6866 - {0x0000a1d8, 0x00000000},
6867 - {0x0000a1dc, 0x00000000},
6868 - {0x0000a1e0, 0x00000000},
6869 - {0x0000a1e4, 0x00000000},
6870 - {0x0000a1e8, 0x00000000},
6871 - {0x0000a1ec, 0x00000000},
6872 - {0x0000a1f0, 0x00000396},
6873 - {0x0000a1f4, 0x00000396},
6874 - {0x0000a1f8, 0x00000396},
6875 - {0x0000a1fc, 0x00000196},
6876 - {0x0000b000, 0x00010000},
6877 - {0x0000b004, 0x00030002},
6878 - {0x0000b008, 0x00050004},
6879 - {0x0000b00c, 0x00810080},
6880 - {0x0000b010, 0x00830082},
6881 - {0x0000b014, 0x01810180},
6882 - {0x0000b018, 0x01830182},
6883 - {0x0000b01c, 0x01850184},
6884 - {0x0000b020, 0x02810280},
6885 - {0x0000b024, 0x02830282},
6886 - {0x0000b028, 0x02850284},
6887 - {0x0000b02c, 0x02890288},
6888 - {0x0000b030, 0x028b028a},
6889 - {0x0000b034, 0x0388028c},
6890 - {0x0000b038, 0x038a0389},
6891 - {0x0000b03c, 0x038c038b},
6892 - {0x0000b040, 0x0390038d},
6893 - {0x0000b044, 0x03920391},
6894 - {0x0000b048, 0x03940393},
6895 - {0x0000b04c, 0x03960395},
6896 - {0x0000b050, 0x00000000},
6897 - {0x0000b054, 0x00000000},
6898 - {0x0000b058, 0x00000000},
6899 - {0x0000b05c, 0x00000000},
6900 - {0x0000b060, 0x00000000},
6901 - {0x0000b064, 0x00000000},
6902 - {0x0000b068, 0x00000000},
6903 - {0x0000b06c, 0x00000000},
6904 - {0x0000b070, 0x00000000},
6905 - {0x0000b074, 0x00000000},
6906 - {0x0000b078, 0x00000000},
6907 - {0x0000b07c, 0x00000000},
6908 - {0x0000b080, 0x2a2d2f32},
6909 - {0x0000b084, 0x21232328},
6910 - {0x0000b088, 0x19191c1e},
6911 - {0x0000b08c, 0x12141417},
6912 - {0x0000b090, 0x07070e0e},
6913 - {0x0000b094, 0x03030305},
6914 - {0x0000b098, 0x00000003},
6915 - {0x0000b09c, 0x00000000},
6916 - {0x0000b0a0, 0x00000000},
6917 - {0x0000b0a4, 0x00000000},
6918 - {0x0000b0a8, 0x00000000},
6919 - {0x0000b0ac, 0x00000000},
6920 - {0x0000b0b0, 0x00000000},
6921 - {0x0000b0b4, 0x00000000},
6922 - {0x0000b0b8, 0x00000000},
6923 - {0x0000b0bc, 0x00000000},
6924 - {0x0000b0c0, 0x003f0020},
6925 - {0x0000b0c4, 0x00400041},
6926 - {0x0000b0c8, 0x0140005f},
6927 - {0x0000b0cc, 0x0160015f},
6928 - {0x0000b0d0, 0x017e017f},
6929 - {0x0000b0d4, 0x02410242},
6930 - {0x0000b0d8, 0x025f0240},
6931 - {0x0000b0dc, 0x027f0260},
6932 - {0x0000b0e0, 0x0341027e},
6933 - {0x0000b0e4, 0x035f0340},
6934 - {0x0000b0e8, 0x037f0360},
6935 - {0x0000b0ec, 0x04400441},
6936 - {0x0000b0f0, 0x0460045f},
6937 - {0x0000b0f4, 0x0541047f},
6938 - {0x0000b0f8, 0x055f0540},
6939 - {0x0000b0fc, 0x057f0560},
6940 - {0x0000b100, 0x06400641},
6941 - {0x0000b104, 0x0660065f},
6942 - {0x0000b108, 0x067e067f},
6943 - {0x0000b10c, 0x07410742},
6944 - {0x0000b110, 0x075f0740},
6945 - {0x0000b114, 0x077f0760},
6946 - {0x0000b118, 0x07800781},
6947 - {0x0000b11c, 0x07a0079f},
6948 - {0x0000b120, 0x07c107bf},
6949 - {0x0000b124, 0x000007c0},
6950 - {0x0000b128, 0x00000000},
6951 - {0x0000b12c, 0x00000000},
6952 - {0x0000b130, 0x00000000},
6953 - {0x0000b134, 0x00000000},
6954 - {0x0000b138, 0x00000000},
6955 - {0x0000b13c, 0x00000000},
6956 - {0x0000b140, 0x003f0020},
6957 - {0x0000b144, 0x00400041},
6958 - {0x0000b148, 0x0140005f},
6959 - {0x0000b14c, 0x0160015f},
6960 - {0x0000b150, 0x017e017f},
6961 - {0x0000b154, 0x02410242},
6962 - {0x0000b158, 0x025f0240},
6963 - {0x0000b15c, 0x027f0260},
6964 - {0x0000b160, 0x0341027e},
6965 - {0x0000b164, 0x035f0340},
6966 - {0x0000b168, 0x037f0360},
6967 - {0x0000b16c, 0x04400441},
6968 - {0x0000b170, 0x0460045f},
6969 - {0x0000b174, 0x0541047f},
6970 - {0x0000b178, 0x055f0540},
6971 - {0x0000b17c, 0x057f0560},
6972 - {0x0000b180, 0x06400641},
6973 - {0x0000b184, 0x0660065f},
6974 - {0x0000b188, 0x067e067f},
6975 - {0x0000b18c, 0x07410742},
6976 - {0x0000b190, 0x075f0740},
6977 - {0x0000b194, 0x077f0760},
6978 - {0x0000b198, 0x07800781},
6979 - {0x0000b19c, 0x07a0079f},
6980 - {0x0000b1a0, 0x07c107bf},
6981 - {0x0000b1a4, 0x000007c0},
6982 - {0x0000b1a8, 0x00000000},
6983 - {0x0000b1ac, 0x00000000},
6984 - {0x0000b1b0, 0x00000000},
6985 - {0x0000b1b4, 0x00000000},
6986 - {0x0000b1b8, 0x00000000},
6987 - {0x0000b1bc, 0x00000000},
6988 - {0x0000b1c0, 0x00000000},
6989 - {0x0000b1c4, 0x00000000},
6990 - {0x0000b1c8, 0x00000000},
6991 - {0x0000b1cc, 0x00000000},
6992 - {0x0000b1d0, 0x00000000},
6993 - {0x0000b1d4, 0x00000000},
6994 - {0x0000b1d8, 0x00000000},
6995 - {0x0000b1dc, 0x00000000},
6996 - {0x0000b1e0, 0x00000000},
6997 - {0x0000b1e4, 0x00000000},
6998 - {0x0000b1e8, 0x00000000},
6999 - {0x0000b1ec, 0x00000000},
7000 - {0x0000b1f0, 0x00000396},
7001 - {0x0000b1f4, 0x00000396},
7002 - {0x0000b1f8, 0x00000396},
7003 - {0x0000b1fc, 0x00000196},
7004 -};
7005 -
7006 -static const u32 ar9462_2p1_modes_low_ob_db_tx_gain[][5] = {
7007 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7008 - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
7009 - {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
7010 - {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
7011 - {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
7012 - {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7013 - {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
7014 - {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7015 - {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7016 - {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
7017 - {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
7018 - {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
7019 - {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
7020 - {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
7021 - {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
7022 - {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
7023 - {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
7024 - {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
7025 - {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
7026 - {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
7027 - {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
7028 - {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
7029 - {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
7030 - {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
7031 - {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
7032 - {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
7033 - {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
7034 - {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
7035 - {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
7036 - {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
7037 - {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
7038 - {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
7039 - {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
7040 - {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
7041 - {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
7042 - {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
7043 - {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
7044 - {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
7045 - {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
7046 - {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
7047 - {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7048 - {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7049 - {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7050 - {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7051 - {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7052 - {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
7053 - {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
7054 - {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
7055 - {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
7056 - {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
7057 - {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
7058 - {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
7059 - {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
7060 - {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
7061 - {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
7062 - {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
7063 - {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
7064 - {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
7065 - {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
7066 - {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7067 - {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
7068 - {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
7069 - {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
7070 - {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
7071 - {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
7072 - {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
7073 -};
7074 -
7075 -static const u32 ar9462_2p1_modes_high_ob_db_tx_gain[][5] = {
7076 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7077 - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
7078 - {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
7079 - {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
7080 - {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
7081 - {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7082 - {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de},
7083 - {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7084 - {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
7085 - {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
7086 - {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
7087 - {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
7088 - {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
7089 - {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
7090 - {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
7091 - {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
7092 - {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
7093 - {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
7094 - {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
7095 - {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
7096 - {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
7097 - {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
7098 - {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
7099 - {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
7100 - {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
7101 - {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
7102 - {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81},
7103 - {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83},
7104 - {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84},
7105 - {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
7106 - {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
7107 - {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
7108 - {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
7109 - {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec},
7110 - {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0},
7111 - {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4},
7112 - {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
7113 - {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
7114 - {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
7115 - {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
7116 - {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7117 - {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7118 - {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7119 - {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7120 - {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
7121 - {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
7122 - {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
7123 - {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
7124 - {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
7125 - {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
7126 - {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
7127 - {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7128 - {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7129 - {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7130 - {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7131 - {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7132 - {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
7133 - {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
7134 - {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
7135 - {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7136 - {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
7137 - {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060},
7138 - {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
7139 - {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
7140 - {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
7141 - {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
7142 -};
7143 -
7144 -static const u32 ar9462_2p1_modes_mix_ob_db_tx_gain[][5] = {
7145 - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7146 - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
7147 - {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
7148 - {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
7149 - {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
7150 - {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7151 - {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de},
7152 - {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7153 - {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
7154 - {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
7155 - {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
7156 - {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
7157 - {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
7158 - {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400},
7159 - {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402},
7160 - {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
7161 - {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603},
7162 - {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02},
7163 - {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04},
7164 - {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20},
7165 - {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20},
7166 - {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22},
7167 - {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24},
7168 - {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640},
7169 - {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660},
7170 - {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861},
7171 - {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81},
7172 - {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83},
7173 - {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84},
7174 - {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3},
7175 - {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5},
7176 - {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9},
7177 - {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb},
7178 - {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec},
7179 - {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0},
7180 - {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4},
7181 - {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
7182 - {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
7183 - {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
7184 - {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
7185 - {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7186 - {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7187 - {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7188 - {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7189 - {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
7190 - {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
7191 - {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
7192 - {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
7193 - {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
7194 - {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
7195 - {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
7196 - {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7197 - {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7198 - {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7199 - {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7200 - {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
7201 - {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
7202 - {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
7203 - {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
7204 - {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7205 -};
7206 -
7207 -static const u32 ar9462_2p1_modes_fast_clock[][3] = {
7208 - /* Addr 5G_HT20 5G_HT40 */
7209 - {0x00001030, 0x00000268, 0x000004d0},
7210 - {0x00001070, 0x0000018c, 0x00000318},
7211 - {0x000010b0, 0x00000fd0, 0x00001fa0},
7212 - {0x00008014, 0x044c044c, 0x08980898},
7213 - {0x0000801c, 0x148ec02b, 0x148ec057},
7214 - {0x00008318, 0x000044c0, 0x00008980},
7215 - {0x00009e00, 0x0372131c, 0x0372131c},
7216 - {0x0000a230, 0x0000400b, 0x00004016},
7217 - {0x0000a254, 0x00000898, 0x00001130},
7218 -};
7219 -
7220 -static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = {
7221 - /* Addr allmodes */
7222 - {0x0000a398, 0x00000000},
7223 - {0x0000a39c, 0x6f7f0301},
7224 - {0x0000a3a0, 0xca9228ee},
7225 -};
7226 -
7227 #endif /* INITVALS_9462_2P1_H */
7228 --- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
7229 +++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
7230 @@ -32,13 +32,6 @@ static const u32 ar9485_1_1_mac_postambl
7231 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
7232 };
7233
7234 -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
7235 - /* Addr allmodes */
7236 - {0x00018c00, 0x18012e5e},
7237 - {0x00018c04, 0x000801d8},
7238 - {0x00018c08, 0x0000080c},
7239 -};
7240 -
7241 static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
7242 /* Addr allmodes */
7243 {0x00009e00, 0x037216a0},
7244 @@ -1101,20 +1094,6 @@ static const u32 ar9485_common_rx_gain_1
7245 {0x0000a1fc, 0x00000296},
7246 };
7247
7248 -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
7249 - /* Addr allmodes */
7250 - {0x00018c00, 0x18052e5e},
7251 - {0x00018c04, 0x000801d8},
7252 - {0x00018c08, 0x0000080c},
7253 -};
7254 -
7255 -static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
7256 - /* Addr allmodes */
7257 - {0x00018c00, 0x18053e5e},
7258 - {0x00018c04, 0x000801d8},
7259 - {0x00018c08, 0x0000080c},
7260 -};
7261 -
7262 static const u32 ar9485_1_1_soc_preamble[][2] = {
7263 /* Addr allmodes */
7264 {0x00004014, 0xba280400},
7265 @@ -1173,13 +1152,6 @@ static const u32 ar9485_1_1_baseband_pos
7266 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7267 };
7268
7269 -static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
7270 - /* Addr allmodes */
7271 - {0x00018c00, 0x18013e5e},
7272 - {0x00018c04, 0x000801d8},
7273 - {0x00018c08, 0x0000080c},
7274 -};
7275 -
7276 static const u32 ar9485_1_1_radio_postamble[][2] = {
7277 /* Addr allmodes */
7278 {0x0001609c, 0x0b283f31},
7279 @@ -1358,4 +1330,18 @@ static const u32 ar9485_1_1_baseband_cor
7280 {0x0000a3a0, 0xca9228ee},
7281 };
7282
7283 +static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
7284 + /* Addr allmodes */
7285 + {0x00018c00, 0x18013e5e},
7286 + {0x00018c04, 0x000801d8},
7287 + {0x00018c08, 0x0000080c},
7288 +};
7289 +
7290 +static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
7291 + /* Addr allmodes */
7292 + {0x00018c00, 0x1801265e},
7293 + {0x00018c04, 0x000801d8},
7294 + {0x00018c08, 0x0000080c},
7295 +};
7296 +
7297 #endif /* INITVALS_9485_H */
7298 --- a/drivers/net/wireless/ath/ath9k/pci.c
7299 +++ b/drivers/net/wireless/ath/ath9k/pci.c
7300 @@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
7301 0x3219),
7302 .driver_data = ATH9K_PCI_BT_ANT_DIV },
7303
7304 + /* AR9485 cards with PLL power-save disabled by default. */
7305 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7306 + 0x0032,
7307 + PCI_VENDOR_ID_AZWAVE,
7308 + 0x2C97),
7309 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7310 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7311 + 0x0032,
7312 + PCI_VENDOR_ID_AZWAVE,
7313 + 0x2100),
7314 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7315 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7316 + 0x0032,
7317 + 0x1C56, /* ASKEY */
7318 + 0x4001),
7319 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7320 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7321 + 0x0032,
7322 + 0x11AD, /* LITEON */
7323 + 0x6627),
7324 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7325 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7326 + 0x0032,
7327 + 0x11AD, /* LITEON */
7328 + 0x6628),
7329 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7330 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7331 + 0x0032,
7332 + PCI_VENDOR_ID_FOXCONN,
7333 + 0xE04E),
7334 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7335 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7336 + 0x0032,
7337 + PCI_VENDOR_ID_FOXCONN,
7338 + 0xE04F),
7339 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7340 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7341 + 0x0032,
7342 + 0x144F, /* ASKEY */
7343 + 0x7197),
7344 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7345 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7346 + 0x0032,
7347 + 0x1B9A, /* XAVI */
7348 + 0x2000),
7349 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7350 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7351 + 0x0032,
7352 + 0x1B9A, /* XAVI */
7353 + 0x2001),
7354 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7355 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7356 + 0x0032,
7357 + PCI_VENDOR_ID_AZWAVE,
7358 + 0x1186),
7359 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7360 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7361 + 0x0032,
7362 + PCI_VENDOR_ID_AZWAVE,
7363 + 0x1F86),
7364 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7365 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7366 + 0x0032,
7367 + PCI_VENDOR_ID_AZWAVE,
7368 + 0x1195),
7369 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7370 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7371 + 0x0032,
7372 + PCI_VENDOR_ID_AZWAVE,
7373 + 0x1F95),
7374 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7375 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7376 + 0x0032,
7377 + 0x1B9A, /* XAVI */
7378 + 0x1C00),
7379 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7380 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7381 + 0x0032,
7382 + 0x1B9A, /* XAVI */
7383 + 0x1C01),
7384 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7385 + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
7386 + 0x0032,
7387 + PCI_VENDOR_ID_ASUSTEK,
7388 + 0x850D),
7389 + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
7390 +
7391 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
7392 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
7393
7394 --- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
7395 +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
7396 @@ -20,7 +20,7 @@
7397
7398 /* AR9462 2.0 */
7399
7400 -static const u32 ar9462_modes_fast_clock_2p0[][3] = {
7401 +static const u32 ar9462_2p0_modes_fast_clock[][3] = {
7402 /* Addr 5G_HT20 5G_HT40 */
7403 {0x00001030, 0x00000268, 0x000004d0},
7404 {0x00001070, 0x0000018c, 0x00000318},
7405 @@ -33,13 +33,6 @@ static const u32 ar9462_modes_fast_clock
7406 {0x0000a254, 0x00000898, 0x00001130},
7407 };
7408
7409 -static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
7410 - /* Addr allmodes */
7411 - {0x00018c00, 0x18253ede},
7412 - {0x00018c04, 0x000801d8},
7413 - {0x00018c08, 0x0003780c},
7414 -};
7415 -
7416 static const u32 ar9462_2p0_baseband_postamble[][5] = {
7417 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7418 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
7419 @@ -99,7 +92,7 @@ static const u32 ar9462_2p0_baseband_pos
7420 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
7421 };
7422
7423 -static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
7424 +static const u32 ar9462_2p0_common_rx_gain[][2] = {
7425 /* Addr allmodes */
7426 {0x0000a000, 0x00010000},
7427 {0x0000a004, 0x00030002},
7428 @@ -359,20 +352,13 @@ static const u32 ar9462_common_rx_gain_t
7429 {0x0000b1fc, 0x00000196},
7430 };
7431
7432 -static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
7433 +static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = {
7434 /* Addr allmodes */
7435 {0x00018c00, 0x18213ede},
7436 {0x00018c04, 0x000801d8},
7437 {0x00018c08, 0x0003780c},
7438 };
7439
7440 -static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
7441 - /* Addr allmodes */
7442 - {0x00018c00, 0x18212ede},
7443 - {0x00018c04, 0x000801d8},
7444 - {0x00018c08, 0x0003780c},
7445 -};
7446 -
7447 static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
7448 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7449 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
7450 @@ -380,7 +366,7 @@ static const u32 ar9462_2p0_radio_postam
7451 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
7452 };
7453
7454 -static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
7455 +static const u32 ar9462_2p0_common_wo_xlna_rx_gain[][2] = {
7456 /* Addr allmodes */
7457 {0x0000a000, 0x00010000},
7458 {0x0000a004, 0x00030002},
7459 @@ -647,7 +633,7 @@ static const u32 ar9462_2p0_baseband_cor
7460 {0x0000a3a0, 0xca9228ee},
7461 };
7462
7463 -static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
7464 +static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = {
7465 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7466 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
7467 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
7468 @@ -879,7 +865,7 @@ static const u32 ar9462_2p0_radio_postam
7469 {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
7470 };
7471
7472 -static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = {
7473 +static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = {
7474 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7475 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
7476 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
7477 @@ -942,7 +928,7 @@ static const u32 ar9462_modes_mix_ob_db_
7478 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7479 };
7480
7481 -static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
7482 +static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = {
7483 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7484 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
7485 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
7486 @@ -1252,7 +1238,7 @@ static const u32 ar9462_2p0_mac_postambl
7487 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
7488 };
7489
7490 -static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
7491 +static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = {
7492 /* Addr allmodes */
7493 {0x0000a000, 0x00010000},
7494 {0x0000a004, 0x00030002},
7495 @@ -1517,7 +1503,7 @@ static const u32 ar9462_2p0_baseband_pos
7496 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
7497 };
7498
7499 -static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = {
7500 +static const u32 ar9462_2p0_common_5g_xlna_only_rxgain[][2] = {
7501 /* Addr allmodes */
7502 {0x0000a000, 0x00010000},
7503 {0x0000a004, 0x00030002},
7504 --- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
7505 +++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
7506 @@ -352,7 +352,7 @@ static const u32 ar9300_2p2_baseband_pos
7507 {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
7508 {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
7509 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
7510 - {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
7511 + {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
7512 {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
7513 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7514 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
7515 @@ -378,9 +378,9 @@ static const u32 ar9300_2p2_baseband_cor
7516 {0x00009814, 0x9280c00a},
7517 {0x00009818, 0x00000000},
7518 {0x0000981c, 0x00020028},
7519 - {0x00009834, 0x6400a290},
7520 + {0x00009834, 0x6400a190},
7521 {0x00009838, 0x0108ecff},
7522 - {0x0000983c, 0x0d000600},
7523 + {0x0000983c, 0x14000600},
7524 {0x00009880, 0x201fff00},
7525 {0x00009884, 0x00001042},
7526 {0x000098a4, 0x00200400},
7527 @@ -401,7 +401,7 @@ static const u32 ar9300_2p2_baseband_cor
7528 {0x00009d04, 0x40206c10},
7529 {0x00009d08, 0x009c4060},
7530 {0x00009d0c, 0x9883800a},
7531 - {0x00009d10, 0x01834061},
7532 + {0x00009d10, 0x01884061},
7533 {0x00009d14, 0x00c0040b},
7534 {0x00009d18, 0x00000000},
7535 {0x00009e08, 0x0038230c},
7536 @@ -459,7 +459,7 @@ static const u32 ar9300_2p2_baseband_cor
7537 {0x0000a3e8, 0x20202020},
7538 {0x0000a3ec, 0x20202020},
7539 {0x0000a3f0, 0x00000000},
7540 - {0x0000a3f4, 0x00000246},
7541 + {0x0000a3f4, 0x00000000},
7542 {0x0000a3f8, 0x0c9bd380},
7543 {0x0000a3fc, 0x000f0f01},
7544 {0x0000a400, 0x8fa91f01},
7545 @@ -644,7 +644,7 @@ static const u32 ar9300Modes_high_ob_db_
7546 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
7547 {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
7548 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7549 - {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
7550 + {0x0000a410, 0x000050d4, 0x000050d4, 0x000050d9, 0x000050d9},
7551 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
7552 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
7553 {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
7554 @@ -1086,8 +1086,8 @@ static const u32 ar9300Common_rx_gain_ta
7555 {0x0000b074, 0x00000000},
7556 {0x0000b078, 0x00000000},
7557 {0x0000b07c, 0x00000000},
7558 - {0x0000b080, 0x2a2d2f32},
7559 - {0x0000b084, 0x21232328},
7560 + {0x0000b080, 0x23232323},
7561 + {0x0000b084, 0x21232323},
7562 {0x0000b088, 0x19191c1e},
7563 {0x0000b08c, 0x12141417},
7564 {0x0000b090, 0x07070e0e},
7565 @@ -1385,9 +1385,9 @@ static const u32 ar9300_2p2_mac_core[][2
7566 {0x000081f8, 0x00000000},
7567 {0x000081fc, 0x00000000},
7568 {0x00008240, 0x00100000},
7569 - {0x00008244, 0x0010f424},
7570 + {0x00008244, 0x0010f400},
7571 {0x00008248, 0x00000800},
7572 - {0x0000824c, 0x0001e848},
7573 + {0x0000824c, 0x0001e800},
7574 {0x00008250, 0x00000000},
7575 {0x00008254, 0x00000000},
7576 {0x00008258, 0x00000000},
7577 @@ -1726,14 +1726,14 @@ static const u32 ar9300PciePhy_pll_on_cl
7578
7579 static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
7580 /* Addr allmodes */
7581 - {0x00004040, 0x08253e5e},
7582 + {0x00004040, 0x0825365e},
7583 {0x00004040, 0x0008003b},
7584 {0x00004044, 0x00000000},
7585 };
7586
7587 static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
7588 /* Addr allmodes */
7589 - {0x00004040, 0x08213e5e},
7590 + {0x00004040, 0x0821365e},
7591 {0x00004040, 0x0008003b},
7592 {0x00004044, 0x00000000},
7593 };
7594 --- /dev/null
7595 +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p1_initvals.h
7596 @@ -0,0 +1,64 @@
7597 +/*
7598 + * Copyright (c) 2010-2011 Atheros Communications Inc.
7599 + * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
7600 + *
7601 + * Permission to use, copy, modify, and/or distribute this software for any
7602 + * purpose with or without fee is hereby granted, provided that the above
7603 + * copyright notice and this permission notice appear in all copies.
7604 + *
7605 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
7606 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
7607 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
7608 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
7609 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
7610 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
7611 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
7612 + */
7613 +
7614 +#ifndef INITVALS_9565_1P1_H
7615 +#define INITVALS_9565_1P1_H
7616 +
7617 +/* AR9565 1.1 */
7618 +
7619 +#define ar9565_1p1_mac_core ar9565_1p0_mac_core
7620 +
7621 +#define ar9565_1p1_mac_postamble ar9565_1p0_mac_postamble
7622 +
7623 +#define ar9565_1p1_baseband_core ar9565_1p0_baseband_core
7624 +
7625 +#define ar9565_1p1_baseband_postamble ar9565_1p0_baseband_postamble
7626 +
7627 +#define ar9565_1p1_radio_core ar9565_1p0_radio_core
7628 +
7629 +#define ar9565_1p1_soc_preamble ar9565_1p0_soc_preamble
7630 +
7631 +#define ar9565_1p1_soc_postamble ar9565_1p0_soc_postamble
7632 +
7633 +#define ar9565_1p1_Common_rx_gain_table ar9565_1p0_Common_rx_gain_table
7634 +
7635 +#define ar9565_1p1_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_Modes_lowest_ob_db_tx_gain_table
7636 +
7637 +#define ar9565_1p1_pciephy_clkreq_disable_L1 ar9565_1p0_pciephy_clkreq_disable_L1
7638 +
7639 +#define ar9565_1p1_modes_fast_clock ar9565_1p0_modes_fast_clock
7640 +
7641 +#define ar9565_1p1_common_wo_xlna_rx_gain_table ar9565_1p0_common_wo_xlna_rx_gain_table
7642 +
7643 +#define ar9565_1p1_modes_low_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
7644 +
7645 +#define ar9565_1p1_modes_high_ob_db_tx_gain_table ar9565_1p0_modes_high_ob_db_tx_gain_table
7646 +
7647 +#define ar9565_1p1_modes_high_power_tx_gain_table ar9565_1p0_modes_high_power_tx_gain_table
7648 +
7649 +#define ar9565_1p1_baseband_core_txfir_coeff_japan_2484 ar9565_1p0_baseband_core_txfir_coeff_japan_2484
7650 +
7651 +static const u32 ar9565_1p1_radio_postamble[][5] = {
7652 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7653 + {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
7654 + {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
7655 + {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
7656 + {0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000},
7657 + {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
7658 +};
7659 +
7660 +#endif /* INITVALS_9565_1P1_H */
7661 --- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
7662 +++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
7663 @@ -20,18 +20,34 @@
7664
7665 /* AR9580 1.0 */
7666
7667 +#define ar9580_1p0_soc_preamble ar9300_2p2_soc_preamble
7668 +
7669 +#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
7670 +
7671 +#define ar9580_1p0_radio_core ar9300_2p2_radio_core
7672 +
7673 +#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
7674 +
7675 +#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
7676 +
7677 +#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
7678 +
7679 +#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
7680 +
7681 #define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
7682
7683 +#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
7684 +
7685 static const u32 ar9580_1p0_radio_postamble[][5] = {
7686 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7687 {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
7688 {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
7689 {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
7690 - {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
7691 + {0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
7692 {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
7693 - {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
7694 + {0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
7695 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
7696 - {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
7697 + {0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
7698 {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
7699 };
7700
7701 @@ -44,9 +60,9 @@ static const u32 ar9580_1p0_baseband_cor
7702 {0x00009814, 0x3280c00a},
7703 {0x00009818, 0x00000000},
7704 {0x0000981c, 0x00020028},
7705 - {0x00009834, 0x6400a290},
7706 + {0x00009834, 0x6400a190},
7707 {0x00009838, 0x0108ecff},
7708 - {0x0000983c, 0x0d000600},
7709 + {0x0000983c, 0x14000600},
7710 {0x00009880, 0x201fff00},
7711 {0x00009884, 0x00001042},
7712 {0x000098a4, 0x00200400},
7713 @@ -67,7 +83,7 @@ static const u32 ar9580_1p0_baseband_cor
7714 {0x00009d04, 0x40206c10},
7715 {0x00009d08, 0x009c4060},
7716 {0x00009d0c, 0x9883800a},
7717 - {0x00009d10, 0x01834061},
7718 + {0x00009d10, 0x01884061},
7719 {0x00009d14, 0x00c0040b},
7720 {0x00009d18, 0x00000000},
7721 {0x00009e08, 0x0038230c},
7722 @@ -198,8 +214,6 @@ static const u32 ar9580_1p0_baseband_cor
7723 {0x0000c420, 0x00000000},
7724 };
7725
7726 -#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
7727 -
7728 static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
7729 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7730 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
7731 @@ -306,7 +320,112 @@ static const u32 ar9580_1p0_low_ob_db_tx
7732 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
7733 };
7734
7735 -#define ar9580_1p0_high_power_tx_gain_table ar9580_1p0_low_ob_db_tx_gain_table
7736 +static const u32 ar9580_1p0_high_power_tx_gain_table[][5] = {
7737 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7738 + {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
7739 + {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
7740 + {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
7741 + {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7742 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
7743 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7744 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
7745 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
7746 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
7747 + {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
7748 + {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
7749 + {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
7750 + {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
7751 + {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
7752 + {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
7753 + {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
7754 + {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
7755 + {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
7756 + {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
7757 + {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
7758 + {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
7759 + {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
7760 + {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
7761 + {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
7762 + {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
7763 + {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
7764 + {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
7765 + {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
7766 + {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
7767 + {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
7768 + {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
7769 + {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
7770 + {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
7771 + {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
7772 + {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
7773 + {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
7774 + {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
7775 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
7776 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
7777 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
7778 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
7779 + {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
7780 + {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
7781 + {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
7782 + {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
7783 + {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
7784 + {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
7785 + {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
7786 + {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
7787 + {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
7788 + {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
7789 + {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
7790 + {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
7791 + {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
7792 + {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
7793 + {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
7794 + {0x0000a5cc, 0x5a88442e, 0x5a88442e, 0x47801a83, 0x47801a83},
7795 + {0x0000a5d0, 0x5e8a4431, 0x5e8a4431, 0x4a801c84, 0x4a801c84},
7796 + {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
7797 + {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
7798 + {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
7799 + {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
7800 + {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
7801 + {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
7802 + {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
7803 + {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
7804 + {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
7805 + {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
7806 + {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
7807 + {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7808 + {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
7809 + {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
7810 + {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
7811 + {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
7812 + {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
7813 + {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
7814 + {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
7815 + {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
7816 + {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
7817 + {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
7818 + {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
7819 + {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
7820 + {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
7821 + {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
7822 + {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
7823 + {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
7824 + {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
7825 + {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
7826 + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7827 + {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
7828 + {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
7829 + {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
7830 + {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
7831 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
7832 + {0x00016048, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
7833 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
7834 + {0x00016288, 0x05a2040a, 0x05a2040a, 0x05a20408, 0x05a20408},
7835 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
7836 + {0x00016448, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
7837 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
7838 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
7839 + {0x00016848, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
7840 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
7841 +};
7842
7843 static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
7844 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7845 @@ -414,8 +533,6 @@ static const u32 ar9580_1p0_lowest_ob_db
7846 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
7847 };
7848
7849 -#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
7850 -
7851 static const u32 ar9580_1p0_mac_core[][2] = {
7852 /* Addr allmodes */
7853 {0x00000008, 0x00000000},
7854 @@ -679,14 +796,6 @@ static const u32 ar9580_1p0_mixed_ob_db_
7855 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
7856 };
7857
7858 -#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
7859 -
7860 -#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
7861 -
7862 -#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
7863 -
7864 -#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
7865 -
7866 static const u32 ar9580_1p0_type6_tx_gain_table[][5] = {
7867 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
7868 {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
7869 @@ -761,160 +870,264 @@ static const u32 ar9580_1p0_type6_tx_gai
7870 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
7871 };
7872
7873 -static const u32 ar9580_1p0_soc_preamble[][2] = {
7874 - /* Addr allmodes */
7875 - {0x000040a4, 0x00a0c1c9},
7876 - {0x00007008, 0x00000000},
7877 - {0x00007020, 0x00000000},
7878 - {0x00007034, 0x00000002},
7879 - {0x00007038, 0x000004c2},
7880 - {0x00007048, 0x00000008},
7881 -};
7882 -
7883 -#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0
7884 -
7885 -static const u32 ar9580_1p0_radio_core[][2] = {
7886 +static const u32 ar9580_1p0_rx_gain_table[][2] = {
7887 /* Addr allmodes */
7888 - {0x00016000, 0x36db6db6},
7889 - {0x00016004, 0x6db6db40},
7890 - {0x00016008, 0x73f00000},
7891 - {0x0001600c, 0x00000000},
7892 - {0x00016040, 0x7f80fff8},
7893 - {0x0001604c, 0x76d005b5},
7894 - {0x00016050, 0x556cf031},
7895 - {0x00016054, 0x13449440},
7896 - {0x00016058, 0x0c51c92c},
7897 - {0x0001605c, 0x3db7fffc},
7898 - {0x00016060, 0xfffffffc},
7899 - {0x00016064, 0x000f0278},
7900 - {0x0001606c, 0x6db60000},
7901 - {0x00016080, 0x00000000},
7902 - {0x00016084, 0x0e48048c},
7903 - {0x00016088, 0x54214514},
7904 - {0x0001608c, 0x119f481e},
7905 - {0x00016090, 0x24926490},
7906 - {0x00016098, 0xd2888888},
7907 - {0x000160a0, 0x0a108ffe},
7908 - {0x000160a4, 0x812fc370},
7909 - {0x000160a8, 0x423c8000},
7910 - {0x000160b4, 0x92480080},
7911 - {0x000160c0, 0x00adb6d0},
7912 - {0x000160c4, 0x6db6db60},
7913 - {0x000160c8, 0x6db6db6c},
7914 - {0x000160cc, 0x01e6c000},
7915 - {0x00016100, 0x3fffbe01},
7916 - {0x00016104, 0xfff80000},
7917 - {0x00016108, 0x00080010},
7918 - {0x00016144, 0x02084080},
7919 - {0x00016148, 0x00000000},
7920 - {0x00016280, 0x058a0001},
7921 - {0x00016284, 0x3d840208},
7922 - {0x00016288, 0x05a20408},
7923 - {0x0001628c, 0x00038c07},
7924 - {0x00016290, 0x00000004},
7925 - {0x00016294, 0x458aa14f},
7926 - {0x00016380, 0x00000000},
7927 - {0x00016384, 0x00000000},
7928 - {0x00016388, 0x00800700},
7929 - {0x0001638c, 0x00800700},
7930 - {0x00016390, 0x00800700},
7931 - {0x00016394, 0x00000000},
7932 - {0x00016398, 0x00000000},
7933 - {0x0001639c, 0x00000000},
7934 - {0x000163a0, 0x00000001},
7935 - {0x000163a4, 0x00000001},
7936 - {0x000163a8, 0x00000000},
7937 - {0x000163ac, 0x00000000},
7938 - {0x000163b0, 0x00000000},
7939 - {0x000163b4, 0x00000000},
7940 - {0x000163b8, 0x00000000},
7941 - {0x000163bc, 0x00000000},
7942 - {0x000163c0, 0x000000a0},
7943 - {0x000163c4, 0x000c0000},
7944 - {0x000163c8, 0x14021402},
7945 - {0x000163cc, 0x00001402},
7946 - {0x000163d0, 0x00000000},
7947 - {0x000163d4, 0x00000000},
7948 - {0x00016400, 0x36db6db6},
7949 - {0x00016404, 0x6db6db40},
7950 - {0x00016408, 0x73f00000},
7951 - {0x0001640c, 0x00000000},
7952 - {0x00016440, 0x7f80fff8},
7953 - {0x0001644c, 0x76d005b5},
7954 - {0x00016450, 0x556cf031},
7955 - {0x00016454, 0x13449440},
7956 - {0x00016458, 0x0c51c92c},
7957 - {0x0001645c, 0x3db7fffc},
7958 - {0x00016460, 0xfffffffc},
7959 - {0x00016464, 0x000f0278},
7960 - {0x0001646c, 0x6db60000},
7961 - {0x00016500, 0x3fffbe01},
7962 - {0x00016504, 0xfff80000},
7963 - {0x00016508, 0x00080010},
7964 - {0x00016544, 0x02084080},
7965 - {0x00016548, 0x00000000},
7966 - {0x00016780, 0x00000000},
7967 - {0x00016784, 0x00000000},
7968 - {0x00016788, 0x00800700},
7969 - {0x0001678c, 0x00800700},
7970 - {0x00016790, 0x00800700},
7971 - {0x00016794, 0x00000000},
7972 - {0x00016798, 0x00000000},
7973 - {0x0001679c, 0x00000000},
7974 - {0x000167a0, 0x00000001},
7975 - {0x000167a4, 0x00000001},
7976 - {0x000167a8, 0x00000000},
7977 - {0x000167ac, 0x00000000},
7978 - {0x000167b0, 0x00000000},
7979 - {0x000167b4, 0x00000000},
7980 - {0x000167b8, 0x00000000},
7981 - {0x000167bc, 0x00000000},
7982 - {0x000167c0, 0x000000a0},
7983 - {0x000167c4, 0x000c0000},
7984 - {0x000167c8, 0x14021402},
7985 - {0x000167cc, 0x00001402},
7986 - {0x000167d0, 0x00000000},
7987 - {0x000167d4, 0x00000000},
7988 - {0x00016800, 0x36db6db6},
7989 - {0x00016804, 0x6db6db40},
7990 - {0x00016808, 0x73f00000},
7991 - {0x0001680c, 0x00000000},
7992 - {0x00016840, 0x7f80fff8},
7993 - {0x0001684c, 0x76d005b5},
7994 - {0x00016850, 0x556cf031},
7995 - {0x00016854, 0x13449440},
7996 - {0x00016858, 0x0c51c92c},
7997 - {0x0001685c, 0x3db7fffc},
7998 - {0x00016860, 0xfffffffc},
7999 - {0x00016864, 0x000f0278},
8000 - {0x0001686c, 0x6db60000},
8001 - {0x00016900, 0x3fffbe01},
8002 - {0x00016904, 0xfff80000},
8003 - {0x00016908, 0x00080010},
8004 - {0x00016944, 0x02084080},
8005 - {0x00016948, 0x00000000},
8006 - {0x00016b80, 0x00000000},
8007 - {0x00016b84, 0x00000000},
8008 - {0x00016b88, 0x00800700},
8009 - {0x00016b8c, 0x00800700},
8010 - {0x00016b90, 0x00800700},
8011 - {0x00016b94, 0x00000000},
8012 - {0x00016b98, 0x00000000},
8013 - {0x00016b9c, 0x00000000},
8014 - {0x00016ba0, 0x00000001},
8015 - {0x00016ba4, 0x00000001},
8016 - {0x00016ba8, 0x00000000},
8017 - {0x00016bac, 0x00000000},
8018 - {0x00016bb0, 0x00000000},
8019 - {0x00016bb4, 0x00000000},
8020 - {0x00016bb8, 0x00000000},
8021 - {0x00016bbc, 0x00000000},
8022 - {0x00016bc0, 0x000000a0},
8023 - {0x00016bc4, 0x000c0000},
8024 - {0x00016bc8, 0x14021402},
8025 - {0x00016bcc, 0x00001402},
8026 - {0x00016bd0, 0x00000000},
8027 - {0x00016bd4, 0x00000000},
8028 + {0x0000a000, 0x00010000},
8029 + {0x0000a004, 0x00030002},
8030 + {0x0000a008, 0x00050004},
8031 + {0x0000a00c, 0x00810080},
8032 + {0x0000a010, 0x00830082},
8033 + {0x0000a014, 0x01810180},
8034 + {0x0000a018, 0x01830182},
8035 + {0x0000a01c, 0x01850184},
8036 + {0x0000a020, 0x01890188},
8037 + {0x0000a024, 0x018b018a},
8038 + {0x0000a028, 0x018d018c},
8039 + {0x0000a02c, 0x01910190},
8040 + {0x0000a030, 0x01930192},
8041 + {0x0000a034, 0x01950194},
8042 + {0x0000a038, 0x038a0196},
8043 + {0x0000a03c, 0x038c038b},
8044 + {0x0000a040, 0x0390038d},
8045 + {0x0000a044, 0x03920391},
8046 + {0x0000a048, 0x03940393},
8047 + {0x0000a04c, 0x03960395},
8048 + {0x0000a050, 0x00000000},
8049 + {0x0000a054, 0x00000000},
8050 + {0x0000a058, 0x00000000},
8051 + {0x0000a05c, 0x00000000},
8052 + {0x0000a060, 0x00000000},
8053 + {0x0000a064, 0x00000000},
8054 + {0x0000a068, 0x00000000},
8055 + {0x0000a06c, 0x00000000},
8056 + {0x0000a070, 0x00000000},
8057 + {0x0000a074, 0x00000000},
8058 + {0x0000a078, 0x00000000},
8059 + {0x0000a07c, 0x00000000},
8060 + {0x0000a080, 0x22222229},
8061 + {0x0000a084, 0x1d1d1d1d},
8062 + {0x0000a088, 0x1d1d1d1d},
8063 + {0x0000a08c, 0x1d1d1d1d},
8064 + {0x0000a090, 0x171d1d1d},
8065 + {0x0000a094, 0x11111717},
8066 + {0x0000a098, 0x00030311},
8067 + {0x0000a09c, 0x00000000},
8068 + {0x0000a0a0, 0x00000000},
8069 + {0x0000a0a4, 0x00000000},
8070 + {0x0000a0a8, 0x00000000},
8071 + {0x0000a0ac, 0x00000000},
8072 + {0x0000a0b0, 0x00000000},
8073 + {0x0000a0b4, 0x00000000},
8074 + {0x0000a0b8, 0x00000000},
8075 + {0x0000a0bc, 0x00000000},
8076 + {0x0000a0c0, 0x001f0000},
8077 + {0x0000a0c4, 0x01000101},
8078 + {0x0000a0c8, 0x011e011f},
8079 + {0x0000a0cc, 0x011c011d},
8080 + {0x0000a0d0, 0x02030204},
8081 + {0x0000a0d4, 0x02010202},
8082 + {0x0000a0d8, 0x021f0200},
8083 + {0x0000a0dc, 0x0302021e},
8084 + {0x0000a0e0, 0x03000301},
8085 + {0x0000a0e4, 0x031e031f},
8086 + {0x0000a0e8, 0x0402031d},
8087 + {0x0000a0ec, 0x04000401},
8088 + {0x0000a0f0, 0x041e041f},
8089 + {0x0000a0f4, 0x0502041d},
8090 + {0x0000a0f8, 0x05000501},
8091 + {0x0000a0fc, 0x051e051f},
8092 + {0x0000a100, 0x06010602},
8093 + {0x0000a104, 0x061f0600},
8094 + {0x0000a108, 0x061d061e},
8095 + {0x0000a10c, 0x07020703},
8096 + {0x0000a110, 0x07000701},
8097 + {0x0000a114, 0x00000000},
8098 + {0x0000a118, 0x00000000},
8099 + {0x0000a11c, 0x00000000},
8100 + {0x0000a120, 0x00000000},
8101 + {0x0000a124, 0x00000000},
8102 + {0x0000a128, 0x00000000},
8103 + {0x0000a12c, 0x00000000},
8104 + {0x0000a130, 0x00000000},
8105 + {0x0000a134, 0x00000000},
8106 + {0x0000a138, 0x00000000},
8107 + {0x0000a13c, 0x00000000},
8108 + {0x0000a140, 0x001f0000},
8109 + {0x0000a144, 0x01000101},
8110 + {0x0000a148, 0x011e011f},
8111 + {0x0000a14c, 0x011c011d},
8112 + {0x0000a150, 0x02030204},
8113 + {0x0000a154, 0x02010202},
8114 + {0x0000a158, 0x021f0200},
8115 + {0x0000a15c, 0x0302021e},
8116 + {0x0000a160, 0x03000301},
8117 + {0x0000a164, 0x031e031f},
8118 + {0x0000a168, 0x0402031d},
8119 + {0x0000a16c, 0x04000401},
8120 + {0x0000a170, 0x041e041f},
8121 + {0x0000a174, 0x0502041d},
8122 + {0x0000a178, 0x05000501},
8123 + {0x0000a17c, 0x051e051f},
8124 + {0x0000a180, 0x06010602},
8125 + {0x0000a184, 0x061f0600},
8126 + {0x0000a188, 0x061d061e},
8127 + {0x0000a18c, 0x07020703},
8128 + {0x0000a190, 0x07000701},
8129 + {0x0000a194, 0x00000000},
8130 + {0x0000a198, 0x00000000},
8131 + {0x0000a19c, 0x00000000},
8132 + {0x0000a1a0, 0x00000000},
8133 + {0x0000a1a4, 0x00000000},
8134 + {0x0000a1a8, 0x00000000},
8135 + {0x0000a1ac, 0x00000000},
8136 + {0x0000a1b0, 0x00000000},
8137 + {0x0000a1b4, 0x00000000},
8138 + {0x0000a1b8, 0x00000000},
8139 + {0x0000a1bc, 0x00000000},
8140 + {0x0000a1c0, 0x00000000},
8141 + {0x0000a1c4, 0x00000000},
8142 + {0x0000a1c8, 0x00000000},
8143 + {0x0000a1cc, 0x00000000},
8144 + {0x0000a1d0, 0x00000000},
8145 + {0x0000a1d4, 0x00000000},
8146 + {0x0000a1d8, 0x00000000},
8147 + {0x0000a1dc, 0x00000000},
8148 + {0x0000a1e0, 0x00000000},
8149 + {0x0000a1e4, 0x00000000},
8150 + {0x0000a1e8, 0x00000000},
8151 + {0x0000a1ec, 0x00000000},
8152 + {0x0000a1f0, 0x00000396},
8153 + {0x0000a1f4, 0x00000396},
8154 + {0x0000a1f8, 0x00000396},
8155 + {0x0000a1fc, 0x00000196},
8156 + {0x0000b000, 0x00010000},
8157 + {0x0000b004, 0x00030002},
8158 + {0x0000b008, 0x00050004},
8159 + {0x0000b00c, 0x00810080},
8160 + {0x0000b010, 0x00830082},
8161 + {0x0000b014, 0x01810180},
8162 + {0x0000b018, 0x01830182},
8163 + {0x0000b01c, 0x01850184},
8164 + {0x0000b020, 0x02810280},
8165 + {0x0000b024, 0x02830282},
8166 + {0x0000b028, 0x02850284},
8167 + {0x0000b02c, 0x02890288},
8168 + {0x0000b030, 0x028b028a},
8169 + {0x0000b034, 0x0388028c},
8170 + {0x0000b038, 0x038a0389},
8171 + {0x0000b03c, 0x038c038b},
8172 + {0x0000b040, 0x0390038d},
8173 + {0x0000b044, 0x03920391},
8174 + {0x0000b048, 0x03940393},
8175 + {0x0000b04c, 0x03960395},
8176 + {0x0000b050, 0x00000000},
8177 + {0x0000b054, 0x00000000},
8178 + {0x0000b058, 0x00000000},
8179 + {0x0000b05c, 0x00000000},
8180 + {0x0000b060, 0x00000000},
8181 + {0x0000b064, 0x00000000},
8182 + {0x0000b068, 0x00000000},
8183 + {0x0000b06c, 0x00000000},
8184 + {0x0000b070, 0x00000000},
8185 + {0x0000b074, 0x00000000},
8186 + {0x0000b078, 0x00000000},
8187 + {0x0000b07c, 0x00000000},
8188 + {0x0000b080, 0x23232323},
8189 + {0x0000b084, 0x21232323},
8190 + {0x0000b088, 0x19191c1e},
8191 + {0x0000b08c, 0x12141417},
8192 + {0x0000b090, 0x07070e0e},
8193 + {0x0000b094, 0x03030305},
8194 + {0x0000b098, 0x00000003},
8195 + {0x0000b09c, 0x00000000},
8196 + {0x0000b0a0, 0x00000000},
8197 + {0x0000b0a4, 0x00000000},
8198 + {0x0000b0a8, 0x00000000},
8199 + {0x0000b0ac, 0x00000000},
8200 + {0x0000b0b0, 0x00000000},
8201 + {0x0000b0b4, 0x00000000},
8202 + {0x0000b0b8, 0x00000000},
8203 + {0x0000b0bc, 0x00000000},
8204 + {0x0000b0c0, 0x003f0020},
8205 + {0x0000b0c4, 0x00400041},
8206 + {0x0000b0c8, 0x0140005f},
8207 + {0x0000b0cc, 0x0160015f},
8208 + {0x0000b0d0, 0x017e017f},
8209 + {0x0000b0d4, 0x02410242},
8210 + {0x0000b0d8, 0x025f0240},
8211 + {0x0000b0dc, 0x027f0260},
8212 + {0x0000b0e0, 0x0341027e},
8213 + {0x0000b0e4, 0x035f0340},
8214 + {0x0000b0e8, 0x037f0360},
8215 + {0x0000b0ec, 0x04400441},
8216 + {0x0000b0f0, 0x0460045f},
8217 + {0x0000b0f4, 0x0541047f},
8218 + {0x0000b0f8, 0x055f0540},
8219 + {0x0000b0fc, 0x057f0560},
8220 + {0x0000b100, 0x06400641},
8221 + {0x0000b104, 0x0660065f},
8222 + {0x0000b108, 0x067e067f},
8223 + {0x0000b10c, 0x07410742},
8224 + {0x0000b110, 0x075f0740},
8225 + {0x0000b114, 0x077f0760},
8226 + {0x0000b118, 0x07800781},
8227 + {0x0000b11c, 0x07a0079f},
8228 + {0x0000b120, 0x07c107bf},
8229 + {0x0000b124, 0x000007c0},
8230 + {0x0000b128, 0x00000000},
8231 + {0x0000b12c, 0x00000000},
8232 + {0x0000b130, 0x00000000},
8233 + {0x0000b134, 0x00000000},
8234 + {0x0000b138, 0x00000000},
8235 + {0x0000b13c, 0x00000000},
8236 + {0x0000b140, 0x003f0020},
8237 + {0x0000b144, 0x00400041},
8238 + {0x0000b148, 0x0140005f},
8239 + {0x0000b14c, 0x0160015f},
8240 + {0x0000b150, 0x017e017f},
8241 + {0x0000b154, 0x02410242},
8242 + {0x0000b158, 0x025f0240},
8243 + {0x0000b15c, 0x027f0260},
8244 + {0x0000b160, 0x0341027e},
8245 + {0x0000b164, 0x035f0340},
8246 + {0x0000b168, 0x037f0360},
8247 + {0x0000b16c, 0x04400441},
8248 + {0x0000b170, 0x0460045f},
8249 + {0x0000b174, 0x0541047f},
8250 + {0x0000b178, 0x055f0540},
8251 + {0x0000b17c, 0x057f0560},
8252 + {0x0000b180, 0x06400641},
8253 + {0x0000b184, 0x0660065f},
8254 + {0x0000b188, 0x067e067f},
8255 + {0x0000b18c, 0x07410742},
8256 + {0x0000b190, 0x075f0740},
8257 + {0x0000b194, 0x077f0760},
8258 + {0x0000b198, 0x07800781},
8259 + {0x0000b19c, 0x07a0079f},
8260 + {0x0000b1a0, 0x07c107bf},
8261 + {0x0000b1a4, 0x000007c0},
8262 + {0x0000b1a8, 0x00000000},
8263 + {0x0000b1ac, 0x00000000},
8264 + {0x0000b1b0, 0x00000000},
8265 + {0x0000b1b4, 0x00000000},
8266 + {0x0000b1b8, 0x00000000},
8267 + {0x0000b1bc, 0x00000000},
8268 + {0x0000b1c0, 0x00000000},
8269 + {0x0000b1c4, 0x00000000},
8270 + {0x0000b1c8, 0x00000000},
8271 + {0x0000b1cc, 0x00000000},
8272 + {0x0000b1d0, 0x00000000},
8273 + {0x0000b1d4, 0x00000000},
8274 + {0x0000b1d8, 0x00000000},
8275 + {0x0000b1dc, 0x00000000},
8276 + {0x0000b1e0, 0x00000000},
8277 + {0x0000b1e4, 0x00000000},
8278 + {0x0000b1e8, 0x00000000},
8279 + {0x0000b1ec, 0x00000000},
8280 + {0x0000b1f0, 0x00000396},
8281 + {0x0000b1f4, 0x00000396},
8282 + {0x0000b1f8, 0x00000396},
8283 + {0x0000b1fc, 0x00000196},
8284 };
8285
8286 static const u32 ar9580_1p0_baseband_postamble[][5] = {
8287 @@ -956,7 +1169,7 @@ static const u32 ar9580_1p0_baseband_pos
8288 {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
8289 {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
8290 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
8291 - {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
8292 + {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
8293 {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
8294 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
8295 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
8296 --- a/drivers/net/wireless/ath/ath9k/reg.h
8297 +++ b/drivers/net/wireless/ath/ath9k/reg.h
8298 @@ -809,6 +809,8 @@
8299 #define AR_SREV_REVISION_9462_21 3
8300 #define AR_SREV_VERSION_9565 0x2C0
8301 #define AR_SREV_REVISION_9565_10 0
8302 +#define AR_SREV_REVISION_9565_101 1
8303 +#define AR_SREV_REVISION_9565_11 2
8304 #define AR_SREV_VERSION_9550 0x400
8305
8306 #define AR_SREV_5416(_ah) \
8307 @@ -927,10 +929,18 @@
8308
8309 #define AR_SREV_9565(_ah) \
8310 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))
8311 -
8312 #define AR_SREV_9565_10(_ah) \
8313 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
8314 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))
8315 +#define AR_SREV_9565_101(_ah) \
8316 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
8317 + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101))
8318 +#define AR_SREV_9565_11(_ah) \
8319 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
8320 + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11))
8321 +#define AR_SREV_9565_11_OR_LATER(_ah) \
8322 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
8323 + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11))
8324
8325 #define AR_SREV_9550(_ah) \
8326 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
lynxis staging tree for omap