1 From: Oleksij Rempel <linux@rempel-privat.de>
2 Date: Sun, 22 Mar 2015 19:29:54 +0100
3 Subject: [PATCH] ath9k: ath9k_hw_loadnf: use REG_RMW
5 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
6 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
9 --- a/drivers/net/wireless/ath/ath9k/calib.c
10 +++ b/drivers/net/wireless/ath/ath9k/calib.c
11 @@ -238,7 +238,6 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s
13 struct ath9k_nfcal_hist *h = NULL;
16 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
17 struct ath_common *common = ath9k_hw_common(ah);
18 s16 default_nf = ath9k_hw_get_default_nf(ah, chan);
19 @@ -246,6 +245,7 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s
21 h = ah->caldata->nfCalHist;
23 + ENABLE_REG_RMW_BUFFER(ah);
24 for (i = 0; i < NUM_NF_READINGS; i++) {
25 if (chainmask & (1 << i)) {
27 @@ -258,10 +258,8 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s
31 - val = REG_READ(ah, ah->nf_regs[i]);
33 - val |= (((u32) nfval << 1) & 0x1ff);
34 - REG_WRITE(ah, ah->nf_regs[i], val);
35 + REG_RMW(ah, ah->nf_regs[i],
36 + (((u32) nfval << 1) & 0x1ff), 0x1ff);
40 @@ -274,6 +272,7 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s
41 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
42 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
43 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
44 + REG_RMW_BUFFER_FLUSH(ah);
47 * Wait for load to complete, should be fast, a few 10s of us.
48 @@ -309,19 +308,17 @@ int ath9k_hw_loadnf(struct ath_hw *ah, s
49 * by the median we just loaded. This will be initial (and max) value
50 * of next noise floor calibration the baseband does.
52 - ENABLE_REGWRITE_BUFFER(ah);
53 + ENABLE_REG_RMW_BUFFER(ah);
54 for (i = 0; i < NUM_NF_READINGS; i++) {
55 if (chainmask & (1 << i)) {
56 if ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(chan))
59 - val = REG_READ(ah, ah->nf_regs[i]);
61 - val |= (((u32) (-50) << 1) & 0x1ff);
62 - REG_WRITE(ah, ah->nf_regs[i], val);
63 + REG_RMW(ah, ah->nf_regs[i],
64 + (((u32) (-50) << 1) & 0x1ff), 0x1ff);
67 - REGWRITE_BUFFER_FLUSH(ah);
68 + REG_RMW_BUFFER_FLUSH(ah);