1 From: Arend van Spriel <arend@broadcom.com>
2 Date: Wed, 11 Mar 2015 16:11:31 +0100
3 Subject: [PATCH] brcmfmac: extract ram size info from internal memory
6 Instead of hard-coded memory sizes it is possible to obtain that
7 information from the internal memory registers.
9 Reviewed-by: Hante Meuleman <meuleman@broadcom.com>
10 Reviewed-by: Franky (Zhenhui) Lin <frankyl@broadcom.com>
11 Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
12 Signed-off-by: Arend van Spriel <arend@broadcom.com>
13 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
16 --- a/drivers/net/wireless/brcm80211/brcmfmac/chip.c
17 +++ b/drivers/net/wireless/brcm80211/brcmfmac/chip.c
19 #define BCM4329_CORE_SOCRAM_BASE 0x18003000
20 /* ARM Cortex M3 core, ID 0x82a */
21 #define BCM4329_CORE_ARM_BASE 0x18002000
22 -#define BCM4329_RAMSIZE 0x48000
24 -#define BCM43143_RAMSIZE 0x70000
26 #define CORE_SB(base, field) \
27 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
28 @@ -150,6 +147,78 @@ struct sbconfig {
29 u32 sbidhigh; /* identification */
32 +/* bankidx and bankinfo reg defines corerev >= 8 */
33 +#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
34 +#define SOCRAM_BANKINFO_SZMASK 0x0000007f
35 +#define SOCRAM_BANKIDX_ROM_MASK 0x00000100
37 +#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
38 +/* socram bankinfo memtype */
39 +#define SOCRAM_MEMTYPE_RAM 0
40 +#define SOCRAM_MEMTYPE_R0M 1
41 +#define SOCRAM_MEMTYPE_DEVRAM 2
43 +#define SOCRAM_BANKINFO_SZBASE 8192
44 +#define SRCI_LSS_MASK 0x00f00000
45 +#define SRCI_LSS_SHIFT 20
46 +#define SRCI_SRNB_MASK 0xf0
47 +#define SRCI_SRNB_SHIFT 4
48 +#define SRCI_SRBSZ_MASK 0xf
49 +#define SRCI_SRBSZ_SHIFT 0
50 +#define SR_BSZ_BASE 14
52 +struct sbsocramregs {
60 + u32 errlogstatus; /* rev 6 */
61 + u32 errlogaddr; /* rev 6 */
62 + /* used for patching rev 3 & 5 */
64 + u32 cambankstandbyctrl;
65 + u32 cambankpatchctrl;
66 + u32 cambankpatchtblbaseaddr;
71 + u32 bankinfo; /* corev 8 */
75 + u32 extmemparitycsr;
76 + u32 extmemparityerrdata;
77 + u32 extmemparityerrcnt;
78 + u32 extmemwrctrlandsize;
81 + u32 pwrctl; /* corerev >= 2 */
83 + u32 sr_control; /* corerev >= 15 */
84 + u32 sr_status; /* corerev >= 15 */
85 + u32 sr_address; /* corerev >= 15 */
86 + u32 sr_data; /* corerev >= 15 */
89 +#define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
91 +#define ARMCR4_CAP (0x04)
92 +#define ARMCR4_BANKIDX (0x40)
93 +#define ARMCR4_BANKINFO (0x44)
94 +#define ARMCR4_BANKPDA (0x4C)
96 +#define ARMCR4_TCBBNB_MASK 0xf0
97 +#define ARMCR4_TCBBNB_SHIFT 4
98 +#define ARMCR4_TCBANB_MASK 0xf
99 +#define ARMCR4_TCBANB_SHIFT 0
101 +#define ARMCR4_BSZ_MASK 0x3f
102 +#define ARMCR4_BSZ_MULT 8192
104 struct brcmf_core_priv {
105 struct brcmf_core pub;
107 @@ -443,10 +512,6 @@ static int brcmf_chip_cores_check(struct
109 case BCMA_CORE_ARM_CR4:
111 - if (ci->pub.rambase == 0) {
112 - brcmf_err("RAM base not provided with ARM CR4 core\n");
118 @@ -462,60 +527,160 @@ static int brcmf_chip_cores_check(struct
119 brcmf_err("RAM core not provided with ARM CM3 core\n");
122 - if (!ci->pub.ramsize) {
123 - brcmf_err("RAM size is undetermined\n");
129 -static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
130 +static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
132 - switch (ci->pub.chip) {
133 - case BRCM_CC_4329_CHIP_ID:
134 - ci->pub.ramsize = BCM4329_RAMSIZE;
136 - case BRCM_CC_43143_CHIP_ID:
137 - ci->pub.ramsize = BCM43143_RAMSIZE;
139 - case BRCM_CC_43241_CHIP_ID:
140 - ci->pub.ramsize = 0x90000;
142 - case BRCM_CC_4330_CHIP_ID:
143 - ci->pub.ramsize = 0x48000;
145 + return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
148 +static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
151 + core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
154 +static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
158 + u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
161 + brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
162 + bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
163 + *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
164 + *banksize *= SOCRAM_BANKINFO_SZBASE;
165 + return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
168 +static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
172 + uint nb, banksize, lss;
179 + if (WARN_ON(sr->pub.rev < 4))
182 + if (!brcmf_chip_iscoreup(&sr->pub))
183 + brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
185 + /* Get info for determining size */
186 + coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
187 + nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
189 + if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
190 + banksize = (coreinfo & SRCI_SRBSZ_MASK);
191 + lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
194 + *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
196 + *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
198 + nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
199 + for (i = 0; i < nb; i++) {
200 + retent = brcmf_chip_socram_banksize(sr, i, &banksize);
201 + *ramsize += banksize;
203 + *srsize += banksize;
207 + /* hardcoded save&restore memory sizes */
208 + switch (sr->chip->pub.chip) {
209 case BRCM_CC_4334_CHIP_ID:
210 - case BRCM_CC_43340_CHIP_ID:
211 - ci->pub.ramsize = 0x80000;
212 + if (sr->chip->pub.chiprev < 2)
213 + *srsize = (32 * 1024);
215 - case BRCM_CC_4335_CHIP_ID:
216 - ci->pub.ramsize = 0xc0000;
217 - ci->pub.rambase = 0x180000;
219 - case BRCM_CC_43362_CHIP_ID:
220 - ci->pub.ramsize = 0x3c000;
226 +/** Return the TCM-RAM size of the ARMCR4 core. */
227 +static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
237 + corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
239 + nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
240 + nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
243 + for (idx = 0; idx < totb; idx++) {
244 + brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
245 + bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
246 + memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
252 +static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
254 + switch (ci->pub.chip) {
255 case BRCM_CC_4345_CHIP_ID:
256 - ci->pub.ramsize = 0xc8000;
257 - ci->pub.rambase = 0x198000;
260 + case BRCM_CC_4335_CHIP_ID:
261 case BRCM_CC_4339_CHIP_ID:
262 case BRCM_CC_4354_CHIP_ID:
263 case BRCM_CC_4356_CHIP_ID:
264 case BRCM_CC_43567_CHIP_ID:
265 case BRCM_CC_43569_CHIP_ID:
266 case BRCM_CC_43570_CHIP_ID:
267 - ci->pub.ramsize = 0xc0000;
268 - ci->pub.rambase = 0x180000;
270 case BRCM_CC_43602_CHIP_ID:
271 - ci->pub.ramsize = 0xf0000;
272 - ci->pub.rambase = 0x180000;
276 brcmf_err("unknown chip: %s\n", ci->pub.name);
282 +static int brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
284 + struct brcmf_core_priv *mem_core;
285 + struct brcmf_core *mem;
287 + mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
289 + mem_core = container_of(mem, struct brcmf_core_priv, pub);
290 + ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
291 + ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
292 + if (!ci->pub.rambase) {
293 + brcmf_err("RAM base not provided with ARM CR4 core\n");
297 + mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_INTERNAL_MEM);
298 + mem_core = container_of(mem, struct brcmf_core_priv, pub);
299 + brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
302 + brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
303 + ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
304 + ci->pub.srsize, ci->pub.srsize);
306 + if (!ci->pub.ramsize) {
307 + brcmf_err("RAM size is undetermined\n");
313 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
314 @@ -668,6 +833,7 @@ static int brcmf_chip_recognition(struct
315 struct brcmf_core *core;
321 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
322 @@ -720,9 +886,13 @@ static int brcmf_chip_recognition(struct
326 - brcmf_chip_get_raminfo(ci);
328 - return brcmf_chip_cores_check(ci);
329 + ret = brcmf_chip_cores_check(ci);
333 + /* assure chip is passive for core access */
334 + brcmf_chip_set_passive(&ci->pub);
335 + return brcmf_chip_get_raminfo(ci);
338 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
339 @@ -827,8 +997,6 @@ struct brcmf_chip *brcmf_chip_attach(voi
343 - /* assure chip is passive for download */
344 - brcmf_chip_set_passive(&chip->pub);
348 --- a/drivers/net/wireless/brcm80211/brcmfmac/chip.h
349 +++ b/drivers/net/wireless/brcm80211/brcmfmac/chip.h
351 * @pmucaps: PMU capabilities.
352 * @pmurev: PMU revision.
353 * @rambase: RAM base address (only applicable for ARM CR4 chips).
354 - * @ramsize: amount of RAM on chip.
355 + * @ramsize: amount of RAM on chip including retention.
356 + * @srsize: amount of retention RAM on chip.
357 * @name: string representation of the chip identifier.
360 @@ -41,6 +42,7 @@ struct brcmf_chip {