1 From 9a3c53da5228607375ab69d6e3cbc375f18a4f82 Mon Sep 17 00:00:00 2001
2 From: Jes Sorensen <Jes.Sorensen@redhat.com>
3 Date: Thu, 21 Jul 2016 17:25:56 -0400
4 Subject: [PATCH] rtl8xxxu: Add PHY IQ calibration code for 8188eu
6 The vendor driver for 8188eu is a bizarre modern style code for path A
7 and old-style code for path B. Most likely because the 8188eu is a
8 1T1R part which never gets to the path B code.
10 Eventually we should look into unifying all the IQ calibration code.
12 Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
14 .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 489 +++++++++++++++++++++
15 1 file changed, 489 insertions(+)
17 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
18 +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
19 @@ -384,6 +384,494 @@ static int rtl8188eu_init_phy_rf(struct
23 +static int rtl8188eu_iqk_path_a(struct rtl8xxxu_priv *priv)
25 + u32 reg_eac, reg_e94, reg_e9c;
28 + /* Path A IQK setting */
29 + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c);
30 + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c);
32 + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214032a);
33 + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000);
35 + /* LO calibration setting */
36 + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
38 + /* One shot, path A LOK & IQK */
39 + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
40 + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
45 + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
46 + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
47 + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
49 + if (!(reg_eac & BIT(28)) &&
50 + ((reg_e94 & 0x03ff0000) != 0x01420000) &&
51 + ((reg_e9c & 0x03ff0000) != 0x00420000))
57 +static int rtl8188eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
59 + u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
62 + /* Leave IQK mode */
63 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
65 + /* Enable path A PA in TX IQK mode */
66 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
67 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
68 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
69 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);
71 + /* PA/PAD control by 0x56, and set = 0x0 */
72 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
73 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
75 + /* Enter IQK mode */
76 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
78 + /* TX IQK setting */
79 + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
80 + rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800);
82 + /* path-A IQK setting */
83 + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c);
84 + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c);
86 + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
87 + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000);
89 + /* LO calibration setting */
90 + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
92 + /* One shot, path A LOK & IQK */
93 + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
94 + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
99 + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
100 + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
101 + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
103 + if (!(reg_eac & BIT(28)) &&
104 + ((reg_e94 & 0x03ff0000) != 0x01420000) &&
105 + ((reg_e9c & 0x03ff0000) != 0x00420000)) {
108 + /* PA/PAD controlled by 0x0 */
109 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
110 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
114 + val32 = 0x80007c00 |
115 + (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);
116 + rtl8xxxu_write32(priv, REG_TX_IQK, val32);
118 + /* Modify RX IQK mode table */
119 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
121 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
122 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
123 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
124 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);
126 + /* Enter IQK mode */
127 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
130 + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
132 + /* Path A IQK setting */
133 + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
134 + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
136 + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c05);
137 + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
139 + /* LO calibration setting */
140 + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
142 + /* One shot, path A LOK & IQK */
143 + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
144 + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
148 + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
149 + reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
151 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
152 + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
154 + if (!(reg_eac & BIT(27)) &&
155 + ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
156 + ((reg_eac & 0x03ff0000) != 0x00360000))
159 + dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
166 +static int rtl8188eu_iqk_path_b(struct rtl8xxxu_priv *priv)
168 + u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
171 + rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
172 + rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
177 + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
178 + reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
179 + reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
180 + reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
181 + reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
183 + if (!(reg_eac & BIT(31)) &&
184 + ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
185 + ((reg_ebc & 0x03ff0000) != 0x00420000))
188 + dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
191 + if (!(reg_eac & BIT(30)) &&
192 + ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
193 + ((reg_ecc & 0x03ff0000) != 0x00360000))
196 + dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
202 +static void rtl8188eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
203 + int result[][8], int t)
205 + struct device *dev = &priv->udev->dev;
207 + int path_a_ok, path_b_ok;
209 + const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
210 + REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
211 + REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
212 + REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
213 + REG_TX_OFDM_BBON, REG_TX_TO_RX,
214 + REG_TX_TO_TX, REG_RX_CCK,
215 + REG_RX_OFDM, REG_RX_WAIT_RIFS,
216 + REG_RX_TO_RX, REG_STANDBY,
217 + REG_SLEEP, REG_PMPD_ANAEN
219 + const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
220 + REG_TXPAUSE, REG_BEACON_CTRL,
221 + REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
223 + const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
224 + REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
225 + REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
226 + REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
227 + REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
231 + * Note: IQ calibration must be performed after loading
232 + * PHY_REG.txt , and radio_a, radio_b.txt
236 + /* Save ADDA parameters, turn Path A ADDA on */
237 + rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
238 + RTL8XXXU_ADDA_REGS);
239 + rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
240 + rtl8xxxu_save_regs(priv, iqk_bb_regs,
241 + priv->bb_backup, RTL8XXXU_BB_REGS);
244 + rtl8xxxu_path_adda_on(priv, adda_regs, true);
247 + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
248 + if (val32 & FPGA0_HSSI_PARM1_PI)
249 + priv->pi_enabled = 1;
252 + if (!priv->pi_enabled) {
253 + /* Switch BB to PI mode to do IQ Calibration. */
254 + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
255 + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
258 + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
259 + val32 &= ~FPGA_RF_MODE_CCK;
260 + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
262 + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
263 + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
264 + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
266 + if (!priv->no_pape) {
267 + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
268 + val32 |= (FPGA0_RF_PAPE |
269 + (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
270 + rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
273 + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
275 + rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
276 + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
278 + rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
280 + if (priv->tx_paths > 1) {
281 + rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
282 + rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
286 + rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
289 + rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
291 + if (priv->tx_paths > 1)
292 + rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
294 + /* IQ calibration setting */
295 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
296 + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
297 + rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800);
299 + for (i = 0; i < retry; i++) {
300 + path_a_ok = rtl8188eu_iqk_path_a(priv);
301 + if (path_a_ok == 0x01) {
302 + val32 = rtl8xxxu_read32(priv,
303 + REG_TX_POWER_BEFORE_IQK_A);
304 + result[t][0] = (val32 >> 16) & 0x3ff;
305 + val32 = rtl8xxxu_read32(priv,
306 + REG_TX_POWER_AFTER_IQK_A);
307 + result[t][1] = (val32 >> 16) & 0x3ff;
313 + dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
315 + for (i = 0; i < retry; i++) {
316 + path_a_ok = rtl8188eu_rx_iqk_path_a(priv);
317 + if (path_a_ok == 0x03) {
318 + val32 = rtl8xxxu_read32(priv,
319 + REG_RX_POWER_BEFORE_IQK_A_2);
320 + result[t][2] = (val32 >> 16) & 0x3ff;
321 + val32 = rtl8xxxu_read32(priv,
322 + REG_RX_POWER_AFTER_IQK_A_2);
323 + result[t][3] = (val32 >> 16) & 0x3ff;
330 + dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
333 + * Path B calibration code in the vendor driver seems to be
334 + * old style and not updated for the 8188eu since it's a 1T1R
335 + * part. Keeping the code here in sync with the vendor code
336 + * to not divert unncessarily, but probably would be good to
337 + * look into modernizing all the code including that for the
340 + if (priv->tx_paths > 1) {
342 + * Path A into standby
344 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
345 + rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
346 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
348 + /* Turn Path B ADDA on */
349 + rtl8xxxu_path_adda_on(priv, adda_regs, false);
351 + for (i = 0; i < retry; i++) {
352 + path_b_ok = rtl8188eu_iqk_path_b(priv);
353 + if (path_b_ok == 0x03) {
354 + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
355 + result[t][4] = (val32 >> 16) & 0x3ff;
356 + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
357 + result[t][5] = (val32 >> 16) & 0x3ff;
358 + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
359 + result[t][6] = (val32 >> 16) & 0x3ff;
360 + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
361 + result[t][7] = (val32 >> 16) & 0x3ff;
363 + } else if (i == (retry - 1) && path_b_ok == 0x01) {
365 + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
366 + result[t][4] = (val32 >> 16) & 0x3ff;
367 + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
368 + result[t][5] = (val32 >> 16) & 0x3ff;
373 + dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
376 + /* Back to BB mode, load original value */
377 + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
380 + if (!priv->pi_enabled) {
382 + * Switch back BB to SI mode after finishing
385 + val32 = 0x01000000;
386 + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
387 + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
390 + /* Reload ADDA power saving parameters */
391 + rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
392 + RTL8XXXU_ADDA_REGS);
394 + /* Reload MAC parameters */
395 + rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
397 + /* Reload BB parameters */
398 + rtl8xxxu_restore_regs(priv, iqk_bb_regs,
399 + priv->bb_backup, RTL8XXXU_BB_REGS);
401 + /* Restore RX initial gain */
402 + rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
404 + if (priv->tx_paths > 1) {
405 + rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
409 + /* Load 0xe30 IQC default value */
410 + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
411 + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
415 +static void rtl8188eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
417 + struct device *dev = &priv->udev->dev;
418 + int result[4][8]; /* last is final result */
420 + bool path_a_ok, path_b_ok;
421 + u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
422 + u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
425 + memset(result, 0, sizeof(result));
426 + result[3][0] = 0x100;
427 + result[3][2] = 0x100;
428 + result[3][4] = 0x100;
429 + result[3][6] = 0x100;
436 + for (i = 0; i < 3; i++) {
437 + rtl8188eu_phy_iqcalibrate(priv, result, i);
440 + simu = rtl8xxxu_gen2_simularity_compare(priv,
449 + simu = rtl8xxxu_gen2_simularity_compare(priv,
456 + simu = rtl8xxxu_gen2_simularity_compare(priv,
465 + for (i = 0; i < 4; i++) {
466 + reg_e94 = result[i][0];
467 + reg_e9c = result[i][1];
468 + reg_ea4 = result[i][2];
469 + reg_eb4 = result[i][4];
470 + reg_ebc = result[i][5];
471 + reg_ec4 = result[i][6];
474 + if (candidate >= 0) {
475 + reg_e94 = result[candidate][0];
476 + priv->rege94 = reg_e94;
477 + reg_e9c = result[candidate][1];
478 + priv->rege9c = reg_e9c;
479 + reg_ea4 = result[candidate][2];
480 + reg_eac = result[candidate][3];
481 + reg_eb4 = result[candidate][4];
482 + priv->regeb4 = reg_eb4;
483 + reg_ebc = result[candidate][5];
484 + priv->regebc = reg_ebc;
485 + reg_ec4 = result[candidate][6];
486 + reg_ecc = result[candidate][7];
487 + dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
489 + "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
490 + "ecc=%x\n ", __func__, reg_e94, reg_e9c,
491 + reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
495 + reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
496 + reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
499 + if (reg_e94 && candidate >= 0)
500 + rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
501 + candidate, (reg_ea4 == 0));
503 + if (priv->rf_paths > 1 && reg_eb4)
504 + rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
505 + candidate, (reg_ec4 == 0));
507 + rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
508 + priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
511 static void rtl8188e_disabled_to_emu(struct rtl8xxxu_priv *priv)
514 @@ -520,6 +1008,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops =
515 .llt_init = rtl8xxxu_auto_llt_table,
516 .init_phy_bb = rtl8188eu_init_phy_bb,
517 .init_phy_rf = rtl8188eu_init_phy_rf,
518 + .phy_iq_calibrate = rtl8188eu_phy_iq_calibrate,
519 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
520 .usb_quirks = rtl8188e_usb_quirks,
521 .writeN_block_size = 128,