1 From 1b92f72f2880049ea322f89680bf5ebea7a0cf05 Mon Sep 17 00:00:00 2001
2 From: Jes Sorensen <Jes.Sorensen@redhat.com>
3 Date: Fri, 22 Jul 2016 13:55:24 -0400
4 Subject: [PATCH] rtl8xxxu: Implement rtl8188e_set_tx_power()
6 This matches the code used to set TX power on 8192eu, except it only
9 We should be able to consolidate this code.
11 Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
13 .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 63 ++++++++++++++++++++++
14 1 file changed, 63 insertions(+)
16 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
17 +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
18 @@ -283,6 +283,68 @@ static struct rtl8xxxu_rfregval rtl8188e
22 +int rtl8xxxu_8188e_channel_to_group(int channel)
28 + else if (channel < 6)
30 + else if (channel < 9)
32 + else if (channel < 12)
34 + else if (channel < 14)
43 +rtl8188e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
45 + u32 val32, ofdm, mcs;
46 + u8 cck, ofdmbase, mcsbase;
50 + group = rtl8xxxu_8188e_channel_to_group(channel);
52 + cck = priv->cck_tx_power_index_A[group];
54 + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
55 + val32 &= 0xffff00ff;
56 + val32 |= (cck << 8);
57 + rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
59 + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
61 + val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
62 + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
64 + ofdmbase = priv->ht40_1s_tx_power_index_A[group];
65 + ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
66 + ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
68 + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
69 + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
71 + mcsbase = priv->ht40_1s_tx_power_index_A[group];
73 + mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
75 + mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
76 + mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
78 + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
79 + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
80 + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
81 + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
84 void rtl8188eu_config_channel(struct ieee80211_hw *hw)
86 struct rtl8xxxu_priv *priv = hw->priv;
87 @@ -1152,6 +1214,7 @@ struct rtl8xxxu_fileops rtl8188eu_fops =
88 .enable_rf = rtl8188e_enable_rf,
89 .disable_rf = rtl8188e_disable_rf,
90 .usb_quirks = rtl8188e_usb_quirks,
91 + .set_tx_power = rtl8188e_set_tx_power,
92 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
93 .report_connect = rtl8xxxu_gen2_report_connect,
94 .writeN_block_size = 128,