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[openwrt/openwrt.git] / package / kernel / mac80211 / patches / rt2x00 / 008-rt2x00-add-RXIQ-calibration-for-MT7620.patch
1 From patchwork Sat Sep 17 20:28:10 2022
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 8bit
5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
6 X-Patchwork-Id: 12979249
7 X-Patchwork-Delegate: kvalo@adurom.com
8 Return-Path: <linux-wireless-owner@kernel.org>
9 Date: Sat, 17 Sep 2022 21:28:10 +0100
10 From: Daniel Golle <daniel@makrotopia.org>
11 To: linux-wireless@vger.kernel.org, Stanislaw Gruszka <stf_xl@wp.pl>,
12 Helmut Schaa <helmut.schaa@googlemail.com>
13 Cc: Kalle Valo <kvalo@kernel.org>,
14 "David S. Miller" <davem@davemloft.net>,
15 Eric Dumazet <edumazet@google.com>,
16 Jakub Kicinski <kuba@kernel.org>,
17 Paolo Abeni <pabeni@redhat.com>,
18 Johannes Berg <johannes.berg@intel.com>
19 Subject: [PATCH v3 08/16] rt2x00: add RXIQ calibration for MT7620
20 Message-ID:
21 <033a39a697d51f6df258acea4c33608e0944fe4c.1663445157.git.daniel@makrotopia.org>
22 References: <cover.1663445157.git.daniel@makrotopia.org>
23 MIME-Version: 1.0
24 Content-Disposition: inline
25 In-Reply-To: <cover.1663445157.git.daniel@makrotopia.org>
26 Precedence: bulk
27 List-ID: <linux-wireless.vger.kernel.org>
28 X-Mailing-List: linux-wireless@vger.kernel.org
29
30 From: Tomislav Požega <pozega.tomislav@gmail.com>
31
32 Add RXIQ calibration found in mtk driver. With old openwrt builds this
33 gets us ~8Mbps more of RX bandwidth (test with iPA/eLNA layout).
34
35 Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
36 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
37 Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
38 ---
39 v2: use rt2800_wait_bbp_rf_ready(), fix indentation
40
41 .../net/wireless/ralink/rt2x00/rt2800lib.c | 375 ++++++++++++++++++
42 1 file changed, 375 insertions(+)
43
44 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
45 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
46 @@ -8666,6 +8666,380 @@ static void rt2800_rxdcoc_calibration(st
47 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
48 }
49
50 +static u32 rt2800_do_sqrt_accumulation(u32 si)
51 +{
52 + u32 root, root_pre, bit;
53 + char i;
54 +
55 + bit = 1 << 15;
56 + root = 0;
57 + for (i = 15; i >= 0; i = i - 1) {
58 + root_pre = root + bit;
59 + if ((root_pre * root_pre) <= si)
60 + root = root_pre;
61 + bit = bit >> 1;
62 + }
63 +
64 + return root;
65 +}
66 +
67 +static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
68 +{
69 + u8 rfb0r1, rfb0r2, rfb0r42;
70 + u8 rfb4r0, rfb4r19;
71 + u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;
72 + u8 rfb6r0, rfb6r19;
73 + u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;
74 +
75 + u8 bbp1, bbp4;
76 + u8 bbpr241, bbpr242;
77 + u32 i;
78 + u8 ch_idx;
79 + u8 bbpval;
80 + u8 rfval, vga_idx = 0;
81 + int mi = 0, mq = 0, si = 0, sq = 0, riq = 0;
82 + int sigma_i, sigma_q, r_iq, g_rx;
83 + int g_imb;
84 + int ph_rx;
85 + u32 savemacsysctrl = 0;
86 + u32 orig_RF_CONTROL0 = 0;
87 + u32 orig_RF_BYPASS0 = 0;
88 + u32 orig_RF_CONTROL1 = 0;
89 + u32 orig_RF_BYPASS1 = 0;
90 + u32 orig_RF_CONTROL3 = 0;
91 + u32 orig_RF_BYPASS3 = 0;
92 + u32 bbpval1 = 0;
93 + static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
94 +
95 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
96 + orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
97 + orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
98 + orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
99 + orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
100 + orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
101 + orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
102 +
103 + bbp1 = rt2800_bbp_read(rt2x00dev, 1);
104 + bbp4 = rt2800_bbp_read(rt2x00dev, 4);
105 +
106 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
107 +
108 + if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
109 + rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n");
110 +
111 + bbpval = bbp4 & (~0x18);
112 + bbpval = bbp4 | 0x00;
113 + rt2800_bbp_write(rt2x00dev, 4, bbpval);
114 +
115 + bbpval = rt2800_bbp_read(rt2x00dev, 21);
116 + bbpval = bbpval | 1;
117 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
118 + bbpval = bbpval & 0xfe;
119 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
120 +
121 + rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
122 + rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
123 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
124 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
125 + else
126 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
127 +
128 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
129 +
130 + rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
131 + rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
132 + rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
133 + rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
134 + rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
135 + rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
136 + rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
137 + rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
138 + rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
139 + rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
140 + rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
141 +
142 + rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
143 + rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
144 + rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
145 + rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
146 + rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
147 + rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
148 + rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
149 + rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
150 +
151 + rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
152 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
153 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
154 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
155 + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
156 + rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
157 + rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
158 + rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
159 +
160 + rt2800_bbp_write(rt2x00dev, 23, 0x0);
161 + rt2800_bbp_write(rt2x00dev, 24, 0x0);
162 +
163 + rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
164 +
165 + bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
166 + bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
167 +
168 + rt2800_bbp_write(rt2x00dev, 241, 0x10);
169 + rt2800_bbp_write(rt2x00dev, 242, 0x84);
170 + rt2800_bbp_write(rt2x00dev, 244, 0x31);
171 +
172 + bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
173 + bbpval = bbpval & (~0x7);
174 + rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
175 +
176 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
177 + udelay(1);
178 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
179 + usleep_range(1, 200);
180 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
181 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
182 + udelay(1);
183 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
184 + rt2800_bbp_write(rt2x00dev, 23, 0x06);
185 + rt2800_bbp_write(rt2x00dev, 24, 0x06);
186 + } else {
187 + rt2800_bbp_write(rt2x00dev, 23, 0x02);
188 + rt2800_bbp_write(rt2x00dev, 24, 0x02);
189 + }
190 +
191 + for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {
192 + if (ch_idx == 0) {
193 + rfval = rfb0r1 & (~0x3);
194 + rfval = rfb0r1 | 0x1;
195 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
196 + rfval = rfb0r2 & (~0x33);
197 + rfval = rfb0r2 | 0x11;
198 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
199 + rfval = rfb0r42 & (~0x50);
200 + rfval = rfb0r42 | 0x10;
201 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
202 +
203 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
204 + udelay(1);
205 +
206 + bbpval = bbp1 & (~0x18);
207 + bbpval = bbpval | 0x00;
208 + rt2800_bbp_write(rt2x00dev, 1, bbpval);
209 +
210 + rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
211 + } else {
212 + rfval = rfb0r1 & (~0x3);
213 + rfval = rfb0r1 | 0x2;
214 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
215 + rfval = rfb0r2 & (~0x33);
216 + rfval = rfb0r2 | 0x22;
217 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
218 + rfval = rfb0r42 & (~0x50);
219 + rfval = rfb0r42 | 0x40;
220 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
221 +
222 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
223 + udelay(1);
224 +
225 + bbpval = bbp1 & (~0x18);
226 + bbpval = bbpval | 0x08;
227 + rt2800_bbp_write(rt2x00dev, 1, bbpval);
228 +
229 + rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
230 + }
231 + usleep_range(500, 1500);
232 +
233 + vga_idx = 0;
234 + while (vga_idx < 11) {
235 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
236 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
237 +
238 + rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
239 +
240 + for (i = 0; i < 10000; i++) {
241 + bbpval = rt2800_bbp_read(rt2x00dev, 159);
242 + if ((bbpval & 0xff) == 0x93)
243 + usleep_range(50, 100);
244 + else
245 + break;
246 + }
247 +
248 + if ((bbpval & 0xff) == 0x93) {
249 + rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
250 + goto restore_value;
251 + }
252 + for (i = 0; i < 5; i++) {
253 + u32 bbptemp = 0;
254 + u8 value = 0;
255 + int result = 0;
256 +
257 + rt2800_bbp_write(rt2x00dev, 158, 0x1e);
258 + rt2800_bbp_write(rt2x00dev, 159, i);
259 + rt2800_bbp_write(rt2x00dev, 158, 0x22);
260 + value = rt2800_bbp_read(rt2x00dev, 159);
261 + bbptemp = bbptemp + (value << 24);
262 + rt2800_bbp_write(rt2x00dev, 158, 0x21);
263 + value = rt2800_bbp_read(rt2x00dev, 159);
264 + bbptemp = bbptemp + (value << 16);
265 + rt2800_bbp_write(rt2x00dev, 158, 0x20);
266 + value = rt2800_bbp_read(rt2x00dev, 159);
267 + bbptemp = bbptemp + (value << 8);
268 + rt2800_bbp_write(rt2x00dev, 158, 0x1f);
269 + value = rt2800_bbp_read(rt2x00dev, 159);
270 + bbptemp = bbptemp + value;
271 +
272 + if (i < 2 && (bbptemp & 0x800000))
273 + result = (bbptemp & 0xffffff) - 0x1000000;
274 + else if (i == 4)
275 + result = bbptemp;
276 + else
277 + result = bbptemp;
278 +
279 + if (i == 0)
280 + mi = result / 4096;
281 + else if (i == 1)
282 + mq = result / 4096;
283 + else if (i == 2)
284 + si = bbptemp / 4096;
285 + else if (i == 3)
286 + sq = bbptemp / 4096;
287 + else
288 + riq = result / 4096;
289 + }
290 +
291 + bbpval1 = si - mi * mi;
292 + rt2x00_dbg(rt2x00dev,
293 + "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d",
294 + si, sq, riq, bbpval1, vga_idx);
295 +
296 + if (bbpval1 >= (100 * 100))
297 + break;
298 +
299 + if (bbpval1 <= 100)
300 + vga_idx = vga_idx + 9;
301 + else if (bbpval1 <= 158)
302 + vga_idx = vga_idx + 8;
303 + else if (bbpval1 <= 251)
304 + vga_idx = vga_idx + 7;
305 + else if (bbpval1 <= 398)
306 + vga_idx = vga_idx + 6;
307 + else if (bbpval1 <= 630)
308 + vga_idx = vga_idx + 5;
309 + else if (bbpval1 <= 1000)
310 + vga_idx = vga_idx + 4;
311 + else if (bbpval1 <= 1584)
312 + vga_idx = vga_idx + 3;
313 + else if (bbpval1 <= 2511)
314 + vga_idx = vga_idx + 2;
315 + else
316 + vga_idx = vga_idx + 1;
317 + }
318 +
319 + sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi));
320 + sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq));
321 + r_iq = 10 * (riq - (mi * mq));
322 +
323 + rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
324 +
325 + if (sigma_i <= 1400 && sigma_i >= 1000 &&
326 + (sigma_i - sigma_q) <= 112 &&
327 + (sigma_i - sigma_q) >= -112 &&
328 + mi <= 32 && mi >= -32 &&
329 + mq <= 32 && mq >= -32) {
330 + r_iq = 10 * (riq - (mi * mq));
331 + rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
332 + sigma_i, sigma_q, r_iq);
333 +
334 + g_rx = (1000 * sigma_q) / sigma_i;
335 + g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
336 + ph_rx = (r_iq * 2292) / (sigma_i * sigma_q);
337 +
338 + if (ph_rx > 20 || ph_rx < -20) {
339 + ph_rx = 0;
340 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
341 + }
342 +
343 + if (g_imb > 12 || g_imb < -12) {
344 + g_imb = 0;
345 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
346 + }
347 + } else {
348 + g_imb = 0;
349 + ph_rx = 0;
350 + rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
351 + sigma_i, sigma_q, r_iq);
352 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
353 + }
354 +
355 + if (ch_idx == 0) {
356 + rt2800_bbp_write(rt2x00dev, 158, 0x37);
357 + rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
358 + rt2800_bbp_write(rt2x00dev, 158, 0x35);
359 + rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
360 + } else {
361 + rt2800_bbp_write(rt2x00dev, 158, 0x55);
362 + rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
363 + rt2800_bbp_write(rt2x00dev, 158, 0x53);
364 + rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
365 + }
366 + }
367 +
368 +restore_value:
369 + rt2800_bbp_write(rt2x00dev, 158, 0x3);
370 + bbpval = rt2800_bbp_read(rt2x00dev, 159);
371 + rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
372 +
373 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
374 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
375 + rt2800_bbp_write(rt2x00dev, 1, bbp1);
376 + rt2800_bbp_write(rt2x00dev, 4, bbp4);
377 + rt2800_bbp_write(rt2x00dev, 241, bbpr241);
378 + rt2800_bbp_write(rt2x00dev, 242, bbpr242);
379 +
380 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
381 + bbpval = rt2800_bbp_read(rt2x00dev, 21);
382 + bbpval |= 0x1;
383 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
384 + usleep_range(10, 200);
385 + bbpval &= 0xfe;
386 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
387 +
388 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
389 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
390 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
391 +
392 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
393 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
394 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
395 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
396 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
397 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
398 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
399 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
400 +
401 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
402 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
403 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
404 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
405 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
406 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
407 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
408 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
409 +
410 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
411 + udelay(1);
412 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
413 + udelay(1);
414 + rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
415 + udelay(1);
416 + rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
417 + rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
418 + rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
419 + rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
420 + rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
421 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
422 +}
423 +
424 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
425 bool set_bw, bool is_ht40)
426 {
427 @@ -9278,6 +9652,7 @@ static void rt2800_init_rfcsr_6352(struc
428 rt2800_rxdcoc_calibration(rt2x00dev);
429 rt2800_bw_filter_calibration(rt2x00dev, true);
430 rt2800_bw_filter_calibration(rt2x00dev, false);
431 + rt2800_rxiq_calibration(rt2x00dev);
432 }
433
434 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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