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[openwrt/staging/stintel.git] / package / kernel / mac80211 / patches / rt2x00 / 986-rt2x00-add-TX-LOFT-calibration.patch
1 From: =?UTF-8?q?Tomislav=20Po=C5=BEega?= <pozega.tomislav@gmail.com>
2 Date: Thu, 11 Jan 2018 19:53:49 +0100
3 Subject: [PATCH] rt2x00: add TX LOFT calibration
4 MIME-Version: 1.0
5 Content-Type: text/plain; charset=UTF-8
6 Content-Transfer-Encoding: 8bit
7
8 Add TX LOFT calibration from mtk driver.
9
10 Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
11 ---
12 .../net/wireless/ralink/rt2x00/rt2800lib.c | 938 ++++++++++++++++++
13 .../net/wireless/ralink/rt2x00/rt2800lib.h | 10 +
14 2 files changed, 948 insertions(+)
15
16 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
17 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
18 @@ -9079,6 +9079,943 @@ restore_value:
19 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
20 }
21
22 +static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_reg_record[][13], u8 chain)
23 +{
24 + u8 rfvalue = 0;
25 +
26 + if (chain == CHAIN_0) {
27 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
28 + rf_reg_record[CHAIN_0][0].bank = 0;
29 + rf_reg_record[CHAIN_0][0].reg = 1;
30 + rf_reg_record[CHAIN_0][0].value = rfvalue;
31 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
32 + rf_reg_record[CHAIN_0][1].bank = 0;
33 + rf_reg_record[CHAIN_0][1].reg = 2;
34 + rf_reg_record[CHAIN_0][1].value = rfvalue;
35 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
36 + rf_reg_record[CHAIN_0][2].bank = 0;
37 + rf_reg_record[CHAIN_0][2].reg = 35;
38 + rf_reg_record[CHAIN_0][2].value = rfvalue;
39 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
40 + rf_reg_record[CHAIN_0][3].bank = 0;
41 + rf_reg_record[CHAIN_0][3].reg = 42;
42 + rf_reg_record[CHAIN_0][3].value = rfvalue;
43 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
44 + rf_reg_record[CHAIN_0][4].bank = 4;
45 + rf_reg_record[CHAIN_0][4].reg = 0;
46 + rf_reg_record[CHAIN_0][4].value = rfvalue;
47 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
48 + rf_reg_record[CHAIN_0][5].bank = 4;
49 + rf_reg_record[CHAIN_0][5].reg = 2;
50 + rf_reg_record[CHAIN_0][5].value = rfvalue;
51 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
52 + rf_reg_record[CHAIN_0][6].bank = 4;
53 + rf_reg_record[CHAIN_0][6].reg = 34;
54 + rf_reg_record[CHAIN_0][6].value = rfvalue;
55 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
56 + rf_reg_record[CHAIN_0][7].bank = 5;
57 + rf_reg_record[CHAIN_0][7].reg = 3;
58 + rf_reg_record[CHAIN_0][7].value = rfvalue;
59 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
60 + rf_reg_record[CHAIN_0][8].bank = 5;
61 + rf_reg_record[CHAIN_0][8].reg = 4;
62 + rf_reg_record[CHAIN_0][8].value = rfvalue;
63 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
64 + rf_reg_record[CHAIN_0][9].bank = 5;
65 + rf_reg_record[CHAIN_0][9].reg = 17;
66 + rf_reg_record[CHAIN_0][9].value = rfvalue;
67 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
68 + rf_reg_record[CHAIN_0][10].bank = 5;
69 + rf_reg_record[CHAIN_0][10].reg = 18;
70 + rf_reg_record[CHAIN_0][10].value = rfvalue;
71 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
72 + rf_reg_record[CHAIN_0][11].bank = 5;
73 + rf_reg_record[CHAIN_0][11].reg = 19;
74 + rf_reg_record[CHAIN_0][11].value = rfvalue;
75 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
76 + rf_reg_record[CHAIN_0][12].bank = 5;
77 + rf_reg_record[CHAIN_0][12].reg = 20;
78 + rf_reg_record[CHAIN_0][12].value = rfvalue;
79 + } else if (chain == CHAIN_1) {
80 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
81 + rf_reg_record[CHAIN_1][0].bank = 0;
82 + rf_reg_record[CHAIN_1][0].reg = 1;
83 + rf_reg_record[CHAIN_1][0].value = rfvalue;
84 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
85 + rf_reg_record[CHAIN_1][1].bank = 0;
86 + rf_reg_record[CHAIN_1][1].reg = 2;
87 + rf_reg_record[CHAIN_1][1].value = rfvalue;
88 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
89 + rf_reg_record[CHAIN_1][2].bank = 0;
90 + rf_reg_record[CHAIN_1][2].reg = 35;
91 + rf_reg_record[CHAIN_1][2].value = rfvalue;
92 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
93 + rf_reg_record[CHAIN_1][3].bank = 0;
94 + rf_reg_record[CHAIN_1][3].reg = 42;
95 + rf_reg_record[CHAIN_1][3].value = rfvalue;
96 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
97 + rf_reg_record[CHAIN_1][4].bank = 6;
98 + rf_reg_record[CHAIN_1][4].reg = 0;
99 + rf_reg_record[CHAIN_1][4].value = rfvalue;
100 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
101 + rf_reg_record[CHAIN_1][5].bank = 6;
102 + rf_reg_record[CHAIN_1][5].reg = 2;
103 + rf_reg_record[CHAIN_1][5].value = rfvalue;
104 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
105 + rf_reg_record[CHAIN_1][6].bank = 6;
106 + rf_reg_record[CHAIN_1][6].reg = 34;
107 + rf_reg_record[CHAIN_1][6].value = rfvalue;
108 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
109 + rf_reg_record[CHAIN_1][7].bank = 7;
110 + rf_reg_record[CHAIN_1][7].reg = 3;
111 + rf_reg_record[CHAIN_1][7].value = rfvalue;
112 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
113 + rf_reg_record[CHAIN_1][8].bank = 7;
114 + rf_reg_record[CHAIN_1][8].reg = 4;
115 + rf_reg_record[CHAIN_1][8].value = rfvalue;
116 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
117 + rf_reg_record[CHAIN_1][9].bank = 7;
118 + rf_reg_record[CHAIN_1][9].reg = 17;
119 + rf_reg_record[CHAIN_1][9].value = rfvalue;
120 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
121 + rf_reg_record[CHAIN_1][10].bank = 7;
122 + rf_reg_record[CHAIN_1][10].reg = 18;
123 + rf_reg_record[CHAIN_1][10].value = rfvalue;
124 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
125 + rf_reg_record[CHAIN_1][11].bank = 7;
126 + rf_reg_record[CHAIN_1][11].reg = 19;
127 + rf_reg_record[CHAIN_1][11].value = rfvalue;
128 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
129 + rf_reg_record[CHAIN_1][12].bank = 7;
130 + rf_reg_record[CHAIN_1][12].reg = 20;
131 + rf_reg_record[CHAIN_1][12].value = rfvalue;
132 + } else {
133 + rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
134 + return;
135 + }
136 +
137 + return;
138 +}
139 +
140 +static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_record[][13])
141 +{
142 + u8 chain_index = 0, record_index = 0;
143 + u8 bank = 0, rf_register = 0, value = 0;
144 +
145 + for (chain_index = 0; chain_index < 2; chain_index++) {
146 + for (record_index = 0; record_index < 13; record_index++) {
147 + bank = rf_record[chain_index][record_index].bank;
148 + rf_register = rf_record[chain_index][record_index].reg;
149 + value = rf_record[chain_index][record_index].value;
150 + rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
151 + rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", bank, rf_register, value);
152 + }
153 + }
154 +
155 + return;
156 +}
157 +
158 +static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
159 +{
160 + rt2800_bbp_write(rt2x00dev, 158, 0xAA);
161 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
162 +
163 + rt2800_bbp_write(rt2x00dev, 158, 0xAB);
164 + rt2800_bbp_write(rt2x00dev, 159, 0x0A);
165 +
166 + rt2800_bbp_write(rt2x00dev, 158, 0xAC);
167 + rt2800_bbp_write(rt2x00dev, 159, 0x3F);
168 +
169 + rt2800_bbp_write(rt2x00dev, 158, 0xAD);
170 + rt2800_bbp_write(rt2x00dev, 159, 0x3F);
171 +
172 + rt2800_bbp_write(rt2x00dev, 244, 0x40);
173 +
174 + return;
175 +}
176 +
177 +static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
178 +{
179 + u32 macvalue = 0;
180 + int fftout_i = 0, fftout_q = 0;
181 + u32 ptmp=0, pint = 0;
182 + u8 bbp = 0;
183 + u8 tidxi;
184 +
185 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
186 + rt2800_bbp_write(rt2x00dev, 159, 0x9b);
187 +
188 + bbp = 0x9b;
189 +
190 + while (bbp == 0x9b) {
191 + udelay(10);
192 + bbp = rt2800_bbp_read(rt2x00dev, 159);
193 + bbp = bbp & 0xff;
194 + }
195 +
196 + rt2800_bbp_write(rt2x00dev, 158, 0xba);
197 + rt2800_bbp_write(rt2x00dev, 159, tidx);
198 + rt2800_bbp_write(rt2x00dev, 159, tidx);
199 + rt2800_bbp_write(rt2x00dev, 159, tidx);
200 +
201 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
202 +
203 + fftout_i = (macvalue >> 16);
204 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
205 + fftout_q = (macvalue & 0xffff);
206 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
207 + ptmp = (fftout_i * fftout_i);
208 + ptmp = ptmp + (fftout_q * fftout_q);
209 + pint = ptmp;
210 + rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
211 + if (read_neg) {
212 + pint = pint >> 1;
213 + tidxi = 0x40 - tidx;
214 + tidxi = tidxi & 0x3f;
215 +
216 + rt2800_bbp_write(rt2x00dev, 158, 0xba);
217 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
218 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
219 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
220 +
221 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
222 +
223 + fftout_i = (macvalue >> 16);
224 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
225 + fftout_q = (macvalue & 0xffff);
226 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
227 + ptmp = (fftout_i * fftout_i);
228 + ptmp = ptmp + (fftout_q * fftout_q);
229 + ptmp = ptmp >> 1;
230 + pint = pint + ptmp;
231 + }
232 +
233 + return pint;
234 +}
235 +
236 +static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) {
237 + u32 macvalue = 0;
238 + int fftout_i = 0, fftout_q = 0;
239 + u32 ptmp=0, pint = 0;
240 +
241 + rt2800_bbp_write(rt2x00dev, 158, 0xBA);
242 + rt2800_bbp_write(rt2x00dev, 159, tidx);
243 + rt2800_bbp_write(rt2x00dev, 159, tidx);
244 + rt2800_bbp_write(rt2x00dev, 159, tidx);
245 +
246 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
247 +
248 + fftout_i = (macvalue >> 16);
249 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
250 + fftout_q = (macvalue & 0xffff);
251 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
252 + ptmp = (fftout_i * fftout_i);
253 + ptmp = ptmp + (fftout_q * fftout_q);
254 + pint = ptmp;
255 + rt2x00_info(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
256 +
257 + return pint;
258 +}
259 +
260 +static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
261 +{
262 + u8 bbp = 0;
263 +
264 + rt2800_bbp_write(rt2x00dev, 158, 0xb0);
265 + bbp = alc | 0x80;
266 + rt2800_bbp_write(rt2x00dev, 159, bbp);
267 +
268 + if (ch_idx == 0)
269 + bbp = (iorq == 0) ? 0xb1: 0xb2;
270 + else
271 + bbp = (iorq == 0) ? 0xb8: 0xb9;
272 +
273 + rt2800_bbp_write(rt2x00dev, 158, bbp);
274 + bbp = dc;
275 + rt2800_bbp_write(rt2x00dev, 159, bbp);
276 +
277 + return;
278 +}
279 +
280 +static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
281 +{
282 + u32 p0 = 0, p1 = 0, pf = 0;
283 + char idx0 = 0, idx1 = 0;
284 + u8 idxf[] = {0x00, 0x00};
285 + u8 ibit = 0x20;
286 + u8 iorq;
287 + char bidx;
288 +
289 + rt2800_bbp_write(rt2x00dev, 158, 0xb0);
290 + rt2800_bbp_write(rt2x00dev, 159, 0x80);
291 +
292 + for (bidx = 5; bidx >= 0; bidx--) {
293 + for (iorq = 0; iorq <= 1; iorq++) {
294 + rt2x00_dbg(rt2x00dev, "\n========================================================\n");
295 +
296 + if (idxf[iorq] == 0x20) {
297 + idx0 = 0x20;
298 + p0 = pf;
299 + } else {
300 + idx0 = idxf[iorq] - ibit;
301 + idx0 = idx0 & 0x3F;
302 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
303 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
304 + }
305 +
306 + idx1 = idxf[iorq] + ((bidx == 5) ? 0 : ibit);
307 + idx1 = idx1 & 0x3F;
308 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
309 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
310 +
311 + rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", alc_idx, iorq, idxf[iorq]);
312 + rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x !\n", p0, p1, pf, idx0, idx1, ibit);
313 +
314 + if ((bidx != 5) && (pf <= p0) && (pf < p1)) {
315 + pf = pf;
316 + idxf[iorq] = idxf[iorq];
317 + } else if (p0 < p1) {
318 + pf = p0;
319 + idxf[iorq] = idx0 & 0x3F;
320 + } else {
321 + pf = p1;
322 + idxf[iorq] = idx1 & 0x3F;
323 + }
324 + rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n", iorq, iorq, idxf[iorq], pf);
325 +
326 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
327 +
328 + }
329 + ibit = ibit >> 1;
330 + }
331 + dc_result[ch_idx][alc_idx][0] = idxf[0];
332 + dc_result[ch_idx][alc_idx][1] = idxf[1];
333 +
334 + return;
335 +}
336 +
337 +static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
338 +{
339 + u32 p0 = 0, p1 = 0, pf = 0;
340 + char perr = 0, gerr = 0, iq_err = 0;
341 + char pef = 0, gef = 0;
342 + char psta, pend;
343 + char gsta, gend;
344 +
345 + u8 ibit = 0x20;
346 + u8 first_search = 0x00, touch_neg_max = 0x00;
347 + char idx0 = 0, idx1 = 0;
348 + u8 gop;
349 + u8 bbp = 0;
350 + char bidx;
351 +
352 + rt2x00_info(rt2x00dev, "IQCalibration Start!\n");
353 + for (bidx = 5; bidx >= 1; bidx--) {
354 + for (gop = 0; gop < 2; gop++) {
355 + rt2x00_dbg(rt2x00dev, "\n========================================================\n");
356 +
357 + if ((gop == 1) || (bidx < 4)) {
358 + if (gop == 0)
359 + iq_err = gerr;
360 + else
361 + iq_err = perr;
362 +
363 + first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
364 + touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : ((iq_err & 0x3F) == 0x20);
365 +
366 + if (touch_neg_max) {
367 + p0 = pf;
368 + idx0 = iq_err;
369 + } else {
370 + idx0 = iq_err - ibit;
371 + bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29): ((gop == 0) ? 0x46 : 0x47);
372 +
373 + rt2800_bbp_write(rt2x00dev, 158, bbp);
374 + rt2800_bbp_write(rt2x00dev, 159, idx0);
375 +
376 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
377 + }
378 +
379 + idx1 = iq_err + (first_search ? 0 : ibit);
380 + idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
381 +
382 + bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
383 +
384 + rt2800_bbp_write(rt2x00dev, 158, bbp);
385 + rt2800_bbp_write(rt2x00dev, 159, idx1);
386 +
387 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
388 +
389 + rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x !\n", p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
390 +
391 + if ((!first_search) && (pf <= p0) && (pf < p1)) {
392 + pf = pf;
393 + } else if (p0 < p1) {
394 + pf = p0;
395 + iq_err = idx0;
396 + } else {
397 + pf = p1;
398 + iq_err = idx1;
399 + }
400 +
401 + bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
402 +
403 + rt2800_bbp_write(rt2x00dev, 158, bbp);
404 + rt2800_bbp_write(rt2x00dev, 159, iq_err);
405 +
406 + if (gop == 0)
407 + gerr = iq_err;
408 + else
409 + perr = iq_err;
410 +
411 + rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", pf, gerr & 0x0F, perr & 0x3F);
412 +
413 + }
414 + }
415 +
416 + if (bidx > 0)
417 + ibit = (ibit >> 1);
418 + }
419 + gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
420 + perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
421 +
422 + gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
423 + gsta = gerr - 1;
424 + gend = gerr + 2;
425 +
426 + perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
427 + psta = perr - 1;
428 + pend = perr + 2;
429 +
430 + for (gef = gsta; gef <= gend; gef = gef + 1)
431 + for (pef = psta; pef <= pend; pef = pef + 1) {
432 + bbp = (ch_idx == 0) ? 0x28 : 0x46;
433 + rt2800_bbp_write(rt2x00dev, 158, bbp);
434 + rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
435 +
436 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
437 + rt2800_bbp_write(rt2x00dev, 158, bbp);
438 + rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
439 +
440 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
441 + if ((gef == gsta) && (pef == psta)) {
442 + pf = p1;
443 + gerr = gef;
444 + perr = pef;
445 + }
446 + else if (pf > p1){
447 + pf = p1;
448 + gerr = gef;
449 + perr = pef;
450 + }
451 + rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", p1, pf, gef & 0x0F, pef & 0x3F);
452 + }
453 +
454 + ges[ch_idx] = gerr & 0x0F;
455 + pes[ch_idx] = perr & 0x3F;
456 +
457 + rt2x00_info(rt2x00dev, "IQCalibration Done! CH = %u, (gain=%2x, phase=%2x)\n", ch_idx, gerr & 0x0F, perr & 0x3F);
458 +
459 + return;
460 +}
461 +
462 +static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
463 +{
464 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
465 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
466 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
467 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
468 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
469 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
470 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
471 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
472 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
473 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
474 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
475 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
476 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
477 +}
478 +
479 +static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
480 +{
481 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
482 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
483 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
484 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
485 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
486 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
487 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
488 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
489 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
490 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
491 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
492 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
493 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
494 +}
495 +
496 +void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
497 +{
498 + rf_reg_pair rf_store[CHAIN_NUM][13];
499 + u32 macorg1 = 0;
500 + u32 macorg2 = 0;
501 + u32 macorg3 = 0;
502 + u32 macorg4 = 0;
503 + u32 macorg5 = 0;
504 + u32 orig528 = 0;
505 + u32 orig52c = 0;
506 +
507 + u32 savemacsysctrl = 0, mtxcycle = 0;
508 + u32 macvalue = 0;
509 + u32 mac13b8 = 0;
510 + u32 p0 = 0, p1 = 0;
511 + u32 p0_idx10 = 0, p1_idx10 = 0;
512 +
513 + u8 rfvalue;
514 + u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
515 + u8 ger[CHAIN_NUM], per[CHAIN_NUM];
516 + u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
517 + u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
518 +
519 + u8 vga_gain[] = {14, 14};
520 + u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
521 + u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
522 + u8 bbpr30, rfb0r39, rfb0r42;
523 + u8 bbpr1;
524 + u8 bbpr4;
525 + u8 bbpr241, bbpr242;
526 + u8 count_step;
527 +
528 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
529 + macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
530 + macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
531 + macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
532 + macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
533 + macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
534 + mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
535 + orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
536 + orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
537 +
538 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
539 + macvalue &= (~0x04);
540 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
541 +
542 + for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
543 + macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
544 + if (macvalue & 0x01)
545 + udelay(50);
546 + else
547 + break;
548 + }
549 +
550 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
551 + macvalue &= (~0x08);
552 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
553 +
554 + for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
555 + macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
556 + if (macvalue & 0x02)
557 + udelay(50);
558 + else
559 + break;
560 + }
561 +
562 + for (ch_idx = 0; ch_idx < 2; ch_idx++) {
563 + rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
564 + }
565 +
566 + bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
567 + rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
568 + rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
569 +
570 + rt2800_bbp_write(rt2x00dev, 30, 0x1F);
571 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
572 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
573 +
574 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
575 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
576 +
577 + rt2800_setbbptonegenerator(rt2x00dev);
578 +
579 + for (ch_idx = 0; ch_idx < 2; ch_idx ++) {
580 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
581 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
582 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
583 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
584 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
585 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
586 + rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
587 + udelay(1);
588 +
589 + if (ch_idx == 0) {
590 + rt2800_rf_aux_tx0_loopback(rt2x00dev);
591 + } else {
592 + rt2800_rf_aux_tx1_loopback(rt2x00dev);
593 + }
594 + udelay(1);
595 +
596 + if (ch_idx == 0) {
597 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
598 + } else {
599 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
600 + }
601 +
602 + rt2800_bbp_write(rt2x00dev, 158, 0x05);
603 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
604 +
605 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
606 + if (ch_idx == 0)
607 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
608 + else
609 + rt2800_bbp_write(rt2x00dev, 159, 0x01);
610 +
611 + vga_gain[ch_idx] = 18;
612 + for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
613 + rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
614 + rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
615 +
616 + macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
617 + macvalue &= (~0x0000F1F1);
618 + macvalue |= (rf_gain[rf_alc_idx] << 4);
619 + macvalue |= (rf_gain[rf_alc_idx] << 12);
620 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
621 + macvalue = (0x0000F1F1);
622 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
623 +
624 + if (rf_alc_idx == 0) {
625 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
626 + for (;vga_gain[ch_idx] > 0;vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
627 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
628 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
629 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
630 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
631 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
632 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
633 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
634 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
635 + rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
636 + if ((p0 < 7000*7000) && (p1 < (7000*7000))) {
637 + break;
638 + }
639 + }
640 +
641 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
642 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
643 +
644 + rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
645 +
646 + if (vga_gain[ch_idx] < 0)
647 + vga_gain[ch_idx] = 0;
648 + }
649 +
650 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
651 +
652 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
653 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
654 +
655 + rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
656 + }
657 + }
658 +
659 + for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
660 + for (idx = 0; idx < 4; idx++) {
661 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
662 + bbp = (idx<<2) + rf_alc_idx;
663 + rt2800_bbp_write(rt2x00dev, 159, bbp);
664 + rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
665 +
666 + rt2800_bbp_write(rt2x00dev, 158, 0xb1);
667 + bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
668 + bbp = bbp & 0x3F;
669 + rt2800_bbp_write(rt2x00dev, 159, bbp);
670 + rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
671 +
672 + rt2800_bbp_write(rt2x00dev, 158, 0xb2);
673 + bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
674 + bbp = bbp & 0x3F;
675 + rt2800_bbp_write(rt2x00dev, 159, bbp);
676 + rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
677 +
678 + rt2800_bbp_write(rt2x00dev, 158, 0xb8);
679 + bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
680 + bbp = bbp & 0x3F;
681 + rt2800_bbp_write(rt2x00dev, 159, bbp);
682 + rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
683 +
684 + rt2800_bbp_write(rt2x00dev, 158, 0xb9);
685 + bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
686 + bbp = bbp & 0x3F;
687 + rt2800_bbp_write(rt2x00dev, 159, bbp);
688 + rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
689 + }
690 + }
691 +
692 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
693 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
694 +
695 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
696 +
697 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
698 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
699 +
700 + bbp = 0x00;
701 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
702 +
703 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
704 + udelay(1);
705 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
706 +
707 + rt2800_rf_configrecover(rt2x00dev, rf_store);
708 +
709 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
710 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
711 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
712 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
713 + rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
714 + udelay(1);
715 + rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
716 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
717 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
718 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
719 + rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
720 + rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
721 + rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
722 +
723 + rt2x00_info(rt2x00dev, "LOFT Calibration Done!\n");
724 +
725 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
726 + macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
727 + macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
728 + macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
729 + macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
730 + macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
731 +
732 + bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
733 + bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
734 + bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
735 + bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
736 + mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
737 +
738 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
739 + macvalue &= (~0x04);
740 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
741 + for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
742 + macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
743 + if (macvalue & 0x01)
744 + udelay(50);
745 + else
746 + break;
747 + }
748 +
749 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
750 + macvalue &= (~0x08);
751 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
752 + for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
753 + macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
754 + if (macvalue & 0x02)
755 + udelay(50);
756 + else
757 + break;
758 + }
759 +
760 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
761 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
762 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
763 + }
764 +
765 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
766 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
767 +
768 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
769 + rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
770 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
771 + udelay(1);
772 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
773 +
774 + rt2800_bbp_write(rt2x00dev, 241, 0x14);
775 + rt2800_bbp_write(rt2x00dev, 242, 0x80);
776 + rt2800_bbp_write(rt2x00dev, 244, 0x31);
777 + } else {
778 + rt2800_setbbptonegenerator(rt2x00dev);
779 + }
780 +
781 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
782 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
783 + udelay(1);
784 +
785 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
786 +
787 + if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
788 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
789 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
790 + }
791 +
792 + rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
793 +
794 + for (ch_idx = 0; ch_idx < 2; ch_idx++) {
795 + rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
796 + }
797 +
798 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
799 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
800 +
801 + rt2800_bbp_write(rt2x00dev, 158, 0x03);
802 + rt2800_bbp_write(rt2x00dev, 159, 0x60);
803 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
804 + rt2800_bbp_write(rt2x00dev, 159, 0x80);
805 +
806 + for (ch_idx = 0; ch_idx < 2; ch_idx ++) {
807 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
808 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
809 +
810 + if (ch_idx == 0) {
811 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
812 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
813 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
814 + bbp = bbpr1 & (~0x18);
815 + bbp = bbp | 0x00;
816 + rt2800_bbp_write(rt2x00dev, 1, bbp);
817 + }
818 + rt2800_rf_aux_tx0_loopback(rt2x00dev);
819 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
820 + } else {
821 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
822 + rt2800_bbp_write(rt2x00dev, 159, 0x01);
823 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
824 + bbp = bbpr1 & (~0x18);
825 + bbp = bbp | 0x08;
826 + rt2800_bbp_write(rt2x00dev, 1, bbp);
827 + }
828 + rt2800_rf_aux_tx1_loopback(rt2x00dev);
829 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
830 + }
831 +
832 + rt2800_bbp_write(rt2x00dev, 158, 0x05);
833 + rt2800_bbp_write(rt2x00dev, 159, 0x04);
834 +
835 + bbp = (ch_idx == 0) ? 0x28 : 0x46;
836 + rt2800_bbp_write(rt2x00dev, 158, bbp);
837 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
838 +
839 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
840 + rt2800_bbp_write(rt2x00dev, 23, 0x06);
841 + rt2800_bbp_write(rt2x00dev, 24, 0x06);
842 + count_step = 1;
843 + } else {
844 + rt2800_bbp_write(rt2x00dev, 23, 0x1F);
845 + rt2800_bbp_write(rt2x00dev, 24, 0x1F);
846 + count_step = 2;
847 + }
848 +
849 + for (;vga_gain[ch_idx] < 19; vga_gain[ch_idx]=(vga_gain[ch_idx] + count_step)) {
850 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
851 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
852 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
853 +
854 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
855 + rt2800_bbp_write(rt2x00dev, 158, bbp);
856 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
857 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
858 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
859 + p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
860 + }
861 +
862 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
863 + rt2800_bbp_write(rt2x00dev, 158, bbp);
864 + rt2800_bbp_write(rt2x00dev, 159, 0x21);
865 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
866 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
867 + p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
868 + }
869 +
870 + rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
871 +
872 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
873 + rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
874 + if ((p0_idx10 > 7000*7000) || (p1_idx10 > 7000*7000)) {
875 + if (vga_gain[ch_idx]!=0)
876 + vga_gain[ch_idx] = vga_gain[ch_idx]-1;
877 + break;
878 + }
879 + }
880 +
881 + if ((p0 > 2500*2500) || (p1 > 2500*2500)) {
882 + break;
883 + }
884 + }
885 +
886 + if (vga_gain[ch_idx] > 18)
887 + vga_gain[ch_idx] = 18;
888 + rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
889 +
890 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
891 + rt2800_bbp_write(rt2x00dev, 158, bbp);
892 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
893 +
894 + rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
895 + }
896 +
897 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
898 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
899 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
900 +
901 + rt2800_bbp_write(rt2x00dev, 158, 0x28);
902 + bbp = ger[CHAIN_0] & 0x0F;
903 + rt2800_bbp_write(rt2x00dev, 159, bbp);
904 +
905 + rt2800_bbp_write(rt2x00dev, 158, 0x29);
906 + bbp = per[CHAIN_0] & 0x3F;
907 + rt2800_bbp_write(rt2x00dev, 159, bbp);
908 +
909 + rt2800_bbp_write(rt2x00dev, 158, 0x46);
910 + bbp = ger[CHAIN_1] & 0x0F;
911 + rt2800_bbp_write(rt2x00dev, 159, bbp);
912 +
913 + rt2800_bbp_write(rt2x00dev, 158, 0x47);
914 + bbp = per[CHAIN_1] & 0x3F;
915 + rt2800_bbp_write(rt2x00dev, 159, bbp);
916 +
917 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
918 + rt2800_bbp_write(rt2x00dev, 1, bbpr1);
919 + rt2800_bbp_write(rt2x00dev, 241, bbpr241);
920 + rt2800_bbp_write(rt2x00dev, 242, bbpr242);
921 + }
922 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
923 +
924 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
925 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
926 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
927 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
928 +
929 + rt2800_bbp_write(rt2x00dev, 30, bbpr30);
930 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
931 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
932 +
933 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
934 + rt2800_bbp_write(rt2x00dev, 4, bbpr4);
935 + }
936 +
937 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
938 + udelay(1);
939 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
940 +
941 + rt2800_rf_configrecover(rt2x00dev, rf_store);
942 +
943 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
944 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
945 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
946 + rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
947 + udelay(1);
948 + rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
949 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
950 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
951 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
952 + rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
953 +
954 + rt2x00_info(rt2x00dev, "TX IQ Calibration Done!\n");
955 +
956 + return;
957 +}
958 +
959 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
960 bool set_bw, bool is_ht40)
961 {
962 @@ -9691,6 +10628,7 @@ static void rt2800_init_rfcsr_6352(struc
963 rt2800_rxdcoc_calibration(rt2x00dev);
964 rt2800_bw_filter_calibration(rt2x00dev, true);
965 rt2800_bw_filter_calibration(rt2x00dev, false);
966 + rt2800_loft_iq_calibration(rt2x00dev);
967 rt2800_rxiq_calibration(rt2x00dev);
968 }
969
970 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
971 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
972 @@ -17,6 +17,16 @@
973 #define WCID_START 33
974 #define WCID_END 222
975 #define STA_IDS_SIZE (WCID_END - WCID_START + 2)
976 +#define CHAIN_0 0x0
977 +#define CHAIN_1 0x1
978 +#define RF_ALC_NUM 6
979 +#define CHAIN_NUM 2
980 +
981 +typedef struct rf_reg_pair {
982 + u8 bank;
983 + u8 reg;
984 + u8 value;
985 +} rf_reg_pair;
986
987 /* RT2800 driver data structure */
988 struct rt2800_drv_data {
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