package/kernel/mac80211/patches/rt2x00/996-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch

   1 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
   2 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
   3 @@ -1056,6 +1056,11 @@
   4  #define MIMO_PS_CFG_RX_STBY_POL                FIELD32(0x00000010)
   5  #define MIMO_PS_CFG_RX_RX_STBY0                FIELD32(0x00000020)
   6
   7 +#define BB_PA_MODE_CFG0                        0x1214
   8 +#define BB_PA_MODE_CFG1                        0x1218
   9 +#define RF_PA_MODE_CFG0                        0x121C
  10 +#define RF_PA_MODE_CFG1                        0x1220
  11 +
  12  /*
  13   * EDCA_AC0_CFG:
  14   */
  15 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  16 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  17 @@ -3836,14 +3836,16 @@ static void rt2800_config_channel_rf7620
  18         rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
  19         rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
  20
  21 -       /* Default: XO=20MHz , SDM mode */
  22 -       rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
  23 -       rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
  24 -       rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
  25 -
  26 -       rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
  27 -       rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
  28 -       rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  29 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
  30 +               /* Default: XO=20MHz , SDM mode */
  31 +               rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
  32 +               rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
  33 +               rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
  34 +
  35 +               rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
  36 +               rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
  37 +               rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  38 +       }
  39
  40         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
  41         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
  42 @@ -3877,18 +3879,23 @@ static void rt2800_config_channel_rf7620
  43                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
  44         }
  45
  46 -       if (conf_is_ht40(conf)) {
  47 -               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
  48 -               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
  49 -       } else {
  50 -               rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
  51 -               rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
  52 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
  53 +               if (conf_is_ht40(conf)) {
  54 +                       rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
  55 +                       rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
  56 +               } else {
  57 +                       rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
  58 +                       rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
  59 +               }
  60         }
  61
  62 -       rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
  63 -       rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
  64 -                         conf_is_ht40(conf) && (rf->channel == 11));
  65 -       rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
  66 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
  67 +           rt2800_hw_get_chipeco(rt2x00dev) == 2) {
  68 +               rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
  69 +               rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
  70 +                                 conf_is_ht40(conf) && (rf->channel == 11));
  71 +               rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
  72 +       }
  73
  74         if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
  75                 if (conf_is_ht40(conf)) {
  76 @@ -4002,25 +4009,29 @@ static void rt2800_config_alc_rt6352(str
  77         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
  78                 rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
  79
  80 -       if (chan->center_freq > 2457) {
  81 -               bbp = rt2800_bbp_read(rt2x00dev, 30);
  82 -               bbp = 0x40;
  83 -               rt2800_bbp_write(rt2x00dev, 30, bbp);
  84 -               rt2800_rfcsr_write(rt2x00dev, 39, 0);
  85 -               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
  86 -                       rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
  87 -               else
  88 -                       rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
  89 -       } else {
  90 -               bbp = rt2800_bbp_read(rt2x00dev, 30);
  91 -               bbp = 0x1f;
  92 -               rt2800_bbp_write(rt2x00dev, 30, bbp);
  93 -               rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
  94 -               if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
  95 -                       rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
  96 -               else
  97 -                       rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
  98 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
  99 +           rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
 100 +               if (chan->center_freq > 2457) {
 101 +                       bbp = rt2800_bbp_read(rt2x00dev, 30);
 102 +                       bbp = 0x40;
 103 +                       rt2800_bbp_write(rt2x00dev, 30, bbp);
 104 +                       rt2800_rfcsr_write(rt2x00dev, 39, 0);
 105 +                       if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 106 +                               rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
 107 +                       else
 108 +                               rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
 109 +               } else {
 110 +                       bbp = rt2800_bbp_read(rt2x00dev, 30);
 111 +                       bbp = 0x1f;
 112 +                       rt2800_bbp_write(rt2x00dev, 30, bbp);
 113 +                       rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
 114 +                       if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
 115 +                               rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
 116 +                       else
 117 +                               rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
 118 +               }
 119         }
 120 +
 121         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
 122
 123         rt2800_vco_calibration(rt2x00dev);
 124 @@ -4513,7 +4524,8 @@ static void rt2800_config_channel(struct
 125         if (rt2x00_rt(rt2x00dev, RT6352)) {
 126                 /* BBP for GLRT BW */
 127                 bbp = conf_is_ht40(conf) ?
 128 -                     0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
 129 +                     0x10 : !rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
 130 +                     0x1a : rt2800_hw_get_chippkg(rt2x00dev) == 1 ?
 131                       0x15 : 0x1a;
 132                 rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
 133
 134 @@ -6017,18 +6029,33 @@ static int rt2800_init_registers(struct
 135         } else if (rt2x00_rt(rt2x00dev, RT5350)) {
 136                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
 137         } else if (rt2x00_rt(rt2x00dev, RT6352)) {
 138 -               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
 139 -               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
 140 -               rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 141 -               rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
 142 -               rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
 143 -               rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
 144 -               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
 145 -               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
 146 -               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
 147 -                                     0x3630363A);
 148 -               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
 149 -                                     0x3630363A);
 150 +               if (rt2800_hw_get_chipver(rt2x00dev) <= 1) {
 151 +                       rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
 152 +                                             0x00000000);
 153 +                       rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG0,
 154 +                                             0x000055FF);
 155 +                       rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG1,
 156 +                                             0x00550055);
 157 +                       rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG0,
 158 +                                             0x000055FF);
 159 +                       rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG1,
 160 +                                             0x00550055);
 161 +               } else {
 162 +                       rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
 163 +                       rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
 164 +                       rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
 165 +                       rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
 166 +                       rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
 167 +                       rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
 168 +                       rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
 169 +                                             0x6C6C666C);
 170 +                       rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
 171 +                                             0x6C6C666C);
 172 +                       rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
 173 +                                             0x3630363A);
 174 +                       rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
 175 +                                             0x3630363A);
 176 +               }
 177                 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
 178                 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
 179                 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
 180 @@ -7141,14 +7168,16 @@ static void rt2800_init_bbp_6352(struct
 181         rt2800_bbp_write(rt2x00dev, 188, 0x00);
 182         rt2800_bbp_write(rt2x00dev, 189, 0x00);
 183
 184 -       rt2800_bbp_write(rt2x00dev, 91, 0x06);
 185 -       rt2800_bbp_write(rt2x00dev, 92, 0x04);
 186 -       rt2800_bbp_write(rt2x00dev, 93, 0x54);
 187 -       rt2800_bbp_write(rt2x00dev, 99, 0x50);
 188 -       rt2800_bbp_write(rt2x00dev, 148, 0x84);
 189 -       rt2800_bbp_write(rt2x00dev, 167, 0x80);
 190 -       rt2800_bbp_write(rt2x00dev, 178, 0xFF);
 191 -       rt2800_bbp_write(rt2x00dev, 106, 0x13);
 192 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
 193 +               rt2800_bbp_write(rt2x00dev, 91, 0x06);
 194 +               rt2800_bbp_write(rt2x00dev, 92, 0x04);
 195 +               rt2800_bbp_write(rt2x00dev, 93, 0x54);
 196 +               rt2800_bbp_write(rt2x00dev, 99, 0x50);
 197 +               rt2800_bbp_write(rt2x00dev, 148, 0x84);
 198 +               rt2800_bbp_write(rt2x00dev, 167, 0x80);
 199 +               rt2800_bbp_write(rt2x00dev, 178, 0xFF);
 200 +               rt2800_bbp_write(rt2x00dev, 106, 0x13);
 201 +       }
 202
 203         /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
 204         rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
 205 @@ -10381,6 +10410,9 @@ static void rt2800_restore_rf_bbp_rt6352
 206                 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
 207         }
 208
 209 +       if (rt2800_hw_get_chippkg(rt2x00dev) != 1)
 210 +               return;
 211 +
 212         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 213                 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
 214                 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
 215 @@ -10458,6 +10490,9 @@ static void rt2800_calibration_rt6352(st
 216                 rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
 217         }
 218
 219 +       if (rt2800_hw_get_chippkg(rt2x00dev) != 1)
 220 +               return;
 221 +
 222         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 223                 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
 224                 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
 225 @@ -10548,31 +10583,36 @@ static void rt2800_init_rfcsr_6352(struc
 226         rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
 227         rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
 228
 229 -       rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
 230 -       if (rt2800_clk_is_20mhz(rt2x00dev))
 231 -               rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
 232 -       else
 233 -               rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
 234 -       rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
 235 -       rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
 236 -       rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
 237 -       rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
 238 -       rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
 239 -       rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
 240 -       rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
 241 -       rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
 242 -       rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
 243 -       rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 244 -       rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
 245 -       rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
 246 -       rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
 247 -       rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
 248 -       rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
 249 -       rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
 250 -
 251 -       rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
 252 -       rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
 253 -       rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
 254 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
 255 +               rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
 256 +               if (rt2800_clk_is_20mhz(rt2x00dev))
 257 +                       rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
 258 +               else
 259 +                       rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
 260 +               rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
 261 +               rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
 262 +               rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
 263 +               rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
 264 +               rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
 265 +               rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
 266 +               rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
 267 +               rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
 268 +               rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
 269 +               rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
 270 +               rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
 271 +               rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
 272 +               rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
 273 +               rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
 274 +               rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
 275 +               rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
 276 +       }
 277 +
 278 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
 279 +           rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
 280 +               rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
 281 +               rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
 282 +               rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
 283 +       }
 284
 285         /* Initialize RF channel register to default value */
 286         rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
 287 @@ -10638,63 +10678,71 @@ static void rt2800_init_rfcsr_6352(struc
 288
 289         rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
 290
 291 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
 292 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
 293 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
 294 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
 295 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
 296 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
 297 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
 298 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
 299 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
 300 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
 301 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
 302 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
 303 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
 304 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
 305 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
 306 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
 307 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
 308 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
 309 -       rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
 310 -       rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
 311 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
 312 -       rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
 313 -       rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
 314 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
 315 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
 316 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
 317 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
 318 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
 319 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
 320 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
 321 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
 322 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
 323 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
 324 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
 325 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
 326 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
 327 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
 328 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
 329 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
 330 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
 331 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
 332 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
 333 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
 334 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
 335 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
 336 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
 337 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
 338 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
 339 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
 340 +               rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
 341 +               rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
 342 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
 343 +               rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
 344 +               rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
 345 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
 346 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
 347 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
 348 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
 349 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
 350 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
 351 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
 352 +       }
 353
 354 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
 355 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
 356 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
 357 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
 358 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
 359 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
 360 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
 361 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
 362 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
 363 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
 364 +           rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
 365 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
 366 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
 367 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
 368 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
 369 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
 370 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
 371 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
 372 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
 373 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
 374 +
 375 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
 376 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
 377 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
 378 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
 379 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
 380 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
 381 +       }
 382
 383 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
 384 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
 385 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
 386 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
 387 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
 388 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
 389 -
 390 -       /* Initialize RF channel register for DRQFN */
 391 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
 392 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
 393 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
 394 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
 395 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
 396 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
 397 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
 398 -       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
 399 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
 400 +           rt2800_hw_get_chipver(rt2x00dev) == 1) {
 401 +               /* Initialize RF channel register for DRQFN */
 402 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
 403 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
 404 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
 405 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
 406 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
 407 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
 408 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
 409 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
 410 +       }
 411
 412         /* Initialize RF DC calibration register to default value */
 413         rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
 414 @@ -10757,12 +10805,17 @@ static void rt2800_init_rfcsr_6352(struc
 415         rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
 416         rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
 417
 418 -       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
 419 -       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
 420 -       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
 421 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
 422 +               rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
 423 +               rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
 424 +               rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
 425 +       }
 426
 427 -       rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
 428 -       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
 429 +       if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
 430 +           rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
 431 +               rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
 432 +               rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
 433 +       }
 434
 435         /* Do calibration and init PA/LNA */
 436         rt2800_calibration_rt6352(rt2x00dev);