package/kernel/qca-ssdk/patches/100-malibu-phy-drop-usage-of-first_phy_addr.patch

   1 From 46ed8163ac0d9a11a629f1c446e8c5e711cf35d6 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Sat, 11 Nov 2023 18:13:02 +0100
   4 Subject: [PATCH] malibu-phy: drop usage of first_phy_addr
   5
   6 I'm very confused by this and to me it's not clear the real usage of
   7 this logic.
   8
   9 From what I can see the usage of this is EXTREMELY FRAGILE and results
  10 in dangerous results if the OEM (or anyone that by chance try to
  11 implement things in a logical manner) deviates from the default values
  12 from the "magical template".
  13
  14 To be in more details. With QSDK 12.4, some tweaks were done to improve
  15 autoneg and now on every call of port status, the phydev is tried to
  16 add. This resulted in the call and log spam of an error with ports that
  17 are actually not present on the system with qsdk reporting phydev is
  18 NULL. This itself is not an error and printing the error is correct.
  19
  20 What is actually an error from ages is setting generic bitmap reporting
  21 presence of port that are actually not present. This is very common on
  22 OEM where the switch_lan_bmp is always a variant of 0x1e (that on bitmap
  23 results in PORT1 PORT2 PORT3 PORT4 present) or 0x3e (PORT1 PORT2 PORT3
  24 PORT4 PORT5). Reality is that many device are used as AP with one LAN
  25 port or one WAN port. (or even exotic configuration with PORT1 not
  26 present and PORT2 PORT3 PORT4 present (Xiaomi 3600)
  27
  28 With this finding one can say... ok nice, then lets update the DT and
  29 set the correct bitmap...
  30
  31 Again world is a bad place and reality is that this cause wonderful
  32 regression in some case of by extreme luck the first ever connected
  33 port working and the rest of the switch dead.
  34
  35 The problem has been bisected to all the device that doesn't have the
  36 PORT1 declared in any of the bitmap.
  37
  38 With this perfection in mind, on to the REAL problem.
  39
  40 malibu_phy_hw_init FOR SOME REASON, set a global variable first_phy_addr
  41 to the first detected PHY addr that coincidentally is always PORT1.
  42 PORT1 addr is 0x0. The entire code in malibu_phy use this variable to
  43 derive the phy addrs in some function.
  44
  45 Declaring a bitmap where the PORT1 is missing (or worse PORT4 the only
  46 one connected) result in first_phy_addr set to 1 or whatever phy addr is
  47 detected first setting wrong value all over the init stage.
  48
  49 To fix this, just drop this variable and hardcode everything to assume
  50 the first phy adrr is ALWAYS 0 and remove calculation and use define for
  51 special case.
  52
  53 With the following change normal switch traffic is restored and ports
  54 function is recovered.
  55
  56 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  57 ---
  58  src/hsl/phy/malibu_phy.c | 63 +++++++++++++++++-----------------------
  59  1 file changed, 26 insertions(+), 37 deletions(-)
  60
  61 --- a/src/hsl/phy/malibu_phy.c
  62 +++ b/src/hsl/phy/malibu_phy.c
  63 @@ -26,8 +26,9 @@
  64  #include "qcaphy_common.h"
  65  #include "ssdk_plat.h"
  66
  67 -static a_uint32_t first_phy_addr = MAX_PHY_ADDR;
  68  static a_uint32_t combo_phy_addr = MAX_PHY_ADDR;
  69 +#define PORT4_PHY_ID 0x4
  70 +#define PORT5_PHY_ID 0x5
  71  #define COMBO_PHY_ID combo_phy_addr
  72
  73  /******************************************************************************
  74 @@ -1250,10 +1251,10 @@ sw_error_t
  75  malibu_phy_serdes_reset(a_uint32_t dev_id)
  76  {
  77
  78 -       hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC,
  79 +       hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_PSGMII_ADDR_INC,
  80                 MALIBU_MODE_RESET_REG, MALIBU_MODE_CHANAGE_RESET);
  81         mdelay(100);
  82 -       hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC,
  83 +       hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_PSGMII_ADDR_INC,
  84                 MALIBU_MODE_RESET_REG, MALIBU_MODE_RESET_DEFAULT_VALUE);
  85
  86         return SW_OK;
  87 @@ -1271,8 +1272,7 @@ malibu_phy_interface_set_mode(a_uint32_t
  88         a_uint16_t phy_data = 0;
  89         static fal_port_interface_mode_t phy_mode = PORT_INTERFACE_MODE_MAX;
  90
  91 -       if ((phy_addr < first_phy_addr) ||
  92 -               (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)))
  93 +       if (phy_addr > MALIBU_PHY_MAX_ADDR_INC)
  94                 return SW_NOT_SUPPORTED;
  95         /*if interface_mode have been configured, then no need to configure again*/
  96         if(phy_mode == interface_mode)
  97 @@ -1295,20 +1295,19 @@ malibu_phy_interface_set_mode(a_uint32_t
  98                 return SW_BAD_PARAM;
  99         }
 100
 101 -       hsl_phy_modify_mii(dev_id,
 102 -               first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG,
 103 +       hsl_phy_modify_mii(dev_id, MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG,
 104                 BITS(0, 4), phy_data);
 105
 106         /* reset operation */
 107         malibu_phy_serdes_reset(dev_id);
 108
 109         if (interface_mode == PHY_PSGMII_FIBER) {
 110 -               hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC,
 111 +               hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_MAX_ADDR_INC,
 112                         MALIBU_PHY_CHIP_CONFIG, MALIBU_MODECTRL_DFLT);
 113 -               hsl_phy_mii_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC,
 114 +               hsl_phy_mii_reg_write(dev_id, MALIBU_PHY_MAX_ADDR_INC,
 115                         MALIBU_PHY_CONTROL, MALIBU_MIICTRL_DFLT);
 116                 hsl_phy_phydev_autoneg_update(dev_id,
 117 -                       first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, A_FALSE, 0);
 118 +                       MALIBU_PHY_MAX_ADDR_INC, A_FALSE, 0);
 119         }
 120         phy_mode = interface_mode;
 121         SSDK_DEBUG("malibu phy is configured as phy_mode:0x%x\n", phy_mode);
 122 @@ -1329,13 +1328,12 @@ malibu_phy_interface_get_mode(a_uint32_t
 123         a_uint16_t phy_data;
 124         a_uint16_t copper_mode;
 125
 126 -       if ((phy_addr < first_phy_addr) ||
 127 -               (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) {
 128 +       if (phy_addr > MALIBU_PHY_MAX_ADDR_INC) {
 129                 return SW_NOT_SUPPORTED;
 130         }
 131
 132         phy_data = hsl_phy_mii_reg_read(dev_id,
 133 -               first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
 134 +               MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
 135         copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf);
 136         phy_data &= 0x000f;
 137
 138 @@ -1344,13 +1342,13 @@ malibu_phy_interface_get_mode(a_uint32_t
 139                         *interface_mode = PHY_PSGMII_BASET;
 140                         break;
 141                 case MALIBU_PHY_PSGMII_BX1000:
 142 -                       if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
 143 +                       if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
 144                                 *interface_mode = PHY_PSGMII_BX1000;
 145                         else
 146                                 *interface_mode = PHY_PSGMII_BASET;
 147                         break;
 148                 case MALIBU_PHY_PSGMII_FX100:
 149 -                       if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
 150 +                       if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
 151                                 *interface_mode = PHY_PSGMII_FX100;
 152                         else
 153                                 *interface_mode = PHY_PSGMII_BASET;
 154 @@ -1359,14 +1357,14 @@ malibu_phy_interface_get_mode(a_uint32_t
 155                         if (copper_mode) {
 156                                 *interface_mode = PHY_PSGMII_BASET;
 157                          } else {
 158 -                               if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
 159 +                               if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
 160                                         *interface_mode = PHY_PSGMII_FIBER;
 161                                 else
 162                                         *interface_mode = PHY_PSGMII_BASET;
 163                          }
 164                         break;
 165                 case MALIBU_PHY_SGMII_BASET:
 166 -                       if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
 167 +                       if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
 168                                 *interface_mode = PHY_SGMII_BASET;
 169                         else
 170                                 *interface_mode = PORT_QSGMII;
 171 @@ -1392,13 +1390,12 @@ malibu_phy_interface_get_mode_status(a_u
 172         a_uint16_t phy_data, phy_mode, phy_mode_status;
 173         a_uint16_t copper_mode;
 174
 175 -       if ((phy_addr < first_phy_addr) ||
 176 -               (phy_addr > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) {
 177 +       if (phy_addr > MALIBU_PHY_MAX_ADDR_INC) {
 178                 return SW_NOT_SUPPORTED;
 179         }
 180
 181         phy_data = hsl_phy_mii_reg_read(dev_id,
 182 -               first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
 183 +               MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG);
 184         copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf);
 185         phy_mode = phy_data & 0x000f;
 186         phy_mode_status = (phy_data & 0x00f0) >> 0x4;
 187 @@ -1407,7 +1404,7 @@ malibu_phy_interface_get_mode_status(a_u
 188                 if (copper_mode) {
 189                         *interface_mode_status = PHY_PSGMII_BASET;
 190                 } else {
 191 -                       if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
 192 +                       if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
 193                                 *interface_mode_status = PHY_PSGMII_FIBER;
 194                         else
 195                                 *interface_mode_status = PHY_PSGMII_BASET;
 196 @@ -1418,19 +1415,19 @@ malibu_phy_interface_get_mode_status(a_u
 197                                 *interface_mode_status = PHY_PSGMII_BASET;
 198                                 break;
 199                         case MALIBU_PHY_PSGMII_BX1000:
 200 -                               if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
 201 +                               if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
 202                                         *interface_mode_status = PHY_PSGMII_BX1000;
 203                                 else
 204                                         *interface_mode_status = PHY_PSGMII_BASET;
 205                                 break;
 206                         case MALIBU_PHY_PSGMII_FX100:
 207 -                               if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
 208 +                               if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
 209                                         *interface_mode_status = PHY_PSGMII_FX100;
 210                                 else
 211                                         *interface_mode_status = PHY_PSGMII_BASET;
 212                                 break;
 213                         case MALIBU_PHY_SGMII_BASET:
 214 -                               if (phy_addr == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC)
 215 +                               if (phy_addr == MALIBU_PHY_MAX_ADDR_INC)
 216                                         *interface_mode_status = PHY_SGMII_BASET;
 217                                 else
 218                                         *interface_mode_status = PORT_QSGMII;
 219 @@ -1795,10 +1792,6 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_
 220                 {
 221                         phy_cnt ++;
 222                         phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id);
 223 -                       if (phy_addr < first_phy_addr)
 224 -                       {
 225 -                               first_phy_addr = phy_addr;
 226 -                       }
 227                         /*enable phy power saving function by default */
 228                         malibu_phy_set_8023az(dev_id, phy_addr, A_TRUE);
 229                         malibu_phy_set_powersave(dev_id, phy_addr, A_TRUE);
 230 @@ -1824,29 +1817,25 @@ malibu_phy_hw_init(a_uint32_t dev_id, a_
 231                                 MALIBU_EXTENDED_NEXT_PAGE_EN, 0);
 232                 }
 233         }
 234 -       /* qca 8072 two ports phy chip's firstly address to init phy chip */
 235 -       if ((phy_cnt == QCA8072_PHY_NUM) && (first_phy_addr >= 0x3)) {
 236 -               first_phy_addr = first_phy_addr - 0x3;
 237 -       }
 238
 239         /*workaround to enable AZ transmitting ability*/
 240 -       hsl_phy_mmd_reg_write(dev_id, first_phy_addr + 5, A_FALSE, MALIBU_PHY_MMD1_NUM,
 241 +       hsl_phy_mmd_reg_write(dev_id, PORT5_PHY_ID, A_FALSE, MALIBU_PHY_MMD1_NUM,
 242                 MALIBU_PSGMII_MODE_CTRL, MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE);
 243
 244         /* adjust psgmii serdes tx amp */
 245 -       hsl_phy_mii_reg_write(dev_id, first_phy_addr + 5,
 246 +       hsl_phy_mii_reg_write(dev_id, PORT5_PHY_ID,
 247                 MALIBU_PSGMII_TX_DRIVER_1_CTRL, MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
 248
 249         /* to avoid psgmii module goes into hibernation, work with psgmii self test*/
 250 -       hsl_phy_modify_mmd(dev_id, first_phy_addr + 4, A_FALSE, MALIBU_PHY_MMD3_NUM,
 251 +       hsl_phy_modify_mmd(dev_id, PORT4_PHY_ID, A_FALSE, MALIBU_PHY_MMD3_NUM,
 252                 MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, BIT(1), 0);
 253
 254         mode = ssdk_dt_global_get_mac_mode(dev_id, 0);
 255         if (mode == PORT_WRAPPER_PSGMII_FIBER)
 256 -               malibu_phy_interface_set_mode(dev_id, first_phy_addr, PHY_PSGMII_FIBER);
 257 +               malibu_phy_interface_set_mode(dev_id, 0x0, PHY_PSGMII_FIBER);
 258
 259         /*init combo phy address*/
 260 -       combo_phy_addr = first_phy_addr+4;
 261 +       combo_phy_addr = PORT4_PHY_ID;
 262
 263         return SW_OK;
 264  }