package/kernel/qca-ssdk/patches/103-mdio-adapt-to-C22-and-C45-read-write-split.patch

   1 From bdae481e89cbe551068a99028bb57119b59f5ff4 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Tue, 26 Mar 2024 12:19:49 +0100
   4 Subject: [PATCH] mdio: adapt to C22 and C45 read/write split
   5
   6 Kernel 6.3 has introduced separate C45 read/write operations, and thus
   7 split them out of the C22 operations completely so the old way of marking
   8 C45 reads and writes via the register value does not work anymore.
   9
  10 This is causing SSDK to fail and find C45 only PHY-s such as Aquantia ones:
  11 [   22.187877] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 8, phy_id = 0x0 phytype doesn't match
  12 [   22.209924] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 0, phy_id = 0x0 phytype doesn't match
  13
  14 This in turn causes USXGMII MAC autoneg bit to not get set and then UNIPHY
  15 autoneg will time out, causing the 10G ports not to work:
  16 [   37.292784] uniphy autoneg time out!
  17
  18 So, lets detect C45 reads and writes by the magic BIT(30) in the register
  19 argument and if so call separate C45 mdiobus read/write functions.
  20
  21 Signed-off-by: Robert Marko <robimarko@gmail.com>
  22 ---
  23  include/init/ssdk_plat.h |  7 +++++++
  24  src/init/ssdk_plat.c     | 30 ++++++++++++++++++++++++++++++
  25  2 files changed, 37 insertions(+)
  26
  27 --- a/include/init/ssdk_plat.h
  28 +++ b/include/init/ssdk_plat.h
  29 @@ -505,3 +505,10 @@ void ssdk_plat_exit(a_uint32_t dev_id);
  30
  31  #endif
  32  /*qca808x_end*/
  33 +
  34 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
  35 +#define MII_ADDR_C45           (1<<30)
  36 +#define MII_DEVADDR_C45_SHIFT  16
  37 +#define MII_DEVADDR_C45_MASK   GENMASK(20, 16)
  38 +#define MII_REGADDR_C45_MASK   GENMASK(15, 0)
  39 +#endif
  40 --- a/src/init/ssdk_plat.c
  41 +++ b/src/init/ssdk_plat.c
  42 @@ -356,6 +356,18 @@ phy_addr_validation_check(a_uint32_t phy
  43                 return A_TRUE;
  44  }
  45
  46 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
  47 +static inline u16 mdiobus_c45_regad(u32 regnum)
  48 +{
  49 +       return FIELD_GET(MII_REGADDR_C45_MASK, regnum);
  50 +}
  51 +
  52 +static inline u16 mdiobus_c45_devad(u32 regnum)
  53 +{
  54 +       return FIELD_GET(MII_DEVADDR_C45_MASK, regnum);
  55 +}
  56 +#endif
  57 +
  58  sw_error_t
  59  qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr,
  60                             a_uint32_t reg, a_uint16_t* data)
  61 @@ -371,9 +383,18 @@ qca_ar8327_phy_read(a_uint32_t dev_id, a
  62         if (!bus)
  63                 return SW_NOT_SUPPORTED;
  64         phy_addr = TO_PHY_ADDR(phy_addr);
  65 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
  66 +       mutex_lock(&bus->mdio_lock);
  67 +       if (reg & MII_ADDR_C45)
  68 +               *data = __mdiobus_c45_read(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg));
  69 +       else
  70 +               *data = __mdiobus_read(bus, phy_addr, reg);
  71 +       mutex_unlock(&bus->mdio_lock);
  72 +#else
  73         mutex_lock(&bus->mdio_lock);
  74         *data = __mdiobus_read(bus, phy_addr, reg);
  75         mutex_unlock(&bus->mdio_lock);
  76 +#endif
  77
  78         return 0;
  79  }
  80 @@ -393,9 +414,18 @@ qca_ar8327_phy_write(a_uint32_t dev_id,
  81         if (!bus)
  82                 return SW_NOT_SUPPORTED;
  83         phy_addr = TO_PHY_ADDR(phy_addr);
  84 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
  85 +       mutex_lock(&bus->mdio_lock);
  86 +       if (reg & MII_ADDR_C45)
  87 +               __mdiobus_c45_write(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg), data);
  88 +       else
  89 +               __mdiobus_write(bus, phy_addr, reg, data);
  90 +       mutex_unlock(&bus->mdio_lock);
  91 +#else
  92         mutex_lock(&bus->mdio_lock);
  93         __mdiobus_write(bus, phy_addr, reg, data);
  94         mutex_unlock(&bus->mdio_lock);
  95 +#endif
  96
  97         return 0;
  98  }