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ath9k: more fixes/cleanups for ar9280 and ar9300
[openwrt/staging/stintel.git] / package / mac80211 / patches / 300-ar9300_support.patch
1 --- a/drivers/net/wireless/ath/ath9k/Makefile
2 +++ b/drivers/net/wireless/ath/ath9k/Makefile
3 @@ -13,16 +13,26 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
4
5 obj-$(CONFIG_ATH9K) += ath9k.o
6
7 -ath9k_hw-y:= hw.o \
8 +ath9k_hw-y:= \
9 + ar9002_hw.o \
10 + ar9003_hw.o \
11 + hw.o \
12 + ar9003_phy.o \
13 + ar9002_phy.o \
14 + ar5008_phy.o \
15 + ar9002_calib.o \
16 + ar9003_calib.o \
17 + calib.o \
18 eeprom.o \
19 eeprom_def.o \
20 eeprom_4k.o \
21 eeprom_9287.o \
22 - calib.o \
23 ani.o \
24 - phy.o \
25 btcoex.o \
26 mac.o \
27 + ar9002_mac.o \
28 + ar9003_mac.o \
29 + ar9003_eeprom.o
30
31 obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
32
33 --- a/drivers/net/wireless/ath/ath9k/ani.c
34 +++ b/drivers/net/wireless/ath/ath9k/ani.c
35 @@ -15,6 +15,7 @@
36 */
37
38 #include "hw.h"
39 +#include "hw-ops.h"
40
41 static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
42 struct ath9k_channel *chan)
43 @@ -37,190 +38,6 @@ static int ath9k_hw_get_ani_channel_idx(
44 return 0;
45 }
46
47 -static bool ath9k_hw_ani_control(struct ath_hw *ah,
48 - enum ath9k_ani_cmd cmd, int param)
49 -{
50 - struct ar5416AniState *aniState = ah->curani;
51 - struct ath_common *common = ath9k_hw_common(ah);
52 -
53 - switch (cmd & ah->ani_function) {
54 - case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
55 - u32 level = param;
56 -
57 - if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
58 - ath_print(common, ATH_DBG_ANI,
59 - "level out of range (%u > %u)\n",
60 - level,
61 - (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
62 - return false;
63 - }
64 -
65 - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
66 - AR_PHY_DESIRED_SZ_TOT_DES,
67 - ah->totalSizeDesired[level]);
68 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
69 - AR_PHY_AGC_CTL1_COARSE_LOW,
70 - ah->coarse_low[level]);
71 - REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
72 - AR_PHY_AGC_CTL1_COARSE_HIGH,
73 - ah->coarse_high[level]);
74 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
75 - AR_PHY_FIND_SIG_FIRPWR,
76 - ah->firpwr[level]);
77 -
78 - if (level > aniState->noiseImmunityLevel)
79 - ah->stats.ast_ani_niup++;
80 - else if (level < aniState->noiseImmunityLevel)
81 - ah->stats.ast_ani_nidown++;
82 - aniState->noiseImmunityLevel = level;
83 - break;
84 - }
85 - case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
86 - const int m1ThreshLow[] = { 127, 50 };
87 - const int m2ThreshLow[] = { 127, 40 };
88 - const int m1Thresh[] = { 127, 0x4d };
89 - const int m2Thresh[] = { 127, 0x40 };
90 - const int m2CountThr[] = { 31, 16 };
91 - const int m2CountThrLow[] = { 63, 48 };
92 - u32 on = param ? 1 : 0;
93 -
94 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
95 - AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
96 - m1ThreshLow[on]);
97 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
98 - AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
99 - m2ThreshLow[on]);
100 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
101 - AR_PHY_SFCORR_M1_THRESH,
102 - m1Thresh[on]);
103 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
104 - AR_PHY_SFCORR_M2_THRESH,
105 - m2Thresh[on]);
106 - REG_RMW_FIELD(ah, AR_PHY_SFCORR,
107 - AR_PHY_SFCORR_M2COUNT_THR,
108 - m2CountThr[on]);
109 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
110 - AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
111 - m2CountThrLow[on]);
112 -
113 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
114 - AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
115 - m1ThreshLow[on]);
116 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
117 - AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
118 - m2ThreshLow[on]);
119 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
120 - AR_PHY_SFCORR_EXT_M1_THRESH,
121 - m1Thresh[on]);
122 - REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
123 - AR_PHY_SFCORR_EXT_M2_THRESH,
124 - m2Thresh[on]);
125 -
126 - if (on)
127 - REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
128 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
129 - else
130 - REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
131 - AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
132 -
133 - if (!on != aniState->ofdmWeakSigDetectOff) {
134 - if (on)
135 - ah->stats.ast_ani_ofdmon++;
136 - else
137 - ah->stats.ast_ani_ofdmoff++;
138 - aniState->ofdmWeakSigDetectOff = !on;
139 - }
140 - break;
141 - }
142 - case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
143 - const int weakSigThrCck[] = { 8, 6 };
144 - u32 high = param ? 1 : 0;
145 -
146 - REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
147 - AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
148 - weakSigThrCck[high]);
149 - if (high != aniState->cckWeakSigThreshold) {
150 - if (high)
151 - ah->stats.ast_ani_cckhigh++;
152 - else
153 - ah->stats.ast_ani_ccklow++;
154 - aniState->cckWeakSigThreshold = high;
155 - }
156 - break;
157 - }
158 - case ATH9K_ANI_FIRSTEP_LEVEL:{
159 - const int firstep[] = { 0, 4, 8 };
160 - u32 level = param;
161 -
162 - if (level >= ARRAY_SIZE(firstep)) {
163 - ath_print(common, ATH_DBG_ANI,
164 - "level out of range (%u > %u)\n",
165 - level,
166 - (unsigned) ARRAY_SIZE(firstep));
167 - return false;
168 - }
169 - REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
170 - AR_PHY_FIND_SIG_FIRSTEP,
171 - firstep[level]);
172 - if (level > aniState->firstepLevel)
173 - ah->stats.ast_ani_stepup++;
174 - else if (level < aniState->firstepLevel)
175 - ah->stats.ast_ani_stepdown++;
176 - aniState->firstepLevel = level;
177 - break;
178 - }
179 - case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
180 - const int cycpwrThr1[] =
181 - { 2, 4, 6, 8, 10, 12, 14, 16 };
182 - u32 level = param;
183 -
184 - if (level >= ARRAY_SIZE(cycpwrThr1)) {
185 - ath_print(common, ATH_DBG_ANI,
186 - "level out of range (%u > %u)\n",
187 - level,
188 - (unsigned) ARRAY_SIZE(cycpwrThr1));
189 - return false;
190 - }
191 - REG_RMW_FIELD(ah, AR_PHY_TIMING5,
192 - AR_PHY_TIMING5_CYCPWR_THR1,
193 - cycpwrThr1[level]);
194 - if (level > aniState->spurImmunityLevel)
195 - ah->stats.ast_ani_spurup++;
196 - else if (level < aniState->spurImmunityLevel)
197 - ah->stats.ast_ani_spurdown++;
198 - aniState->spurImmunityLevel = level;
199 - break;
200 - }
201 - case ATH9K_ANI_PRESENT:
202 - break;
203 - default:
204 - ath_print(common, ATH_DBG_ANI,
205 - "invalid cmd %u\n", cmd);
206 - return false;
207 - }
208 -
209 - ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
210 - ath_print(common, ATH_DBG_ANI,
211 - "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
212 - "ofdmWeakSigDetectOff=%d\n",
213 - aniState->noiseImmunityLevel,
214 - aniState->spurImmunityLevel,
215 - !aniState->ofdmWeakSigDetectOff);
216 - ath_print(common, ATH_DBG_ANI,
217 - "cckWeakSigThreshold=%d, "
218 - "firstepLevel=%d, listenTime=%d\n",
219 - aniState->cckWeakSigThreshold,
220 - aniState->firstepLevel,
221 - aniState->listenTime);
222 - ath_print(common, ATH_DBG_ANI,
223 - "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
224 - aniState->cycleCount,
225 - aniState->ofdmPhyErrCount,
226 - aniState->cckPhyErrCount);
227 -
228 - return true;
229 -}
230 -
231 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
232 struct ath9k_mib_stats *stats)
233 {
234 --- /dev/null
235 +++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
236 @@ -0,0 +1,873 @@
237 +/*
238 + * Copyright (c) 2008-2009 Atheros Communications Inc.
239 + *
240 + * Permission to use, copy, modify, and/or distribute this software for any
241 + * purpose with or without fee is hereby granted, provided that the above
242 + * copyright notice and this permission notice appear in all copies.
243 + *
244 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
245 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
246 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
247 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
248 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
249 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
250 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
251 + */
252 +
253 +#ifndef INITVALS_AR5008_H
254 +#define INITVALS_AR5008_H
255 +
256 +static const u32 ar5416Modes[][6] = {
257 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
258 + 0x000001e0},
259 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
260 + 0x000001e0},
261 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
262 + 0x00001180},
263 + {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000,
264 + 0x00014008},
265 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
266 + 0x06e006e0},
267 + {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab,
268 + 0x098813cf},
269 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810,
270 + 0x08f04810},
271 + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a,
272 + 0x0000320a},
273 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
274 + 0x00000303},
275 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
276 + 0x02020200},
277 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
278 + 0x00000e0e},
279 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
280 + 0x0a020001},
281 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
282 + 0x00000e0e},
283 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
284 + 0x00000007},
285 + {0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0,
286 + 0x137216a0},
287 + {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
288 + 0x00197a68},
289 + {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
290 + 0x00197a68},
291 + {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
292 + 0x00197a68},
293 + {0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de,
294 + 0x6c48b0de},
295 + {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e,
296 + 0x7ec82d2e},
297 + {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e,
298 + 0x31395d5e},
299 + {0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18,
300 + 0x00049d18},
301 + {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
302 + 0x0001ce00},
303 + {0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190,
304 + 0x409a4190},
305 + {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081,
306 + 0x050cb081},
307 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
308 + 0x000007d0},
309 + {0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134,
310 + 0x00000134},
311 + {0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b,
312 + 0xd0058a0b},
313 + {0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020,
314 + 0xffb81020},
315 + {0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80,
316 + 0x00012d80},
317 + {0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80,
318 + 0x00012d80},
319 + {0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80,
320 + 0x00012d80},
321 + {0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120,
322 + 0x00001120},
323 + {0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00,
324 + 0x001a0a00},
325 + {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be,
326 + 0x038919be},
327 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
328 + 0x06336f77},
329 + {0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c,
330 + 0x6af6532c},
331 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
332 + 0x08f186c8},
333 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
334 + 0x00046384},
335 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
336 + 0x00000000},
337 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
338 + 0x00000000},
339 + {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880,
340 + 0x00000880},
341 + {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788,
342 + 0xd03e4788},
343 + {0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120,
344 + 0x002ac120},
345 + {0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120,
346 + 0x002ac120},
347 + {0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120,
348 + 0x002ac120},
349 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
350 + 0x1883800a},
351 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
352 + 0x00000000},
353 + {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa,
354 + 0x0a1a7caa},
355 + {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000,
356 + 0x18010000},
357 + {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402,
358 + 0x2e032402},
359 + {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06,
360 + 0x4a0a3c06},
361 + {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b,
362 + 0x621a540b},
363 + {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b,
364 + 0x764f6c1b},
365 + {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a,
366 + 0x845b7a5a},
367 + {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf,
368 + 0x950f8ccf},
369 + {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f,
370 + 0xa5cf9b4f},
371 + {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f,
372 + 0xbddfaf1f},
373 + {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f,
374 + 0xd1ffc93f},
375 + {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000,
376 + 0x00000000},
377 + {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
378 + 0x00000000},
379 + {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
380 + 0x00000000},
381 + {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
382 + 0x00000000},
383 +};
384 +
385 +static const u32 ar5416Common[][2] = {
386 + {0x0000000c, 0x00000000},
387 + {0x00000030, 0x00020015},
388 + {0x00000034, 0x00000005},
389 + {0x00000040, 0x00000000},
390 + {0x00000044, 0x00000008},
391 + {0x00000048, 0x00000008},
392 + {0x0000004c, 0x00000010},
393 + {0x00000050, 0x00000000},
394 + {0x00000054, 0x0000001f},
395 + {0x00000800, 0x00000000},
396 + {0x00000804, 0x00000000},
397 + {0x00000808, 0x00000000},
398 + {0x0000080c, 0x00000000},
399 + {0x00000810, 0x00000000},
400 + {0x00000814, 0x00000000},
401 + {0x00000818, 0x00000000},
402 + {0x0000081c, 0x00000000},
403 + {0x00000820, 0x00000000},
404 + {0x00000824, 0x00000000},
405 + {0x00001040, 0x002ffc0f},
406 + {0x00001044, 0x002ffc0f},
407 + {0x00001048, 0x002ffc0f},
408 + {0x0000104c, 0x002ffc0f},
409 + {0x00001050, 0x002ffc0f},
410 + {0x00001054, 0x002ffc0f},
411 + {0x00001058, 0x002ffc0f},
412 + {0x0000105c, 0x002ffc0f},
413 + {0x00001060, 0x002ffc0f},
414 + {0x00001064, 0x002ffc0f},
415 + {0x00001230, 0x00000000},
416 + {0x00001270, 0x00000000},
417 + {0x00001038, 0x00000000},
418 + {0x00001078, 0x00000000},
419 + {0x000010b8, 0x00000000},
420 + {0x000010f8, 0x00000000},
421 + {0x00001138, 0x00000000},
422 + {0x00001178, 0x00000000},
423 + {0x000011b8, 0x00000000},
424 + {0x000011f8, 0x00000000},
425 + {0x00001238, 0x00000000},
426 + {0x00001278, 0x00000000},
427 + {0x000012b8, 0x00000000},
428 + {0x000012f8, 0x00000000},
429 + {0x00001338, 0x00000000},
430 + {0x00001378, 0x00000000},
431 + {0x000013b8, 0x00000000},
432 + {0x000013f8, 0x00000000},
433 + {0x00001438, 0x00000000},
434 + {0x00001478, 0x00000000},
435 + {0x000014b8, 0x00000000},
436 + {0x000014f8, 0x00000000},
437 + {0x00001538, 0x00000000},
438 + {0x00001578, 0x00000000},
439 + {0x000015b8, 0x00000000},
440 + {0x000015f8, 0x00000000},
441 + {0x00001638, 0x00000000},
442 + {0x00001678, 0x00000000},
443 + {0x000016b8, 0x00000000},
444 + {0x000016f8, 0x00000000},
445 + {0x00001738, 0x00000000},
446 + {0x00001778, 0x00000000},
447 + {0x000017b8, 0x00000000},
448 + {0x000017f8, 0x00000000},
449 + {0x0000103c, 0x00000000},
450 + {0x0000107c, 0x00000000},
451 + {0x000010bc, 0x00000000},
452 + {0x000010fc, 0x00000000},
453 + {0x0000113c, 0x00000000},
454 + {0x0000117c, 0x00000000},
455 + {0x000011bc, 0x00000000},
456 + {0x000011fc, 0x00000000},
457 + {0x0000123c, 0x00000000},
458 + {0x0000127c, 0x00000000},
459 + {0x000012bc, 0x00000000},
460 + {0x000012fc, 0x00000000},
461 + {0x0000133c, 0x00000000},
462 + {0x0000137c, 0x00000000},
463 + {0x000013bc, 0x00000000},
464 + {0x000013fc, 0x00000000},
465 + {0x0000143c, 0x00000000},
466 + {0x0000147c, 0x00000000},
467 + {0x00004030, 0x00000002},
468 + {0x0000403c, 0x00000002},
469 + {0x00007010, 0x00000000},
470 + {0x00007038, 0x000004c2},
471 + {0x00008004, 0x00000000},
472 + {0x00008008, 0x00000000},
473 + {0x0000800c, 0x00000000},
474 + {0x00008018, 0x00000700},
475 + {0x00008020, 0x00000000},
476 + {0x00008038, 0x00000000},
477 + {0x0000803c, 0x00000000},
478 + {0x00008048, 0x40000000},
479 + {0x00008054, 0x00000000},
480 + {0x00008058, 0x00000000},
481 + {0x0000805c, 0x000fc78f},
482 + {0x00008060, 0x0000000f},
483 + {0x00008064, 0x00000000},
484 + {0x000080c0, 0x2a82301a},
485 + {0x000080c4, 0x05dc01e0},
486 + {0x000080c8, 0x1f402710},
487 + {0x000080cc, 0x01f40000},
488 + {0x000080d0, 0x00001e00},
489 + {0x000080d4, 0x00000000},
490 + {0x000080d8, 0x00400000},
491 + {0x000080e0, 0xffffffff},
492 + {0x000080e4, 0x0000ffff},
493 + {0x000080e8, 0x003f3f3f},
494 + {0x000080ec, 0x00000000},
495 + {0x000080f0, 0x00000000},
496 + {0x000080f4, 0x00000000},
497 + {0x000080f8, 0x00000000},
498 + {0x000080fc, 0x00020000},
499 + {0x00008100, 0x00020000},
500 + {0x00008104, 0x00000001},
501 + {0x00008108, 0x00000052},
502 + {0x0000810c, 0x00000000},
503 + {0x00008110, 0x00000168},
504 + {0x00008118, 0x000100aa},
505 + {0x0000811c, 0x00003210},
506 + {0x00008124, 0x00000000},
507 + {0x00008128, 0x00000000},
508 + {0x0000812c, 0x00000000},
509 + {0x00008130, 0x00000000},
510 + {0x00008134, 0x00000000},
511 + {0x00008138, 0x00000000},
512 + {0x0000813c, 0x00000000},
513 + {0x00008144, 0xffffffff},
514 + {0x00008168, 0x00000000},
515 + {0x0000816c, 0x00000000},
516 + {0x00008170, 0x32143320},
517 + {0x00008174, 0xfaa4fa50},
518 + {0x00008178, 0x00000100},
519 + {0x0000817c, 0x00000000},
520 + {0x000081c4, 0x00000000},
521 + {0x000081ec, 0x00000000},
522 + {0x000081f0, 0x00000000},
523 + {0x000081f4, 0x00000000},
524 + {0x000081f8, 0x00000000},
525 + {0x000081fc, 0x00000000},
526 + {0x00008200, 0x00000000},
527 + {0x00008204, 0x00000000},
528 + {0x00008208, 0x00000000},
529 + {0x0000820c, 0x00000000},
530 + {0x00008210, 0x00000000},
531 + {0x00008214, 0x00000000},
532 + {0x00008218, 0x00000000},
533 + {0x0000821c, 0x00000000},
534 + {0x00008220, 0x00000000},
535 + {0x00008224, 0x00000000},
536 + {0x00008228, 0x00000000},
537 + {0x0000822c, 0x00000000},
538 + {0x00008230, 0x00000000},
539 + {0x00008234, 0x00000000},
540 + {0x00008238, 0x00000000},
541 + {0x0000823c, 0x00000000},
542 + {0x00008240, 0x00100000},
543 + {0x00008244, 0x0010f400},
544 + {0x00008248, 0x00000100},
545 + {0x0000824c, 0x0001e800},
546 + {0x00008250, 0x00000000},
547 + {0x00008254, 0x00000000},
548 + {0x00008258, 0x00000000},
549 + {0x0000825c, 0x400000ff},
550 + {0x00008260, 0x00080922},
551 + {0x00008264, 0xa8000010},
552 + {0x00008270, 0x00000000},
553 + {0x00008274, 0x40000000},
554 + {0x00008278, 0x003e4180},
555 + {0x0000827c, 0x00000000},
556 + {0x00008284, 0x0000002c},
557 + {0x00008288, 0x0000002c},
558 + {0x0000828c, 0x00000000},
559 + {0x00008294, 0x00000000},
560 + {0x00008298, 0x00000000},
561 + {0x00008300, 0x00000000},
562 + {0x00008304, 0x00000000},
563 + {0x00008308, 0x00000000},
564 + {0x0000830c, 0x00000000},
565 + {0x00008310, 0x00000000},
566 + {0x00008314, 0x00000000},
567 + {0x00008318, 0x00000000},
568 + {0x00008328, 0x00000000},
569 + {0x0000832c, 0x00000007},
570 + {0x00008330, 0x00000302},
571 + {0x00008334, 0x00000e00},
572 + {0x00008338, 0x00070000},
573 + {0x0000833c, 0x00000000},
574 + {0x00008340, 0x000107ff},
575 + {0x00009808, 0x00000000},
576 + {0x0000980c, 0xad848e19},
577 + {0x00009810, 0x7d14e000},
578 + {0x00009814, 0x9c0a9f6b},
579 + {0x0000981c, 0x00000000},
580 + {0x0000982c, 0x0000a000},
581 + {0x00009830, 0x00000000},
582 + {0x0000983c, 0x00200400},
583 + {0x00009840, 0x206a002e},
584 + {0x0000984c, 0x1284233c},
585 + {0x00009854, 0x00000859},
586 + {0x00009900, 0x00000000},
587 + {0x00009904, 0x00000000},
588 + {0x00009908, 0x00000000},
589 + {0x0000990c, 0x00000000},
590 + {0x0000991c, 0x10000fff},
591 + {0x00009920, 0x05100000},
592 + {0x0000a920, 0x05100000},
593 + {0x0000b920, 0x05100000},
594 + {0x00009928, 0x00000001},
595 + {0x0000992c, 0x00000004},
596 + {0x00009934, 0x1e1f2022},
597 + {0x00009938, 0x0a0b0c0d},
598 + {0x0000993c, 0x00000000},
599 + {0x00009948, 0x9280b212},
600 + {0x0000994c, 0x00020028},
601 + {0x00009954, 0x5d50e188},
602 + {0x00009958, 0x00081fff},
603 + {0x0000c95c, 0x004b6a8e},
604 + {0x0000c968, 0x000003ce},
605 + {0x00009970, 0x190fb515},
606 + {0x00009974, 0x00000000},
607 + {0x00009978, 0x00000001},
608 + {0x0000997c, 0x00000000},
609 + {0x00009980, 0x00000000},
610 + {0x00009984, 0x00000000},
611 + {0x00009988, 0x00000000},
612 + {0x0000998c, 0x00000000},
613 + {0x00009990, 0x00000000},
614 + {0x00009994, 0x00000000},
615 + {0x00009998, 0x00000000},
616 + {0x0000999c, 0x00000000},
617 + {0x000099a0, 0x00000000},
618 + {0x000099a4, 0x00000001},
619 + {0x000099a8, 0x001fff00},
620 + {0x000099ac, 0x00000000},
621 + {0x000099b0, 0x03051000},
622 + {0x000099dc, 0x00000000},
623 + {0x000099e0, 0x00000200},
624 + {0x000099e4, 0xaaaaaaaa},
625 + {0x000099e8, 0x3c466478},
626 + {0x000099ec, 0x000000aa},
627 + {0x000099fc, 0x00001042},
628 + {0x00009b00, 0x00000000},
629 + {0x00009b04, 0x00000001},
630 + {0x00009b08, 0x00000002},
631 + {0x00009b0c, 0x00000003},
632 + {0x00009b10, 0x00000004},
633 + {0x00009b14, 0x00000005},
634 + {0x00009b18, 0x00000008},
635 + {0x00009b1c, 0x00000009},
636 + {0x00009b20, 0x0000000a},
637 + {0x00009b24, 0x0000000b},
638 + {0x00009b28, 0x0000000c},
639 + {0x00009b2c, 0x0000000d},
640 + {0x00009b30, 0x00000010},
641 + {0x00009b34, 0x00000011},
642 + {0x00009b38, 0x00000012},
643 + {0x00009b3c, 0x00000013},
644 + {0x00009b40, 0x00000014},
645 + {0x00009b44, 0x00000015},
646 + {0x00009b48, 0x00000018},
647 + {0x00009b4c, 0x00000019},
648 + {0x00009b50, 0x0000001a},
649 + {0x00009b54, 0x0000001b},
650 + {0x00009b58, 0x0000001c},
651 + {0x00009b5c, 0x0000001d},
652 + {0x00009b60, 0x00000020},
653 + {0x00009b64, 0x00000021},
654 + {0x00009b68, 0x00000022},
655 + {0x00009b6c, 0x00000023},
656 + {0x00009b70, 0x00000024},
657 + {0x00009b74, 0x00000025},
658 + {0x00009b78, 0x00000028},
659 + {0x00009b7c, 0x00000029},
660 + {0x00009b80, 0x0000002a},
661 + {0x00009b84, 0x0000002b},
662 + {0x00009b88, 0x0000002c},
663 + {0x00009b8c, 0x0000002d},
664 + {0x00009b90, 0x00000030},
665 + {0x00009b94, 0x00000031},
666 + {0x00009b98, 0x00000032},
667 + {0x00009b9c, 0x00000033},
668 + {0x00009ba0, 0x00000034},
669 + {0x00009ba4, 0x00000035},
670 + {0x00009ba8, 0x00000035},
671 + {0x00009bac, 0x00000035},
672 + {0x00009bb0, 0x00000035},
673 + {0x00009bb4, 0x00000035},
674 + {0x00009bb8, 0x00000035},
675 + {0x00009bbc, 0x00000035},
676 + {0x00009bc0, 0x00000035},
677 + {0x00009bc4, 0x00000035},
678 + {0x00009bc8, 0x00000035},
679 + {0x00009bcc, 0x00000035},
680 + {0x00009bd0, 0x00000035},
681 + {0x00009bd4, 0x00000035},
682 + {0x00009bd8, 0x00000035},
683 + {0x00009bdc, 0x00000035},
684 + {0x00009be0, 0x00000035},
685 + {0x00009be4, 0x00000035},
686 + {0x00009be8, 0x00000035},
687 + {0x00009bec, 0x00000035},
688 + {0x00009bf0, 0x00000035},
689 + {0x00009bf4, 0x00000035},
690 + {0x00009bf8, 0x00000010},
691 + {0x00009bfc, 0x0000001a},
692 + {0x0000a210, 0x40806333},
693 + {0x0000a214, 0x00106c10},
694 + {0x0000a218, 0x009c4060},
695 + {0x0000a220, 0x018830c6},
696 + {0x0000a224, 0x00000400},
697 + {0x0000a228, 0x00000bb5},
698 + {0x0000a22c, 0x00000011},
699 + {0x0000a234, 0x20202020},
700 + {0x0000a238, 0x20202020},
701 + {0x0000a23c, 0x13c889af},
702 + {0x0000a240, 0x38490a20},
703 + {0x0000a244, 0x00007bb6},
704 + {0x0000a248, 0x0fff3ffc},
705 + {0x0000a24c, 0x00000001},
706 + {0x0000a250, 0x0000a000},
707 + {0x0000a254, 0x00000000},
708 + {0x0000a258, 0x0cc75380},
709 + {0x0000a25c, 0x0f0f0f01},
710 + {0x0000a260, 0xdfa91f01},
711 + {0x0000a268, 0x00000000},
712 + {0x0000a26c, 0x0e79e5c6},
713 + {0x0000b26c, 0x0e79e5c6},
714 + {0x0000c26c, 0x0e79e5c6},
715 + {0x0000d270, 0x00820820},
716 + {0x0000a278, 0x1ce739ce},
717 + {0x0000a27c, 0x051701ce},
718 + {0x0000a338, 0x00000000},
719 + {0x0000a33c, 0x00000000},
720 + {0x0000a340, 0x00000000},
721 + {0x0000a344, 0x00000000},
722 + {0x0000a348, 0x3fffffff},
723 + {0x0000a34c, 0x3fffffff},
724 + {0x0000a350, 0x3fffffff},
725 + {0x0000a354, 0x0003ffff},
726 + {0x0000a358, 0x79a8aa1f},
727 + {0x0000d35c, 0x07ffffef},
728 + {0x0000d360, 0x0fffffe7},
729 + {0x0000d364, 0x17ffffe5},
730 + {0x0000d368, 0x1fffffe4},
731 + {0x0000d36c, 0x37ffffe3},
732 + {0x0000d370, 0x3fffffe3},
733 + {0x0000d374, 0x57ffffe3},
734 + {0x0000d378, 0x5fffffe2},
735 + {0x0000d37c, 0x7fffffe2},
736 + {0x0000d380, 0x7f3c7bba},
737 + {0x0000d384, 0xf3307ff0},
738 + {0x0000a388, 0x08000000},
739 + {0x0000a38c, 0x20202020},
740 + {0x0000a390, 0x20202020},
741 + {0x0000a394, 0x1ce739ce},
742 + {0x0000a398, 0x000001ce},
743 + {0x0000a39c, 0x00000001},
744 + {0x0000a3a0, 0x00000000},
745 + {0x0000a3a4, 0x00000000},
746 + {0x0000a3a8, 0x00000000},
747 + {0x0000a3ac, 0x00000000},
748 + {0x0000a3b0, 0x00000000},
749 + {0x0000a3b4, 0x00000000},
750 + {0x0000a3b8, 0x00000000},
751 + {0x0000a3bc, 0x00000000},
752 + {0x0000a3c0, 0x00000000},
753 + {0x0000a3c4, 0x00000000},
754 + {0x0000a3c8, 0x00000246},
755 + {0x0000a3cc, 0x20202020},
756 + {0x0000a3d0, 0x20202020},
757 + {0x0000a3d4, 0x20202020},
758 + {0x0000a3dc, 0x1ce739ce},
759 + {0x0000a3e0, 0x000001ce},
760 +};
761 +
762 +static const u32 ar5416Bank0[][2] = {
763 + {0x000098b0, 0x1e5795e5},
764 + {0x000098e0, 0x02008020},
765 +};
766 +
767 +static const u32 ar5416BB_RfGain[][3] = {
768 + {0x00009a00, 0x00000000, 0x00000000},
769 + {0x00009a04, 0x00000040, 0x00000040},
770 + {0x00009a08, 0x00000080, 0x00000080},
771 + {0x00009a0c, 0x000001a1, 0x00000141},
772 + {0x00009a10, 0x000001e1, 0x00000181},
773 + {0x00009a14, 0x00000021, 0x000001c1},
774 + {0x00009a18, 0x00000061, 0x00000001},
775 + {0x00009a1c, 0x00000168, 0x00000041},
776 + {0x00009a20, 0x000001a8, 0x000001a8},
777 + {0x00009a24, 0x000001e8, 0x000001e8},
778 + {0x00009a28, 0x00000028, 0x00000028},
779 + {0x00009a2c, 0x00000068, 0x00000068},
780 + {0x00009a30, 0x00000189, 0x000000a8},
781 + {0x00009a34, 0x000001c9, 0x00000169},
782 + {0x00009a38, 0x00000009, 0x000001a9},
783 + {0x00009a3c, 0x00000049, 0x000001e9},
784 + {0x00009a40, 0x00000089, 0x00000029},
785 + {0x00009a44, 0x00000170, 0x00000069},
786 + {0x00009a48, 0x000001b0, 0x00000190},
787 + {0x00009a4c, 0x000001f0, 0x000001d0},
788 + {0x00009a50, 0x00000030, 0x00000010},
789 + {0x00009a54, 0x00000070, 0x00000050},
790 + {0x00009a58, 0x00000191, 0x00000090},
791 + {0x00009a5c, 0x000001d1, 0x00000151},
792 + {0x00009a60, 0x00000011, 0x00000191},
793 + {0x00009a64, 0x00000051, 0x000001d1},
794 + {0x00009a68, 0x00000091, 0x00000011},
795 + {0x00009a6c, 0x000001b8, 0x00000051},
796 + {0x00009a70, 0x000001f8, 0x00000198},
797 + {0x00009a74, 0x00000038, 0x000001d8},
798 + {0x00009a78, 0x00000078, 0x00000018},
799 + {0x00009a7c, 0x00000199, 0x00000058},
800 + {0x00009a80, 0x000001d9, 0x00000098},
801 + {0x00009a84, 0x00000019, 0x00000159},
802 + {0x00009a88, 0x00000059, 0x00000199},
803 + {0x00009a8c, 0x00000099, 0x000001d9},
804 + {0x00009a90, 0x000000d9, 0x00000019},
805 + {0x00009a94, 0x000000f9, 0x00000059},
806 + {0x00009a98, 0x000000f9, 0x00000099},
807 + {0x00009a9c, 0x000000f9, 0x000000d9},
808 + {0x00009aa0, 0x000000f9, 0x000000f9},
809 + {0x00009aa4, 0x000000f9, 0x000000f9},
810 + {0x00009aa8, 0x000000f9, 0x000000f9},
811 + {0x00009aac, 0x000000f9, 0x000000f9},
812 + {0x00009ab0, 0x000000f9, 0x000000f9},
813 + {0x00009ab4, 0x000000f9, 0x000000f9},
814 + {0x00009ab8, 0x000000f9, 0x000000f9},
815 + {0x00009abc, 0x000000f9, 0x000000f9},
816 + {0x00009ac0, 0x000000f9, 0x000000f9},
817 + {0x00009ac4, 0x000000f9, 0x000000f9},
818 + {0x00009ac8, 0x000000f9, 0x000000f9},
819 + {0x00009acc, 0x000000f9, 0x000000f9},
820 + {0x00009ad0, 0x000000f9, 0x000000f9},
821 + {0x00009ad4, 0x000000f9, 0x000000f9},
822 + {0x00009ad8, 0x000000f9, 0x000000f9},
823 + {0x00009adc, 0x000000f9, 0x000000f9},
824 + {0x00009ae0, 0x000000f9, 0x000000f9},
825 + {0x00009ae4, 0x000000f9, 0x000000f9},
826 + {0x00009ae8, 0x000000f9, 0x000000f9},
827 + {0x00009aec, 0x000000f9, 0x000000f9},
828 + {0x00009af0, 0x000000f9, 0x000000f9},
829 + {0x00009af4, 0x000000f9, 0x000000f9},
830 + {0x00009af8, 0x000000f9, 0x000000f9},
831 + {0x00009afc, 0x000000f9, 0x000000f9},
832 +};
833 +
834 +static const u32 ar5416Bank1[][2] = {
835 + {0x000098b0, 0x02108421},
836 + {0x000098ec, 0x00000008},
837 +};
838 +
839 +static const u32 ar5416Bank2[][2] = {
840 + {0x000098b0, 0x0e73ff17},
841 + {0x000098e0, 0x00000420},
842 +};
843 +
844 +static const u32 ar5416Bank3[][3] = {
845 + {0x000098f0, 0x01400018, 0x01c00018},
846 +};
847 +
848 +static const u32 ar5416Bank6[][3] = {
849 +
850 + {0x0000989c, 0x00000000, 0x00000000},
851 + {0x0000989c, 0x00000000, 0x00000000},
852 + {0x0000989c, 0x00000000, 0x00000000},
853 + {0x0000989c, 0x00e00000, 0x00e00000},
854 + {0x0000989c, 0x005e0000, 0x005e0000},
855 + {0x0000989c, 0x00120000, 0x00120000},
856 + {0x0000989c, 0x00620000, 0x00620000},
857 + {0x0000989c, 0x00020000, 0x00020000},
858 + {0x0000989c, 0x00ff0000, 0x00ff0000},
859 + {0x0000989c, 0x00ff0000, 0x00ff0000},
860 + {0x0000989c, 0x00ff0000, 0x00ff0000},
861 + {0x0000989c, 0x40ff0000, 0x40ff0000},
862 + {0x0000989c, 0x005f0000, 0x005f0000},
863 + {0x0000989c, 0x00870000, 0x00870000},
864 + {0x0000989c, 0x00f90000, 0x00f90000},
865 + {0x0000989c, 0x007b0000, 0x007b0000},
866 + {0x0000989c, 0x00ff0000, 0x00ff0000},
867 + {0x0000989c, 0x00f50000, 0x00f50000},
868 + {0x0000989c, 0x00dc0000, 0x00dc0000},
869 + {0x0000989c, 0x00110000, 0x00110000},
870 + {0x0000989c, 0x006100a8, 0x006100a8},
871 + {0x0000989c, 0x004210a2, 0x004210a2},
872 + {0x0000989c, 0x0014008f, 0x0014008f},
873 + {0x0000989c, 0x00c40003, 0x00c40003},
874 + {0x0000989c, 0x003000f2, 0x003000f2},
875 + {0x0000989c, 0x00440016, 0x00440016},
876 + {0x0000989c, 0x00410040, 0x00410040},
877 + {0x0000989c, 0x0001805e, 0x0001805e},
878 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
879 + {0x0000989c, 0x000000f1, 0x000000f1},
880 + {0x0000989c, 0x00002081, 0x00002081},
881 + {0x0000989c, 0x000000d4, 0x000000d4},
882 + {0x000098d0, 0x0000000f, 0x0010000f},
883 +};
884 +
885 +static const u32 ar5416Bank6TPC[][3] = {
886 + {0x0000989c, 0x00000000, 0x00000000},
887 + {0x0000989c, 0x00000000, 0x00000000},
888 + {0x0000989c, 0x00000000, 0x00000000},
889 + {0x0000989c, 0x00e00000, 0x00e00000},
890 + {0x0000989c, 0x005e0000, 0x005e0000},
891 + {0x0000989c, 0x00120000, 0x00120000},
892 + {0x0000989c, 0x00620000, 0x00620000},
893 + {0x0000989c, 0x00020000, 0x00020000},
894 + {0x0000989c, 0x00ff0000, 0x00ff0000},
895 + {0x0000989c, 0x00ff0000, 0x00ff0000},
896 + {0x0000989c, 0x00ff0000, 0x00ff0000},
897 + {0x0000989c, 0x40ff0000, 0x40ff0000},
898 + {0x0000989c, 0x005f0000, 0x005f0000},
899 + {0x0000989c, 0x00870000, 0x00870000},
900 + {0x0000989c, 0x00f90000, 0x00f90000},
901 + {0x0000989c, 0x007b0000, 0x007b0000},
902 + {0x0000989c, 0x00ff0000, 0x00ff0000},
903 + {0x0000989c, 0x00f50000, 0x00f50000},
904 + {0x0000989c, 0x00dc0000, 0x00dc0000},
905 + {0x0000989c, 0x00110000, 0x00110000},
906 + {0x0000989c, 0x006100a8, 0x006100a8},
907 + {0x0000989c, 0x00423022, 0x00423022},
908 + {0x0000989c, 0x201400df, 0x201400df},
909 + {0x0000989c, 0x00c40002, 0x00c40002},
910 + {0x0000989c, 0x003000f2, 0x003000f2},
911 + {0x0000989c, 0x00440016, 0x00440016},
912 + {0x0000989c, 0x00410040, 0x00410040},
913 + {0x0000989c, 0x0001805e, 0x0001805e},
914 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
915 + {0x0000989c, 0x000000e1, 0x000000e1},
916 + {0x0000989c, 0x00007081, 0x00007081},
917 + {0x0000989c, 0x000000d4, 0x000000d4},
918 + {0x000098d0, 0x0000000f, 0x0010000f},
919 +};
920 +
921 +static const u32 ar5416Bank7[][2] = {
922 + {0x0000989c, 0x00000500},
923 + {0x0000989c, 0x00000800},
924 + {0x000098cc, 0x0000000e},
925 +};
926 +
927 +static const u32 ar5416Addac[][2] = {
928 + {0x0000989c, 0x00000000},
929 + {0x0000989c, 0x00000003},
930 + {0x0000989c, 0x00000000},
931 + {0x0000989c, 0x0000000c},
932 + {0x0000989c, 0x00000000},
933 + {0x0000989c, 0x00000030},
934 + {0x0000989c, 0x00000000},
935 + {0x0000989c, 0x00000000},
936 + {0x0000989c, 0x00000000},
937 + {0x0000989c, 0x00000000},
938 + {0x0000989c, 0x00000000},
939 + {0x0000989c, 0x00000000},
940 + {0x0000989c, 0x00000000},
941 + {0x0000989c, 0x00000000},
942 + {0x0000989c, 0x00000000},
943 + {0x0000989c, 0x00000000},
944 + {0x0000989c, 0x00000000},
945 + {0x0000989c, 0x00000000},
946 + {0x0000989c, 0x00000060},
947 + {0x0000989c, 0x00000000},
948 + {0x0000989c, 0x00000000},
949 + {0x0000989c, 0x00000000},
950 + {0x0000989c, 0x00000000},
951 + {0x0000989c, 0x00000000},
952 + {0x0000989c, 0x00000000},
953 + {0x0000989c, 0x00000000},
954 + {0x0000989c, 0x00000000},
955 + {0x0000989c, 0x00000000},
956 + {0x0000989c, 0x00000000},
957 + {0x0000989c, 0x00000000},
958 + {0x0000989c, 0x00000000},
959 + {0x0000989c, 0x00000058},
960 + {0x0000989c, 0x00000000},
961 + {0x0000989c, 0x00000000},
962 + {0x0000989c, 0x00000000},
963 + {0x0000989c, 0x00000000},
964 + {0x000098cc, 0x00000000},
965 +};
966 +
967 +static const u32 ar5416Modes_9100[][6] = {
968 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
969 + 0x000001e0},
970 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
971 + 0x000001e0},
972 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
973 + 0x00001180},
974 + {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000,
975 + 0x00014008},
976 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
977 + 0x06e006e0},
978 + {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab,
979 + 0x098813cf},
980 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
981 + 0x00000303},
982 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
983 + 0x02020200},
984 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
985 + 0x00000e0e},
986 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
987 + 0x0a020001},
988 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
989 + 0x00000e0e},
990 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
991 + 0x00000007},
992 + {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0,
993 + 0x037216a0},
994 + {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
995 + 0x00197a68},
996 + {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
997 + 0x00197a68},
998 + {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
999 + 0x00197a68},
1000 + {0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2,
1001 + 0x6d48b0e2},
1002 + {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e,
1003 + 0x7ec82d2e},
1004 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e,
1005 + 0x3139605e},
1006 + {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20,
1007 + 0x00048d18},
1008 + {0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
1009 + 0x0001ce00},
1010 + {0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0,
1011 + 0x409a40d0},
1012 + {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081,
1013 + 0x050cb081},
1014 + {0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898,
1015 + 0x000007d0},
1016 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
1017 + 0x00000016},
1018 + {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d,
1019 + 0xd00a8a0d},
1020 + {0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204,
1021 + 0xfff81204},
1022 + {0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020,
1023 + 0xdfb81020},
1024 + {0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e,
1025 + 0xe250a51e},
1026 + {0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff,
1027 + 0x3388ffff},
1028 +#ifdef TB243
1029 + {0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40,
1030 + 0x00012d80},
1031 + {0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40,
1032 + 0x00012d80},
1033 + {0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40,
1034 + 0x00012d80},
1035 + {0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210,
1036 + 0x00001120},
1037 +#else
1038 + {0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0,
1039 + 0x0001bfc0},
1040 + {0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0,
1041 + 0x0001bfc0},
1042 + {0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0,
1043 + 0x0001bfc0},
1044 + {0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120,
1045 + 0x00001120},
1046 +#endif
1047 + {0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00,
1048 + 0x001a0c00},
1049 + {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be,
1050 + 0x038919be},
1051 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
1052 + 0x06336f77},
1053 + {0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329,
1054 + 0x60f65329},
1055 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
1056 + 0x08f186c8},
1057 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
1058 + 0x00046384},
1059 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1060 + 0x00000000},
1061 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1062 + 0x00000000},
1063 + {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880,
1064 + 0x00000880},
1065 + {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788,
1066 + 0xd03e4788},
1067 + {0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
1068 + 0x002ac120},
1069 + {0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
1070 + 0x002ac120},
1071 + {0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
1072 + 0x002ac120},
1073 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
1074 + 0x1883800a},
1075 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
1076 + 0x00000000},
1077 + {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa,
1078 + 0x0a1a7caa},
1079 + {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000,
1080 + 0x18010000},
1081 + {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402,
1082 + 0x2e032402},
1083 + {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06,
1084 + 0x4a0a3c06},
1085 + {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b,
1086 + 0x621a540b},
1087 + {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b,
1088 + 0x764f6c1b},
1089 + {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a,
1090 + 0x845b7a5a},
1091 + {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf,
1092 + 0x950f8ccf},
1093 + {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f,
1094 + 0xa5cf9b4f},
1095 + {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f,
1096 + 0xbddfaf1f},
1097 + {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f,
1098 + 0xd1ffc93f},
1099 + {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000,
1100 + 0x00000000},
1101 + {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1102 + 0x00000000},
1103 + {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1104 + 0x00000000},
1105 + {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1106 + 0x00000000},
1107 +};
1108 +
1109 +#endif /* INITVALS_AR5008_H */
1110 --- /dev/null
1111 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
1112 @@ -0,0 +1,1278 @@
1113 +/*
1114 + * Copyright (c) 2008-2010 Atheros Communications Inc.
1115 + *
1116 + * Permission to use, copy, modify, and/or distribute this software for any
1117 + * purpose with or without fee is hereby granted, provided that the above
1118 + * copyright notice and this permission notice appear in all copies.
1119 + *
1120 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
1121 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
1122 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
1123 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
1124 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
1125 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
1126 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
1127 + */
1128 +
1129 +#include "hw.h"
1130 +#include "hw-ops.h"
1131 +#include "../regd.h"
1132 +#include "ar9002_phy.h"
1133 +
1134 +/* All code below is for non single-chip solutions */
1135 +
1136 +/**
1137 + * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
1138 + * @rfbuf:
1139 + * @reg32:
1140 + * @numBits:
1141 + * @firstBit:
1142 + * @column:
1143 + *
1144 + * Performs analog "swizzling" of parameters into their location.
1145 + * Used on external AR2133/AR5133 radios.
1146 + */
1147 +static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
1148 + u32 numBits, u32 firstBit,
1149 + u32 column)
1150 +{
1151 + u32 tmp32, mask, arrayEntry, lastBit;
1152 + int32_t bitPosition, bitsLeft;
1153 +
1154 + tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
1155 + arrayEntry = (firstBit - 1) / 8;
1156 + bitPosition = (firstBit - 1) % 8;
1157 + bitsLeft = numBits;
1158 + while (bitsLeft > 0) {
1159 + lastBit = (bitPosition + bitsLeft > 8) ?
1160 + 8 : bitPosition + bitsLeft;
1161 + mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
1162 + (column * 8);
1163 + rfBuf[arrayEntry] &= ~mask;
1164 + rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
1165 + (column * 8)) & mask;
1166 + bitsLeft -= 8 - bitPosition;
1167 + tmp32 = tmp32 >> (8 - bitPosition);
1168 + bitPosition = 0;
1169 + arrayEntry++;
1170 + }
1171 +}
1172 +
1173 +/*
1174 + * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
1175 + * rf_pwd_icsyndiv.
1176 + *
1177 + * Theoretical Rules:
1178 + * if 2 GHz band
1179 + * if forceBiasAuto
1180 + * if synth_freq < 2412
1181 + * bias = 0
1182 + * else if 2412 <= synth_freq <= 2422
1183 + * bias = 1
1184 + * else // synth_freq > 2422
1185 + * bias = 2
1186 + * else if forceBias > 0
1187 + * bias = forceBias & 7
1188 + * else
1189 + * no change, use value from ini file
1190 + * else
1191 + * no change, invalid band
1192 + *
1193 + * 1st Mod:
1194 + * 2422 also uses value of 2
1195 + * <approved>
1196 + *
1197 + * 2nd Mod:
1198 + * Less than 2412 uses value of 0, 2412 and above uses value of 2
1199 + */
1200 +static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
1201 +{
1202 + struct ath_common *common = ath9k_hw_common(ah);
1203 + u32 tmp_reg;
1204 + int reg_writes = 0;
1205 + u32 new_bias = 0;
1206 +
1207 + if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
1208 + return;
1209 + }
1210 +
1211 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1212 +
1213 + if (synth_freq < 2412)
1214 + new_bias = 0;
1215 + else if (synth_freq < 2422)
1216 + new_bias = 1;
1217 + else
1218 + new_bias = 2;
1219 +
1220 + /* pre-reverse this field */
1221 + tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
1222 +
1223 + ath_print(common, ATH_DBG_CONFIG,
1224 + "Force rf_pwd_icsyndiv to %1d on %4d\n",
1225 + new_bias, synth_freq);
1226 +
1227 + /* swizzle rf_pwd_icsyndiv */
1228 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
1229 +
1230 + /* write Bank 6 with new params */
1231 + REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
1232 +}
1233 +
1234 +/**
1235 + * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
1236 + * @ah: atheros hardware stucture
1237 + * @chan:
1238 + *
1239 + * For the external AR2133/AR5133 radios, takes the MHz channel value and set
1240 + * the channel value. Assumes writes enabled to analog bus and bank6 register
1241 + * cache in ah->analogBank6Data.
1242 + */
1243 +static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
1244 +{
1245 + struct ath_common *common = ath9k_hw_common(ah);
1246 + u32 channelSel = 0;
1247 + u32 bModeSynth = 0;
1248 + u32 aModeRefSel = 0;
1249 + u32 reg32 = 0;
1250 + u16 freq;
1251 + struct chan_centers centers;
1252 +
1253 + ath9k_hw_get_channel_centers(ah, chan, &centers);
1254 + freq = centers.synth_center;
1255 +
1256 + if (freq < 4800) {
1257 + u32 txctl;
1258 +
1259 + if (((freq - 2192) % 5) == 0) {
1260 + channelSel = ((freq - 672) * 2 - 3040) / 10;
1261 + bModeSynth = 0;
1262 + } else if (((freq - 2224) % 5) == 0) {
1263 + channelSel = ((freq - 704) * 2 - 3040) / 10;
1264 + bModeSynth = 1;
1265 + } else {
1266 + ath_print(common, ATH_DBG_FATAL,
1267 + "Invalid channel %u MHz\n", freq);
1268 + return -EINVAL;
1269 + }
1270 +
1271 + channelSel = (channelSel << 2) & 0xff;
1272 + channelSel = ath9k_hw_reverse_bits(channelSel, 8);
1273 +
1274 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
1275 + if (freq == 2484) {
1276 +
1277 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1278 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
1279 + } else {
1280 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
1281 + txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
1282 + }
1283 +
1284 + } else if ((freq % 20) == 0 && freq >= 5120) {
1285 + channelSel =
1286 + ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
1287 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1288 + } else if ((freq % 10) == 0) {
1289 + channelSel =
1290 + ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
1291 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1292 + aModeRefSel = ath9k_hw_reverse_bits(2, 2);
1293 + else
1294 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1295 + } else if ((freq % 5) == 0) {
1296 + channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
1297 + aModeRefSel = ath9k_hw_reverse_bits(1, 2);
1298 + } else {
1299 + ath_print(common, ATH_DBG_FATAL,
1300 + "Invalid channel %u MHz\n", freq);
1301 + return -EINVAL;
1302 + }
1303 +
1304 + ar5008_hw_force_bias(ah, freq);
1305 +
1306 + reg32 =
1307 + (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
1308 + (1 << 5) | 0x1;
1309 +
1310 + REG_WRITE(ah, AR_PHY(0x37), reg32);
1311 +
1312 + ah->curchan = chan;
1313 + ah->curchan_rad_index = -1;
1314 +
1315 + return 0;
1316 +}
1317 +
1318 +/**
1319 + * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
1320 + * @ah: atheros hardware structure
1321 + * @chan:
1322 + *
1323 + * For non single-chip solutions. Converts to baseband spur frequency given the
1324 + * input channel frequency and compute register settings below.
1325 + */
1326 +static void ar5008_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1327 +{
1328 + int bb_spur = AR_NO_SPUR;
1329 + int bin, cur_bin;
1330 + int spur_freq_sd;
1331 + int spur_delta_phase;
1332 + int denominator;
1333 + int upper, lower, cur_vit_mask;
1334 + int tmp, new;
1335 + int i;
1336 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1337 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1338 + };
1339 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1340 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1341 + };
1342 + int inc[4] = { 0, 100, 0, 0 };
1343 +
1344 + int8_t mask_m[123];
1345 + int8_t mask_p[123];
1346 + int8_t mask_amt;
1347 + int tmp_mask;
1348 + int cur_bb_spur;
1349 + bool is2GHz = IS_CHAN_2GHZ(chan);
1350 +
1351 + memset(&mask_m, 0, sizeof(int8_t) * 123);
1352 + memset(&mask_p, 0, sizeof(int8_t) * 123);
1353 +
1354 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1355 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1356 + if (AR_NO_SPUR == cur_bb_spur)
1357 + break;
1358 + cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1359 + if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1360 + bb_spur = cur_bb_spur;
1361 + break;
1362 + }
1363 + }
1364 +
1365 + if (AR_NO_SPUR == bb_spur)
1366 + return;
1367 +
1368 + bin = bb_spur * 32;
1369 +
1370 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1371 + new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1372 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1373 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1374 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1375 +
1376 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1377 +
1378 + new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1379 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1380 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1381 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1382 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1383 + REG_WRITE(ah, AR_PHY_SPUR_REG, new);
1384 +
1385 + spur_delta_phase = ((bb_spur * 524288) / 100) &
1386 + AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1387 +
1388 + denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
1389 + spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
1390 +
1391 + new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1392 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1393 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1394 + REG_WRITE(ah, AR_PHY_TIMING11, new);
1395 +
1396 + cur_bin = -6000;
1397 + upper = bin + 100;
1398 + lower = bin - 100;
1399 +
1400 + for (i = 0; i < 4; i++) {
1401 + int pilot_mask = 0;
1402 + int chan_mask = 0;
1403 + int bp = 0;
1404 + for (bp = 0; bp < 30; bp++) {
1405 + if ((cur_bin > lower) && (cur_bin < upper)) {
1406 + pilot_mask = pilot_mask | 0x1 << bp;
1407 + chan_mask = chan_mask | 0x1 << bp;
1408 + }
1409 + cur_bin += 100;
1410 + }
1411 + cur_bin += inc[i];
1412 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1413 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1414 + }
1415 +
1416 + cur_vit_mask = 6100;
1417 + upper = bin + 120;
1418 + lower = bin - 120;
1419 +
1420 + for (i = 0; i < 123; i++) {
1421 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1422 +
1423 + /* workaround for gcc bug #37014 */
1424 + volatile int tmp_v = abs(cur_vit_mask - bin);
1425 +
1426 + if (tmp_v < 75)
1427 + mask_amt = 1;
1428 + else
1429 + mask_amt = 0;
1430 + if (cur_vit_mask < 0)
1431 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1432 + else
1433 + mask_p[cur_vit_mask / 100] = mask_amt;
1434 + }
1435 + cur_vit_mask -= 100;
1436 + }
1437 +
1438 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1439 + | (mask_m[48] << 26) | (mask_m[49] << 24)
1440 + | (mask_m[50] << 22) | (mask_m[51] << 20)
1441 + | (mask_m[52] << 18) | (mask_m[53] << 16)
1442 + | (mask_m[54] << 14) | (mask_m[55] << 12)
1443 + | (mask_m[56] << 10) | (mask_m[57] << 8)
1444 + | (mask_m[58] << 6) | (mask_m[59] << 4)
1445 + | (mask_m[60] << 2) | (mask_m[61] << 0);
1446 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1447 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1448 +
1449 + tmp_mask = (mask_m[31] << 28)
1450 + | (mask_m[32] << 26) | (mask_m[33] << 24)
1451 + | (mask_m[34] << 22) | (mask_m[35] << 20)
1452 + | (mask_m[36] << 18) | (mask_m[37] << 16)
1453 + | (mask_m[48] << 14) | (mask_m[39] << 12)
1454 + | (mask_m[40] << 10) | (mask_m[41] << 8)
1455 + | (mask_m[42] << 6) | (mask_m[43] << 4)
1456 + | (mask_m[44] << 2) | (mask_m[45] << 0);
1457 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1458 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1459 +
1460 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1461 + | (mask_m[18] << 26) | (mask_m[18] << 24)
1462 + | (mask_m[20] << 22) | (mask_m[20] << 20)
1463 + | (mask_m[22] << 18) | (mask_m[22] << 16)
1464 + | (mask_m[24] << 14) | (mask_m[24] << 12)
1465 + | (mask_m[25] << 10) | (mask_m[26] << 8)
1466 + | (mask_m[27] << 6) | (mask_m[28] << 4)
1467 + | (mask_m[29] << 2) | (mask_m[30] << 0);
1468 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1469 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1470 +
1471 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1472 + | (mask_m[2] << 26) | (mask_m[3] << 24)
1473 + | (mask_m[4] << 22) | (mask_m[5] << 20)
1474 + | (mask_m[6] << 18) | (mask_m[7] << 16)
1475 + | (mask_m[8] << 14) | (mask_m[9] << 12)
1476 + | (mask_m[10] << 10) | (mask_m[11] << 8)
1477 + | (mask_m[12] << 6) | (mask_m[13] << 4)
1478 + | (mask_m[14] << 2) | (mask_m[15] << 0);
1479 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1480 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1481 +
1482 + tmp_mask = (mask_p[15] << 28)
1483 + | (mask_p[14] << 26) | (mask_p[13] << 24)
1484 + | (mask_p[12] << 22) | (mask_p[11] << 20)
1485 + | (mask_p[10] << 18) | (mask_p[9] << 16)
1486 + | (mask_p[8] << 14) | (mask_p[7] << 12)
1487 + | (mask_p[6] << 10) | (mask_p[5] << 8)
1488 + | (mask_p[4] << 6) | (mask_p[3] << 4)
1489 + | (mask_p[2] << 2) | (mask_p[1] << 0);
1490 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1491 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1492 +
1493 + tmp_mask = (mask_p[30] << 28)
1494 + | (mask_p[29] << 26) | (mask_p[28] << 24)
1495 + | (mask_p[27] << 22) | (mask_p[26] << 20)
1496 + | (mask_p[25] << 18) | (mask_p[24] << 16)
1497 + | (mask_p[23] << 14) | (mask_p[22] << 12)
1498 + | (mask_p[21] << 10) | (mask_p[20] << 8)
1499 + | (mask_p[19] << 6) | (mask_p[18] << 4)
1500 + | (mask_p[17] << 2) | (mask_p[16] << 0);
1501 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1502 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1503 +
1504 + tmp_mask = (mask_p[45] << 28)
1505 + | (mask_p[44] << 26) | (mask_p[43] << 24)
1506 + | (mask_p[42] << 22) | (mask_p[41] << 20)
1507 + | (mask_p[40] << 18) | (mask_p[39] << 16)
1508 + | (mask_p[38] << 14) | (mask_p[37] << 12)
1509 + | (mask_p[36] << 10) | (mask_p[35] << 8)
1510 + | (mask_p[34] << 6) | (mask_p[33] << 4)
1511 + | (mask_p[32] << 2) | (mask_p[31] << 0);
1512 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1513 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1514 +
1515 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1516 + | (mask_p[59] << 26) | (mask_p[58] << 24)
1517 + | (mask_p[57] << 22) | (mask_p[56] << 20)
1518 + | (mask_p[55] << 18) | (mask_p[54] << 16)
1519 + | (mask_p[53] << 14) | (mask_p[52] << 12)
1520 + | (mask_p[51] << 10) | (mask_p[50] << 8)
1521 + | (mask_p[49] << 6) | (mask_p[48] << 4)
1522 + | (mask_p[47] << 2) | (mask_p[46] << 0);
1523 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1524 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1525 +}
1526 +
1527 +/**
1528 + * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
1529 + * @ah: atheros hardware structure
1530 + *
1531 + * Only required for older devices with external AR2133/AR5133 radios.
1532 + */
1533 +static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
1534 +{
1535 +#define ATH_ALLOC_BANK(bank, size) do { \
1536 + bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
1537 + if (!bank) { \
1538 + ath_print(common, ATH_DBG_FATAL, \
1539 + "Cannot allocate RF banks\n"); \
1540 + return -ENOMEM; \
1541 + } \
1542 + } while (0);
1543 +
1544 + struct ath_common *common = ath9k_hw_common(ah);
1545 +
1546 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1547 +
1548 + ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
1549 + ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
1550 + ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
1551 + ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
1552 + ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
1553 + ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
1554 + ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
1555 + ATH_ALLOC_BANK(ah->addac5416_21,
1556 + ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
1557 + ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
1558 +
1559 + return 0;
1560 +#undef ATH_ALLOC_BANK
1561 +}
1562 +
1563 +
1564 +/**
1565 + * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
1566 + * @ah: atheros hardware struture
1567 + * For the external AR2133/AR5133 radios banks.
1568 + */
1569 +static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
1570 +{
1571 +#define ATH_FREE_BANK(bank) do { \
1572 + kfree(bank); \
1573 + bank = NULL; \
1574 + } while (0);
1575 +
1576 + BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
1577 +
1578 + ATH_FREE_BANK(ah->analogBank0Data);
1579 + ATH_FREE_BANK(ah->analogBank1Data);
1580 + ATH_FREE_BANK(ah->analogBank2Data);
1581 + ATH_FREE_BANK(ah->analogBank3Data);
1582 + ATH_FREE_BANK(ah->analogBank6Data);
1583 + ATH_FREE_BANK(ah->analogBank6TPCData);
1584 + ATH_FREE_BANK(ah->analogBank7Data);
1585 + ATH_FREE_BANK(ah->addac5416_21);
1586 + ATH_FREE_BANK(ah->bank6Temp);
1587 +
1588 +#undef ATH_FREE_BANK
1589 +}
1590 +
1591 +/* *
1592 + * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
1593 + * @ah: atheros hardware structure
1594 + * @chan:
1595 + * @modesIndex:
1596 + *
1597 + * Used for the external AR2133/AR5133 radios.
1598 + *
1599 + * Reads the EEPROM header info from the device structure and programs
1600 + * all rf registers. This routine requires access to the analog
1601 + * rf device. This is not required for single-chip devices.
1602 + */
1603 +static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
1604 + struct ath9k_channel *chan,
1605 + u16 modesIndex)
1606 +{
1607 + u32 eepMinorRev;
1608 + u32 ob5GHz = 0, db5GHz = 0;
1609 + u32 ob2GHz = 0, db2GHz = 0;
1610 + int regWrites = 0;
1611 +
1612 + /*
1613 + * Software does not need to program bank data
1614 + * for single chip devices, that is AR9280 or anything
1615 + * after that.
1616 + */
1617 + if (AR_SREV_9280_10_OR_LATER(ah))
1618 + return true;
1619 +
1620 + /* Setup rf parameters */
1621 + eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
1622 +
1623 + /* Setup Bank 0 Write */
1624 + RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
1625 +
1626 + /* Setup Bank 1 Write */
1627 + RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
1628 +
1629 + /* Setup Bank 2 Write */
1630 + RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
1631 +
1632 + /* Setup Bank 6 Write */
1633 + RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
1634 + modesIndex);
1635 + {
1636 + int i;
1637 + for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
1638 + ah->analogBank6Data[i] =
1639 + INI_RA(&ah->iniBank6TPC, i, modesIndex);
1640 + }
1641 + }
1642 +
1643 + /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
1644 + if (eepMinorRev >= 2) {
1645 + if (IS_CHAN_2GHZ(chan)) {
1646 + ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
1647 + db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
1648 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1649 + ob2GHz, 3, 197, 0);
1650 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1651 + db2GHz, 3, 194, 0);
1652 + } else {
1653 + ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
1654 + db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
1655 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1656 + ob5GHz, 3, 203, 0);
1657 + ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
1658 + db5GHz, 3, 200, 0);
1659 + }
1660 + }
1661 +
1662 + /* Setup Bank 7 Setup */
1663 + RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
1664 +
1665 + /* Write Analog registers */
1666 + REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
1667 + regWrites);
1668 + REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
1669 + regWrites);
1670 + REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
1671 + regWrites);
1672 + REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
1673 + regWrites);
1674 + REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
1675 + regWrites);
1676 + REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
1677 + regWrites);
1678 +
1679 + return true;
1680 +}
1681 +
1682 +static void ar5008_hw_init_bb(struct ath_hw *ah,
1683 + struct ath9k_channel *chan)
1684 +{
1685 + u32 synthDelay;
1686 +
1687 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1688 + if (IS_CHAN_B(chan))
1689 + synthDelay = (4 * synthDelay) / 22;
1690 + else
1691 + synthDelay /= 10;
1692 +
1693 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1694 +
1695 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
1696 +}
1697 +
1698 +static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
1699 +{
1700 + int rx_chainmask, tx_chainmask;
1701 +
1702 + rx_chainmask = ah->rxchainmask;
1703 + tx_chainmask = ah->txchainmask;
1704 +
1705 + switch (rx_chainmask) {
1706 + case 0x5:
1707 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1708 + AR_PHY_SWAP_ALT_CHAIN);
1709 + case 0x3:
1710 + if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1711 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1712 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1713 + break;
1714 + }
1715 + case 0x1:
1716 + case 0x2:
1717 + case 0x7:
1718 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1719 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1720 + break;
1721 + default:
1722 + break;
1723 + }
1724 +
1725 + REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1726 + if (tx_chainmask == 0x5) {
1727 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1728 + AR_PHY_SWAP_ALT_CHAIN);
1729 + }
1730 + if (AR_SREV_9100(ah))
1731 + REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1732 + REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1733 +}
1734 +
1735 +static void ar5008_hw_override_ini(struct ath_hw *ah,
1736 + struct ath9k_channel *chan)
1737 +{
1738 + u32 val;
1739 +
1740 + /*
1741 + * Set the RX_ABORT and RX_DIS and clear if off only after
1742 + * RXE is set for MAC. This prevents frames with corrupted
1743 + * descriptor status.
1744 + */
1745 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1746 +
1747 + if (AR_SREV_9280_10_OR_LATER(ah)) {
1748 + val = REG_READ(ah, AR_PCU_MISC_MODE2);
1749 +
1750 + if (!AR_SREV_9271(ah))
1751 + val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1752 +
1753 + if (AR_SREV_9287_10_OR_LATER(ah))
1754 + val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1755 +
1756 + REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1757 + }
1758 +
1759 + if (!AR_SREV_5416_20_OR_LATER(ah) ||
1760 + AR_SREV_9280_10_OR_LATER(ah))
1761 + return;
1762 + /*
1763 + * Disable BB clock gating
1764 + * Necessary to avoid issues on AR5416 2.0
1765 + */
1766 + REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1767 +
1768 + /*
1769 + * Disable RIFS search on some chips to avoid baseband
1770 + * hang issues.
1771 + */
1772 + if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1773 + val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1774 + val &= ~AR_PHY_RIFS_INIT_DELAY;
1775 + REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1776 + }
1777 +}
1778 +
1779 +static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
1780 + struct ath9k_channel *chan)
1781 +{
1782 + u32 phymode;
1783 + u32 enableDacFifo = 0;
1784 +
1785 + if (AR_SREV_9285_10_OR_LATER(ah))
1786 + enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1787 + AR_PHY_FC_ENABLE_DAC_FIFO);
1788 +
1789 + phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1790 + | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1791 +
1792 + if (IS_CHAN_HT40(chan)) {
1793 + phymode |= AR_PHY_FC_DYN2040_EN;
1794 +
1795 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1796 + (chan->chanmode == CHANNEL_G_HT40PLUS))
1797 + phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1798 +
1799 + }
1800 + REG_WRITE(ah, AR_PHY_TURBO, phymode);
1801 +
1802 + ath9k_hw_set11nmac2040(ah);
1803 +
1804 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1805 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1806 +}
1807 +
1808 +
1809 +static int ar5008_hw_process_ini(struct ath_hw *ah,
1810 + struct ath9k_channel *chan)
1811 +{
1812 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1813 + int i, regWrites = 0;
1814 + struct ieee80211_channel *channel = chan->chan;
1815 + u32 modesIndex, freqIndex;
1816 +
1817 + switch (chan->chanmode) {
1818 + case CHANNEL_A:
1819 + case CHANNEL_A_HT20:
1820 + modesIndex = 1;
1821 + freqIndex = 1;
1822 + break;
1823 + case CHANNEL_A_HT40PLUS:
1824 + case CHANNEL_A_HT40MINUS:
1825 + modesIndex = 2;
1826 + freqIndex = 1;
1827 + break;
1828 + case CHANNEL_G:
1829 + case CHANNEL_G_HT20:
1830 + case CHANNEL_B:
1831 + modesIndex = 4;
1832 + freqIndex = 2;
1833 + break;
1834 + case CHANNEL_G_HT40PLUS:
1835 + case CHANNEL_G_HT40MINUS:
1836 + modesIndex = 3;
1837 + freqIndex = 2;
1838 + break;
1839 +
1840 + default:
1841 + return -EINVAL;
1842 + }
1843 +
1844 + if (AR_SREV_9287_12_OR_LATER(ah)) {
1845 + /* Enable ASYNC FIFO */
1846 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1847 + AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1848 + REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1849 + REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1850 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1851 + REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1852 + AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1853 + }
1854 +
1855 + /* Set correct baseband to analog shift setting to access analog chips */
1856 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
1857 +
1858 + /* Write ADDAC shifts */
1859 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1860 + ah->eep_ops->set_addac(ah, chan);
1861 +
1862 + if (AR_SREV_5416_22_OR_LATER(ah)) {
1863 + REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1864 + } else {
1865 + struct ar5416IniArray temp;
1866 + u32 addacSize =
1867 + sizeof(u32) * ah->iniAddac.ia_rows *
1868 + ah->iniAddac.ia_columns;
1869 +
1870 + /* For AR5416 2.0/2.1 */
1871 + memcpy(ah->addac5416_21,
1872 + ah->iniAddac.ia_array, addacSize);
1873 +
1874 + /* override CLKDRV value at [row, column] = [31, 1] */
1875 + (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1876 +
1877 + temp.ia_array = ah->addac5416_21;
1878 + temp.ia_columns = ah->iniAddac.ia_columns;
1879 + temp.ia_rows = ah->iniAddac.ia_rows;
1880 + REG_WRITE_ARRAY(&temp, 1, regWrites);
1881 + }
1882 +
1883 + REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1884 +
1885 + for (i = 0; i < ah->iniModes.ia_rows; i++) {
1886 + u32 reg = INI_RA(&ah->iniModes, i, 0);
1887 + u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1888 +
1889 + if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1890 + val &= ~AR_AN_TOP2_PWDCLKIND;
1891 +
1892 + REG_WRITE(ah, reg, val);
1893 +
1894 + if (reg >= 0x7800 && reg < 0x78a0
1895 + && ah->config.analog_shiftreg) {
1896 + udelay(100);
1897 + }
1898 +
1899 + DO_DELAY(regWrites);
1900 + }
1901 +
1902 + if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1903 + REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1904 +
1905 + if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1906 + AR_SREV_9287_10_OR_LATER(ah))
1907 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1908 +
1909 + if (AR_SREV_9271_10(ah))
1910 + REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1911 + modesIndex, regWrites);
1912 +
1913 + /* Write common array parameters */
1914 + for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1915 + u32 reg = INI_RA(&ah->iniCommon, i, 0);
1916 + u32 val = INI_RA(&ah->iniCommon, i, 1);
1917 +
1918 + REG_WRITE(ah, reg, val);
1919 +
1920 + if (reg >= 0x7800 && reg < 0x78a0
1921 + && ah->config.analog_shiftreg) {
1922 + udelay(100);
1923 + }
1924 +
1925 + DO_DELAY(regWrites);
1926 + }
1927 +
1928 + if (AR_SREV_9271(ah)) {
1929 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1930 + REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1931 + modesIndex, regWrites);
1932 + else
1933 + REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1934 + modesIndex, regWrites);
1935 + }
1936 +
1937 + REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
1938 +
1939 + if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1940 + REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1941 + regWrites);
1942 + }
1943 +
1944 + ar5008_hw_override_ini(ah, chan);
1945 + ar5008_hw_set_channel_regs(ah, chan);
1946 + ar5008_hw_init_chain_masks(ah);
1947 + ath9k_olc_init(ah);
1948 +
1949 + /* Set TX power */
1950 + ah->eep_ops->set_txpower(ah, chan,
1951 + ath9k_regd_get_ctl(regulatory, chan),
1952 + channel->max_antenna_gain * 2,
1953 + channel->max_power * 2,
1954 + min((u32) MAX_RATE_POWER,
1955 + (u32) regulatory->power_limit));
1956 +
1957 + /* Write analog registers */
1958 + if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1959 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1960 + "ar5416SetRfRegs failed\n");
1961 + return -EIO;
1962 + }
1963 +
1964 + return 0;
1965 +}
1966 +
1967 +static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1968 +{
1969 + u32 rfMode = 0;
1970 +
1971 + if (chan == NULL)
1972 + return;
1973 +
1974 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1975 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1976 +
1977 + if (!AR_SREV_9280_10_OR_LATER(ah))
1978 + rfMode |= (IS_CHAN_5GHZ(chan)) ?
1979 + AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1980 +
1981 + if ((AR_SREV_9280_20(ah) || AR_SREV_9300_20_OR_LATER(ah))
1982 + && IS_CHAN_A_5MHZ_SPACED(chan))
1983 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1984 +
1985 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
1986 +}
1987 +
1988 +static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
1989 +{
1990 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1991 +}
1992 +
1993 +static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
1994 + struct ath9k_channel *chan)
1995 +{
1996 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
1997 + u32 clockMhzScaled = 0x64000000;
1998 + struct chan_centers centers;
1999 +
2000 + if (IS_CHAN_HALF_RATE(chan))
2001 + clockMhzScaled = clockMhzScaled >> 1;
2002 + else if (IS_CHAN_QUARTER_RATE(chan))
2003 + clockMhzScaled = clockMhzScaled >> 2;
2004 +
2005 + ath9k_hw_get_channel_centers(ah, chan, &centers);
2006 + coef_scaled = clockMhzScaled / centers.synth_center;
2007 +
2008 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
2009 + &ds_coef_exp);
2010 +
2011 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
2012 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
2013 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
2014 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
2015 +
2016 + coef_scaled = (9 * coef_scaled) / 10;
2017 +
2018 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
2019 + &ds_coef_exp);
2020 +
2021 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
2022 + AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
2023 + REG_RMW_FIELD(ah, AR_PHY_HALFGI,
2024 + AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
2025 +}
2026 +
2027 +static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
2028 +{
2029 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
2030 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
2031 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
2032 +}
2033 +
2034 +static void ar5008_hw_rfbus_done(struct ath_hw *ah)
2035 +{
2036 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
2037 + if (IS_CHAN_B(ah->curchan))
2038 + synthDelay = (4 * synthDelay) / 22;
2039 + else
2040 + synthDelay /= 10;
2041 +
2042 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
2043 +
2044 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
2045 +}
2046 +
2047 +static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
2048 +{
2049 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2050 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2051 +
2052 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2053 + AR_GPIO_INPUT_MUX2_RFSILENT);
2054 +
2055 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2056 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2057 +}
2058 +
2059 +static void ar5008_restore_chainmask(struct ath_hw *ah)
2060 +{
2061 + int rx_chainmask = ah->rxchainmask;
2062 +
2063 + if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2064 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2065 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2066 + }
2067 +}
2068 +
2069 +static void ar5008_set_diversity(struct ath_hw *ah, bool value)
2070 +{
2071 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
2072 + if (value)
2073 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
2074 + else
2075 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
2076 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
2077 +}
2078 +
2079 +static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
2080 + struct ath9k_channel *chan)
2081 +{
2082 + if (chan && IS_CHAN_5GHZ(chan))
2083 + return 0x1450;
2084 + return 0x1458;
2085 +}
2086 +
2087 +static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
2088 + struct ath9k_channel *chan)
2089 +{
2090 + u32 pll;
2091 +
2092 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
2093 +
2094 + if (chan && IS_CHAN_HALF_RATE(chan))
2095 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
2096 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
2097 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
2098 +
2099 + if (chan && IS_CHAN_5GHZ(chan))
2100 + pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
2101 + else
2102 + pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
2103 +
2104 + return pll;
2105 +}
2106 +
2107 +static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
2108 + struct ath9k_channel *chan)
2109 +{
2110 + u32 pll;
2111 +
2112 + pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
2113 +
2114 + if (chan && IS_CHAN_HALF_RATE(chan))
2115 + pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
2116 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
2117 + pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
2118 +
2119 + if (chan && IS_CHAN_5GHZ(chan))
2120 + pll |= SM(0xa, AR_RTC_PLL_DIV);
2121 + else
2122 + pll |= SM(0xb, AR_RTC_PLL_DIV);
2123 +
2124 + return pll;
2125 +}
2126 +
2127 +static bool ar5008_hw_ani_control(struct ath_hw *ah,
2128 + enum ath9k_ani_cmd cmd, int param)
2129 +{
2130 + struct ar5416AniState *aniState = ah->curani;
2131 + struct ath_common *common = ath9k_hw_common(ah);
2132 +
2133 + switch (cmd & ah->ani_function) {
2134 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2135 + u32 level = param;
2136 +
2137 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
2138 + ath_print(common, ATH_DBG_ANI,
2139 + "level out of range (%u > %u)\n",
2140 + level,
2141 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
2142 + return false;
2143 + }
2144 +
2145 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2146 + AR_PHY_DESIRED_SZ_TOT_DES,
2147 + ah->totalSizeDesired[level]);
2148 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2149 + AR_PHY_AGC_CTL1_COARSE_LOW,
2150 + ah->coarse_low[level]);
2151 + REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2152 + AR_PHY_AGC_CTL1_COARSE_HIGH,
2153 + ah->coarse_high[level]);
2154 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2155 + AR_PHY_FIND_SIG_FIRPWR,
2156 + ah->firpwr[level]);
2157 +
2158 + if (level > aniState->noiseImmunityLevel)
2159 + ah->stats.ast_ani_niup++;
2160 + else if (level < aniState->noiseImmunityLevel)
2161 + ah->stats.ast_ani_nidown++;
2162 + aniState->noiseImmunityLevel = level;
2163 + break;
2164 + }
2165 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2166 + const int m1ThreshLow[] = { 127, 50 };
2167 + const int m2ThreshLow[] = { 127, 40 };
2168 + const int m1Thresh[] = { 127, 0x4d };
2169 + const int m2Thresh[] = { 127, 0x40 };
2170 + const int m2CountThr[] = { 31, 16 };
2171 + const int m2CountThrLow[] = { 63, 48 };
2172 + u32 on = param ? 1 : 0;
2173 +
2174 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2175 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2176 + m1ThreshLow[on]);
2177 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2178 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2179 + m2ThreshLow[on]);
2180 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2181 + AR_PHY_SFCORR_M1_THRESH,
2182 + m1Thresh[on]);
2183 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2184 + AR_PHY_SFCORR_M2_THRESH,
2185 + m2Thresh[on]);
2186 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2187 + AR_PHY_SFCORR_M2COUNT_THR,
2188 + m2CountThr[on]);
2189 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2190 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2191 + m2CountThrLow[on]);
2192 +
2193 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2194 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2195 + m1ThreshLow[on]);
2196 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2197 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2198 + m2ThreshLow[on]);
2199 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2200 + AR_PHY_SFCORR_EXT_M1_THRESH,
2201 + m1Thresh[on]);
2202 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2203 + AR_PHY_SFCORR_EXT_M2_THRESH,
2204 + m2Thresh[on]);
2205 +
2206 + if (on)
2207 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2208 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2209 + else
2210 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2211 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2212 +
2213 + if (!on != aniState->ofdmWeakSigDetectOff) {
2214 + if (on)
2215 + ah->stats.ast_ani_ofdmon++;
2216 + else
2217 + ah->stats.ast_ani_ofdmoff++;
2218 + aniState->ofdmWeakSigDetectOff = !on;
2219 + }
2220 + break;
2221 + }
2222 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2223 + const int weakSigThrCck[] = { 8, 6 };
2224 + u32 high = param ? 1 : 0;
2225 +
2226 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2227 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2228 + weakSigThrCck[high]);
2229 + if (high != aniState->cckWeakSigThreshold) {
2230 + if (high)
2231 + ah->stats.ast_ani_cckhigh++;
2232 + else
2233 + ah->stats.ast_ani_ccklow++;
2234 + aniState->cckWeakSigThreshold = high;
2235 + }
2236 + break;
2237 + }
2238 + case ATH9K_ANI_FIRSTEP_LEVEL:{
2239 + const int firstep[] = { 0, 4, 8 };
2240 + u32 level = param;
2241 +
2242 + if (level >= ARRAY_SIZE(firstep)) {
2243 + ath_print(common, ATH_DBG_ANI,
2244 + "level out of range (%u > %u)\n",
2245 + level,
2246 + (unsigned) ARRAY_SIZE(firstep));
2247 + return false;
2248 + }
2249 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2250 + AR_PHY_FIND_SIG_FIRSTEP,
2251 + firstep[level]);
2252 + if (level > aniState->firstepLevel)
2253 + ah->stats.ast_ani_stepup++;
2254 + else if (level < aniState->firstepLevel)
2255 + ah->stats.ast_ani_stepdown++;
2256 + aniState->firstepLevel = level;
2257 + break;
2258 + }
2259 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2260 + const int cycpwrThr1[] =
2261 + { 2, 4, 6, 8, 10, 12, 14, 16 };
2262 + u32 level = param;
2263 +
2264 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
2265 + ath_print(common, ATH_DBG_ANI,
2266 + "level out of range (%u > %u)\n",
2267 + level,
2268 + (unsigned) ARRAY_SIZE(cycpwrThr1));
2269 + return false;
2270 + }
2271 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2272 + AR_PHY_TIMING5_CYCPWR_THR1,
2273 + cycpwrThr1[level]);
2274 + if (level > aniState->spurImmunityLevel)
2275 + ah->stats.ast_ani_spurup++;
2276 + else if (level < aniState->spurImmunityLevel)
2277 + ah->stats.ast_ani_spurdown++;
2278 + aniState->spurImmunityLevel = level;
2279 + break;
2280 + }
2281 + case ATH9K_ANI_PRESENT:
2282 + break;
2283 + default:
2284 + ath_print(common, ATH_DBG_ANI,
2285 + "invalid cmd %u\n", cmd);
2286 + return false;
2287 + }
2288 +
2289 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
2290 + ath_print(common, ATH_DBG_ANI,
2291 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2292 + "ofdmWeakSigDetectOff=%d\n",
2293 + aniState->noiseImmunityLevel,
2294 + aniState->spurImmunityLevel,
2295 + !aniState->ofdmWeakSigDetectOff);
2296 + ath_print(common, ATH_DBG_ANI,
2297 + "cckWeakSigThreshold=%d, "
2298 + "firstepLevel=%d, listenTime=%d\n",
2299 + aniState->cckWeakSigThreshold,
2300 + aniState->firstepLevel,
2301 + aniState->listenTime);
2302 + ath_print(common, ATH_DBG_ANI,
2303 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2304 + aniState->cycleCount,
2305 + aniState->ofdmPhyErrCount,
2306 + aniState->cckPhyErrCount);
2307 +
2308 + return true;
2309 +}
2310 +
2311 +static void ar5008_hw_do_getnf(struct ath_hw *ah,
2312 + int16_t nfarray[NUM_NF_READINGS])
2313 +{
2314 + struct ath_common *common = ath9k_hw_common(ah);
2315 + int16_t nf;
2316 +
2317 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
2318 + if (nf & 0x100)
2319 + nf = 0 - ((nf ^ 0x1ff) + 1);
2320 + ath_print(common, ATH_DBG_CALIBRATE,
2321 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
2322 + nfarray[0] = nf;
2323 +
2324 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
2325 + if (nf & 0x100)
2326 + nf = 0 - ((nf ^ 0x1ff) + 1);
2327 + ath_print(common, ATH_DBG_CALIBRATE,
2328 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
2329 + nfarray[1] = nf;
2330 +
2331 + nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
2332 + if (nf & 0x100)
2333 + nf = 0 - ((nf ^ 0x1ff) + 1);
2334 + ath_print(common, ATH_DBG_CALIBRATE,
2335 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
2336 + nfarray[2] = nf;
2337 +
2338 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
2339 + if (nf & 0x100)
2340 + nf = 0 - ((nf ^ 0x1ff) + 1);
2341 + ath_print(common, ATH_DBG_CALIBRATE,
2342 + "NF calibrated [ext] [chain 0] is %d\n", nf);
2343 + nfarray[3] = nf;
2344 +
2345 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
2346 + if (nf & 0x100)
2347 + nf = 0 - ((nf ^ 0x1ff) + 1);
2348 + ath_print(common, ATH_DBG_CALIBRATE,
2349 + "NF calibrated [ext] [chain 1] is %d\n", nf);
2350 + nfarray[4] = nf;
2351 +
2352 + nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
2353 + if (nf & 0x100)
2354 + nf = 0 - ((nf ^ 0x1ff) + 1);
2355 + ath_print(common, ATH_DBG_CALIBRATE,
2356 + "NF calibrated [ext] [chain 2] is %d\n", nf);
2357 + nfarray[5] = nf;
2358 +}
2359 +
2360 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
2361 +{
2362 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
2363 +
2364 + priv_ops->rf_set_freq = ar5008_hw_set_channel;
2365 + priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
2366 +
2367 + priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
2368 + priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
2369 + priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
2370 + priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
2371 + priv_ops->init_bb = ar5008_hw_init_bb;
2372 + priv_ops->process_ini = ar5008_hw_process_ini;
2373 + priv_ops->set_rfmode = ar5008_hw_set_rfmode;
2374 + priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
2375 + priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
2376 + priv_ops->rfbus_req = ar5008_hw_rfbus_req;
2377 + priv_ops->rfbus_done = ar5008_hw_rfbus_done;
2378 + priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
2379 + priv_ops->restore_chainmask = ar5008_restore_chainmask;
2380 + priv_ops->set_diversity = ar5008_set_diversity;
2381 + priv_ops->ani_control = ar5008_hw_ani_control;
2382 + priv_ops->do_getnf = ar5008_hw_do_getnf;
2383 +
2384 + if (AR_SREV_9100(ah))
2385 + priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
2386 + else if (AR_SREV_9160_10_OR_LATER(ah))
2387 + priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
2388 + else
2389 + priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
2390 +}
2391 --- /dev/null
2392 +++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
2393 @@ -0,0 +1,1314 @@
2394 +
2395 +static const u32 ar5416Common_9100[][2] = {
2396 + {0x0000000c, 0x00000000},
2397 + {0x00000030, 0x00020015},
2398 + {0x00000034, 0x00000005},
2399 + {0x00000040, 0x00000000},
2400 + {0x00000044, 0x00000008},
2401 + {0x00000048, 0x00000008},
2402 + {0x0000004c, 0x00000010},
2403 + {0x00000050, 0x00000000},
2404 + {0x00000054, 0x0000001f},
2405 + {0x00000800, 0x00000000},
2406 + {0x00000804, 0x00000000},
2407 + {0x00000808, 0x00000000},
2408 + {0x0000080c, 0x00000000},
2409 + {0x00000810, 0x00000000},
2410 + {0x00000814, 0x00000000},
2411 + {0x00000818, 0x00000000},
2412 + {0x0000081c, 0x00000000},
2413 + {0x00000820, 0x00000000},
2414 + {0x00000824, 0x00000000},
2415 + {0x00001040, 0x002ffc0f},
2416 + {0x00001044, 0x002ffc0f},
2417 + {0x00001048, 0x002ffc0f},
2418 + {0x0000104c, 0x002ffc0f},
2419 + {0x00001050, 0x002ffc0f},
2420 + {0x00001054, 0x002ffc0f},
2421 + {0x00001058, 0x002ffc0f},
2422 + {0x0000105c, 0x002ffc0f},
2423 + {0x00001060, 0x002ffc0f},
2424 + {0x00001064, 0x002ffc0f},
2425 + {0x00001230, 0x00000000},
2426 + {0x00001270, 0x00000000},
2427 + {0x00001038, 0x00000000},
2428 + {0x00001078, 0x00000000},
2429 + {0x000010b8, 0x00000000},
2430 + {0x000010f8, 0x00000000},
2431 + {0x00001138, 0x00000000},
2432 + {0x00001178, 0x00000000},
2433 + {0x000011b8, 0x00000000},
2434 + {0x000011f8, 0x00000000},
2435 + {0x00001238, 0x00000000},
2436 + {0x00001278, 0x00000000},
2437 + {0x000012b8, 0x00000000},
2438 + {0x000012f8, 0x00000000},
2439 + {0x00001338, 0x00000000},
2440 + {0x00001378, 0x00000000},
2441 + {0x000013b8, 0x00000000},
2442 + {0x000013f8, 0x00000000},
2443 + {0x00001438, 0x00000000},
2444 + {0x00001478, 0x00000000},
2445 + {0x000014b8, 0x00000000},
2446 + {0x000014f8, 0x00000000},
2447 + {0x00001538, 0x00000000},
2448 + {0x00001578, 0x00000000},
2449 + {0x000015b8, 0x00000000},
2450 + {0x000015f8, 0x00000000},
2451 + {0x00001638, 0x00000000},
2452 + {0x00001678, 0x00000000},
2453 + {0x000016b8, 0x00000000},
2454 + {0x000016f8, 0x00000000},
2455 + {0x00001738, 0x00000000},
2456 + {0x00001778, 0x00000000},
2457 + {0x000017b8, 0x00000000},
2458 + {0x000017f8, 0x00000000},
2459 + {0x0000103c, 0x00000000},
2460 + {0x0000107c, 0x00000000},
2461 + {0x000010bc, 0x00000000},
2462 + {0x000010fc, 0x00000000},
2463 + {0x0000113c, 0x00000000},
2464 + {0x0000117c, 0x00000000},
2465 + {0x000011bc, 0x00000000},
2466 + {0x000011fc, 0x00000000},
2467 + {0x0000123c, 0x00000000},
2468 + {0x0000127c, 0x00000000},
2469 + {0x000012bc, 0x00000000},
2470 + {0x000012fc, 0x00000000},
2471 + {0x0000133c, 0x00000000},
2472 + {0x0000137c, 0x00000000},
2473 + {0x000013bc, 0x00000000},
2474 + {0x000013fc, 0x00000000},
2475 + {0x0000143c, 0x00000000},
2476 + {0x0000147c, 0x00000000},
2477 + {0x00020010, 0x00000003},
2478 + {0x00020038, 0x000004c2},
2479 + {0x00008004, 0x00000000},
2480 + {0x00008008, 0x00000000},
2481 + {0x0000800c, 0x00000000},
2482 + {0x00008018, 0x00000700},
2483 + {0x00008020, 0x00000000},
2484 + {0x00008038, 0x00000000},
2485 + {0x0000803c, 0x00000000},
2486 + {0x00008048, 0x40000000},
2487 + {0x00008054, 0x00004000},
2488 + {0x00008058, 0x00000000},
2489 + {0x0000805c, 0x000fc78f},
2490 + {0x00008060, 0x0000000f},
2491 + {0x00008064, 0x00000000},
2492 + {0x000080c0, 0x2a82301a},
2493 + {0x000080c4, 0x05dc01e0},
2494 + {0x000080c8, 0x1f402710},
2495 + {0x000080cc, 0x01f40000},
2496 + {0x000080d0, 0x00001e00},
2497 + {0x000080d4, 0x00000000},
2498 + {0x000080d8, 0x00400000},
2499 + {0x000080e0, 0xffffffff},
2500 + {0x000080e4, 0x0000ffff},
2501 + {0x000080e8, 0x003f3f3f},
2502 + {0x000080ec, 0x00000000},
2503 + {0x000080f0, 0x00000000},
2504 + {0x000080f4, 0x00000000},
2505 + {0x000080f8, 0x00000000},
2506 + {0x000080fc, 0x00020000},
2507 + {0x00008100, 0x00020000},
2508 + {0x00008104, 0x00000001},
2509 + {0x00008108, 0x00000052},
2510 + {0x0000810c, 0x00000000},
2511 + {0x00008110, 0x00000168},
2512 + {0x00008118, 0x000100aa},
2513 + {0x0000811c, 0x00003210},
2514 + {0x00008120, 0x08f04800},
2515 + {0x00008124, 0x00000000},
2516 + {0x00008128, 0x00000000},
2517 + {0x0000812c, 0x00000000},
2518 + {0x00008130, 0x00000000},
2519 + {0x00008134, 0x00000000},
2520 + {0x00008138, 0x00000000},
2521 + {0x0000813c, 0x00000000},
2522 + {0x00008144, 0x00000000},
2523 + {0x00008168, 0x00000000},
2524 + {0x0000816c, 0x00000000},
2525 + {0x00008170, 0x32143320},
2526 + {0x00008174, 0xfaa4fa50},
2527 + {0x00008178, 0x00000100},
2528 + {0x0000817c, 0x00000000},
2529 + {0x000081c4, 0x00000000},
2530 + {0x000081d0, 0x00003210},
2531 + {0x000081ec, 0x00000000},
2532 + {0x000081f0, 0x00000000},
2533 + {0x000081f4, 0x00000000},
2534 + {0x000081f8, 0x00000000},
2535 + {0x000081fc, 0x00000000},
2536 + {0x00008200, 0x00000000},
2537 + {0x00008204, 0x00000000},
2538 + {0x00008208, 0x00000000},
2539 + {0x0000820c, 0x00000000},
2540 + {0x00008210, 0x00000000},
2541 + {0x00008214, 0x00000000},
2542 + {0x00008218, 0x00000000},
2543 + {0x0000821c, 0x00000000},
2544 + {0x00008220, 0x00000000},
2545 + {0x00008224, 0x00000000},
2546 + {0x00008228, 0x00000000},
2547 + {0x0000822c, 0x00000000},
2548 + {0x00008230, 0x00000000},
2549 + {0x00008234, 0x00000000},
2550 + {0x00008238, 0x00000000},
2551 + {0x0000823c, 0x00000000},
2552 + {0x00008240, 0x00100000},
2553 + {0x00008244, 0x0010f400},
2554 + {0x00008248, 0x00000100},
2555 + {0x0000824c, 0x0001e800},
2556 + {0x00008250, 0x00000000},
2557 + {0x00008254, 0x00000000},
2558 + {0x00008258, 0x00000000},
2559 + {0x0000825c, 0x400000ff},
2560 + {0x00008260, 0x00080922},
2561 + {0x00008270, 0x00000000},
2562 + {0x00008274, 0x40000000},
2563 + {0x00008278, 0x003e4180},
2564 + {0x0000827c, 0x00000000},
2565 + {0x00008284, 0x0000002c},
2566 + {0x00008288, 0x0000002c},
2567 + {0x0000828c, 0x00000000},
2568 + {0x00008294, 0x00000000},
2569 + {0x00008298, 0x00000000},
2570 + {0x00008300, 0x00000000},
2571 + {0x00008304, 0x00000000},
2572 + {0x00008308, 0x00000000},
2573 + {0x0000830c, 0x00000000},
2574 + {0x00008310, 0x00000000},
2575 + {0x00008314, 0x00000000},
2576 + {0x00008318, 0x00000000},
2577 + {0x00008328, 0x00000000},
2578 + {0x0000832c, 0x00000007},
2579 + {0x00008330, 0x00000302},
2580 + {0x00008334, 0x00000e00},
2581 + {0x00008338, 0x00000000},
2582 + {0x0000833c, 0x00000000},
2583 + {0x00008340, 0x000107ff},
2584 + {0x00009808, 0x00000000},
2585 + {0x0000980c, 0xad848e19},
2586 + {0x00009810, 0x7d14e000},
2587 + {0x00009814, 0x9c0a9f6b},
2588 + {0x0000981c, 0x00000000},
2589 + {0x0000982c, 0x0000a000},
2590 + {0x00009830, 0x00000000},
2591 + {0x0000983c, 0x00200400},
2592 + {0x00009840, 0x206a01ae},
2593 + {0x0000984c, 0x1284233c},
2594 + {0x00009854, 0x00000859},
2595 + {0x00009900, 0x00000000},
2596 + {0x00009904, 0x00000000},
2597 + {0x00009908, 0x00000000},
2598 + {0x0000990c, 0x00000000},
2599 + {0x0000991c, 0x10000fff},
2600 + {0x00009920, 0x05100000},
2601 + {0x0000a920, 0x05100000},
2602 + {0x0000b920, 0x05100000},
2603 + {0x00009928, 0x00000001},
2604 + {0x0000992c, 0x00000004},
2605 + {0x00009934, 0x1e1f2022},
2606 + {0x00009938, 0x0a0b0c0d},
2607 + {0x0000993c, 0x00000000},
2608 + {0x00009948, 0x9280b212},
2609 + {0x0000994c, 0x00020028},
2610 + {0x0000c95c, 0x004b6a8e},
2611 + {0x0000c968, 0x000003ce},
2612 + {0x00009970, 0x190fb515},
2613 + {0x00009974, 0x00000000},
2614 + {0x00009978, 0x00000001},
2615 + {0x0000997c, 0x00000000},
2616 + {0x00009980, 0x00000000},
2617 + {0x00009984, 0x00000000},
2618 + {0x00009988, 0x00000000},
2619 + {0x0000998c, 0x00000000},
2620 + {0x00009990, 0x00000000},
2621 + {0x00009994, 0x00000000},
2622 + {0x00009998, 0x00000000},
2623 + {0x0000999c, 0x00000000},
2624 + {0x000099a0, 0x00000000},
2625 + {0x000099a4, 0x00000001},
2626 + {0x000099a8, 0x201fff00},
2627 + {0x000099ac, 0x006f0000},
2628 + {0x000099b0, 0x03051000},
2629 + {0x000099dc, 0x00000000},
2630 + {0x000099e0, 0x00000200},
2631 + {0x000099e4, 0xaaaaaaaa},
2632 + {0x000099e8, 0x3c466478},
2633 + {0x000099ec, 0x0cc80caa},
2634 + {0x000099fc, 0x00001042},
2635 + {0x00009b00, 0x00000000},
2636 + {0x00009b04, 0x00000001},
2637 + {0x00009b08, 0x00000002},
2638 + {0x00009b0c, 0x00000003},
2639 + {0x00009b10, 0x00000004},
2640 + {0x00009b14, 0x00000005},
2641 + {0x00009b18, 0x00000008},
2642 + {0x00009b1c, 0x00000009},
2643 + {0x00009b20, 0x0000000a},
2644 + {0x00009b24, 0x0000000b},
2645 + {0x00009b28, 0x0000000c},
2646 + {0x00009b2c, 0x0000000d},
2647 + {0x00009b30, 0x00000010},
2648 + {0x00009b34, 0x00000011},
2649 + {0x00009b38, 0x00000012},
2650 + {0x00009b3c, 0x00000013},
2651 + {0x00009b40, 0x00000014},
2652 + {0x00009b44, 0x00000015},
2653 + {0x00009b48, 0x00000018},
2654 + {0x00009b4c, 0x00000019},
2655 + {0x00009b50, 0x0000001a},
2656 + {0x00009b54, 0x0000001b},
2657 + {0x00009b58, 0x0000001c},
2658 + {0x00009b5c, 0x0000001d},
2659 + {0x00009b60, 0x00000020},
2660 + {0x00009b64, 0x00000021},
2661 + {0x00009b68, 0x00000022},
2662 + {0x00009b6c, 0x00000023},
2663 + {0x00009b70, 0x00000024},
2664 + {0x00009b74, 0x00000025},
2665 + {0x00009b78, 0x00000028},
2666 + {0x00009b7c, 0x00000029},
2667 + {0x00009b80, 0x0000002a},
2668 + {0x00009b84, 0x0000002b},
2669 + {0x00009b88, 0x0000002c},
2670 + {0x00009b8c, 0x0000002d},
2671 + {0x00009b90, 0x00000030},
2672 + {0x00009b94, 0x00000031},
2673 + {0x00009b98, 0x00000032},
2674 + {0x00009b9c, 0x00000033},
2675 + {0x00009ba0, 0x00000034},
2676 + {0x00009ba4, 0x00000035},
2677 + {0x00009ba8, 0x00000035},
2678 + {0x00009bac, 0x00000035},
2679 + {0x00009bb0, 0x00000035},
2680 + {0x00009bb4, 0x00000035},
2681 + {0x00009bb8, 0x00000035},
2682 + {0x00009bbc, 0x00000035},
2683 + {0x00009bc0, 0x00000035},
2684 + {0x00009bc4, 0x00000035},
2685 + {0x00009bc8, 0x00000035},
2686 + {0x00009bcc, 0x00000035},
2687 + {0x00009bd0, 0x00000035},
2688 + {0x00009bd4, 0x00000035},
2689 + {0x00009bd8, 0x00000035},
2690 + {0x00009bdc, 0x00000035},
2691 + {0x00009be0, 0x00000035},
2692 + {0x00009be4, 0x00000035},
2693 + {0x00009be8, 0x00000035},
2694 + {0x00009bec, 0x00000035},
2695 + {0x00009bf0, 0x00000035},
2696 + {0x00009bf4, 0x00000035},
2697 + {0x00009bf8, 0x00000010},
2698 + {0x00009bfc, 0x0000001a},
2699 + {0x0000a210, 0x40806333},
2700 + {0x0000a214, 0x00106c10},
2701 + {0x0000a218, 0x009c4060},
2702 + {0x0000a220, 0x018830c6},
2703 + {0x0000a224, 0x00000400},
2704 + {0x0000a228, 0x001a0bb5},
2705 + {0x0000a22c, 0x00000000},
2706 + {0x0000a234, 0x20202020},
2707 + {0x0000a238, 0x20202020},
2708 + {0x0000a23c, 0x13c889ae},
2709 + {0x0000a240, 0x38490a20},
2710 + {0x0000a244, 0x00007bb6},
2711 + {0x0000a248, 0x0fff3ffc},
2712 + {0x0000a24c, 0x00000001},
2713 + {0x0000a250, 0x0000a000},
2714 + {0x0000a254, 0x00000000},
2715 + {0x0000a258, 0x0cc75380},
2716 + {0x0000a25c, 0x0f0f0f01},
2717 + {0x0000a260, 0xdfa91f01},
2718 + {0x0000a268, 0x00000001},
2719 + {0x0000a26c, 0x0ebae9c6},
2720 + {0x0000b26c, 0x0ebae9c6},
2721 + {0x0000c26c, 0x0ebae9c6},
2722 + {0x0000d270, 0x00820820},
2723 + {0x0000a278, 0x1ce739ce},
2724 + {0x0000a27c, 0x050701ce},
2725 + {0x0000a338, 0x00000000},
2726 + {0x0000a33c, 0x00000000},
2727 + {0x0000a340, 0x00000000},
2728 + {0x0000a344, 0x00000000},
2729 + {0x0000a348, 0x3fffffff},
2730 + {0x0000a34c, 0x3fffffff},
2731 + {0x0000a350, 0x3fffffff},
2732 + {0x0000a354, 0x0003ffff},
2733 + {0x0000a358, 0x79a8aa33},
2734 + {0x0000d35c, 0x07ffffef},
2735 + {0x0000d360, 0x0fffffe7},
2736 + {0x0000d364, 0x17ffffe5},
2737 + {0x0000d368, 0x1fffffe4},
2738 + {0x0000d36c, 0x37ffffe3},
2739 + {0x0000d370, 0x3fffffe3},
2740 + {0x0000d374, 0x57ffffe3},
2741 + {0x0000d378, 0x5fffffe2},
2742 + {0x0000d37c, 0x7fffffe2},
2743 + {0x0000d380, 0x7f3c7bba},
2744 + {0x0000d384, 0xf3307ff0},
2745 + {0x0000a388, 0x0c000000},
2746 + {0x0000a38c, 0x20202020},
2747 + {0x0000a390, 0x20202020},
2748 + {0x0000a394, 0x1ce739ce},
2749 + {0x0000a398, 0x000001ce},
2750 + {0x0000a39c, 0x00000001},
2751 + {0x0000a3a0, 0x00000000},
2752 + {0x0000a3a4, 0x00000000},
2753 + {0x0000a3a8, 0x00000000},
2754 + {0x0000a3ac, 0x00000000},
2755 + {0x0000a3b0, 0x00000000},
2756 + {0x0000a3b4, 0x00000000},
2757 + {0x0000a3b8, 0x00000000},
2758 + {0x0000a3bc, 0x00000000},
2759 + {0x0000a3c0, 0x00000000},
2760 + {0x0000a3c4, 0x00000000},
2761 + {0x0000a3c8, 0x00000246},
2762 + {0x0000a3cc, 0x20202020},
2763 + {0x0000a3d0, 0x20202020},
2764 + {0x0000a3d4, 0x20202020},
2765 + {0x0000a3dc, 0x1ce739ce},
2766 + {0x0000a3e0, 0x000001ce},
2767 +};
2768 +
2769 +static const u32 ar5416Bank0_9100[][2] = {
2770 + {0x000098b0, 0x1e5795e5},
2771 + {0x000098e0, 0x02008020},
2772 +};
2773 +
2774 +static const u32 ar5416BB_RfGain_9100[][3] = {
2775 + {0x00009a00, 0x00000000, 0x00000000},
2776 + {0x00009a04, 0x00000040, 0x00000040},
2777 + {0x00009a08, 0x00000080, 0x00000080},
2778 + {0x00009a0c, 0x000001a1, 0x00000141},
2779 + {0x00009a10, 0x000001e1, 0x00000181},
2780 + {0x00009a14, 0x00000021, 0x000001c1},
2781 + {0x00009a18, 0x00000061, 0x00000001},
2782 + {0x00009a1c, 0x00000168, 0x00000041},
2783 + {0x00009a20, 0x000001a8, 0x000001a8},
2784 + {0x00009a24, 0x000001e8, 0x000001e8},
2785 + {0x00009a28, 0x00000028, 0x00000028},
2786 + {0x00009a2c, 0x00000068, 0x00000068},
2787 + {0x00009a30, 0x00000189, 0x000000a8},
2788 + {0x00009a34, 0x000001c9, 0x00000169},
2789 + {0x00009a38, 0x00000009, 0x000001a9},
2790 + {0x00009a3c, 0x00000049, 0x000001e9},
2791 + {0x00009a40, 0x00000089, 0x00000029},
2792 + {0x00009a44, 0x00000170, 0x00000069},
2793 + {0x00009a48, 0x000001b0, 0x00000190},
2794 + {0x00009a4c, 0x000001f0, 0x000001d0},
2795 + {0x00009a50, 0x00000030, 0x00000010},
2796 + {0x00009a54, 0x00000070, 0x00000050},
2797 + {0x00009a58, 0x00000191, 0x00000090},
2798 + {0x00009a5c, 0x000001d1, 0x00000151},
2799 + {0x00009a60, 0x00000011, 0x00000191},
2800 + {0x00009a64, 0x00000051, 0x000001d1},
2801 + {0x00009a68, 0x00000091, 0x00000011},
2802 + {0x00009a6c, 0x000001b8, 0x00000051},
2803 + {0x00009a70, 0x000001f8, 0x00000198},
2804 + {0x00009a74, 0x00000038, 0x000001d8},
2805 + {0x00009a78, 0x00000078, 0x00000018},
2806 + {0x00009a7c, 0x00000199, 0x00000058},
2807 + {0x00009a80, 0x000001d9, 0x00000098},
2808 + {0x00009a84, 0x00000019, 0x00000159},
2809 + {0x00009a88, 0x00000059, 0x00000199},
2810 + {0x00009a8c, 0x00000099, 0x000001d9},
2811 + {0x00009a90, 0x000000d9, 0x00000019},
2812 + {0x00009a94, 0x000000f9, 0x00000059},
2813 + {0x00009a98, 0x000000f9, 0x00000099},
2814 + {0x00009a9c, 0x000000f9, 0x000000d9},
2815 + {0x00009aa0, 0x000000f9, 0x000000f9},
2816 + {0x00009aa4, 0x000000f9, 0x000000f9},
2817 + {0x00009aa8, 0x000000f9, 0x000000f9},
2818 + {0x00009aac, 0x000000f9, 0x000000f9},
2819 + {0x00009ab0, 0x000000f9, 0x000000f9},
2820 + {0x00009ab4, 0x000000f9, 0x000000f9},
2821 + {0x00009ab8, 0x000000f9, 0x000000f9},
2822 + {0x00009abc, 0x000000f9, 0x000000f9},
2823 + {0x00009ac0, 0x000000f9, 0x000000f9},
2824 + {0x00009ac4, 0x000000f9, 0x000000f9},
2825 + {0x00009ac8, 0x000000f9, 0x000000f9},
2826 + {0x00009acc, 0x000000f9, 0x000000f9},
2827 + {0x00009ad0, 0x000000f9, 0x000000f9},
2828 + {0x00009ad4, 0x000000f9, 0x000000f9},
2829 + {0x00009ad8, 0x000000f9, 0x000000f9},
2830 + {0x00009adc, 0x000000f9, 0x000000f9},
2831 + {0x00009ae0, 0x000000f9, 0x000000f9},
2832 + {0x00009ae4, 0x000000f9, 0x000000f9},
2833 + {0x00009ae8, 0x000000f9, 0x000000f9},
2834 + {0x00009aec, 0x000000f9, 0x000000f9},
2835 + {0x00009af0, 0x000000f9, 0x000000f9},
2836 + {0x00009af4, 0x000000f9, 0x000000f9},
2837 + {0x00009af8, 0x000000f9, 0x000000f9},
2838 + {0x00009afc, 0x000000f9, 0x000000f9},
2839 +};
2840 +
2841 +static const u32 ar5416Bank1_9100[][2] = {
2842 + {0x000098b0, 0x02108421},
2843 + {0x000098ec, 0x00000008},
2844 +};
2845 +
2846 +static const u32 ar5416Bank2_9100[][2] = {
2847 + {0x000098b0, 0x0e73ff17},
2848 + {0x000098e0, 0x00000420},
2849 +};
2850 +
2851 +static const u32 ar5416Bank3_9100[][3] = {
2852 + {0x000098f0, 0x01400018, 0x01c00018},
2853 +};
2854 +
2855 +static const u32 ar5416Bank6_9100[][3] = {
2856 +
2857 + {0x0000989c, 0x00000000, 0x00000000},
2858 + {0x0000989c, 0x00000000, 0x00000000},
2859 + {0x0000989c, 0x00000000, 0x00000000},
2860 + {0x0000989c, 0x00e00000, 0x00e00000},
2861 + {0x0000989c, 0x005e0000, 0x005e0000},
2862 + {0x0000989c, 0x00120000, 0x00120000},
2863 + {0x0000989c, 0x00620000, 0x00620000},
2864 + {0x0000989c, 0x00020000, 0x00020000},
2865 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2866 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2867 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2868 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2869 + {0x0000989c, 0x005f0000, 0x005f0000},
2870 + {0x0000989c, 0x00870000, 0x00870000},
2871 + {0x0000989c, 0x00f90000, 0x00f90000},
2872 + {0x0000989c, 0x007b0000, 0x007b0000},
2873 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2874 + {0x0000989c, 0x00f50000, 0x00f50000},
2875 + {0x0000989c, 0x00dc0000, 0x00dc0000},
2876 + {0x0000989c, 0x00110000, 0x00110000},
2877 + {0x0000989c, 0x006100a8, 0x006100a8},
2878 + {0x0000989c, 0x004210a2, 0x004210a2},
2879 + {0x0000989c, 0x0014000f, 0x0014000f},
2880 + {0x0000989c, 0x00c40002, 0x00c40002},
2881 + {0x0000989c, 0x003000f2, 0x003000f2},
2882 + {0x0000989c, 0x00440016, 0x00440016},
2883 + {0x0000989c, 0x00410040, 0x00410040},
2884 + {0x0000989c, 0x000180d6, 0x000180d6},
2885 + {0x0000989c, 0x0000c0aa, 0x0000c0aa},
2886 + {0x0000989c, 0x000000b1, 0x000000b1},
2887 + {0x0000989c, 0x00002000, 0x00002000},
2888 + {0x0000989c, 0x000000d4, 0x000000d4},
2889 + {0x000098d0, 0x0000000f, 0x0010000f},
2890 +};
2891 +
2892 +static const u32 ar5416Bank6TPC_9100[][3] = {
2893 +
2894 + {0x0000989c, 0x00000000, 0x00000000},
2895 + {0x0000989c, 0x00000000, 0x00000000},
2896 + {0x0000989c, 0x00000000, 0x00000000},
2897 + {0x0000989c, 0x00e00000, 0x00e00000},
2898 + {0x0000989c, 0x005e0000, 0x005e0000},
2899 + {0x0000989c, 0x00120000, 0x00120000},
2900 + {0x0000989c, 0x00620000, 0x00620000},
2901 + {0x0000989c, 0x00020000, 0x00020000},
2902 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2903 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2904 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2905 + {0x0000989c, 0x40ff0000, 0x40ff0000},
2906 + {0x0000989c, 0x005f0000, 0x005f0000},
2907 + {0x0000989c, 0x00870000, 0x00870000},
2908 + {0x0000989c, 0x00f90000, 0x00f90000},
2909 + {0x0000989c, 0x007b0000, 0x007b0000},
2910 + {0x0000989c, 0x00ff0000, 0x00ff0000},
2911 + {0x0000989c, 0x00f50000, 0x00f50000},
2912 + {0x0000989c, 0x00dc0000, 0x00dc0000},
2913 + {0x0000989c, 0x00110000, 0x00110000},
2914 + {0x0000989c, 0x006100a8, 0x006100a8},
2915 + {0x0000989c, 0x00423022, 0x00423022},
2916 + {0x0000989c, 0x2014008f, 0x2014008f},
2917 + {0x0000989c, 0x00c40002, 0x00c40002},
2918 + {0x0000989c, 0x003000f2, 0x003000f2},
2919 + {0x0000989c, 0x00440016, 0x00440016},
2920 + {0x0000989c, 0x00410040, 0x00410040},
2921 + {0x0000989c, 0x0001805e, 0x0001805e},
2922 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
2923 + {0x0000989c, 0x000000e1, 0x000000e1},
2924 + {0x0000989c, 0x00007080, 0x00007080},
2925 + {0x0000989c, 0x000000d4, 0x000000d4},
2926 + {0x000098d0, 0x0000000f, 0x0010000f},
2927 +};
2928 +
2929 +static const u32 ar5416Bank7_9100[][2] = {
2930 + {0x0000989c, 0x00000500},
2931 + {0x0000989c, 0x00000800},
2932 + {0x000098cc, 0x0000000e},
2933 +};
2934 +
2935 +static const u32 ar5416Addac_9100[][2] = {
2936 + {0x0000989c, 0x00000000},
2937 + {0x0000989c, 0x00000000},
2938 + {0x0000989c, 0x00000000},
2939 + {0x0000989c, 0x00000000},
2940 + {0x0000989c, 0x00000000},
2941 + {0x0000989c, 0x00000000},
2942 + {0x0000989c, 0x00000000},
2943 + {0x0000989c, 0x00000010},
2944 + {0x0000989c, 0x00000000},
2945 + {0x0000989c, 0x00000000},
2946 + {0x0000989c, 0x00000000},
2947 + {0x0000989c, 0x00000000},
2948 + {0x0000989c, 0x00000000},
2949 + {0x0000989c, 0x00000000},
2950 + {0x0000989c, 0x00000000},
2951 + {0x0000989c, 0x00000000},
2952 + {0x0000989c, 0x00000000},
2953 + {0x0000989c, 0x00000000},
2954 + {0x0000989c, 0x00000000},
2955 + {0x0000989c, 0x00000000},
2956 + {0x0000989c, 0x00000000},
2957 + {0x0000989c, 0x000000c0},
2958 + {0x0000989c, 0x00000015},
2959 + {0x0000989c, 0x00000000},
2960 + {0x0000989c, 0x00000000},
2961 + {0x0000989c, 0x00000000},
2962 + {0x0000989c, 0x00000000},
2963 + {0x0000989c, 0x00000000},
2964 + {0x0000989c, 0x00000000},
2965 + {0x0000989c, 0x00000000},
2966 + {0x0000989c, 0x00000000},
2967 + {0x000098cc, 0x00000000},
2968 +};
2969 +
2970 +static const u32 ar5416Modes_9160[][6] = {
2971 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
2972 + 0x000001e0},
2973 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
2974 + 0x000001e0},
2975 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
2976 + 0x00001180},
2977 + {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000,
2978 + 0x00014008},
2979 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
2980 + 0x06e006e0},
2981 + {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab,
2982 + 0x098813cf},
2983 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
2984 + 0x00000303},
2985 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
2986 + 0x02020200},
2987 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
2988 + 0x00000e0e},
2989 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
2990 + 0x0a020001},
2991 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
2992 + 0x00000e0e},
2993 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
2994 + 0x00000007},
2995 + {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0,
2996 + 0x037216a0},
2997 + {0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
2998 + 0x00197a68},
2999 + {0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
3000 + 0x00197a68},
3001 + {0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68,
3002 + 0x00197a68},
3003 + {0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2,
3004 + 0x6c48b0e2},
3005 + {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e,
3006 + 0x7ec82d2e},
3007 + {0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e,
3008 + 0x31395d5e},
3009 + {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20,
3010 + 0x00048d18},
3011 + {0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
3012 + 0x0001ce00},
3013 + {0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0,
3014 + 0x409a40d0},
3015 + {0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081,
3016 + 0x050cb081},
3017 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
3018 + 0x000007d0},
3019 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
3020 + 0x00000016},
3021 + {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d,
3022 + 0xd00a8a0d},
3023 + {0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020,
3024 + 0xffb81020},
3025 + {0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40,
3026 + 0x00009b40},
3027 + {0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40,
3028 + 0x00009b40},
3029 + {0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40,
3030 + 0x00009b40},
3031 + {0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120,
3032 + 0x00001120},
3033 + {0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce,
3034 + 0x000003ce},
3035 + {0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00,
3036 + 0x001a0c00},
3037 + {0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be,
3038 + 0x038919be},
3039 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
3040 + 0x06336f77},
3041 + {0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329,
3042 + 0x60f65329},
3043 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
3044 + 0x08f186c8},
3045 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
3046 + 0x00046384},
3047 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3048 + 0x00000000},
3049 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3050 + 0x00000000},
3051 + {0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880,
3052 + 0x00000880},
3053 + {0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788,
3054 + 0xd03e4788},
3055 + {0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
3056 + 0x002ac120},
3057 + {0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
3058 + 0x002ac120},
3059 + {0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120,
3060 + 0x002ac120},
3061 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
3062 + 0x1883800a},
3063 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
3064 + 0x00000000},
3065 + {0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa,
3066 + 0x0a1a7caa},
3067 + {0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000,
3068 + 0x18010000},
3069 + {0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402,
3070 + 0x2e032402},
3071 + {0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06,
3072 + 0x4a0a3c06},
3073 + {0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b,
3074 + 0x621a540b},
3075 + {0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b,
3076 + 0x764f6c1b},
3077 + {0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a,
3078 + 0x845b7a5a},
3079 + {0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf,
3080 + 0x950f8ccf},
3081 + {0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f,
3082 + 0xa5cf9b4f},
3083 + {0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f,
3084 + 0xbddfaf1f},
3085 + {0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f,
3086 + 0xd1ffc93f},
3087 + {0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000,
3088 + 0x00000000},
3089 + {0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3090 + 0x00000000},
3091 + {0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3092 + 0x00000000},
3093 + {0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
3094 + 0x00000000},
3095 +};
3096 +
3097 +static const u32 ar5416Common_9160[][2] = {
3098 + {0x0000000c, 0x00000000},
3099 + {0x00000030, 0x00020015},
3100 + {0x00000034, 0x00000005},
3101 + {0x00000040, 0x00000000},
3102 + {0x00000044, 0x00000008},
3103 + {0x00000048, 0x00000008},
3104 + {0x0000004c, 0x00000010},
3105 + {0x00000050, 0x00000000},
3106 + {0x00000054, 0x0000001f},
3107 + {0x00000800, 0x00000000},
3108 + {0x00000804, 0x00000000},
3109 + {0x00000808, 0x00000000},
3110 + {0x0000080c, 0x00000000},
3111 + {0x00000810, 0x00000000},
3112 + {0x00000814, 0x00000000},
3113 + {0x00000818, 0x00000000},
3114 + {0x0000081c, 0x00000000},
3115 + {0x00000820, 0x00000000},
3116 + {0x00000824, 0x00000000},
3117 + {0x00001040, 0x002ffc0f},
3118 + {0x00001044, 0x002ffc0f},
3119 + {0x00001048, 0x002ffc0f},
3120 + {0x0000104c, 0x002ffc0f},
3121 + {0x00001050, 0x002ffc0f},
3122 + {0x00001054, 0x002ffc0f},
3123 + {0x00001058, 0x002ffc0f},
3124 + {0x0000105c, 0x002ffc0f},
3125 + {0x00001060, 0x002ffc0f},
3126 + {0x00001064, 0x002ffc0f},
3127 + {0x00001230, 0x00000000},
3128 + {0x00001270, 0x00000000},
3129 + {0x00001038, 0x00000000},
3130 + {0x00001078, 0x00000000},
3131 + {0x000010b8, 0x00000000},
3132 + {0x000010f8, 0x00000000},
3133 + {0x00001138, 0x00000000},
3134 + {0x00001178, 0x00000000},
3135 + {0x000011b8, 0x00000000},
3136 + {0x000011f8, 0x00000000},
3137 + {0x00001238, 0x00000000},
3138 + {0x00001278, 0x00000000},
3139 + {0x000012b8, 0x00000000},
3140 + {0x000012f8, 0x00000000},
3141 + {0x00001338, 0x00000000},
3142 + {0x00001378, 0x00000000},
3143 + {0x000013b8, 0x00000000},
3144 + {0x000013f8, 0x00000000},
3145 + {0x00001438, 0x00000000},
3146 + {0x00001478, 0x00000000},
3147 + {0x000014b8, 0x00000000},
3148 + {0x000014f8, 0x00000000},
3149 + {0x00001538, 0x00000000},
3150 + {0x00001578, 0x00000000},
3151 + {0x000015b8, 0x00000000},
3152 + {0x000015f8, 0x00000000},
3153 + {0x00001638, 0x00000000},
3154 + {0x00001678, 0x00000000},
3155 + {0x000016b8, 0x00000000},
3156 + {0x000016f8, 0x00000000},
3157 + {0x00001738, 0x00000000},
3158 + {0x00001778, 0x00000000},
3159 + {0x000017b8, 0x00000000},
3160 + {0x000017f8, 0x00000000},
3161 + {0x0000103c, 0x00000000},
3162 + {0x0000107c, 0x00000000},
3163 + {0x000010bc, 0x00000000},
3164 + {0x000010fc, 0x00000000},
3165 + {0x0000113c, 0x00000000},
3166 + {0x0000117c, 0x00000000},
3167 + {0x000011bc, 0x00000000},
3168 + {0x000011fc, 0x00000000},
3169 + {0x0000123c, 0x00000000},
3170 + {0x0000127c, 0x00000000},
3171 + {0x000012bc, 0x00000000},
3172 + {0x000012fc, 0x00000000},
3173 + {0x0000133c, 0x00000000},
3174 + {0x0000137c, 0x00000000},
3175 + {0x000013bc, 0x00000000},
3176 + {0x000013fc, 0x00000000},
3177 + {0x0000143c, 0x00000000},
3178 + {0x0000147c, 0x00000000},
3179 + {0x00004030, 0x00000002},
3180 + {0x0000403c, 0x00000002},
3181 + {0x00007010, 0x00000020},
3182 + {0x00007038, 0x000004c2},
3183 + {0x00008004, 0x00000000},
3184 + {0x00008008, 0x00000000},
3185 + {0x0000800c, 0x00000000},
3186 + {0x00008018, 0x00000700},
3187 + {0x00008020, 0x00000000},
3188 + {0x00008038, 0x00000000},
3189 + {0x0000803c, 0x00000000},
3190 + {0x00008048, 0x40000000},
3191 + {0x00008054, 0x00000000},
3192 + {0x00008058, 0x00000000},
3193 + {0x0000805c, 0x000fc78f},
3194 + {0x00008060, 0x0000000f},
3195 + {0x00008064, 0x00000000},
3196 + {0x000080c0, 0x2a82301a},
3197 + {0x000080c4, 0x05dc01e0},
3198 + {0x000080c8, 0x1f402710},
3199 + {0x000080cc, 0x01f40000},
3200 + {0x000080d0, 0x00001e00},
3201 + {0x000080d4, 0x00000000},
3202 + {0x000080d8, 0x00400000},
3203 + {0x000080e0, 0xffffffff},
3204 + {0x000080e4, 0x0000ffff},
3205 + {0x000080e8, 0x003f3f3f},
3206 + {0x000080ec, 0x00000000},
3207 + {0x000080f0, 0x00000000},
3208 + {0x000080f4, 0x00000000},
3209 + {0x000080f8, 0x00000000},
3210 + {0x000080fc, 0x00020000},
3211 + {0x00008100, 0x00020000},
3212 + {0x00008104, 0x00000001},
3213 + {0x00008108, 0x00000052},
3214 + {0x0000810c, 0x00000000},
3215 + {0x00008110, 0x00000168},
3216 + {0x00008118, 0x000100aa},
3217 + {0x0000811c, 0x00003210},
3218 + {0x00008120, 0x08f04800},
3219 + {0x00008124, 0x00000000},
3220 + {0x00008128, 0x00000000},
3221 + {0x0000812c, 0x00000000},
3222 + {0x00008130, 0x00000000},
3223 + {0x00008134, 0x00000000},
3224 + {0x00008138, 0x00000000},
3225 + {0x0000813c, 0x00000000},
3226 + {0x00008144, 0xffffffff},
3227 + {0x00008168, 0x00000000},
3228 + {0x0000816c, 0x00000000},
3229 + {0x00008170, 0x32143320},
3230 + {0x00008174, 0xfaa4fa50},
3231 + {0x00008178, 0x00000100},
3232 + {0x0000817c, 0x00000000},
3233 + {0x000081c4, 0x00000000},
3234 + {0x000081d0, 0x00003210},
3235 + {0x000081ec, 0x00000000},
3236 + {0x000081f0, 0x00000000},
3237 + {0x000081f4, 0x00000000},
3238 + {0x000081f8, 0x00000000},
3239 + {0x000081fc, 0x00000000},
3240 + {0x00008200, 0x00000000},
3241 + {0x00008204, 0x00000000},
3242 + {0x00008208, 0x00000000},
3243 + {0x0000820c, 0x00000000},
3244 + {0x00008210, 0x00000000},
3245 + {0x00008214, 0x00000000},
3246 + {0x00008218, 0x00000000},
3247 + {0x0000821c, 0x00000000},
3248 + {0x00008220, 0x00000000},
3249 + {0x00008224, 0x00000000},
3250 + {0x00008228, 0x00000000},
3251 + {0x0000822c, 0x00000000},
3252 + {0x00008230, 0x00000000},
3253 + {0x00008234, 0x00000000},
3254 + {0x00008238, 0x00000000},
3255 + {0x0000823c, 0x00000000},
3256 + {0x00008240, 0x00100000},
3257 + {0x00008244, 0x0010f400},
3258 + {0x00008248, 0x00000100},
3259 + {0x0000824c, 0x0001e800},
3260 + {0x00008250, 0x00000000},
3261 + {0x00008254, 0x00000000},
3262 + {0x00008258, 0x00000000},
3263 + {0x0000825c, 0x400000ff},
3264 + {0x00008260, 0x00080922},
3265 + {0x00008270, 0x00000000},
3266 + {0x00008274, 0x40000000},
3267 + {0x00008278, 0x003e4180},
3268 + {0x0000827c, 0x00000000},
3269 + {0x00008284, 0x0000002c},
3270 + {0x00008288, 0x0000002c},
3271 + {0x0000828c, 0x00000000},
3272 + {0x00008294, 0x00000000},
3273 + {0x00008298, 0x00000000},
3274 + {0x00008300, 0x00000000},
3275 + {0x00008304, 0x00000000},
3276 + {0x00008308, 0x00000000},
3277 + {0x0000830c, 0x00000000},
3278 + {0x00008310, 0x00000000},
3279 + {0x00008314, 0x00000000},
3280 + {0x00008318, 0x00000000},
3281 + {0x00008328, 0x00000000},
3282 + {0x0000832c, 0x00000007},
3283 + {0x00008330, 0x00000302},
3284 + {0x00008334, 0x00000e00},
3285 + {0x00008338, 0x00ff0000},
3286 + {0x0000833c, 0x00000000},
3287 + {0x00008340, 0x000107ff},
3288 + {0x00009808, 0x00000000},
3289 + {0x0000980c, 0xad848e19},
3290 + {0x00009810, 0x7d14e000},
3291 + {0x00009814, 0x9c0a9f6b},
3292 + {0x0000981c, 0x00000000},
3293 + {0x0000982c, 0x0000a000},
3294 + {0x00009830, 0x00000000},
3295 + {0x0000983c, 0x00200400},
3296 + {0x00009840, 0x206a01ae},
3297 + {0x0000984c, 0x1284233c},
3298 + {0x00009854, 0x00000859},
3299 + {0x00009900, 0x00000000},
3300 + {0x00009904, 0x00000000},
3301 + {0x00009908, 0x00000000},
3302 + {0x0000990c, 0x00000000},
3303 + {0x0000991c, 0x10000fff},
3304 + {0x00009920, 0x05100000},
3305 + {0x0000a920, 0x05100000},
3306 + {0x0000b920, 0x05100000},
3307 + {0x00009928, 0x00000001},
3308 + {0x0000992c, 0x00000004},
3309 + {0x00009934, 0x1e1f2022},
3310 + {0x00009938, 0x0a0b0c0d},
3311 + {0x0000993c, 0x00000000},
3312 + {0x00009948, 0x9280b212},
3313 + {0x0000994c, 0x00020028},
3314 + {0x00009954, 0x5f3ca3de},
3315 + {0x00009958, 0x2108ecff},
3316 + {0x00009940, 0x00750604},
3317 + {0x0000c95c, 0x004b6a8e},
3318 + {0x00009970, 0x190fb515},
3319 + {0x00009974, 0x00000000},
3320 + {0x00009978, 0x00000001},
3321 + {0x0000997c, 0x00000000},
3322 + {0x00009980, 0x00000000},
3323 + {0x00009984, 0x00000000},
3324 + {0x00009988, 0x00000000},
3325 + {0x0000998c, 0x00000000},
3326 + {0x00009990, 0x00000000},
3327 + {0x00009994, 0x00000000},
3328 + {0x00009998, 0x00000000},
3329 + {0x0000999c, 0x00000000},
3330 + {0x000099a0, 0x00000000},
3331 + {0x000099a4, 0x00000001},
3332 + {0x000099a8, 0x201fff00},
3333 + {0x000099ac, 0x006f0000},
3334 + {0x000099b0, 0x03051000},
3335 + {0x000099dc, 0x00000000},
3336 + {0x000099e0, 0x00000200},
3337 + {0x000099e4, 0xaaaaaaaa},
3338 + {0x000099e8, 0x3c466478},
3339 + {0x000099ec, 0x0cc80caa},
3340 + {0x000099fc, 0x00001042},
3341 + {0x00009b00, 0x00000000},
3342 + {0x00009b04, 0x00000001},
3343 + {0x00009b08, 0x00000002},
3344 + {0x00009b0c, 0x00000003},
3345 + {0x00009b10, 0x00000004},
3346 + {0x00009b14, 0x00000005},
3347 + {0x00009b18, 0x00000008},
3348 + {0x00009b1c, 0x00000009},
3349 + {0x00009b20, 0x0000000a},
3350 + {0x00009b24, 0x0000000b},
3351 + {0x00009b28, 0x0000000c},
3352 + {0x00009b2c, 0x0000000d},
3353 + {0x00009b30, 0x00000010},
3354 + {0x00009b34, 0x00000011},
3355 + {0x00009b38, 0x00000012},
3356 + {0x00009b3c, 0x00000013},
3357 + {0x00009b40, 0x00000014},
3358 + {0x00009b44, 0x00000015},
3359 + {0x00009b48, 0x00000018},
3360 + {0x00009b4c, 0x00000019},
3361 + {0x00009b50, 0x0000001a},
3362 + {0x00009b54, 0x0000001b},
3363 + {0x00009b58, 0x0000001c},
3364 + {0x00009b5c, 0x0000001d},
3365 + {0x00009b60, 0x00000020},
3366 + {0x00009b64, 0x00000021},
3367 + {0x00009b68, 0x00000022},
3368 + {0x00009b6c, 0x00000023},
3369 + {0x00009b70, 0x00000024},
3370 + {0x00009b74, 0x00000025},
3371 + {0x00009b78, 0x00000028},
3372 + {0x00009b7c, 0x00000029},
3373 + {0x00009b80, 0x0000002a},
3374 + {0x00009b84, 0x0000002b},
3375 + {0x00009b88, 0x0000002c},
3376 + {0x00009b8c, 0x0000002d},
3377 + {0x00009b90, 0x00000030},
3378 + {0x00009b94, 0x00000031},
3379 + {0x00009b98, 0x00000032},
3380 + {0x00009b9c, 0x00000033},
3381 + {0x00009ba0, 0x00000034},
3382 + {0x00009ba4, 0x00000035},
3383 + {0x00009ba8, 0x00000035},
3384 + {0x00009bac, 0x00000035},
3385 + {0x00009bb0, 0x00000035},
3386 + {0x00009bb4, 0x00000035},
3387 + {0x00009bb8, 0x00000035},
3388 + {0x00009bbc, 0x00000035},
3389 + {0x00009bc0, 0x00000035},
3390 + {0x00009bc4, 0x00000035},
3391 + {0x00009bc8, 0x00000035},
3392 + {0x00009bcc, 0x00000035},
3393 + {0x00009bd0, 0x00000035},
3394 + {0x00009bd4, 0x00000035},
3395 + {0x00009bd8, 0x00000035},
3396 + {0x00009bdc, 0x00000035},
3397 + {0x00009be0, 0x00000035},
3398 + {0x00009be4, 0x00000035},
3399 + {0x00009be8, 0x00000035},
3400 + {0x00009bec, 0x00000035},
3401 + {0x00009bf0, 0x00000035},
3402 + {0x00009bf4, 0x00000035},
3403 + {0x00009bf8, 0x00000010},
3404 + {0x00009bfc, 0x0000001a},
3405 + {0x0000a210, 0x40806333},
3406 + {0x0000a214, 0x00106c10},
3407 + {0x0000a218, 0x009c4060},
3408 + {0x0000a220, 0x018830c6},
3409 + {0x0000a224, 0x00000400},
3410 + {0x0000a228, 0x001a0bb5},
3411 + {0x0000a22c, 0x00000000},
3412 + {0x0000a234, 0x20202020},
3413 + {0x0000a238, 0x20202020},
3414 + {0x0000a23c, 0x13c889af},
3415 + {0x0000a240, 0x38490a20},
3416 + {0x0000a244, 0x00007bb6},
3417 + {0x0000a248, 0x0fff3ffc},
3418 + {0x0000a24c, 0x00000001},
3419 + {0x0000a250, 0x0000e000},
3420 + {0x0000a254, 0x00000000},
3421 + {0x0000a258, 0x0cc75380},
3422 + {0x0000a25c, 0x0f0f0f01},
3423 + {0x0000a260, 0xdfa91f01},
3424 + {0x0000a268, 0x00000001},
3425 + {0x0000a26c, 0x0ebae9c6},
3426 + {0x0000b26c, 0x0ebae9c6},
3427 + {0x0000c26c, 0x0ebae9c6},
3428 + {0x0000d270, 0x00820820},
3429 + {0x0000a278, 0x1ce739ce},
3430 + {0x0000a27c, 0x050701ce},
3431 + {0x0000a338, 0x00000000},
3432 + {0x0000a33c, 0x00000000},
3433 + {0x0000a340, 0x00000000},
3434 + {0x0000a344, 0x00000000},
3435 + {0x0000a348, 0x3fffffff},
3436 + {0x0000a34c, 0x3fffffff},
3437 + {0x0000a350, 0x3fffffff},
3438 + {0x0000a354, 0x0003ffff},
3439 + {0x0000a358, 0x79bfaa03},
3440 + {0x0000d35c, 0x07ffffef},
3441 + {0x0000d360, 0x0fffffe7},
3442 + {0x0000d364, 0x17ffffe5},
3443 + {0x0000d368, 0x1fffffe4},
3444 + {0x0000d36c, 0x37ffffe3},
3445 + {0x0000d370, 0x3fffffe3},
3446 + {0x0000d374, 0x57ffffe3},
3447 + {0x0000d378, 0x5fffffe2},
3448 + {0x0000d37c, 0x7fffffe2},
3449 + {0x0000d380, 0x7f3c7bba},
3450 + {0x0000d384, 0xf3307ff0},
3451 + {0x0000a388, 0x0c000000},
3452 + {0x0000a38c, 0x20202020},
3453 + {0x0000a390, 0x20202020},
3454 + {0x0000a394, 0x1ce739ce},
3455 + {0x0000a398, 0x000001ce},
3456 + {0x0000a39c, 0x00000001},
3457 + {0x0000a3a0, 0x00000000},
3458 + {0x0000a3a4, 0x00000000},
3459 + {0x0000a3a8, 0x00000000},
3460 + {0x0000a3ac, 0x00000000},
3461 + {0x0000a3b0, 0x00000000},
3462 + {0x0000a3b4, 0x00000000},
3463 + {0x0000a3b8, 0x00000000},
3464 + {0x0000a3bc, 0x00000000},
3465 + {0x0000a3c0, 0x00000000},
3466 + {0x0000a3c4, 0x00000000},
3467 + {0x0000a3c8, 0x00000246},
3468 + {0x0000a3cc, 0x20202020},
3469 + {0x0000a3d0, 0x20202020},
3470 + {0x0000a3d4, 0x20202020},
3471 + {0x0000a3dc, 0x1ce739ce},
3472 + {0x0000a3e0, 0x000001ce},
3473 +};
3474 +
3475 +static const u32 ar5416Bank0_9160[][2] = {
3476 + {0x000098b0, 0x1e5795e5},
3477 + {0x000098e0, 0x02008020},
3478 +};
3479 +
3480 +static const u32 ar5416BB_RfGain_9160[][3] = {
3481 + {0x00009a00, 0x00000000, 0x00000000},
3482 + {0x00009a04, 0x00000040, 0x00000040},
3483 + {0x00009a08, 0x00000080, 0x00000080},
3484 + {0x00009a0c, 0x000001a1, 0x00000141},
3485 + {0x00009a10, 0x000001e1, 0x00000181},
3486 + {0x00009a14, 0x00000021, 0x000001c1},
3487 + {0x00009a18, 0x00000061, 0x00000001},
3488 + {0x00009a1c, 0x00000168, 0x00000041},
3489 + {0x00009a20, 0x000001a8, 0x000001a8},
3490 + {0x00009a24, 0x000001e8, 0x000001e8},
3491 + {0x00009a28, 0x00000028, 0x00000028},
3492 + {0x00009a2c, 0x00000068, 0x00000068},
3493 + {0x00009a30, 0x00000189, 0x000000a8},
3494 + {0x00009a34, 0x000001c9, 0x00000169},
3495 + {0x00009a38, 0x00000009, 0x000001a9},
3496 + {0x00009a3c, 0x00000049, 0x000001e9},
3497 + {0x00009a40, 0x00000089, 0x00000029},
3498 + {0x00009a44, 0x00000170, 0x00000069},
3499 + {0x00009a48, 0x000001b0, 0x00000190},
3500 + {0x00009a4c, 0x000001f0, 0x000001d0},
3501 + {0x00009a50, 0x00000030, 0x00000010},
3502 + {0x00009a54, 0x00000070, 0x00000050},
3503 + {0x00009a58, 0x00000191, 0x00000090},
3504 + {0x00009a5c, 0x000001d1, 0x00000151},
3505 + {0x00009a60, 0x00000011, 0x00000191},
3506 + {0x00009a64, 0x00000051, 0x000001d1},
3507 + {0x00009a68, 0x00000091, 0x00000011},
3508 + {0x00009a6c, 0x000001b8, 0x00000051},
3509 + {0x00009a70, 0x000001f8, 0x00000198},
3510 + {0x00009a74, 0x00000038, 0x000001d8},
3511 + {0x00009a78, 0x00000078, 0x00000018},
3512 + {0x00009a7c, 0x00000199, 0x00000058},
3513 + {0x00009a80, 0x000001d9, 0x00000098},
3514 + {0x00009a84, 0x00000019, 0x00000159},
3515 + {0x00009a88, 0x00000059, 0x00000199},
3516 + {0x00009a8c, 0x00000099, 0x000001d9},
3517 + {0x00009a90, 0x000000d9, 0x00000019},
3518 + {0x00009a94, 0x000000f9, 0x00000059},
3519 + {0x00009a98, 0x000000f9, 0x00000099},
3520 + {0x00009a9c, 0x000000f9, 0x000000d9},
3521 + {0x00009aa0, 0x000000f9, 0x000000f9},
3522 + {0x00009aa4, 0x000000f9, 0x000000f9},
3523 + {0x00009aa8, 0x000000f9, 0x000000f9},
3524 + {0x00009aac, 0x000000f9, 0x000000f9},
3525 + {0x00009ab0, 0x000000f9, 0x000000f9},
3526 + {0x00009ab4, 0x000000f9, 0x000000f9},
3527 + {0x00009ab8, 0x000000f9, 0x000000f9},
3528 + {0x00009abc, 0x000000f9, 0x000000f9},
3529 + {0x00009ac0, 0x000000f9, 0x000000f9},
3530 + {0x00009ac4, 0x000000f9, 0x000000f9},
3531 + {0x00009ac8, 0x000000f9, 0x000000f9},
3532 + {0x00009acc, 0x000000f9, 0x000000f9},
3533 + {0x00009ad0, 0x000000f9, 0x000000f9},
3534 + {0x00009ad4, 0x000000f9, 0x000000f9},
3535 + {0x00009ad8, 0x000000f9, 0x000000f9},
3536 + {0x00009adc, 0x000000f9, 0x000000f9},
3537 + {0x00009ae0, 0x000000f9, 0x000000f9},
3538 + {0x00009ae4, 0x000000f9, 0x000000f9},
3539 + {0x00009ae8, 0x000000f9, 0x000000f9},
3540 + {0x00009aec, 0x000000f9, 0x000000f9},
3541 + {0x00009af0, 0x000000f9, 0x000000f9},
3542 + {0x00009af4, 0x000000f9, 0x000000f9},
3543 + {0x00009af8, 0x000000f9, 0x000000f9},
3544 + {0x00009afc, 0x000000f9, 0x000000f9},
3545 +};
3546 +
3547 +static const u32 ar5416Bank1_9160[][2] = {
3548 + {0x000098b0, 0x02108421},
3549 + {0x000098ec, 0x00000008},
3550 +};
3551 +
3552 +static const u32 ar5416Bank2_9160[][2] = {
3553 + {0x000098b0, 0x0e73ff17},
3554 + {0x000098e0, 0x00000420},
3555 +};
3556 +
3557 +static const u32 ar5416Bank3_9160[][3] = {
3558 + {0x000098f0, 0x01400018, 0x01c00018},
3559 +};
3560 +
3561 +static const u32 ar5416Bank6_9160[][3] = {
3562 + {0x0000989c, 0x00000000, 0x00000000},
3563 + {0x0000989c, 0x00000000, 0x00000000},
3564 + {0x0000989c, 0x00000000, 0x00000000},
3565 + {0x0000989c, 0x00e00000, 0x00e00000},
3566 + {0x0000989c, 0x005e0000, 0x005e0000},
3567 + {0x0000989c, 0x00120000, 0x00120000},
3568 + {0x0000989c, 0x00620000, 0x00620000},
3569 + {0x0000989c, 0x00020000, 0x00020000},
3570 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3571 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3572 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3573 + {0x0000989c, 0x40ff0000, 0x40ff0000},
3574 + {0x0000989c, 0x005f0000, 0x005f0000},
3575 + {0x0000989c, 0x00870000, 0x00870000},
3576 + {0x0000989c, 0x00f90000, 0x00f90000},
3577 + {0x0000989c, 0x007b0000, 0x007b0000},
3578 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3579 + {0x0000989c, 0x00f50000, 0x00f50000},
3580 + {0x0000989c, 0x00dc0000, 0x00dc0000},
3581 + {0x0000989c, 0x00110000, 0x00110000},
3582 + {0x0000989c, 0x006100a8, 0x006100a8},
3583 + {0x0000989c, 0x004210a2, 0x004210a2},
3584 + {0x0000989c, 0x0014008f, 0x0014008f},
3585 + {0x0000989c, 0x00c40003, 0x00c40003},
3586 + {0x0000989c, 0x003000f2, 0x003000f2},
3587 + {0x0000989c, 0x00440016, 0x00440016},
3588 + {0x0000989c, 0x00410040, 0x00410040},
3589 + {0x0000989c, 0x0001805e, 0x0001805e},
3590 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
3591 + {0x0000989c, 0x000000f1, 0x000000f1},
3592 + {0x0000989c, 0x00002081, 0x00002081},
3593 + {0x0000989c, 0x000000d4, 0x000000d4},
3594 + {0x000098d0, 0x0000000f, 0x0010000f},
3595 +};
3596 +
3597 +static const u32 ar5416Bank6TPC_9160[][3] = {
3598 + {0x0000989c, 0x00000000, 0x00000000},
3599 + {0x0000989c, 0x00000000, 0x00000000},
3600 + {0x0000989c, 0x00000000, 0x00000000},
3601 + {0x0000989c, 0x00e00000, 0x00e00000},
3602 + {0x0000989c, 0x005e0000, 0x005e0000},
3603 + {0x0000989c, 0x00120000, 0x00120000},
3604 + {0x0000989c, 0x00620000, 0x00620000},
3605 + {0x0000989c, 0x00020000, 0x00020000},
3606 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3607 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3608 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3609 + {0x0000989c, 0x40ff0000, 0x40ff0000},
3610 + {0x0000989c, 0x005f0000, 0x005f0000},
3611 + {0x0000989c, 0x00870000, 0x00870000},
3612 + {0x0000989c, 0x00f90000, 0x00f90000},
3613 + {0x0000989c, 0x007b0000, 0x007b0000},
3614 + {0x0000989c, 0x00ff0000, 0x00ff0000},
3615 + {0x0000989c, 0x00f50000, 0x00f50000},
3616 + {0x0000989c, 0x00dc0000, 0x00dc0000},
3617 + {0x0000989c, 0x00110000, 0x00110000},
3618 + {0x0000989c, 0x006100a8, 0x006100a8},
3619 + {0x0000989c, 0x00423022, 0x00423022},
3620 + {0x0000989c, 0x2014008f, 0x2014008f},
3621 + {0x0000989c, 0x00c40002, 0x00c40002},
3622 + {0x0000989c, 0x003000f2, 0x003000f2},
3623 + {0x0000989c, 0x00440016, 0x00440016},
3624 + {0x0000989c, 0x00410040, 0x00410040},
3625 + {0x0000989c, 0x0001805e, 0x0001805e},
3626 + {0x0000989c, 0x0000c0ab, 0x0000c0ab},
3627 + {0x0000989c, 0x000000e1, 0x000000e1},
3628 + {0x0000989c, 0x00007080, 0x00007080},
3629 + {0x0000989c, 0x000000d4, 0x000000d4},
3630 + {0x000098d0, 0x0000000f, 0x0010000f},
3631 +};
3632 +
3633 +static const u32 ar5416Bank7_9160[][2] = {
3634 + {0x0000989c, 0x00000500},
3635 + {0x0000989c, 0x00000800},
3636 + {0x000098cc, 0x0000000e},
3637 +};
3638 +
3639 +static u32 ar5416Addac_9160[][2] = {
3640 + {0x0000989c, 0x00000000},
3641 + {0x0000989c, 0x00000000},
3642 + {0x0000989c, 0x00000000},
3643 + {0x0000989c, 0x00000000},
3644 + {0x0000989c, 0x00000000},
3645 + {0x0000989c, 0x00000000},
3646 + {0x0000989c, 0x000000c0},
3647 + {0x0000989c, 0x00000018},
3648 + {0x0000989c, 0x00000004},
3649 + {0x0000989c, 0x00000000},
3650 + {0x0000989c, 0x00000000},
3651 + {0x0000989c, 0x00000000},
3652 + {0x0000989c, 0x00000000},
3653 + {0x0000989c, 0x00000000},
3654 + {0x0000989c, 0x00000000},
3655 + {0x0000989c, 0x00000000},
3656 + {0x0000989c, 0x00000000},
3657 + {0x0000989c, 0x00000000},
3658 + {0x0000989c, 0x00000000},
3659 + {0x0000989c, 0x00000000},
3660 + {0x0000989c, 0x00000000},
3661 + {0x0000989c, 0x000000c0},
3662 + {0x0000989c, 0x00000019},
3663 + {0x0000989c, 0x00000004},
3664 + {0x0000989c, 0x00000000},
3665 + {0x0000989c, 0x00000000},
3666 + {0x0000989c, 0x00000000},
3667 + {0x0000989c, 0x00000004},
3668 + {0x0000989c, 0x00000003},
3669 + {0x0000989c, 0x00000008},
3670 + {0x0000989c, 0x00000000},
3671 + {0x000098cc, 0x00000000},
3672 +};
3673 +
3674 +static u32 ar5416Addac_91601_1[][2] = {
3675 + {0x0000989c, 0x00000000},
3676 + {0x0000989c, 0x00000000},
3677 + {0x0000989c, 0x00000000},
3678 + {0x0000989c, 0x00000000},
3679 + {0x0000989c, 0x00000000},
3680 + {0x0000989c, 0x00000000},
3681 + {0x0000989c, 0x000000c0},
3682 + {0x0000989c, 0x00000018},
3683 + {0x0000989c, 0x00000004},
3684 + {0x0000989c, 0x00000000},
3685 + {0x0000989c, 0x00000000},
3686 + {0x0000989c, 0x00000000},
3687 + {0x0000989c, 0x00000000},
3688 + {0x0000989c, 0x00000000},
3689 + {0x0000989c, 0x00000000},
3690 + {0x0000989c, 0x00000000},
3691 + {0x0000989c, 0x00000000},
3692 + {0x0000989c, 0x00000000},
3693 + {0x0000989c, 0x00000000},
3694 + {0x0000989c, 0x00000000},
3695 + {0x0000989c, 0x00000000},
3696 + {0x0000989c, 0x000000c0},
3697 + {0x0000989c, 0x00000019},
3698 + {0x0000989c, 0x00000004},
3699 + {0x0000989c, 0x00000000},
3700 + {0x0000989c, 0x00000000},
3701 + {0x0000989c, 0x00000000},
3702 + {0x0000989c, 0x00000000},
3703 + {0x0000989c, 0x00000000},
3704 + {0x0000989c, 0x00000000},
3705 + {0x0000989c, 0x00000000},
3706 + {0x000098cc, 0x00000000},
3707 +};
3708 --- /dev/null
3709 +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
3710 @@ -0,0 +1,988 @@
3711 +/*
3712 + * Copyright (c) 2008-2010 Atheros Communications Inc.
3713 + *
3714 + * Permission to use, copy, modify, and/or distribute this software for any
3715 + * purpose with or without fee is hereby granted, provided that the above
3716 + * copyright notice and this permission notice appear in all copies.
3717 + *
3718 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
3719 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
3720 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
3721 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
3722 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
3723 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
3724 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
3725 + */
3726 +
3727 +#include "hw.h"
3728 +#include "hw-ops.h"
3729 +#include "ar9002_phy.h"
3730 +
3731 +#define AR9285_CLCAL_REDO_THRESH 1
3732 +
3733 +static void ar9002_hw_setup_calibration(struct ath_hw *ah,
3734 + struct ath9k_cal_list *currCal)
3735 +{
3736 + struct ath_common *common = ath9k_hw_common(ah);
3737 +
3738 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
3739 + AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
3740 + currCal->calData->calCountMax);
3741 +
3742 + switch (currCal->calData->calType) {
3743 + case IQ_MISMATCH_CAL:
3744 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
3745 + ath_print(common, ATH_DBG_CALIBRATE,
3746 + "starting IQ Mismatch Calibration\n");
3747 + break;
3748 + case ADC_GAIN_CAL:
3749 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
3750 + ath_print(common, ATH_DBG_CALIBRATE,
3751 + "starting ADC Gain Calibration\n");
3752 + break;
3753 + case ADC_DC_CAL:
3754 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
3755 + ath_print(common, ATH_DBG_CALIBRATE,
3756 + "starting ADC DC Calibration\n");
3757 + break;
3758 + case ADC_DC_INIT_CAL:
3759 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
3760 + ath_print(common, ATH_DBG_CALIBRATE,
3761 + "starting Init ADC DC Calibration\n");
3762 + break;
3763 + case TEMP_COMP_CAL:
3764 + break; /* Not supported */
3765 + }
3766 +
3767 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3768 + AR_PHY_TIMING_CTRL4_DO_CAL);
3769 +}
3770 +
3771 +static bool ar9002_hw_per_calibration(struct ath_hw *ah,
3772 + struct ath9k_channel *ichan,
3773 + u8 rxchainmask,
3774 + struct ath9k_cal_list *currCal)
3775 +{
3776 + bool iscaldone = false;
3777 +
3778 + if (currCal->calState == CAL_RUNNING) {
3779 + if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
3780 + AR_PHY_TIMING_CTRL4_DO_CAL)) {
3781 +
3782 + currCal->calData->calCollect(ah);
3783 + ah->cal_samples++;
3784 +
3785 + if (ah->cal_samples >= currCal->calData->calNumSamples) {
3786 + int i, numChains = 0;
3787 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3788 + if (rxchainmask & (1 << i))
3789 + numChains++;
3790 + }
3791 +
3792 + currCal->calData->calPostProc(ah, numChains);
3793 + ichan->CalValid |= currCal->calData->calType;
3794 + currCal->calState = CAL_DONE;
3795 + iscaldone = true;
3796 + } else {
3797 + ar9002_hw_setup_calibration(ah, currCal);
3798 + }
3799 + }
3800 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
3801 + ath9k_hw_reset_calibration(ah, currCal);
3802 + }
3803 +
3804 + return iscaldone;
3805 +}
3806 +
3807 +/* Assumes you are talking about the currently configured channel */
3808 +static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
3809 + enum ath9k_cal_types calType)
3810 +{
3811 + struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3812 +
3813 + switch (calType & ah->supp_cals) {
3814 + case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
3815 + return true;
3816 + case ADC_GAIN_CAL:
3817 + case ADC_DC_CAL:
3818 + if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
3819 + conf_is_ht20(conf)))
3820 + return true;
3821 + break;
3822 + }
3823 + return false;
3824 +}
3825 +
3826 +static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
3827 +{
3828 + int i;
3829 +
3830 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3831 + ah->totalPowerMeasI[i] +=
3832 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3833 + ah->totalPowerMeasQ[i] +=
3834 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3835 + ah->totalIqCorrMeas[i] +=
3836 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3837 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3838 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
3839 + ah->cal_samples, i, ah->totalPowerMeasI[i],
3840 + ah->totalPowerMeasQ[i],
3841 + ah->totalIqCorrMeas[i]);
3842 + }
3843 +}
3844 +
3845 +static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
3846 +{
3847 + int i;
3848 +
3849 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3850 + ah->totalAdcIOddPhase[i] +=
3851 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3852 + ah->totalAdcIEvenPhase[i] +=
3853 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3854 + ah->totalAdcQOddPhase[i] +=
3855 + REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3856 + ah->totalAdcQEvenPhase[i] +=
3857 + REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3858 +
3859 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3860 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3861 + "oddq=0x%08x; evenq=0x%08x;\n",
3862 + ah->cal_samples, i,
3863 + ah->totalAdcIOddPhase[i],
3864 + ah->totalAdcIEvenPhase[i],
3865 + ah->totalAdcQOddPhase[i],
3866 + ah->totalAdcQEvenPhase[i]);
3867 + }
3868 +}
3869 +
3870 +static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
3871 +{
3872 + int i;
3873 +
3874 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3875 + ah->totalAdcDcOffsetIOddPhase[i] +=
3876 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
3877 + ah->totalAdcDcOffsetIEvenPhase[i] +=
3878 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
3879 + ah->totalAdcDcOffsetQOddPhase[i] +=
3880 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
3881 + ah->totalAdcDcOffsetQEvenPhase[i] +=
3882 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
3883 +
3884 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
3885 + "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
3886 + "oddq=0x%08x; evenq=0x%08x;\n",
3887 + ah->cal_samples, i,
3888 + ah->totalAdcDcOffsetIOddPhase[i],
3889 + ah->totalAdcDcOffsetIEvenPhase[i],
3890 + ah->totalAdcDcOffsetQOddPhase[i],
3891 + ah->totalAdcDcOffsetQEvenPhase[i]);
3892 + }
3893 +}
3894 +
3895 +static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
3896 +{
3897 + struct ath_common *common = ath9k_hw_common(ah);
3898 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
3899 + u32 qCoffDenom, iCoffDenom;
3900 + int32_t qCoff, iCoff;
3901 + int iqCorrNeg, i;
3902 +
3903 + for (i = 0; i < numChains; i++) {
3904 + powerMeasI = ah->totalPowerMeasI[i];
3905 + powerMeasQ = ah->totalPowerMeasQ[i];
3906 + iqCorrMeas = ah->totalIqCorrMeas[i];
3907 +
3908 + ath_print(common, ATH_DBG_CALIBRATE,
3909 + "Starting IQ Cal and Correction for Chain %d\n",
3910 + i);
3911 +
3912 + ath_print(common, ATH_DBG_CALIBRATE,
3913 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
3914 + i, ah->totalIqCorrMeas[i]);
3915 +
3916 + iqCorrNeg = 0;
3917 +
3918 + if (iqCorrMeas > 0x80000000) {
3919 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
3920 + iqCorrNeg = 1;
3921 + }
3922 +
3923 + ath_print(common, ATH_DBG_CALIBRATE,
3924 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
3925 + ath_print(common, ATH_DBG_CALIBRATE,
3926 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
3927 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
3928 + iqCorrNeg);
3929 +
3930 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
3931 + qCoffDenom = powerMeasQ / 64;
3932 +
3933 + if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
3934 + (qCoffDenom != 0)) {
3935 + iCoff = iqCorrMeas / iCoffDenom;
3936 + qCoff = powerMeasI / qCoffDenom - 64;
3937 + ath_print(common, ATH_DBG_CALIBRATE,
3938 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
3939 + ath_print(common, ATH_DBG_CALIBRATE,
3940 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
3941 +
3942 + iCoff = iCoff & 0x3f;
3943 + ath_print(common, ATH_DBG_CALIBRATE,
3944 + "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
3945 + if (iqCorrNeg == 0x0)
3946 + iCoff = 0x40 - iCoff;
3947 +
3948 + if (qCoff > 15)
3949 + qCoff = 15;
3950 + else if (qCoff <= -16)
3951 + qCoff = 16;
3952 +
3953 + ath_print(common, ATH_DBG_CALIBRATE,
3954 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
3955 + i, iCoff, qCoff);
3956 +
3957 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3958 + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
3959 + iCoff);
3960 + REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
3961 + AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
3962 + qCoff);
3963 + ath_print(common, ATH_DBG_CALIBRATE,
3964 + "IQ Cal and Correction done for Chain %d\n",
3965 + i);
3966 + }
3967 + }
3968 +
3969 + REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
3970 + AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
3971 +}
3972 +
3973 +static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
3974 +{
3975 + struct ath_common *common = ath9k_hw_common(ah);
3976 + u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
3977 + u32 qGainMismatch, iGainMismatch, val, i;
3978 +
3979 + for (i = 0; i < numChains; i++) {
3980 + iOddMeasOffset = ah->totalAdcIOddPhase[i];
3981 + iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
3982 + qOddMeasOffset = ah->totalAdcQOddPhase[i];
3983 + qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
3984 +
3985 + ath_print(common, ATH_DBG_CALIBRATE,
3986 + "Starting ADC Gain Cal for Chain %d\n", i);
3987 +
3988 + ath_print(common, ATH_DBG_CALIBRATE,
3989 + "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
3990 + iOddMeasOffset);
3991 + ath_print(common, ATH_DBG_CALIBRATE,
3992 + "Chn %d pwr_meas_even_i = 0x%08x\n", i,
3993 + iEvenMeasOffset);
3994 + ath_print(common, ATH_DBG_CALIBRATE,
3995 + "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
3996 + qOddMeasOffset);
3997 + ath_print(common, ATH_DBG_CALIBRATE,
3998 + "Chn %d pwr_meas_even_q = 0x%08x\n", i,
3999 + qEvenMeasOffset);
4000 +
4001 + if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
4002 + iGainMismatch =
4003 + ((iEvenMeasOffset * 32) /
4004 + iOddMeasOffset) & 0x3f;
4005 + qGainMismatch =
4006 + ((qOddMeasOffset * 32) /
4007 + qEvenMeasOffset) & 0x3f;
4008 +
4009 + ath_print(common, ATH_DBG_CALIBRATE,
4010 + "Chn %d gain_mismatch_i = 0x%08x\n", i,
4011 + iGainMismatch);
4012 + ath_print(common, ATH_DBG_CALIBRATE,
4013 + "Chn %d gain_mismatch_q = 0x%08x\n", i,
4014 + qGainMismatch);
4015 +
4016 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
4017 + val &= 0xfffff000;
4018 + val |= (qGainMismatch) | (iGainMismatch << 6);
4019 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
4020 +
4021 + ath_print(common, ATH_DBG_CALIBRATE,
4022 + "ADC Gain Cal done for Chain %d\n", i);
4023 + }
4024 + }
4025 +
4026 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
4027 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
4028 + AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
4029 +}
4030 +
4031 +static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
4032 +{
4033 + struct ath_common *common = ath9k_hw_common(ah);
4034 + u32 iOddMeasOffset, iEvenMeasOffset, val, i;
4035 + int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
4036 + const struct ath9k_percal_data *calData =
4037 + ah->cal_list_curr->calData;
4038 + u32 numSamples =
4039 + (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
4040 +
4041 + for (i = 0; i < numChains; i++) {
4042 + iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
4043 + iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
4044 + qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
4045 + qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
4046 +
4047 + ath_print(common, ATH_DBG_CALIBRATE,
4048 + "Starting ADC DC Offset Cal for Chain %d\n", i);
4049 +
4050 + ath_print(common, ATH_DBG_CALIBRATE,
4051 + "Chn %d pwr_meas_odd_i = %d\n", i,
4052 + iOddMeasOffset);
4053 + ath_print(common, ATH_DBG_CALIBRATE,
4054 + "Chn %d pwr_meas_even_i = %d\n", i,
4055 + iEvenMeasOffset);
4056 + ath_print(common, ATH_DBG_CALIBRATE,
4057 + "Chn %d pwr_meas_odd_q = %d\n", i,
4058 + qOddMeasOffset);
4059 + ath_print(common, ATH_DBG_CALIBRATE,
4060 + "Chn %d pwr_meas_even_q = %d\n", i,
4061 + qEvenMeasOffset);
4062 +
4063 + iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
4064 + numSamples) & 0x1ff;
4065 + qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
4066 + numSamples) & 0x1ff;
4067 +
4068 + ath_print(common, ATH_DBG_CALIBRATE,
4069 + "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
4070 + iDcMismatch);
4071 + ath_print(common, ATH_DBG_CALIBRATE,
4072 + "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
4073 + qDcMismatch);
4074 +
4075 + val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
4076 + val &= 0xc0000fff;
4077 + val |= (qDcMismatch << 12) | (iDcMismatch << 21);
4078 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
4079 +
4080 + ath_print(common, ATH_DBG_CALIBRATE,
4081 + "ADC DC Offset Cal done for Chain %d\n", i);
4082 + }
4083 +
4084 + REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
4085 + REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
4086 + AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
4087 +}
4088 +
4089 +static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
4090 +{
4091 + u32 rddata;
4092 + int32_t delta, currPDADC, slope;
4093 +
4094 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
4095 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
4096 +
4097 + if (ah->initPDADC == 0 || currPDADC == 0) {
4098 + /*
4099 + * Zero value indicates that no frames have been transmitted yet,
4100 + * can't do temperature compensation until frames are transmitted.
4101 + */
4102 + return;
4103 + } else {
4104 + slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
4105 +
4106 + if (slope == 0) { /* to avoid divide by zero case */
4107 + delta = 0;
4108 + } else {
4109 + delta = ((currPDADC - ah->initPDADC)*4) / slope;
4110 + }
4111 + REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
4112 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
4113 + REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
4114 + AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
4115 + }
4116 +}
4117 +
4118 +static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
4119 +{
4120 + u32 rddata, i;
4121 + int delta, currPDADC, regval;
4122 +
4123 + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
4124 + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
4125 +
4126 + if (ah->initPDADC == 0 || currPDADC == 0)
4127 + return;
4128 +
4129 + if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
4130 + delta = (currPDADC - ah->initPDADC + 4) / 8;
4131 + else
4132 + delta = (currPDADC - ah->initPDADC + 5) / 10;
4133 +
4134 + if (delta != ah->PDADCdelta) {
4135 + ah->PDADCdelta = delta;
4136 + for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
4137 + regval = ah->originalGain[i] - delta;
4138 + if (regval < 0)
4139 + regval = 0;
4140 +
4141 + REG_RMW_FIELD(ah,
4142 + AR_PHY_TX_GAIN_TBL1 + i * 4,
4143 + AR_PHY_TX_GAIN, regval);
4144 + }
4145 + }
4146 +}
4147 +
4148 +static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4149 +{
4150 + u32 regVal;
4151 + unsigned int i;
4152 + u32 regList [][2] = {
4153 + { 0x786c, 0 },
4154 + { 0x7854, 0 },
4155 + { 0x7820, 0 },
4156 + { 0x7824, 0 },
4157 + { 0x7868, 0 },
4158 + { 0x783c, 0 },
4159 + { 0x7838, 0 } ,
4160 + { 0x7828, 0 } ,
4161 + };
4162 +
4163 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4164 + regList[i][1] = REG_READ(ah, regList[i][0]);
4165 +
4166 + regVal = REG_READ(ah, 0x7834);
4167 + regVal &= (~(0x1));
4168 + REG_WRITE(ah, 0x7834, regVal);
4169 + regVal = REG_READ(ah, 0x9808);
4170 + regVal |= (0x1 << 27);
4171 + REG_WRITE(ah, 0x9808, regVal);
4172 +
4173 + /* 786c,b23,1, pwddac=1 */
4174 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4175 + /* 7854, b5,1, pdrxtxbb=1 */
4176 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4177 + /* 7854, b7,1, pdv2i=1 */
4178 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4179 + /* 7854, b8,1, pddacinterface=1 */
4180 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4181 + /* 7824,b12,0, offcal=0 */
4182 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4183 + /* 7838, b1,0, pwddb=0 */
4184 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4185 + /* 7820,b11,0, enpacal=0 */
4186 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4187 + /* 7820,b25,1, pdpadrv1=0 */
4188 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4189 + /* 7820,b24,0, pdpadrv2=0 */
4190 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
4191 + /* 7820,b23,0, pdpaout=0 */
4192 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4193 + /* 783c,b14-16,7, padrvgn2tab_0=7 */
4194 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4195 + /*
4196 + * 7838,b29-31,0, padrvgn1tab_0=0
4197 + * does not matter since we turn it off
4198 + */
4199 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4200 +
4201 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
4202 +
4203 + /* Set:
4204 + * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
4205 + * txon=1,paon=1,oscon=1,synthon_force=1
4206 + */
4207 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4208 + udelay(30);
4209 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
4210 +
4211 + /* find off_6_1; */
4212 + for (i = 6; i > 0; i--) {
4213 + regVal = REG_READ(ah, 0x7834);
4214 + regVal |= (1 << (20 + i));
4215 + REG_WRITE(ah, 0x7834, regVal);
4216 + udelay(1);
4217 + //regVal = REG_READ(ah, 0x7834);
4218 + regVal &= (~(0x1 << (20 + i)));
4219 + regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
4220 + << (20 + i));
4221 + REG_WRITE(ah, 0x7834, regVal);
4222 + }
4223 +
4224 + regVal = (regVal >>20) & 0x7f;
4225 +
4226 + /* Update PA cal info */
4227 + if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
4228 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4229 + ah->pacal_info.max_skipcount =
4230 + 2 * ah->pacal_info.max_skipcount;
4231 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4232 + } else {
4233 + ah->pacal_info.max_skipcount = 1;
4234 + ah->pacal_info.skipcount = 0;
4235 + ah->pacal_info.prev_offset = regVal;
4236 + }
4237 +
4238 + regVal = REG_READ(ah, 0x7834);
4239 + regVal |= 0x1;
4240 + REG_WRITE(ah, 0x7834, regVal);
4241 + regVal = REG_READ(ah, 0x9808);
4242 + regVal &= (~(0x1 << 27));
4243 + REG_WRITE(ah, 0x9808, regVal);
4244 +
4245 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4246 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4247 +}
4248 +
4249 +static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4250 +{
4251 + struct ath_common *common = ath9k_hw_common(ah);
4252 + u32 regVal;
4253 + int i, offset, offs_6_1, offs_0;
4254 + u32 ccomp_org, reg_field;
4255 + u32 regList[][2] = {
4256 + { 0x786c, 0 },
4257 + { 0x7854, 0 },
4258 + { 0x7820, 0 },
4259 + { 0x7824, 0 },
4260 + { 0x7868, 0 },
4261 + { 0x783c, 0 },
4262 + { 0x7838, 0 },
4263 + };
4264 +
4265 + ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
4266 +
4267 + /* PA CAL is not needed for high power solution */
4268 + if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
4269 + AR5416_EEP_TXGAIN_HIGH_POWER)
4270 + return;
4271 +
4272 + if (AR_SREV_9285_11(ah)) {
4273 + REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
4274 + udelay(10);
4275 + }
4276 +
4277 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4278 + regList[i][1] = REG_READ(ah, regList[i][0]);
4279 +
4280 + regVal = REG_READ(ah, 0x7834);
4281 + regVal &= (~(0x1));
4282 + REG_WRITE(ah, 0x7834, regVal);
4283 + regVal = REG_READ(ah, 0x9808);
4284 + regVal |= (0x1 << 27);
4285 + REG_WRITE(ah, 0x9808, regVal);
4286 +
4287 + REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
4288 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
4289 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
4290 + REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
4291 + REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
4292 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
4293 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
4294 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
4295 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
4296 + REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
4297 + REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
4298 + REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
4299 + ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
4300 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
4301 +
4302 + REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
4303 + udelay(30);
4304 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
4305 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
4306 +
4307 + for (i = 6; i > 0; i--) {
4308 + regVal = REG_READ(ah, 0x7834);
4309 + regVal |= (1 << (19 + i));
4310 + REG_WRITE(ah, 0x7834, regVal);
4311 + udelay(1);
4312 + regVal = REG_READ(ah, 0x7834);
4313 + regVal &= (~(0x1 << (19 + i)));
4314 + reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
4315 + regVal |= (reg_field << (19 + i));
4316 + REG_WRITE(ah, 0x7834, regVal);
4317 + }
4318 +
4319 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
4320 + udelay(1);
4321 + reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
4322 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
4323 + offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
4324 + offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
4325 +
4326 + offset = (offs_6_1<<1) | offs_0;
4327 + offset = offset - 0;
4328 + offs_6_1 = offset>>1;
4329 + offs_0 = offset & 1;
4330 +
4331 + if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
4332 + if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
4333 + ah->pacal_info.max_skipcount =
4334 + 2 * ah->pacal_info.max_skipcount;
4335 + ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
4336 + } else {
4337 + ah->pacal_info.max_skipcount = 1;
4338 + ah->pacal_info.skipcount = 0;
4339 + ah->pacal_info.prev_offset = offset;
4340 + }
4341 +
4342 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
4343 + REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
4344 +
4345 + regVal = REG_READ(ah, 0x7834);
4346 + regVal |= 0x1;
4347 + REG_WRITE(ah, 0x7834, regVal);
4348 + regVal = REG_READ(ah, 0x9808);
4349 + regVal &= (~(0x1 << 27));
4350 + REG_WRITE(ah, 0x9808, regVal);
4351 +
4352 + for (i = 0; i < ARRAY_SIZE(regList); i++)
4353 + REG_WRITE(ah, regList[i][0], regList[i][1]);
4354 +
4355 + REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
4356 +
4357 + if (AR_SREV_9285_11(ah))
4358 + REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
4359 +
4360 +}
4361 +
4362 +static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
4363 +{
4364 + if (AR_SREV_9271(ah)) {
4365 + if (is_reset || !ah->pacal_info.skipcount)
4366 + ar9271_hw_pa_cal(ah, is_reset);
4367 + else
4368 + ah->pacal_info.skipcount--;
4369 + } else if (AR_SREV_9285_11_OR_LATER(ah)) {
4370 + if (is_reset || !ah->pacal_info.skipcount)
4371 + ar9285_hw_pa_cal(ah, is_reset);
4372 + else
4373 + ah->pacal_info.skipcount--;
4374 + }
4375 +}
4376 +
4377 +static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
4378 +{
4379 + if (OLC_FOR_AR9287_10_LATER)
4380 + ar9287_hw_olc_temp_compensation(ah);
4381 + else if (OLC_FOR_AR9280_20_LATER)
4382 + ar9280_hw_olc_temp_compensation(ah);
4383 +}
4384 +
4385 +static bool ar9002_hw_calibrate(struct ath_hw *ah,
4386 + struct ath9k_channel *chan,
4387 + u8 rxchainmask,
4388 + bool longcal)
4389 +{
4390 + bool iscaldone = true;
4391 + struct ath9k_cal_list *currCal = ah->cal_list_curr;
4392 +
4393 + if (currCal &&
4394 + (currCal->calState == CAL_RUNNING ||
4395 + currCal->calState == CAL_WAITING)) {
4396 + iscaldone = ar9002_hw_per_calibration(ah, chan,
4397 + rxchainmask, currCal);
4398 + if (iscaldone) {
4399 + ah->cal_list_curr = currCal = currCal->calNext;
4400 +
4401 + if (currCal->calState == CAL_WAITING) {
4402 + iscaldone = false;
4403 + ath9k_hw_reset_calibration(ah, currCal);
4404 + }
4405 + }
4406 + }
4407 +
4408 + /* Do NF cal only at longer intervals */
4409 + if (longcal) {
4410 + /* Do periodic PAOffset Cal */
4411 + ar9002_hw_pa_cal(ah, false);
4412 + ar9002_hw_olc_temp_compensation(ah);
4413 +
4414 + /* Get the value from the previous NF cal and update history buffer */
4415 + ath9k_hw_getnf(ah, chan);
4416 +
4417 + /*
4418 + * Load the NF from history buffer of the current channel.
4419 + * NF is slow time-variant, so it is OK to use a historical value.
4420 + */
4421 + ath9k_hw_loadnf(ah, ah->curchan);
4422 +
4423 + ath9k_hw_start_nfcal(ah);
4424 + }
4425 +
4426 + return iscaldone;
4427 +}
4428 +
4429 +/* Carrier leakage Calibration fix */
4430 +static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
4431 +{
4432 + struct ath_common *common = ath9k_hw_common(ah);
4433 +
4434 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4435 + if (IS_CHAN_HT20(chan)) {
4436 + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
4437 + REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
4438 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
4439 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4440 + REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
4441 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
4442 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
4443 + AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
4444 + ath_print(common, ATH_DBG_CALIBRATE, "offset "
4445 + "calibration failed to complete in "
4446 + "1ms; noisy ??\n");
4447 + return false;
4448 + }
4449 + REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
4450 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
4451 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4452 + }
4453 + REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
4454 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
4455 + REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
4456 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
4457 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
4458 + 0, AH_WAIT_TIMEOUT)) {
4459 + ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
4460 + "failed to complete in 1ms; noisy ??\n");
4461 + return false;
4462 + }
4463 +
4464 + REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
4465 + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
4466 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
4467 +
4468 + return true;
4469 +}
4470 +
4471 +static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
4472 +{
4473 + int i;
4474 + u_int32_t txgain_max;
4475 + u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
4476 + u_int32_t reg_clc_I0, reg_clc_Q0;
4477 + u_int32_t i0_num = 0;
4478 + u_int32_t q0_num = 0;
4479 + u_int32_t total_num = 0;
4480 + u_int32_t reg_rf2g5_org;
4481 + bool retv = true;
4482 +
4483 + if (!(ar9285_hw_cl_cal(ah, chan)))
4484 + return false;
4485 +
4486 + txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
4487 + AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
4488 +
4489 + for (i = 0; i < (txgain_max+1); i++) {
4490 + clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
4491 + AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
4492 + if (!(gain_mask & (1 << clc_gain))) {
4493 + gain_mask |= (1 << clc_gain);
4494 + clc_num++;
4495 + }
4496 + }
4497 +
4498 + for (i = 0; i < clc_num; i++) {
4499 + reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
4500 + & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
4501 + reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
4502 + & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
4503 + if (reg_clc_I0 == 0)
4504 + i0_num++;
4505 +
4506 + if (reg_clc_Q0 == 0)
4507 + q0_num++;
4508 + }
4509 + total_num = i0_num + q0_num;
4510 + if (total_num > AR9285_CLCAL_REDO_THRESH) {
4511 + reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
4512 + if (AR_SREV_9285E_20(ah)) {
4513 + REG_WRITE(ah, AR9285_RF2G5,
4514 + (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
4515 + AR9285_RF2G5_IC50TX_XE_SET);
4516 + } else {
4517 + REG_WRITE(ah, AR9285_RF2G5,
4518 + (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
4519 + AR9285_RF2G5_IC50TX_SET);
4520 + }
4521 + retv = ar9285_hw_cl_cal(ah, chan);
4522 + REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
4523 + }
4524 + return retv;
4525 +}
4526 +
4527 +static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
4528 +{
4529 + struct ath_common *common = ath9k_hw_common(ah);
4530 +
4531 + if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
4532 + if (!ar9285_hw_clc(ah, chan))
4533 + return false;
4534 + } else {
4535 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4536 + if (!AR_SREV_9287_10_OR_LATER(ah))
4537 + REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
4538 + AR_PHY_ADC_CTL_OFF_PWDADC);
4539 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
4540 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4541 + }
4542 +
4543 + /* Calibrate the AGC */
4544 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4545 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
4546 + AR_PHY_AGC_CONTROL_CAL);
4547 +
4548 + /* Poll for offset calibration complete */
4549 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
4550 + 0, AH_WAIT_TIMEOUT)) {
4551 + ath_print(common, ATH_DBG_CALIBRATE,
4552 + "offset calibration failed to "
4553 + "complete in 1ms; noisy environment?\n");
4554 + return false;
4555 + }
4556 +
4557 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4558 + if (!AR_SREV_9287_10_OR_LATER(ah))
4559 + REG_SET_BIT(ah, AR_PHY_ADC_CTL,
4560 + AR_PHY_ADC_CTL_OFF_PWDADC);
4561 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
4562 + AR_PHY_AGC_CONTROL_FLTR_CAL);
4563 + }
4564 + }
4565 +
4566 + /* Do PA Calibration */
4567 + ar9002_hw_pa_cal(ah, true);
4568 +
4569 + /* Do NF Calibration after DC offset and other calibrations */
4570 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
4571 + REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
4572 +
4573 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
4574 +
4575 + /* Enable IQ, ADC Gain and ADC DC offset CALs */
4576 + if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
4577 + if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
4578 + INIT_CAL(&ah->adcgain_caldata);
4579 + INSERT_CAL(ah, &ah->adcgain_caldata);
4580 + ath_print(common, ATH_DBG_CALIBRATE,
4581 + "enabling ADC Gain Calibration.\n");
4582 + }
4583 + if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
4584 + INIT_CAL(&ah->adcdc_caldata);
4585 + INSERT_CAL(ah, &ah->adcdc_caldata);
4586 + ath_print(common, ATH_DBG_CALIBRATE,
4587 + "enabling ADC DC Calibration.\n");
4588 + }
4589 + if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
4590 + INIT_CAL(&ah->iq_caldata);
4591 + INSERT_CAL(ah, &ah->iq_caldata);
4592 + ath_print(common, ATH_DBG_CALIBRATE,
4593 + "enabling IQ Calibration.\n");
4594 + }
4595 +
4596 + ah->cal_list_curr = ah->cal_list;
4597 +
4598 + if (ah->cal_list_curr)
4599 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
4600 + }
4601 +
4602 + chan->CalValid = 0;
4603 +
4604 + return true;
4605 +}
4606 +
4607 +static const struct ath9k_percal_data iq_cal_multi_sample = {
4608 + IQ_MISMATCH_CAL,
4609 + MAX_CAL_SAMPLES,
4610 + PER_MIN_LOG_COUNT,
4611 + ar9002_hw_iqcal_collect,
4612 + ar9002_hw_iqcalibrate
4613 +};
4614 +static const struct ath9k_percal_data iq_cal_single_sample = {
4615 + IQ_MISMATCH_CAL,
4616 + MIN_CAL_SAMPLES,
4617 + PER_MAX_LOG_COUNT,
4618 + ar9002_hw_iqcal_collect,
4619 + ar9002_hw_iqcalibrate
4620 +};
4621 +static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
4622 + ADC_GAIN_CAL,
4623 + MAX_CAL_SAMPLES,
4624 + PER_MIN_LOG_COUNT,
4625 + ar9002_hw_adc_gaincal_collect,
4626 + ar9002_hw_adc_gaincal_calibrate
4627 +};
4628 +static const struct ath9k_percal_data adc_gain_cal_single_sample = {
4629 + ADC_GAIN_CAL,
4630 + MIN_CAL_SAMPLES,
4631 + PER_MAX_LOG_COUNT,
4632 + ar9002_hw_adc_gaincal_collect,
4633 + ar9002_hw_adc_gaincal_calibrate
4634 +};
4635 +static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
4636 + ADC_DC_CAL,
4637 + MAX_CAL_SAMPLES,
4638 + PER_MIN_LOG_COUNT,
4639 + ar9002_hw_adc_dccal_collect,
4640 + ar9002_hw_adc_dccal_calibrate
4641 +};
4642 +static const struct ath9k_percal_data adc_dc_cal_single_sample = {
4643 + ADC_DC_CAL,
4644 + MIN_CAL_SAMPLES,
4645 + PER_MAX_LOG_COUNT,
4646 + ar9002_hw_adc_dccal_collect,
4647 + ar9002_hw_adc_dccal_calibrate
4648 +};
4649 +static const struct ath9k_percal_data adc_init_dc_cal = {
4650 + ADC_DC_INIT_CAL,
4651 + MIN_CAL_SAMPLES,
4652 + INIT_LOG_COUNT,
4653 + ar9002_hw_adc_dccal_collect,
4654 + ar9002_hw_adc_dccal_calibrate
4655 +};
4656 +
4657 +static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
4658 +{
4659 + if (AR_SREV_9100(ah)) {
4660 + ah->iq_caldata.calData = &iq_cal_multi_sample;
4661 + ah->supp_cals = IQ_MISMATCH_CAL;
4662 + return;
4663 + }
4664 +
4665 + if (AR_SREV_9160_10_OR_LATER(ah)) {
4666 + if (AR_SREV_9280_10_OR_LATER(ah)) {
4667 + ah->iq_caldata.calData = &iq_cal_single_sample;
4668 + ah->adcgain_caldata.calData =
4669 + &adc_gain_cal_single_sample;
4670 + ah->adcdc_caldata.calData =
4671 + &adc_dc_cal_single_sample;
4672 + ah->adcdc_calinitdata.calData =
4673 + &adc_init_dc_cal;
4674 + } else {
4675 + ah->iq_caldata.calData = &iq_cal_multi_sample;
4676 + ah->adcgain_caldata.calData =
4677 + &adc_gain_cal_multi_sample;
4678 + ah->adcdc_caldata.calData =
4679 + &adc_dc_cal_multi_sample;
4680 + ah->adcdc_calinitdata.calData =
4681 + &adc_init_dc_cal;
4682 + }
4683 + ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
4684 + }
4685 +}
4686 +
4687 +void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
4688 +{
4689 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
4690 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
4691 +
4692 + priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
4693 + priv_ops->init_cal = ar9002_hw_init_cal;
4694 + priv_ops->setup_calibration = ar9002_hw_setup_calibration;
4695 + priv_ops->iscal_supported = ar9002_hw_iscal_supported;
4696 +
4697 + ops->calibrate = ar9002_hw_calibrate;
4698 +}
4699 --- /dev/null
4700 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
4701 @@ -0,0 +1,584 @@
4702 +/*
4703 + * Copyright (c) 2008-2010 Atheros Communications Inc.
4704 + *
4705 + * Permission to use, copy, modify, and/or distribute this software for any
4706 + * purpose with or without fee is hereby granted, provided that the above
4707 + * copyright notice and this permission notice appear in all copies.
4708 + *
4709 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
4710 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
4711 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
4712 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
4713 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
4714 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
4715 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
4716 + */
4717 +
4718 +#include "hw.h"
4719 +#include "ar5008_initvals.h"
4720 +#include "ar9001_initvals.h"
4721 +#include "ar9002_initvals.h"
4722 +
4723 +/* General hardware code for the A5008/AR9001/AR9002 hadware families */
4724 +
4725 +static bool ar9002_hw_macversion_supported(u32 macversion)
4726 +{
4727 + switch (macversion) {
4728 + case AR_SREV_VERSION_5416_PCI:
4729 + case AR_SREV_VERSION_5416_PCIE:
4730 + case AR_SREV_VERSION_9160:
4731 + case AR_SREV_VERSION_9100:
4732 + case AR_SREV_VERSION_9280:
4733 + case AR_SREV_VERSION_9285:
4734 + case AR_SREV_VERSION_9287:
4735 + case AR_SREV_VERSION_9271:
4736 + return true;
4737 + default:
4738 + break;
4739 + }
4740 + return false;
4741 +}
4742 +
4743 +static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
4744 +{
4745 + if (AR_SREV_9271(ah)) {
4746 + INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
4747 + ARRAY_SIZE(ar9271Modes_9271), 6);
4748 + INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
4749 + ARRAY_SIZE(ar9271Common_9271), 2);
4750 + INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
4751 + ar9271Common_normal_cck_fir_coeff_9271,
4752 + ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
4753 + INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
4754 + ar9271Common_japan_2484_cck_fir_coeff_9271,
4755 + ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
4756 + INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
4757 + ar9271Modes_9271_1_0_only,
4758 + ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
4759 + INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
4760 + ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
4761 + INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
4762 + ar9271Modes_high_power_tx_gain_9271,
4763 + ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
4764 + INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
4765 + ar9271Modes_normal_power_tx_gain_9271,
4766 + ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
4767 + return;
4768 + }
4769 +
4770 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4771 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
4772 + ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
4773 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
4774 + ARRAY_SIZE(ar9287Common_9287_1_1), 2);
4775 + if (ah->config.pcie_clock_req)
4776 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4777 + ar9287PciePhy_clkreq_off_L1_9287_1_1,
4778 + ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
4779 + else
4780 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4781 + ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
4782 + ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
4783 + 2);
4784 + } else if (AR_SREV_9287_10_OR_LATER(ah)) {
4785 + INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
4786 + ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
4787 + INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
4788 + ARRAY_SIZE(ar9287Common_9287_1_0), 2);
4789 +
4790 + if (ah->config.pcie_clock_req)
4791 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4792 + ar9287PciePhy_clkreq_off_L1_9287_1_0,
4793 + ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
4794 + else
4795 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4796 + ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
4797 + ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
4798 + 2);
4799 + } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4800 +
4801 +
4802 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
4803 + ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
4804 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
4805 + ARRAY_SIZE(ar9285Common_9285_1_2), 2);
4806 +
4807 + if (ah->config.pcie_clock_req) {
4808 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4809 + ar9285PciePhy_clkreq_off_L1_9285_1_2,
4810 + ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
4811 + } else {
4812 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4813 + ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
4814 + ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
4815 + 2);
4816 + }
4817 + } else if (AR_SREV_9285_10_OR_LATER(ah)) {
4818 + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
4819 + ARRAY_SIZE(ar9285Modes_9285), 6);
4820 + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
4821 + ARRAY_SIZE(ar9285Common_9285), 2);
4822 +
4823 + if (ah->config.pcie_clock_req) {
4824 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4825 + ar9285PciePhy_clkreq_off_L1_9285,
4826 + ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
4827 + } else {
4828 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4829 + ar9285PciePhy_clkreq_always_on_L1_9285,
4830 + ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
4831 + }
4832 + } else if (AR_SREV_9280_20_OR_LATER(ah)) {
4833 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
4834 + ARRAY_SIZE(ar9280Modes_9280_2), 6);
4835 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
4836 + ARRAY_SIZE(ar9280Common_9280_2), 2);
4837 +
4838 + if (ah->config.pcie_clock_req) {
4839 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4840 + ar9280PciePhy_clkreq_off_L1_9280,
4841 + ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
4842 + } else {
4843 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
4844 + ar9280PciePhy_clkreq_always_on_L1_9280,
4845 + ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
4846 + }
4847 + INIT_INI_ARRAY(&ah->iniModesAdditional,
4848 + ar9280Modes_fast_clock_9280_2,
4849 + ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
4850 + } else if (AR_SREV_9280_10_OR_LATER(ah)) {
4851 + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
4852 + ARRAY_SIZE(ar9280Modes_9280), 6);
4853 + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
4854 + ARRAY_SIZE(ar9280Common_9280), 2);
4855 + } else if (AR_SREV_9160_10_OR_LATER(ah)) {
4856 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
4857 + ARRAY_SIZE(ar5416Modes_9160), 6);
4858 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
4859 + ARRAY_SIZE(ar5416Common_9160), 2);
4860 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
4861 + ARRAY_SIZE(ar5416Bank0_9160), 2);
4862 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
4863 + ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
4864 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
4865 + ARRAY_SIZE(ar5416Bank1_9160), 2);
4866 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
4867 + ARRAY_SIZE(ar5416Bank2_9160), 2);
4868 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
4869 + ARRAY_SIZE(ar5416Bank3_9160), 3);
4870 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
4871 + ARRAY_SIZE(ar5416Bank6_9160), 3);
4872 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
4873 + ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
4874 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
4875 + ARRAY_SIZE(ar5416Bank7_9160), 2);
4876 + if (AR_SREV_9160_11(ah)) {
4877 + INIT_INI_ARRAY(&ah->iniAddac,
4878 + ar5416Addac_91601_1,
4879 + ARRAY_SIZE(ar5416Addac_91601_1), 2);
4880 + } else {
4881 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
4882 + ARRAY_SIZE(ar5416Addac_9160), 2);
4883 + }
4884 + } else if (AR_SREV_9100_OR_LATER(ah)) {
4885 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
4886 + ARRAY_SIZE(ar5416Modes_9100), 6);
4887 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
4888 + ARRAY_SIZE(ar5416Common_9100), 2);
4889 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
4890 + ARRAY_SIZE(ar5416Bank0_9100), 2);
4891 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
4892 + ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
4893 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
4894 + ARRAY_SIZE(ar5416Bank1_9100), 2);
4895 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
4896 + ARRAY_SIZE(ar5416Bank2_9100), 2);
4897 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
4898 + ARRAY_SIZE(ar5416Bank3_9100), 3);
4899 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
4900 + ARRAY_SIZE(ar5416Bank6_9100), 3);
4901 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
4902 + ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
4903 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
4904 + ARRAY_SIZE(ar5416Bank7_9100), 2);
4905 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
4906 + ARRAY_SIZE(ar5416Addac_9100), 2);
4907 + } else {
4908 + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
4909 + ARRAY_SIZE(ar5416Modes), 6);
4910 + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
4911 + ARRAY_SIZE(ar5416Common), 2);
4912 + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
4913 + ARRAY_SIZE(ar5416Bank0), 2);
4914 + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
4915 + ARRAY_SIZE(ar5416BB_RfGain), 3);
4916 + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
4917 + ARRAY_SIZE(ar5416Bank1), 2);
4918 + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
4919 + ARRAY_SIZE(ar5416Bank2), 2);
4920 + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
4921 + ARRAY_SIZE(ar5416Bank3), 3);
4922 + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
4923 + ARRAY_SIZE(ar5416Bank6), 3);
4924 + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
4925 + ARRAY_SIZE(ar5416Bank6TPC), 3);
4926 + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
4927 + ARRAY_SIZE(ar5416Bank7), 2);
4928 + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
4929 + ARRAY_SIZE(ar5416Addac), 2);
4930 + }
4931 +}
4932 +
4933 +/* Support for Japan ch.14 (2484) spread */
4934 +void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
4935 +{
4936 + if (AR_SREV_9287_11_OR_LATER(ah)) {
4937 + INIT_INI_ARRAY(&ah->iniCckfirNormal,
4938 + ar9287Common_normal_cck_fir_coeff_92871_1,
4939 + ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
4940 + INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
4941 + ar9287Common_japan_2484_cck_fir_coeff_92871_1,
4942 + ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
4943 + }
4944 +}
4945 +
4946 +static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
4947 +{
4948 + u32 rxgain_type;
4949 +
4950 + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
4951 + rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
4952 +
4953 + if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
4954 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4955 + ar9280Modes_backoff_13db_rxgain_9280_2,
4956 + ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
4957 + else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
4958 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4959 + ar9280Modes_backoff_23db_rxgain_9280_2,
4960 + ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
4961 + else
4962 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4963 + ar9280Modes_original_rxgain_9280_2,
4964 + ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
4965 + } else {
4966 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4967 + ar9280Modes_original_rxgain_9280_2,
4968 + ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
4969 + }
4970 +}
4971 +
4972 +static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
4973 +{
4974 + u32 txgain_type;
4975 +
4976 + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
4977 + txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
4978 +
4979 + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
4980 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4981 + ar9280Modes_high_power_tx_gain_9280_2,
4982 + ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
4983 + else
4984 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4985 + ar9280Modes_original_tx_gain_9280_2,
4986 + ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
4987 + } else {
4988 + INIT_INI_ARRAY(&ah->iniModesTxGain,
4989 + ar9280Modes_original_tx_gain_9280_2,
4990 + ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
4991 + }
4992 +}
4993 +
4994 +static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
4995 +{
4996 + if (AR_SREV_9287_11_OR_LATER(ah))
4997 + INIT_INI_ARRAY(&ah->iniModesRxGain,
4998 + ar9287Modes_rx_gain_9287_1_1,
4999 + ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
5000 + else if (AR_SREV_9287_10(ah))
5001 + INIT_INI_ARRAY(&ah->iniModesRxGain,
5002 + ar9287Modes_rx_gain_9287_1_0,
5003 + ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
5004 + else if (AR_SREV_9280_20(ah))
5005 + ar9280_20_hw_init_rxgain_ini(ah);
5006 +
5007 + if (AR_SREV_9287_11_OR_LATER(ah)) {
5008 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5009 + ar9287Modes_tx_gain_9287_1_1,
5010 + ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
5011 + } else if (AR_SREV_9287_10(ah)) {
5012 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5013 + ar9287Modes_tx_gain_9287_1_0,
5014 + ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
5015 + } else if (AR_SREV_9280_20(ah)) {
5016 + ar9280_20_hw_init_txgain_ini(ah);
5017 + } else if (AR_SREV_9285_12_OR_LATER(ah)) {
5018 + u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
5019 +
5020 + /* txgain table */
5021 + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
5022 + if (AR_SREV_9285E_20(ah)) {
5023 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5024 + ar9285Modes_XE2_0_high_power,
5025 + ARRAY_SIZE(
5026 + ar9285Modes_XE2_0_high_power), 6);
5027 + } else {
5028 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5029 + ar9285Modes_high_power_tx_gain_9285_1_2,
5030 + ARRAY_SIZE(
5031 + ar9285Modes_high_power_tx_gain_9285_1_2), 6);
5032 + }
5033 + } else {
5034 + if (AR_SREV_9285E_20(ah)) {
5035 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5036 + ar9285Modes_XE2_0_normal_power,
5037 + ARRAY_SIZE(
5038 + ar9285Modes_XE2_0_normal_power), 6);
5039 + } else {
5040 + INIT_INI_ARRAY(&ah->iniModesTxGain,
5041 + ar9285Modes_original_tx_gain_9285_1_2,
5042 + ARRAY_SIZE(
5043 + ar9285Modes_original_tx_gain_9285_1_2), 6);
5044 + }
5045 + }
5046 + }
5047 +}
5048 +
5049 +/*
5050 + * Helper for ASPM support.
5051 + *
5052 + * Disable PLL when in L0s as well as receiver clock when in L1.
5053 + * This power saving option must be enabled through the SerDes.
5054 + *
5055 + * Programming the SerDes must go through the same 288 bit serial shift
5056 + * register as the other analog registers. Hence the 9 writes.
5057 + */
5058 +static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
5059 + int restore,
5060 + int power_off)
5061 +{
5062 + u8 i;
5063 + u32 val;
5064 +
5065 + if (ah->is_pciexpress != true)
5066 + return;
5067 +
5068 + /* Do not touch SerDes registers */
5069 + if (ah->config.pcie_powersave_enable == 2)
5070 + return;
5071 +
5072 + /* Nothing to do on restore for 11N */
5073 + if (!restore) {
5074 + if (AR_SREV_9280_20_OR_LATER(ah)) {
5075 + /*
5076 + * AR9280 2.0 or later chips use SerDes values from the
5077 + * initvals.h initialized depending on chipset during
5078 + * __ath9k_hw_init()
5079 + */
5080 + for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
5081 + REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
5082 + INI_RA(&ah->iniPcieSerdes, i, 1));
5083 + }
5084 + } else if (AR_SREV_9280(ah) &&
5085 + (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
5086 + REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
5087 + REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
5088 +
5089 + /* RX shut off when elecidle is asserted */
5090 + REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
5091 + REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
5092 + REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
5093 +
5094 + /* Shut off CLKREQ active in L1 */
5095 + if (ah->config.pcie_clock_req)
5096 + REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
5097 + else
5098 + REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
5099 +
5100 + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
5101 + REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
5102 + REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
5103 +
5104 + /* Load the new settings */
5105 + REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
5106 +
5107 + } else {
5108 + REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
5109 + REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
5110 +
5111 + /* RX shut off when elecidle is asserted */
5112 + REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
5113 + REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
5114 + REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
5115 +
5116 + /*
5117 + * Ignore ah->ah_config.pcie_clock_req setting for
5118 + * pre-AR9280 11n
5119 + */
5120 + REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
5121 +
5122 + REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
5123 + REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
5124 + REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
5125 +
5126 + /* Load the new settings */
5127 + REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
5128 + }
5129 +
5130 + udelay(1000);
5131 +
5132 + /* set bit 19 to allow forcing of pcie core into L1 state */
5133 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
5134 +
5135 + /* Several PCIe massages to ensure proper behaviour */
5136 + if (ah->config.pcie_waen) {
5137 + val = ah->config.pcie_waen;
5138 + if (!power_off)
5139 + val &= (~AR_WA_D3_L1_DISABLE);
5140 + } else {
5141 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
5142 + AR_SREV_9287(ah)) {
5143 + val = AR9285_WA_DEFAULT;
5144 + if (!power_off)
5145 + val &= (~AR_WA_D3_L1_DISABLE);
5146 + } else if (AR_SREV_9280(ah)) {
5147 + /*
5148 + * On AR9280 chips bit 22 of 0x4004 needs to be
5149 + * set otherwise card may disappear.
5150 + */
5151 + val = AR9280_WA_DEFAULT;
5152 + if (!power_off)
5153 + val &= (~AR_WA_D3_L1_DISABLE);
5154 + } else
5155 + val = AR_WA_DEFAULT;
5156 + }
5157 +
5158 + REG_WRITE(ah, AR_WA, val);
5159 + }
5160 +
5161 + if (power_off) {
5162 + /*
5163 + * Set PCIe workaround bits
5164 + * bit 14 in WA register (disable L1) should only
5165 + * be set when device enters D3 and be cleared
5166 + * when device comes back to D0.
5167 + */
5168 + if (ah->config.pcie_waen) {
5169 + if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
5170 + REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
5171 + } else {
5172 + if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
5173 + AR_SREV_9287(ah)) &&
5174 + (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
5175 + (AR_SREV_9280(ah) &&
5176 + (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
5177 + REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
5178 + }
5179 + }
5180 + }
5181 +}
5182 +
5183 +static int ar9002_hw_get_radiorev(struct ath_hw *ah)
5184 +{
5185 + u32 val;
5186 + int i;
5187 +
5188 + REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
5189 +
5190 + for (i = 0; i < 8; i++)
5191 + REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
5192 + val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
5193 + val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
5194 +
5195 + return ath9k_hw_reverse_bits(val, 8);
5196 +}
5197 +
5198 +int ar9002_hw_rf_claim(struct ath_hw *ah)
5199 +{
5200 + u32 val;
5201 +
5202 + REG_WRITE(ah, AR_PHY(0), 0x00000007);
5203 +
5204 + val = ar9002_hw_get_radiorev(ah);
5205 + switch (val & AR_RADIO_SREV_MAJOR) {
5206 + case 0:
5207 + val = AR_RAD5133_SREV_MAJOR;
5208 + break;
5209 + case AR_RAD5133_SREV_MAJOR:
5210 + case AR_RAD5122_SREV_MAJOR:
5211 + case AR_RAD2133_SREV_MAJOR:
5212 + case AR_RAD2122_SREV_MAJOR:
5213 + break;
5214 + default:
5215 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
5216 + "Radio Chip Rev 0x%02X not supported\n",
5217 + val & AR_RADIO_SREV_MAJOR);
5218 + return -EOPNOTSUPP;
5219 + }
5220 +
5221 + ah->hw_version.analog5GhzRev = val;
5222 +
5223 + return 0;
5224 +}
5225 +
5226 +/*
5227 + * Enable ASYNC FIFO
5228 + *
5229 + * If Async FIFO is enabled, the following counters change as MAC now runs
5230 + * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
5231 + *
5232 + * The values below tested for ht40 2 chain.
5233 + * Overwrite the delay/timeouts initialized in process ini.
5234 + */
5235 +void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
5236 +{
5237 + if (AR_SREV_9287_12_OR_LATER(ah)) {
5238 + REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
5239 + AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
5240 + REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
5241 + AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
5242 + REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
5243 + AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
5244 +
5245 + REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
5246 + REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
5247 +
5248 + REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
5249 + AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
5250 + REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
5251 + AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
5252 + }
5253 +}
5254 +
5255 +/*
5256 + * We don't enable WEP aggregation on mac80211 but we keep this
5257 + * around for HAL unification purposes.
5258 + */
5259 +void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
5260 +{
5261 + if (AR_SREV_9287_12_OR_LATER(ah)) {
5262 + REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
5263 + AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
5264 + }
5265 +}
5266 +
5267 +/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
5268 +void ar9002_hw_attach_ops(struct ath_hw *ah)
5269 +{
5270 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
5271 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
5272 +
5273 + priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
5274 + priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
5275 + priv_ops->macversion_supported = ar9002_hw_macversion_supported;
5276 +
5277 + ops->config_pci_powersave = ar9002_hw_configpcipowersave;
5278 +
5279 + ar5008_hw_attach_phy_ops(ah);
5280 + if (AR_SREV_9280_10_OR_LATER(ah))
5281 + ar9002_hw_attach_phy_ops(ah);
5282 +
5283 + ar9002_hw_attach_calib_ops(ah);
5284 + ar9002_hw_attach_mac_ops(ah);
5285 +}
5286 --- /dev/null
5287 +++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
5288 @@ -0,0 +1,7768 @@
5289 +/*
5290 + * Copyright (c) 2010 Atheros Communications Inc.
5291 + *
5292 + * Permission to use, copy, modify, and/or distribute this software for any
5293 + * purpose with or without fee is hereby granted, provided that the above
5294 + * copyright notice and this permission notice appear in all copies.
5295 + *
5296 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
5297 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
5298 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
5299 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
5300 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
5301 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
5302 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
5303 + */
5304 +
5305 +#ifndef INITVALS_9002_10_H
5306 +#define INITVALS_9002_10_H
5307 +
5308 +static const u32 ar9280Modes_9280[][6] = {
5309 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
5310 + 0x000001e0},
5311 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
5312 + 0x000001e0},
5313 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
5314 + 0x00001180},
5315 + {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000,
5316 + 0x00014008},
5317 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840,
5318 + 0x06e006e0},
5319 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
5320 + 0x0988004f},
5321 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
5322 + 0x00000303},
5323 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
5324 + 0x02020200},
5325 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
5326 + 0x00000e0e},
5327 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
5328 + 0x0a020001},
5329 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
5330 + 0x00000e0e},
5331 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
5332 + 0x00000007},
5333 + {0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0,
5334 + 0x137216a0},
5335 + {0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563,
5336 + 0x00028563},
5337 + {0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563,
5338 + 0x00028563},
5339 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
5340 + 0x6d4000e2},
5341 + {0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e,
5342 + 0x7ec82d2e},
5343 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e,
5344 + 0x3139605e},
5345 + {0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20,
5346 + 0x00049d18},
5347 + {0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
5348 + 0x0001ce00},
5349 + {0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190,
5350 + 0x5ac64190},
5351 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
5352 + 0x06903881},
5353 + {0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898,
5354 + 0x000007d0},
5355 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
5356 + 0x00000016},
5357 + {0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d,
5358 + 0xd00a8a0d},
5359 + {0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010,
5360 + 0xdfbc1010},
5361 + {0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010,
5362 + 0x00000010},
5363 + {0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010,
5364 + 0x00000010},
5365 + {0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210,
5366 + 0x00000210},
5367 + {0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a,
5368 + 0x0000001a},
5369 + {0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00,
5370 + 0x00000c00},
5371 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
5372 + 0x05eea6d4},
5373 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
5374 + 0x06336f77},
5375 + {0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c,
5376 + 0x60f6532c},
5377 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
5378 + 0x08f186c8},
5379 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
5380 + 0x00046384},
5381 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5382 + 0x00000000},
5383 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5384 + 0x00000000},
5385 + {0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214,
5386 + 0x00000214},
5387 + {0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218,
5388 + 0x00000218},
5389 + {0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224,
5390 + 0x00000224},
5391 + {0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228,
5392 + 0x00000228},
5393 + {0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c,
5394 + 0x0000022c},
5395 + {0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230,
5396 + 0x00000230},
5397 + {0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4,
5398 + 0x000002a4},
5399 + {0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8,
5400 + 0x000002a8},
5401 + {0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac,
5402 + 0x000002ac},
5403 + {0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0,
5404 + 0x000002b0},
5405 + {0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4,
5406 + 0x000002b4},
5407 + {0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8,
5408 + 0x000002b8},
5409 + {0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390,
5410 + 0x00000390},
5411 + {0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394,
5412 + 0x00000394},
5413 + {0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398,
5414 + 0x00000398},
5415 + {0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334,
5416 + 0x00000334},
5417 + {0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338,
5418 + 0x00000338},
5419 + {0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac,
5420 + 0x000003ac},
5421 + {0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0,
5422 + 0x000003b0},
5423 + {0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4,
5424 + 0x000003b4},
5425 + {0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8,
5426 + 0x000003b8},
5427 + {0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5,
5428 + 0x000003a5},
5429 + {0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9,
5430 + 0x000003a9},
5431 + {0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad,
5432 + 0x000003ad},
5433 + {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194,
5434 + 0x00008194},
5435 + {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0,
5436 + 0x000081a0},
5437 + {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c,
5438 + 0x0000820c},
5439 + {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8,
5440 + 0x000081a8},
5441 + {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284,
5442 + 0x00008284},
5443 + {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288,
5444 + 0x00008288},
5445 + {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224,
5446 + 0x00008224},
5447 + {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290,
5448 + 0x00008290},
5449 + {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300,
5450 + 0x00008300},
5451 + {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304,
5452 + 0x00008304},
5453 + {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308,
5454 + 0x00008308},
5455 + {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c,
5456 + 0x0000830c},
5457 + {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380,
5458 + 0x00008380},
5459 + {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384,
5460 + 0x00008384},
5461 + {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700,
5462 + 0x00008700},
5463 + {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704,
5464 + 0x00008704},
5465 + {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708,
5466 + 0x00008708},
5467 + {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c,
5468 + 0x0000870c},
5469 + {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780,
5470 + 0x00008780},
5471 + {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784,
5472 + 0x00008784},
5473 + {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00,
5474 + 0x00008b00},
5475 + {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04,
5476 + 0x00008b04},
5477 + {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08,
5478 + 0x00008b08},
5479 + {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c,
5480 + 0x00008b0c},
5481 + {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80,
5482 + 0x00008b80},
5483 + {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84,
5484 + 0x00008b84},
5485 + {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88,
5486 + 0x00008b88},
5487 + {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c,
5488 + 0x00008b8c},
5489 + {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90,
5490 + 0x00008b90},
5491 + {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80,
5492 + 0x00008f80},
5493 + {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84,
5494 + 0x00008f84},
5495 + {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88,
5496 + 0x00008f88},
5497 + {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c,
5498 + 0x00008f8c},
5499 + {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90,
5500 + 0x00008f90},
5501 + {0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c,
5502 + 0x0000930c},
5503 + {0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310,
5504 + 0x00009310},
5505 + {0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384,
5506 + 0x00009384},
5507 + {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388,
5508 + 0x00009388},
5509 + {0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324,
5510 + 0x00009324},
5511 + {0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704,
5512 + 0x00009704},
5513 + {0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4,
5514 + 0x000096a4},
5515 + {0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8,
5516 + 0x000096a8},
5517 + {0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710,
5518 + 0x00009710},
5519 + {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714,
5520 + 0x00009714},
5521 + {0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720,
5522 + 0x00009720},
5523 + {0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724,
5524 + 0x00009724},
5525 + {0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728,
5526 + 0x00009728},
5527 + {0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c,
5528 + 0x0000972c},
5529 + {0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0,
5530 + 0x000097a0},
5531 + {0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4,
5532 + 0x000097a4},
5533 + {0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8,
5534 + 0x000097a8},
5535 + {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0,
5536 + 0x000097b0},
5537 + {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4,
5538 + 0x000097b4},
5539 + {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8,
5540 + 0x000097b8},
5541 + {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5,
5542 + 0x000097a5},
5543 + {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9,
5544 + 0x000097a9},
5545 + {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad,
5546 + 0x000097ad},
5547 + {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1,
5548 + 0x000097b1},
5549 + {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5,
5550 + 0x000097b5},
5551 + {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9,
5552 + 0x000097b9},
5553 + {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5,
5554 + 0x000097c5},
5555 + {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9,
5556 + 0x000097c9},
5557 + {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1,
5558 + 0x000097d1},
5559 + {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5,
5560 + 0x000097d5},
5561 + {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9,
5562 + 0x000097d9},
5563 + {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6,
5564 + 0x000097c6},
5565 + {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca,
5566 + 0x000097ca},
5567 + {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce,
5568 + 0x000097ce},
5569 + {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2,
5570 + 0x000097d2},
5571 + {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6,
5572 + 0x000097d6},
5573 + {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3,
5574 + 0x000097c3},
5575 + {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7,
5576 + 0x000097c7},
5577 + {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb,
5578 + 0x000097cb},
5579 + {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf,
5580 + 0x000097cf},
5581 + {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7,
5582 + 0x000097d7},
5583 + {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db,
5584 + 0x000097db},
5585 + {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db,
5586 + 0x000097db},
5587 + {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db,
5588 + 0x000097db},
5589 + {0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5590 + 0x000097db},
5591 + {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5592 + 0x000097db},
5593 + {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5594 + 0x000097db},
5595 + {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5596 + 0x000097db},
5597 + {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5598 + 0x000097db},
5599 + {0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5600 + 0x000097db},
5601 + {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5602 + 0x000097db},
5603 + {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5604 + 0x000097db},
5605 + {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5606 + 0x000097db},
5607 + {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5608 + 0x000097db},
5609 + {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5610 + 0x000097db},
5611 + {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5612 + 0x000097db},
5613 + {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5614 + 0x000097db},
5615 + {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5616 + 0x000097db},
5617 + {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5618 + 0x000097db},
5619 + {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5620 + 0x000097db},
5621 + {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5622 + 0x000097db},
5623 + {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5624 + 0x000097db},
5625 + {0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5626 + 0x000097db},
5627 + {0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5628 + 0x000097db},
5629 + {0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5630 + 0x000097db},
5631 + {0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5632 + 0x000097db},
5633 + {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5634 + 0x000097db},
5635 + {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5636 + 0x000097db},
5637 + {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5638 + 0x000097db},
5639 + {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
5640 + 0x000097db},
5641 + {0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444,
5642 + 0x00000444},
5643 + {0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788,
5644 + 0x803e4788},
5645 + {0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019,
5646 + 0x000c6019},
5647 + {0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019,
5648 + 0x000c6019},
5649 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
5650 + 0x1883800a},
5651 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
5652 + 0x00000000},
5653 + {0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652,
5654 + 0x0a1aa652},
5655 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5656 + 0x00000000},
5657 + {0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002,
5658 + 0x00003002},
5659 + {0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009,
5660 + 0x00008009},
5661 + {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b,
5662 + 0x0000b00b},
5663 + {0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012,
5664 + 0x0000e012},
5665 + {0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048,
5666 + 0x00012048},
5667 + {0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a,
5668 + 0x0001604a},
5669 + {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211,
5670 + 0x0001a211},
5671 + {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213,
5672 + 0x0001e213},
5673 + {0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b,
5674 + 0x0002121b},
5675 + {0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412,
5676 + 0x00024412},
5677 + {0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414,
5678 + 0x00028414},
5679 + {0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a,
5680 + 0x0002b44a},
5681 + {0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649,
5682 + 0x00030649},
5683 + {0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b,
5684 + 0x0003364b},
5685 + {0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49,
5686 + 0x00038a49},
5687 + {0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48,
5688 + 0x0003be48},
5689 + {0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a,
5690 + 0x0003ee4a},
5691 + {0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88,
5692 + 0x00042e88},
5693 + {0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a,
5694 + 0x00046e8a},
5695 + {0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9,
5696 + 0x00049ec9},
5697 + {0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42,
5698 + 0x0004bf42},
5699 + {0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c,
5700 + 0x0e4d048c},
5701 + {0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828,
5702 + 0x12035828},
5703 + {0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000,
5704 + 0x807ec000},
5705 + {0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000,
5706 + 0x00110000},
5707 +};
5708 +
5709 +static const u32 ar9280Common_9280[][2] = {
5710 + {0x0000000c, 0x00000000},
5711 + {0x00000030, 0x00020015},
5712 + {0x00000034, 0x00000005},
5713 + {0x00000040, 0x00000000},
5714 + {0x00000044, 0x00000008},
5715 + {0x00000048, 0x00000008},
5716 + {0x0000004c, 0x00000010},
5717 + {0x00000050, 0x00000000},
5718 + {0x00000054, 0x0000001f},
5719 + {0x00000800, 0x00000000},
5720 + {0x00000804, 0x00000000},
5721 + {0x00000808, 0x00000000},
5722 + {0x0000080c, 0x00000000},
5723 + {0x00000810, 0x00000000},
5724 + {0x00000814, 0x00000000},
5725 + {0x00000818, 0x00000000},
5726 + {0x0000081c, 0x00000000},
5727 + {0x00000820, 0x00000000},
5728 + {0x00000824, 0x00000000},
5729 + {0x00001040, 0x002ffc0f},
5730 + {0x00001044, 0x002ffc0f},
5731 + {0x00001048, 0x002ffc0f},
5732 + {0x0000104c, 0x002ffc0f},
5733 + {0x00001050, 0x002ffc0f},
5734 + {0x00001054, 0x002ffc0f},
5735 + {0x00001058, 0x002ffc0f},
5736 + {0x0000105c, 0x002ffc0f},
5737 + {0x00001060, 0x002ffc0f},
5738 + {0x00001064, 0x002ffc0f},
5739 + {0x00001230, 0x00000000},
5740 + {0x00001270, 0x00000000},
5741 + {0x00001038, 0x00000000},
5742 + {0x00001078, 0x00000000},
5743 + {0x000010b8, 0x00000000},
5744 + {0x000010f8, 0x00000000},
5745 + {0x00001138, 0x00000000},
5746 + {0x00001178, 0x00000000},
5747 + {0x000011b8, 0x00000000},
5748 + {0x000011f8, 0x00000000},
5749 + {0x00001238, 0x00000000},
5750 + {0x00001278, 0x00000000},
5751 + {0x000012b8, 0x00000000},
5752 + {0x000012f8, 0x00000000},
5753 + {0x00001338, 0x00000000},
5754 + {0x00001378, 0x00000000},
5755 + {0x000013b8, 0x00000000},
5756 + {0x000013f8, 0x00000000},
5757 + {0x00001438, 0x00000000},
5758 + {0x00001478, 0x00000000},
5759 + {0x000014b8, 0x00000000},
5760 + {0x000014f8, 0x00000000},
5761 + {0x00001538, 0x00000000},
5762 + {0x00001578, 0x00000000},
5763 + {0x000015b8, 0x00000000},
5764 + {0x000015f8, 0x00000000},
5765 + {0x00001638, 0x00000000},
5766 + {0x00001678, 0x00000000},
5767 + {0x000016b8, 0x00000000},
5768 + {0x000016f8, 0x00000000},
5769 + {0x00001738, 0x00000000},
5770 + {0x00001778, 0x00000000},
5771 + {0x000017b8, 0x00000000},
5772 + {0x000017f8, 0x00000000},
5773 + {0x0000103c, 0x00000000},
5774 + {0x0000107c, 0x00000000},
5775 + {0x000010bc, 0x00000000},
5776 + {0x000010fc, 0x00000000},
5777 + {0x0000113c, 0x00000000},
5778 + {0x0000117c, 0x00000000},
5779 + {0x000011bc, 0x00000000},
5780 + {0x000011fc, 0x00000000},
5781 + {0x0000123c, 0x00000000},
5782 + {0x0000127c, 0x00000000},
5783 + {0x000012bc, 0x00000000},
5784 + {0x000012fc, 0x00000000},
5785 + {0x0000133c, 0x00000000},
5786 + {0x0000137c, 0x00000000},
5787 + {0x000013bc, 0x00000000},
5788 + {0x000013fc, 0x00000000},
5789 + {0x0000143c, 0x00000000},
5790 + {0x0000147c, 0x00000000},
5791 + {0x00004030, 0x00000002},
5792 + {0x0000403c, 0x00000002},
5793 + {0x00004024, 0x0000001f},
5794 + {0x00007010, 0x00000033},
5795 + {0x00007038, 0x000004c2},
5796 + {0x00008004, 0x00000000},
5797 + {0x00008008, 0x00000000},
5798 + {0x0000800c, 0x00000000},
5799 + {0x00008018, 0x00000700},
5800 + {0x00008020, 0x00000000},
5801 + {0x00008038, 0x00000000},
5802 + {0x0000803c, 0x00000000},
5803 + {0x00008048, 0x40000000},
5804 + {0x00008054, 0x00000000},
5805 + {0x00008058, 0x00000000},
5806 + {0x0000805c, 0x000fc78f},
5807 + {0x00008060, 0x0000000f},
5808 + {0x00008064, 0x00000000},
5809 + {0x00008070, 0x00000000},
5810 + {0x000080c0, 0x2a82301a},
5811 + {0x000080c4, 0x05dc01e0},
5812 + {0x000080c8, 0x1f402710},
5813 + {0x000080cc, 0x01f40000},
5814 + {0x000080d0, 0x00001e00},
5815 + {0x000080d4, 0x00000000},
5816 + {0x000080d8, 0x00400000},
5817 + {0x000080e0, 0xffffffff},
5818 + {0x000080e4, 0x0000ffff},
5819 + {0x000080e8, 0x003f3f3f},
5820 + {0x000080ec, 0x00000000},
5821 + {0x000080f0, 0x00000000},
5822 + {0x000080f4, 0x00000000},
5823 + {0x000080f8, 0x00000000},
5824 + {0x000080fc, 0x00020000},
5825 + {0x00008100, 0x00020000},
5826 + {0x00008104, 0x00000001},
5827 + {0x00008108, 0x00000052},
5828 + {0x0000810c, 0x00000000},
5829 + {0x00008110, 0x00000168},
5830 + {0x00008118, 0x000100aa},
5831 + {0x0000811c, 0x00003210},
5832 + {0x00008120, 0x08f04800},
5833 + {0x00008124, 0x00000000},
5834 + {0x00008128, 0x00000000},
5835 + {0x0000812c, 0x00000000},
5836 + {0x00008130, 0x00000000},
5837 + {0x00008134, 0x00000000},
5838 + {0x00008138, 0x00000000},
5839 + {0x0000813c, 0x00000000},
5840 + {0x00008144, 0x00000000},
5841 + {0x00008168, 0x00000000},
5842 + {0x0000816c, 0x00000000},
5843 + {0x00008170, 0x32143320},
5844 + {0x00008174, 0xfaa4fa50},
5845 + {0x00008178, 0x00000100},
5846 + {0x0000817c, 0x00000000},
5847 + {0x000081c4, 0x00000000},
5848 + {0x000081d0, 0x00003210},
5849 + {0x000081ec, 0x00000000},
5850 + {0x000081f0, 0x00000000},
5851 + {0x000081f4, 0x00000000},
5852 + {0x000081f8, 0x00000000},
5853 + {0x000081fc, 0x00000000},
5854 + {0x00008200, 0x00000000},
5855 + {0x00008204, 0x00000000},
5856 + {0x00008208, 0x00000000},
5857 + {0x0000820c, 0x00000000},
5858 + {0x00008210, 0x00000000},
5859 + {0x00008214, 0x00000000},
5860 + {0x00008218, 0x00000000},
5861 + {0x0000821c, 0x00000000},
5862 + {0x00008220, 0x00000000},
5863 + {0x00008224, 0x00000000},
5864 + {0x00008228, 0x00000000},
5865 + {0x0000822c, 0x00000000},
5866 + {0x00008230, 0x00000000},
5867 + {0x00008234, 0x00000000},
5868 + {0x00008238, 0x00000000},
5869 + {0x0000823c, 0x00000000},
5870 + {0x00008240, 0x00100000},
5871 + {0x00008244, 0x0010f400},
5872 + {0x00008248, 0x00000100},
5873 + {0x0000824c, 0x0001e800},
5874 + {0x00008250, 0x00000000},
5875 + {0x00008254, 0x00000000},
5876 + {0x00008258, 0x00000000},
5877 + {0x0000825c, 0x400000ff},
5878 + {0x00008260, 0x00080922},
5879 + {0x00008270, 0x00000000},
5880 + {0x00008274, 0x40000000},
5881 + {0x00008278, 0x003e4180},
5882 + {0x0000827c, 0x00000000},
5883 + {0x00008284, 0x0000002c},
5884 + {0x00008288, 0x0000002c},
5885 + {0x0000828c, 0x00000000},
5886 + {0x00008294, 0x00000000},
5887 + {0x00008298, 0x00000000},
5888 + {0x00008300, 0x00000000},
5889 + {0x00008304, 0x00000000},
5890 + {0x00008308, 0x00000000},
5891 + {0x0000830c, 0x00000000},
5892 + {0x00008310, 0x00000000},
5893 + {0x00008314, 0x00000000},
5894 + {0x00008318, 0x00000000},
5895 + {0x00008328, 0x00000000},
5896 + {0x0000832c, 0x00000007},
5897 + {0x00008330, 0x00000302},
5898 + {0x00008334, 0x00000e00},
5899 + {0x00008338, 0x00000000},
5900 + {0x0000833c, 0x00000000},
5901 + {0x00008340, 0x000107ff},
5902 + {0x00008344, 0x00000000},
5903 + {0x00009808, 0x00000000},
5904 + {0x0000980c, 0xaf268e30},
5905 + {0x00009810, 0xfd14e000},
5906 + {0x00009814, 0x9c0a9f6b},
5907 + {0x0000981c, 0x00000000},
5908 + {0x0000982c, 0x0000a000},
5909 + {0x00009830, 0x00000000},
5910 + {0x0000983c, 0x00200400},
5911 + {0x00009840, 0x206a01ae},
5912 + {0x0000984c, 0x0040233c},
5913 + {0x0000a84c, 0x0040233c},
5914 + {0x00009854, 0x00000044},
5915 + {0x00009900, 0x00000000},
5916 + {0x00009904, 0x00000000},
5917 + {0x00009908, 0x00000000},
5918 + {0x0000990c, 0x00000000},
5919 + {0x0000991c, 0x10000fff},
5920 + {0x00009920, 0x04900000},
5921 + {0x0000a920, 0x04900000},
5922 + {0x00009928, 0x00000001},
5923 + {0x0000992c, 0x00000004},
5924 + {0x00009934, 0x1e1f2022},
5925 + {0x00009938, 0x0a0b0c0d},
5926 + {0x0000993c, 0x00000000},
5927 + {0x00009948, 0x9280c00a},
5928 + {0x0000994c, 0x00020028},
5929 + {0x00009954, 0xe250a51e},
5930 + {0x00009958, 0x3388ffff},
5931 + {0x00009940, 0x00781204},
5932 + {0x0000c95c, 0x004b6a8e},
5933 + {0x0000c968, 0x000003ce},
5934 + {0x00009970, 0x190fb514},
5935 + {0x00009974, 0x00000000},
5936 + {0x00009978, 0x00000001},
5937 + {0x0000997c, 0x00000000},
5938 + {0x00009980, 0x00000000},
5939 + {0x00009984, 0x00000000},
5940 + {0x00009988, 0x00000000},
5941 + {0x0000998c, 0x00000000},
5942 + {0x00009990, 0x00000000},
5943 + {0x00009994, 0x00000000},
5944 + {0x00009998, 0x00000000},
5945 + {0x0000999c, 0x00000000},
5946 + {0x000099a0, 0x00000000},
5947 + {0x000099a4, 0x00000001},
5948 + {0x000099a8, 0x201fff00},
5949 + {0x000099ac, 0x006f00c4},
5950 + {0x000099b0, 0x03051000},
5951 + {0x000099b4, 0x00000820},
5952 + {0x000099dc, 0x00000000},
5953 + {0x000099e0, 0x00000000},
5954 + {0x000099e4, 0xaaaaaaaa},
5955 + {0x000099e8, 0x3c466478},
5956 + {0x000099ec, 0x0cc80caa},
5957 + {0x000099fc, 0x00001042},
5958 + {0x0000a210, 0x4080a333},
5959 + {0x0000a214, 0x40206c10},
5960 + {0x0000a218, 0x009c4060},
5961 + {0x0000a220, 0x01834061},
5962 + {0x0000a224, 0x00000400},
5963 + {0x0000a228, 0x000003b5},
5964 + {0x0000a22c, 0x23277200},
5965 + {0x0000a234, 0x20202020},
5966 + {0x0000a238, 0x20202020},
5967 + {0x0000a23c, 0x13c889af},
5968 + {0x0000a240, 0x38490a20},
5969 + {0x0000a244, 0x00007bb6},
5970 + {0x0000a248, 0x0fff3ffc},
5971 + {0x0000a24c, 0x00000001},
5972 + {0x0000a250, 0x001da000},
5973 + {0x0000a254, 0x00000000},
5974 + {0x0000a258, 0x0cdbd380},
5975 + {0x0000a25c, 0x0f0f0f01},
5976 + {0x0000a260, 0xdfa91f01},
5977 + {0x0000a268, 0x00000000},
5978 + {0x0000a26c, 0x0ebae9c6},
5979 + {0x0000b26c, 0x0ebae9c6},
5980 + {0x0000d270, 0x00820820},
5981 + {0x0000a278, 0x1ce739ce},
5982 + {0x0000a27c, 0x050701ce},
5983 + {0x0000a358, 0x7999aa0f},
5984 + {0x0000d35c, 0x07ffffef},
5985 + {0x0000d360, 0x0fffffe7},
5986 + {0x0000d364, 0x17ffffe5},
5987 + {0x0000d368, 0x1fffffe4},
5988 + {0x0000d36c, 0x37ffffe3},
5989 + {0x0000d370, 0x3fffffe3},
5990 + {0x0000d374, 0x57ffffe3},
5991 + {0x0000d378, 0x5fffffe2},
5992 + {0x0000d37c, 0x7fffffe2},
5993 + {0x0000d380, 0x7f3c7bba},
5994 + {0x0000d384, 0xf3307ff0},
5995 + {0x0000a388, 0x0c000000},
5996 + {0x0000a38c, 0x20202020},
5997 + {0x0000a390, 0x20202020},
5998 + {0x0000a394, 0x1ce739ce},
5999 + {0x0000a398, 0x000001ce},
6000 + {0x0000a39c, 0x00000001},
6001 + {0x0000a3a0, 0x00000000},
6002 + {0x0000a3a4, 0x00000000},
6003 + {0x0000a3a8, 0x00000000},
6004 + {0x0000a3ac, 0x00000000},
6005 + {0x0000a3b0, 0x00000000},
6006 + {0x0000a3b4, 0x00000000},
6007 + {0x0000a3b8, 0x00000000},
6008 + {0x0000a3bc, 0x00000000},
6009 + {0x0000a3c0, 0x00000000},
6010 + {0x0000a3c4, 0x00000000},
6011 + {0x0000a3c8, 0x00000246},
6012 + {0x0000a3cc, 0x20202020},
6013 + {0x0000a3d0, 0x20202020},
6014 + {0x0000a3d4, 0x20202020},
6015 + {0x0000a3dc, 0x1ce739ce},
6016 + {0x0000a3e0, 0x000001ce},
6017 + {0x0000a3e4, 0x00000000},
6018 + {0x0000a3e8, 0x18c43433},
6019 + {0x0000a3ec, 0x00f38081},
6020 + {0x00007800, 0x00040000},
6021 + {0x00007804, 0xdb005012},
6022 + {0x00007808, 0x04924914},
6023 + {0x0000780c, 0x21084210},
6024 + {0x00007810, 0x6d801300},
6025 + {0x00007814, 0x0019beff},
6026 + {0x00007818, 0x07e40000},
6027 + {0x0000781c, 0x00492000},
6028 + {0x00007820, 0x92492480},
6029 + {0x00007824, 0x00040000},
6030 + {0x00007828, 0xdb005012},
6031 + {0x0000782c, 0x04924914},
6032 + {0x00007830, 0x21084210},
6033 + {0x00007834, 0x6d801300},
6034 + {0x00007838, 0x0019beff},
6035 + {0x0000783c, 0x07e40000},
6036 + {0x00007840, 0x00492000},
6037 + {0x00007844, 0x92492480},
6038 + {0x00007848, 0x00120000},
6039 + {0x00007850, 0x54214514},
6040 + {0x00007858, 0x92592692},
6041 + {0x00007860, 0x52802000},
6042 + {0x00007864, 0x0a8e370e},
6043 + {0x00007868, 0xc0102850},
6044 + {0x0000786c, 0x812d4000},
6045 + {0x00007874, 0x001b6db0},
6046 + {0x00007878, 0x00376b63},
6047 + {0x0000787c, 0x06db6db6},
6048 + {0x00007880, 0x006d8000},
6049 + {0x00007884, 0xffeffffe},
6050 + {0x00007888, 0xffeffffe},
6051 + {0x00007890, 0x00060aeb},
6052 + {0x00007894, 0x5a108000},
6053 + {0x00007898, 0x2a850160},
6054 +};
6055 +
6056 +/* XXX 9280 2 */
6057 +static const u32 ar9280Modes_9280_2[][6] = {
6058 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
6059 + 0x000001e0},
6060 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
6061 + 0x000001e0},
6062 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
6063 + 0x00001180},
6064 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6065 + 0x00000008},
6066 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
6067 + 0x06e006e0},
6068 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
6069 + 0x0988004f},
6070 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810,
6071 + 0x08f04810},
6072 + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a,
6073 + 0x0000320a},
6074 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440,
6075 + 0x00006880},
6076 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
6077 + 0x00000303},
6078 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
6079 + 0x02020200},
6080 + {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e,
6081 + 0x01000e0e},
6082 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
6083 + 0x0a020001},
6084 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
6085 + 0x00000e0e},
6086 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
6087 + 0x00000007},
6088 + {0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e,
6089 + 0x206a012e},
6090 + {0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0,
6091 + 0x037216a0},
6092 + {0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2,
6093 + 0x6c4000e2},
6094 + {0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e,
6095 + 0x7ec84d2e},
6096 + {0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e,
6097 + 0x31395d5e},
6098 + {0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20,
6099 + 0x00048d18},
6100 + {0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00,
6101 + 0x0001ce00},
6102 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
6103 + 0x5ac640d0},
6104 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
6105 + 0x06903881},
6106 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
6107 + 0x000007d0},
6108 + {0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b,
6109 + 0x00000016},
6110 + {0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d,
6111 + 0xd00a8a0d},
6112 + {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010,
6113 + 0xffbc1010},
6114 + {0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010,
6115 + 0x00000010},
6116 + {0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010,
6117 + 0x00000010},
6118 + {0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210,
6119 + 0x00000210},
6120 + {0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce,
6121 + 0x000003ce},
6122 + {0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c,
6123 + 0x0000001c},
6124 + {0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00,
6125 + 0x00000c00},
6126 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
6127 + 0x05eea6d4},
6128 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
6129 + 0x06336f77},
6130 + {0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329,
6131 + 0x60f65329},
6132 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
6133 + 0x08f186c8},
6134 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
6135 + 0x00046384},
6136 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6137 + 0x00000000},
6138 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6139 + 0x00000000},
6140 + {0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444,
6141 + 0x00000444},
6142 + {0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019,
6143 + 0x0001f019},
6144 + {0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019,
6145 + 0x0001f019},
6146 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
6147 + 0x1883800a},
6148 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
6149 + 0x00000000},
6150 + {0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000,
6151 + 0x13c88000},
6152 + {0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000,
6153 + 0x0004a000},
6154 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
6155 + 0x7999aa0e},
6156 + {0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000,
6157 + 0x0c000000},
6158 + {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6159 + 0x00000000},
6160 + {0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000,
6161 + 0x5a508000},
6162 +};
6163 +
6164 +static const u32 ar9280Common_9280_2[][2] = {
6165 + {0x0000000c, 0x00000000},
6166 + {0x00000030, 0x00020015},
6167 + {0x00000034, 0x00000005},
6168 + {0x00000040, 0x00000000},
6169 + {0x00000044, 0x00000008},
6170 + {0x00000048, 0x00000008},
6171 + {0x0000004c, 0x00000010},
6172 + {0x00000050, 0x00000000},
6173 + {0x00000054, 0x0000001f},
6174 + {0x00000800, 0x00000000},
6175 + {0x00000804, 0x00000000},
6176 + {0x00000808, 0x00000000},
6177 + {0x0000080c, 0x00000000},
6178 + {0x00000810, 0x00000000},
6179 + {0x00000814, 0x00000000},
6180 + {0x00000818, 0x00000000},
6181 + {0x0000081c, 0x00000000},
6182 + {0x00000820, 0x00000000},
6183 + {0x00000824, 0x00000000},
6184 + {0x00001040, 0x002ffc0f},
6185 + {0x00001044, 0x002ffc0f},
6186 + {0x00001048, 0x002ffc0f},
6187 + {0x0000104c, 0x002ffc0f},
6188 + {0x00001050, 0x002ffc0f},
6189 + {0x00001054, 0x002ffc0f},
6190 + {0x00001058, 0x002ffc0f},
6191 + {0x0000105c, 0x002ffc0f},
6192 + {0x00001060, 0x002ffc0f},
6193 + {0x00001064, 0x002ffc0f},
6194 + {0x00001230, 0x00000000},
6195 + {0x00001270, 0x00000000},
6196 + {0x00001038, 0x00000000},
6197 + {0x00001078, 0x00000000},
6198 + {0x000010b8, 0x00000000},
6199 + {0x000010f8, 0x00000000},
6200 + {0x00001138, 0x00000000},
6201 + {0x00001178, 0x00000000},
6202 + {0x000011b8, 0x00000000},
6203 + {0x000011f8, 0x00000000},
6204 + {0x00001238, 0x00000000},
6205 + {0x00001278, 0x00000000},
6206 + {0x000012b8, 0x00000000},
6207 + {0x000012f8, 0x00000000},
6208 + {0x00001338, 0x00000000},
6209 + {0x00001378, 0x00000000},
6210 + {0x000013b8, 0x00000000},
6211 + {0x000013f8, 0x00000000},
6212 + {0x00001438, 0x00000000},
6213 + {0x00001478, 0x00000000},
6214 + {0x000014b8, 0x00000000},
6215 + {0x000014f8, 0x00000000},
6216 + {0x00001538, 0x00000000},
6217 + {0x00001578, 0x00000000},
6218 + {0x000015b8, 0x00000000},
6219 + {0x000015f8, 0x00000000},
6220 + {0x00001638, 0x00000000},
6221 + {0x00001678, 0x00000000},
6222 + {0x000016b8, 0x00000000},
6223 + {0x000016f8, 0x00000000},
6224 + {0x00001738, 0x00000000},
6225 + {0x00001778, 0x00000000},
6226 + {0x000017b8, 0x00000000},
6227 + {0x000017f8, 0x00000000},
6228 + {0x0000103c, 0x00000000},
6229 + {0x0000107c, 0x00000000},
6230 + {0x000010bc, 0x00000000},
6231 + {0x000010fc, 0x00000000},
6232 + {0x0000113c, 0x00000000},
6233 + {0x0000117c, 0x00000000},
6234 + {0x000011bc, 0x00000000},
6235 + {0x000011fc, 0x00000000},
6236 + {0x0000123c, 0x00000000},
6237 + {0x0000127c, 0x00000000},
6238 + {0x000012bc, 0x00000000},
6239 + {0x000012fc, 0x00000000},
6240 + {0x0000133c, 0x00000000},
6241 + {0x0000137c, 0x00000000},
6242 + {0x000013bc, 0x00000000},
6243 + {0x000013fc, 0x00000000},
6244 + {0x0000143c, 0x00000000},
6245 + {0x0000147c, 0x00000000},
6246 + {0x00004030, 0x00000002},
6247 + {0x0000403c, 0x00000002},
6248 + {0x00004024, 0x0000001f},
6249 + {0x00004060, 0x00000000},
6250 + {0x00004064, 0x00000000},
6251 + {0x00007010, 0x00000033},
6252 + {0x00007034, 0x00000002},
6253 + {0x00007038, 0x000004c2},
6254 + {0x00008004, 0x00000000},
6255 + {0x00008008, 0x00000000},
6256 + {0x0000800c, 0x00000000},
6257 + {0x00008018, 0x00000700},
6258 + {0x00008020, 0x00000000},
6259 + {0x00008038, 0x00000000},
6260 + {0x0000803c, 0x00000000},
6261 + {0x00008048, 0x40000000},
6262 + {0x00008054, 0x00000000},
6263 + {0x00008058, 0x00000000},
6264 + {0x0000805c, 0x000fc78f},
6265 + {0x00008060, 0x0000000f},
6266 + {0x00008064, 0x00000000},
6267 + {0x00008070, 0x00000000},
6268 + {0x000080c0, 0x2a80001a},
6269 + {0x000080c4, 0x05dc01e0},
6270 + {0x000080c8, 0x1f402710},
6271 + {0x000080cc, 0x01f40000},
6272 + {0x000080d0, 0x00001e00},
6273 + {0x000080d4, 0x00000000},
6274 + {0x000080d8, 0x00400000},
6275 + {0x000080e0, 0xffffffff},
6276 + {0x000080e4, 0x0000ffff},
6277 + {0x000080e8, 0x003f3f3f},
6278 + {0x000080ec, 0x00000000},
6279 + {0x000080f0, 0x00000000},
6280 + {0x000080f4, 0x00000000},
6281 + {0x000080f8, 0x00000000},
6282 + {0x000080fc, 0x00020000},
6283 + {0x00008100, 0x00020000},
6284 + {0x00008104, 0x00000001},
6285 + {0x00008108, 0x00000052},
6286 + {0x0000810c, 0x00000000},
6287 + {0x00008110, 0x00000168},
6288 + {0x00008118, 0x000100aa},
6289 + {0x0000811c, 0x00003210},
6290 + {0x00008124, 0x00000000},
6291 + {0x00008128, 0x00000000},
6292 + {0x0000812c, 0x00000000},
6293 + {0x00008130, 0x00000000},
6294 + {0x00008134, 0x00000000},
6295 + {0x00008138, 0x00000000},
6296 + {0x0000813c, 0x00000000},
6297 + {0x00008144, 0xffffffff},
6298 + {0x00008168, 0x00000000},
6299 + {0x0000816c, 0x00000000},
6300 + {0x00008170, 0x32143320},
6301 + {0x00008174, 0xfaa4fa50},
6302 + {0x00008178, 0x00000100},
6303 + {0x0000817c, 0x00000000},
6304 + {0x000081c0, 0x00000000},
6305 + {0x000081ec, 0x00000000},
6306 + {0x000081f0, 0x00000000},
6307 + {0x000081f4, 0x00000000},
6308 + {0x000081f8, 0x00000000},
6309 + {0x000081fc, 0x00000000},
6310 + {0x00008200, 0x00000000},
6311 + {0x00008204, 0x00000000},
6312 + {0x00008208, 0x00000000},
6313 + {0x0000820c, 0x00000000},
6314 + {0x00008210, 0x00000000},
6315 + {0x00008214, 0x00000000},
6316 + {0x00008218, 0x00000000},
6317 + {0x0000821c, 0x00000000},
6318 + {0x00008220, 0x00000000},
6319 + {0x00008224, 0x00000000},
6320 + {0x00008228, 0x00000000},
6321 + {0x0000822c, 0x00000000},
6322 + {0x00008230, 0x00000000},
6323 + {0x00008234, 0x00000000},
6324 + {0x00008238, 0x00000000},
6325 + {0x0000823c, 0x00000000},
6326 + {0x00008240, 0x00100000},
6327 + {0x00008244, 0x0010f400},
6328 + {0x00008248, 0x00000100},
6329 + {0x0000824c, 0x0001e800},
6330 + {0x00008250, 0x00000000},
6331 + {0x00008254, 0x00000000},
6332 + {0x00008258, 0x00000000},
6333 + {0x0000825c, 0x400000ff},
6334 + {0x00008260, 0x00080922},
6335 + {0x00008264, 0xa8a00010},
6336 + {0x00008270, 0x00000000},
6337 + {0x00008274, 0x40000000},
6338 + {0x00008278, 0x003e4180},
6339 + {0x0000827c, 0x00000000},
6340 + {0x00008284, 0x0000002c},
6341 + {0x00008288, 0x0000002c},
6342 + {0x0000828c, 0x00000000},
6343 + {0x00008294, 0x00000000},
6344 + {0x00008298, 0x00000000},
6345 + {0x0000829c, 0x00000000},
6346 + {0x00008300, 0x00000040},
6347 + {0x00008314, 0x00000000},
6348 + {0x00008328, 0x00000000},
6349 + {0x0000832c, 0x00000007},
6350 + {0x00008330, 0x00000302},
6351 + {0x00008334, 0x00000e00},
6352 + {0x00008338, 0x00ff0000},
6353 + {0x0000833c, 0x00000000},
6354 + {0x00008340, 0x000107ff},
6355 + {0x00008344, 0x00481043},
6356 + {0x00009808, 0x00000000},
6357 + {0x0000980c, 0xafa68e30},
6358 + {0x00009810, 0xfd14e000},
6359 + {0x00009814, 0x9c0a9f6b},
6360 + {0x0000981c, 0x00000000},
6361 + {0x0000982c, 0x0000a000},
6362 + {0x00009830, 0x00000000},
6363 + {0x0000983c, 0x00200400},
6364 + {0x0000984c, 0x0040233c},
6365 + {0x0000a84c, 0x0040233c},
6366 + {0x00009854, 0x00000044},
6367 + {0x00009900, 0x00000000},
6368 + {0x00009904, 0x00000000},
6369 + {0x00009908, 0x00000000},
6370 + {0x0000990c, 0x00000000},
6371 + {0x00009910, 0x01002310},
6372 + {0x0000991c, 0x10000fff},
6373 + {0x00009920, 0x04900000},
6374 + {0x0000a920, 0x04900000},
6375 + {0x00009928, 0x00000001},
6376 + {0x0000992c, 0x00000004},
6377 + {0x00009934, 0x1e1f2022},
6378 + {0x00009938, 0x0a0b0c0d},
6379 + {0x0000993c, 0x00000000},
6380 + {0x00009948, 0x9280c00a},
6381 + {0x0000994c, 0x00020028},
6382 + {0x00009954, 0x5f3ca3de},
6383 + {0x00009958, 0x2108ecff},
6384 + {0x00009940, 0x14750604},
6385 + {0x0000c95c, 0x004b6a8e},
6386 + {0x00009970, 0x190fb515},
6387 + {0x00009974, 0x00000000},
6388 + {0x00009978, 0x00000001},
6389 + {0x0000997c, 0x00000000},
6390 + {0x00009980, 0x00000000},
6391 + {0x00009984, 0x00000000},
6392 + {0x00009988, 0x00000000},
6393 + {0x0000998c, 0x00000000},
6394 + {0x00009990, 0x00000000},
6395 + {0x00009994, 0x00000000},
6396 + {0x00009998, 0x00000000},
6397 + {0x0000999c, 0x00000000},
6398 + {0x000099a0, 0x00000000},
6399 + {0x000099a4, 0x00000001},
6400 + {0x000099a8, 0x201fff00},
6401 + {0x000099ac, 0x006f0000},
6402 + {0x000099b0, 0x03051000},
6403 + {0x000099b4, 0x00000820},
6404 + {0x000099dc, 0x00000000},
6405 + {0x000099e0, 0x00000000},
6406 + {0x000099e4, 0xaaaaaaaa},
6407 + {0x000099e8, 0x3c466478},
6408 + {0x000099ec, 0x0cc80caa},
6409 + {0x000099f0, 0x00000000},
6410 + {0x000099fc, 0x00001042},
6411 + {0x0000a208, 0x803e4788},
6412 + {0x0000a210, 0x4080a333},
6413 + {0x0000a214, 0x40206c10},
6414 + {0x0000a218, 0x009c4060},
6415 + {0x0000a220, 0x01834061},
6416 + {0x0000a224, 0x00000400},
6417 + {0x0000a228, 0x000003b5},
6418 + {0x0000a22c, 0x233f7180},
6419 + {0x0000a234, 0x20202020},
6420 + {0x0000a238, 0x20202020},
6421 + {0x0000a240, 0x38490a20},
6422 + {0x0000a244, 0x00007bb6},
6423 + {0x0000a248, 0x0fff3ffc},
6424 + {0x0000a24c, 0x00000000},
6425 + {0x0000a254, 0x00000000},
6426 + {0x0000a258, 0x0cdbd380},
6427 + {0x0000a25c, 0x0f0f0f01},
6428 + {0x0000a260, 0xdfa91f01},
6429 + {0x0000a268, 0x00000000},
6430 + {0x0000a26c, 0x0e79e5c6},
6431 + {0x0000b26c, 0x0e79e5c6},
6432 + {0x0000d270, 0x00820820},
6433 + {0x0000a278, 0x1ce739ce},
6434 + {0x0000d35c, 0x07ffffef},
6435 + {0x0000d360, 0x0fffffe7},
6436 + {0x0000d364, 0x17ffffe5},
6437 + {0x0000d368, 0x1fffffe4},
6438 + {0x0000d36c, 0x37ffffe3},
6439 + {0x0000d370, 0x3fffffe3},
6440 + {0x0000d374, 0x57ffffe3},
6441 + {0x0000d378, 0x5fffffe2},
6442 + {0x0000d37c, 0x7fffffe2},
6443 + {0x0000d380, 0x7f3c7bba},
6444 + {0x0000d384, 0xf3307ff0},
6445 + {0x0000a38c, 0x20202020},
6446 + {0x0000a390, 0x20202020},
6447 + {0x0000a394, 0x1ce739ce},
6448 + {0x0000a398, 0x000001ce},
6449 + {0x0000a39c, 0x00000001},
6450 + {0x0000a3a0, 0x00000000},
6451 + {0x0000a3a4, 0x00000000},
6452 + {0x0000a3a8, 0x00000000},
6453 + {0x0000a3ac, 0x00000000},
6454 + {0x0000a3b0, 0x00000000},
6455 + {0x0000a3b4, 0x00000000},
6456 + {0x0000a3b8, 0x00000000},
6457 + {0x0000a3bc, 0x00000000},
6458 + {0x0000a3c0, 0x00000000},
6459 + {0x0000a3c4, 0x00000000},
6460 + {0x0000a3c8, 0x00000246},
6461 + {0x0000a3cc, 0x20202020},
6462 + {0x0000a3d0, 0x20202020},
6463 + {0x0000a3d4, 0x20202020},
6464 + {0x0000a3dc, 0x1ce739ce},
6465 + {0x0000a3e0, 0x000001ce},
6466 + {0x0000a3e4, 0x00000000},
6467 + {0x0000a3e8, 0x18c43433},
6468 + {0x0000a3ec, 0x00f70081},
6469 + {0x00007800, 0x00040000},
6470 + {0x00007804, 0xdb005012},
6471 + {0x00007808, 0x04924914},
6472 + {0x0000780c, 0x21084210},
6473 + {0x00007810, 0x6d801300},
6474 + {0x00007818, 0x07e41000},
6475 + {0x00007824, 0x00040000},
6476 + {0x00007828, 0xdb005012},
6477 + {0x0000782c, 0x04924914},
6478 + {0x00007830, 0x21084210},
6479 + {0x00007834, 0x6d801300},
6480 + {0x0000783c, 0x07e40000},
6481 + {0x00007848, 0x00100000},
6482 + {0x0000784c, 0x773f0567},
6483 + {0x00007850, 0x54214514},
6484 + {0x00007854, 0x12035828},
6485 + {0x00007858, 0x9259269a},
6486 + {0x00007860, 0x52802000},
6487 + {0x00007864, 0x0a8e370e},
6488 + {0x00007868, 0xc0102850},
6489 + {0x0000786c, 0x812d4000},
6490 + {0x00007870, 0x807ec400},
6491 + {0x00007874, 0x001b6db0},
6492 + {0x00007878, 0x00376b63},
6493 + {0x0000787c, 0x06db6db6},
6494 + {0x00007880, 0x006d8000},
6495 + {0x00007884, 0xffeffffe},
6496 + {0x00007888, 0xffeffffe},
6497 + {0x0000788c, 0x00010000},
6498 + {0x00007890, 0x02060aeb},
6499 + {0x00007898, 0x2a850160},
6500 +};
6501 +
6502 +static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
6503 + {0x00001030, 0x00000268, 0x000004d0},
6504 + {0x00001070, 0x0000018c, 0x00000318},
6505 + {0x000010b0, 0x00000fd0, 0x00001fa0},
6506 + {0x00008014, 0x044c044c, 0x08980898},
6507 + {0x0000801c, 0x148ec02b, 0x148ec057},
6508 + {0x00008318, 0x000044c0, 0x00008980},
6509 + {0x00009820, 0x02020200, 0x02020200},
6510 + {0x00009824, 0x01000f0f, 0x01000f0f},
6511 + {0x00009828, 0x0b020001, 0x0b020001},
6512 + {0x00009834, 0x00000f0f, 0x00000f0f},
6513 + {0x00009844, 0x03721821, 0x03721821},
6514 + {0x00009914, 0x00000898, 0x00001130},
6515 + {0x00009918, 0x0000000b, 0x00000016},
6516 +};
6517 +
6518 +static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
6519 + {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290,
6520 + 0x00000290},
6521 + {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300,
6522 + 0x00000300},
6523 + {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304,
6524 + 0x00000304},
6525 + {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308,
6526 + 0x00000308},
6527 + {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c,
6528 + 0x0000030c},
6529 + {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000,
6530 + 0x00008000},
6531 + {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004,
6532 + 0x00008004},
6533 + {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008,
6534 + 0x00008008},
6535 + {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c,
6536 + 0x0000800c},
6537 + {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080,
6538 + 0x00008080},
6539 + {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084,
6540 + 0x00008084},
6541 + {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088,
6542 + 0x00008088},
6543 + {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c,
6544 + 0x0000808c},
6545 + {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100,
6546 + 0x00008100},
6547 + {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104,
6548 + 0x00008104},
6549 + {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108,
6550 + 0x00008108},
6551 + {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c,
6552 + 0x0000810c},
6553 + {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110,
6554 + 0x00008110},
6555 + {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114,
6556 + 0x00008114},
6557 + {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180,
6558 + 0x00008180},
6559 + {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184,
6560 + 0x00008184},
6561 + {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188,
6562 + 0x00008188},
6563 + {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c,
6564 + 0x0000818c},
6565 + {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190,
6566 + 0x00008190},
6567 + {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194,
6568 + 0x00008194},
6569 + {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0,
6570 + 0x000081a0},
6571 + {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c,
6572 + 0x0000820c},
6573 + {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8,
6574 + 0x000081a8},
6575 + {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284,
6576 + 0x00008284},
6577 + {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288,
6578 + 0x00008288},
6579 + {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224,
6580 + 0x00008224},
6581 + {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290,
6582 + 0x00008290},
6583 + {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300,
6584 + 0x00008300},
6585 + {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304,
6586 + 0x00008304},
6587 + {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308,
6588 + 0x00008308},
6589 + {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c,
6590 + 0x0000830c},
6591 + {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380,
6592 + 0x00008380},
6593 + {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384,
6594 + 0x00008384},
6595 + {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700,
6596 + 0x00008700},
6597 + {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704,
6598 + 0x00008704},
6599 + {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708,
6600 + 0x00008708},
6601 + {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c,
6602 + 0x0000870c},
6603 + {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780,
6604 + 0x00008780},
6605 + {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784,
6606 + 0x00008784},
6607 + {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00,
6608 + 0x00008b00},
6609 + {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04,
6610 + 0x00008b04},
6611 + {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08,
6612 + 0x00008b08},
6613 + {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c,
6614 + 0x00008b0c},
6615 + {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10,
6616 + 0x00008b10},
6617 + {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14,
6618 + 0x00008b14},
6619 + {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01,
6620 + 0x00008b01},
6621 + {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05,
6622 + 0x00008b05},
6623 + {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09,
6624 + 0x00008b09},
6625 + {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d,
6626 + 0x00008b0d},
6627 + {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11,
6628 + 0x00008b11},
6629 + {0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15,
6630 + 0x00008b15},
6631 + {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02,
6632 + 0x00008b02},
6633 + {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06,
6634 + 0x00008b06},
6635 + {0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a,
6636 + 0x00008b0a},
6637 + {0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e,
6638 + 0x00008b0e},
6639 + {0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12,
6640 + 0x00008b12},
6641 + {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16,
6642 + 0x00008b16},
6643 + {0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03,
6644 + 0x00008b03},
6645 + {0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07,
6646 + 0x00008b07},
6647 + {0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b,
6648 + 0x00008b0b},
6649 + {0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f,
6650 + 0x00008b0f},
6651 + {0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13,
6652 + 0x00008b13},
6653 + {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17,
6654 + 0x00008b17},
6655 + {0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23,
6656 + 0x00008b23},
6657 + {0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27,
6658 + 0x00008b27},
6659 + {0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b,
6660 + 0x00008b2b},
6661 + {0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f,
6662 + 0x00008b2f},
6663 + {0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33,
6664 + 0x00008b33},
6665 + {0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37,
6666 + 0x00008b37},
6667 + {0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43,
6668 + 0x00008b43},
6669 + {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47,
6670 + 0x00008b47},
6671 + {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b,
6672 + 0x00008b4b},
6673 + {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f,
6674 + 0x00008b4f},
6675 + {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53,
6676 + 0x00008b53},
6677 + {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57,
6678 + 0x00008b57},
6679 + {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b,
6680 + 0x00008b5b},
6681 + {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b,
6682 + 0x00008b5b},
6683 + {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b,
6684 + 0x00008b5b},
6685 + {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b,
6686 + 0x00008b5b},
6687 + {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b,
6688 + 0x00008b5b},
6689 + {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b,
6690 + 0x00008b5b},
6691 + {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b,
6692 + 0x00008b5b},
6693 + {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b,
6694 + 0x00008b5b},
6695 + {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b,
6696 + 0x00008b5b},
6697 + {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b,
6698 + 0x00008b5b},
6699 + {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b,
6700 + 0x00008b5b},
6701 + {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b,
6702 + 0x00008b5b},
6703 + {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b,
6704 + 0x00008b5b},
6705 + {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b,
6706 + 0x00008b5b},
6707 + {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b,
6708 + 0x00008b5b},
6709 + {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b,
6710 + 0x00008b5b},
6711 + {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b,
6712 + 0x00008b5b},
6713 + {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b,
6714 + 0x00008b5b},
6715 + {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b,
6716 + 0x00008b5b},
6717 + {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b,
6718 + 0x00008b5b},
6719 + {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b,
6720 + 0x00008b5b},
6721 + {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b,
6722 + 0x00008b5b},
6723 + {0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6724 + 0x00008b5b},
6725 + {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6726 + 0x00008b5b},
6727 + {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6728 + 0x00008b5b},
6729 + {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6730 + 0x00008b5b},
6731 + {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6732 + 0x00008b5b},
6733 + {0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6734 + 0x00008b5b},
6735 + {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6736 + 0x00008b5b},
6737 + {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6738 + 0x00008b5b},
6739 + {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6740 + 0x00008b5b},
6741 + {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6742 + 0x00008b5b},
6743 + {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6744 + 0x00008b5b},
6745 + {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6746 + 0x00008b5b},
6747 + {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6748 + 0x00008b5b},
6749 + {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6750 + 0x00008b5b},
6751 + {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6752 + 0x00008b5b},
6753 + {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6754 + 0x00008b5b},
6755 + {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6756 + 0x00008b5b},
6757 + {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6758 + 0x00008b5b},
6759 + {0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6760 + 0x00008b5b},
6761 + {0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6762 + 0x00008b5b},
6763 + {0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6764 + 0x00008b5b},
6765 + {0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6766 + 0x00008b5b},
6767 + {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6768 + 0x00008b5b},
6769 + {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6770 + 0x00008b5b},
6771 + {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6772 + 0x00008b5b},
6773 + {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b,
6774 + 0x00008b5b},
6775 + {0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050,
6776 + 0x00001050},
6777 + {0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050,
6778 + 0x00001050},
6779 +};
6780 +
6781 +static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
6782 + {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290,
6783 + 0x00000290},
6784 + {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300,
6785 + 0x00000300},
6786 + {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304,
6787 + 0x00000304},
6788 + {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308,
6789 + 0x00000308},
6790 + {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c,
6791 + 0x0000030c},
6792 + {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000,
6793 + 0x00008000},
6794 + {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004,
6795 + 0x00008004},
6796 + {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008,
6797 + 0x00008008},
6798 + {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c,
6799 + 0x0000800c},
6800 + {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080,
6801 + 0x00008080},
6802 + {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084,
6803 + 0x00008084},
6804 + {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088,
6805 + 0x00008088},
6806 + {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c,
6807 + 0x0000808c},
6808 + {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100,
6809 + 0x00008100},
6810 + {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104,
6811 + 0x00008104},
6812 + {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108,
6813 + 0x00008108},
6814 + {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c,
6815 + 0x0000810c},
6816 + {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110,
6817 + 0x00008110},
6818 + {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114,
6819 + 0x00008114},
6820 + {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180,
6821 + 0x00008180},
6822 + {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184,
6823 + 0x00008184},
6824 + {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188,
6825 + 0x00008188},
6826 + {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c,
6827 + 0x0000818c},
6828 + {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190,
6829 + 0x00008190},
6830 + {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194,
6831 + 0x00008194},
6832 + {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0,
6833 + 0x000081a0},
6834 + {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c,
6835 + 0x0000820c},
6836 + {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8,
6837 + 0x000081a8},
6838 + {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284,
6839 + 0x00008284},
6840 + {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288,
6841 + 0x00008288},
6842 + {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224,
6843 + 0x00008224},
6844 + {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290,
6845 + 0x00008290},
6846 + {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300,
6847 + 0x00008300},
6848 + {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304,
6849 + 0x00008304},
6850 + {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308,
6851 + 0x00008308},
6852 + {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c,
6853 + 0x0000830c},
6854 + {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380,
6855 + 0x00008380},
6856 + {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384,
6857 + 0x00008384},
6858 + {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700,
6859 + 0x00008700},
6860 + {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704,
6861 + 0x00008704},
6862 + {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708,
6863 + 0x00008708},
6864 + {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c,
6865 + 0x0000870c},
6866 + {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780,
6867 + 0x00008780},
6868 + {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784,
6869 + 0x00008784},
6870 + {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00,
6871 + 0x00008b00},
6872 + {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04,
6873 + 0x00008b04},
6874 + {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08,
6875 + 0x00008b08},
6876 + {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c,
6877 + 0x00008b0c},
6878 + {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80,
6879 + 0x00008b80},
6880 + {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84,
6881 + 0x00008b84},
6882 + {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88,
6883 + 0x00008b88},
6884 + {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c,
6885 + 0x00008b8c},
6886 + {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90,
6887 + 0x00008b90},
6888 + {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80,
6889 + 0x00008f80},
6890 + {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84,
6891 + 0x00008f84},
6892 + {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88,
6893 + 0x00008f88},
6894 + {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c,
6895 + 0x00008f8c},
6896 + {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90,
6897 + 0x00008f90},
6898 + {0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c,
6899 + 0x0000930c},
6900 + {0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310,
6901 + 0x00009310},
6902 + {0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384,
6903 + 0x00009384},
6904 + {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388,
6905 + 0x00009388},
6906 + {0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324,
6907 + 0x00009324},
6908 + {0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704,
6909 + 0x00009704},
6910 + {0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4,
6911 + 0x000096a4},
6912 + {0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8,
6913 + 0x000096a8},
6914 + {0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710,
6915 + 0x00009710},
6916 + {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714,
6917 + 0x00009714},
6918 + {0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720,
6919 + 0x00009720},
6920 + {0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724,
6921 + 0x00009724},
6922 + {0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728,
6923 + 0x00009728},
6924 + {0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c,
6925 + 0x0000972c},
6926 + {0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0,
6927 + 0x000097a0},
6928 + {0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4,
6929 + 0x000097a4},
6930 + {0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8,
6931 + 0x000097a8},
6932 + {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0,
6933 + 0x000097b0},
6934 + {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4,
6935 + 0x000097b4},
6936 + {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8,
6937 + 0x000097b8},
6938 + {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5,
6939 + 0x000097a5},
6940 + {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9,
6941 + 0x000097a9},
6942 + {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad,
6943 + 0x000097ad},
6944 + {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1,
6945 + 0x000097b1},
6946 + {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5,
6947 + 0x000097b5},
6948 + {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9,
6949 + 0x000097b9},
6950 + {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5,
6951 + 0x000097c5},
6952 + {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9,
6953 + 0x000097c9},
6954 + {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1,
6955 + 0x000097d1},
6956 + {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5,
6957 + 0x000097d5},
6958 + {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9,
6959 + 0x000097d9},
6960 + {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6,
6961 + 0x000097c6},
6962 + {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca,
6963 + 0x000097ca},
6964 + {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce,
6965 + 0x000097ce},
6966 + {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2,
6967 + 0x000097d2},
6968 + {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6,
6969 + 0x000097d6},
6970 + {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3,
6971 + 0x000097c3},
6972 + {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7,
6973 + 0x000097c7},
6974 + {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb,
6975 + 0x000097cb},
6976 + {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf,
6977 + 0x000097cf},
6978 + {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7,
6979 + 0x000097d7},
6980 + {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db,
6981 + 0x000097db},
6982 + {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db,
6983 + 0x000097db},
6984 + {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db,
6985 + 0x000097db},
6986 + {0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
6987 + 0x000097db},
6988 + {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
6989 + 0x000097db},
6990 + {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
6991 + 0x000097db},
6992 + {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
6993 + 0x000097db},
6994 + {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
6995 + 0x000097db},
6996 + {0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
6997 + 0x000097db},
6998 + {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
6999 + 0x000097db},
7000 + {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7001 + 0x000097db},
7002 + {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7003 + 0x000097db},
7004 + {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7005 + 0x000097db},
7006 + {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7007 + 0x000097db},
7008 + {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7009 + 0x000097db},
7010 + {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7011 + 0x000097db},
7012 + {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7013 + 0x000097db},
7014 + {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7015 + 0x000097db},
7016 + {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7017 + 0x000097db},
7018 + {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7019 + 0x000097db},
7020 + {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7021 + 0x000097db},
7022 + {0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7023 + 0x000097db},
7024 + {0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7025 + 0x000097db},
7026 + {0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7027 + 0x000097db},
7028 + {0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7029 + 0x000097db},
7030 + {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7031 + 0x000097db},
7032 + {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7033 + 0x000097db},
7034 + {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7035 + 0x000097db},
7036 + {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db,
7037 + 0x000097db},
7038 + {0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063,
7039 + 0x00001063},
7040 + {0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063,
7041 + 0x00001063},
7042 +};
7043 +
7044 +static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
7045 + {0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290,
7046 + 0x00000290},
7047 + {0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300,
7048 + 0x00000300},
7049 + {0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304,
7050 + 0x00000304},
7051 + {0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308,
7052 + 0x00000308},
7053 + {0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c,
7054 + 0x0000030c},
7055 + {0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000,
7056 + 0x00008000},
7057 + {0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004,
7058 + 0x00008004},
7059 + {0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008,
7060 + 0x00008008},
7061 + {0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c,
7062 + 0x0000800c},
7063 + {0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080,
7064 + 0x00008080},
7065 + {0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084,
7066 + 0x00008084},
7067 + {0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088,
7068 + 0x00008088},
7069 + {0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c,
7070 + 0x0000808c},
7071 + {0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100,
7072 + 0x00008100},
7073 + {0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104,
7074 + 0x00008104},
7075 + {0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108,
7076 + 0x00008108},
7077 + {0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c,
7078 + 0x0000810c},
7079 + {0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110,
7080 + 0x00008110},
7081 + {0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114,
7082 + 0x00008114},
7083 + {0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180,
7084 + 0x00008180},
7085 + {0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184,
7086 + 0x00008184},
7087 + {0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188,
7088 + 0x00008188},
7089 + {0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c,
7090 + 0x0000818c},
7091 + {0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190,
7092 + 0x00008190},
7093 + {0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194,
7094 + 0x00008194},
7095 + {0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0,
7096 + 0x000081a0},
7097 + {0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c,
7098 + 0x0000820c},
7099 + {0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8,
7100 + 0x000081a8},
7101 + {0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284,
7102 + 0x00008284},
7103 + {0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288,
7104 + 0x00008288},
7105 + {0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224,
7106 + 0x00008224},
7107 + {0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290,
7108 + 0x00008290},
7109 + {0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300,
7110 + 0x00008300},
7111 + {0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304,
7112 + 0x00008304},
7113 + {0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308,
7114 + 0x00008308},
7115 + {0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c,
7116 + 0x0000830c},
7117 + {0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380,
7118 + 0x00008380},
7119 + {0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384,
7120 + 0x00008384},
7121 + {0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700,
7122 + 0x00008700},
7123 + {0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704,
7124 + 0x00008704},
7125 + {0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708,
7126 + 0x00008708},
7127 + {0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c,
7128 + 0x0000870c},
7129 + {0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780,
7130 + 0x00008780},
7131 + {0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784,
7132 + 0x00008784},
7133 + {0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00,
7134 + 0x00008b00},
7135 + {0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04,
7136 + 0x00008b04},
7137 + {0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08,
7138 + 0x00008b08},
7139 + {0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c,
7140 + 0x00008b0c},
7141 + {0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80,
7142 + 0x00008b80},
7143 + {0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84,
7144 + 0x00008b84},
7145 + {0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88,
7146 + 0x00008b88},
7147 + {0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c,
7148 + 0x00008b8c},
7149 + {0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90,
7150 + 0x00008b90},
7151 + {0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80,
7152 + 0x00008f80},
7153 + {0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84,
7154 + 0x00008f84},
7155 + {0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88,
7156 + 0x00008f88},
7157 + {0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c,
7158 + 0x00008f8c},
7159 + {0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90,
7160 + 0x00008f90},
7161 + {0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310,
7162 + 0x00009310},
7163 + {0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314,
7164 + 0x00009314},
7165 + {0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320,
7166 + 0x00009320},
7167 + {0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324,
7168 + 0x00009324},
7169 + {0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328,
7170 + 0x00009328},
7171 + {0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c,
7172 + 0x0000932c},
7173 + {0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330,
7174 + 0x00009330},
7175 + {0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334,
7176 + 0x00009334},
7177 + {0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321,
7178 + 0x00009321},
7179 + {0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325,
7180 + 0x00009325},
7181 + {0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329,
7182 + 0x00009329},
7183 + {0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d,
7184 + 0x0000932d},
7185 + {0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331,
7186 + 0x00009331},
7187 + {0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335,
7188 + 0x00009335},
7189 + {0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322,
7190 + 0x00009322},
7191 + {0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326,
7192 + 0x00009326},
7193 + {0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a,
7194 + 0x0000932a},
7195 + {0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e,
7196 + 0x0000932e},
7197 + {0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332,
7198 + 0x00009332},
7199 + {0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336,
7200 + 0x00009336},
7201 + {0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323,
7202 + 0x00009323},
7203 + {0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327,
7204 + 0x00009327},
7205 + {0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b,
7206 + 0x0000932b},
7207 + {0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f,
7208 + 0x0000932f},
7209 + {0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333,
7210 + 0x00009333},
7211 + {0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337,
7212 + 0x00009337},
7213 + {0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343,
7214 + 0x00009343},
7215 + {0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347,
7216 + 0x00009347},
7217 + {0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b,
7218 + 0x0000934b},
7219 + {0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f,
7220 + 0x0000934f},
7221 + {0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353,
7222 + 0x00009353},
7223 + {0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357,
7224 + 0x00009357},
7225 + {0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b,
7226 + 0x0000935b},
7227 + {0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b,
7228 + 0x0000935b},
7229 + {0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b,
7230 + 0x0000935b},
7231 + {0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b,
7232 + 0x0000935b},
7233 + {0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b,
7234 + 0x0000935b},
7235 + {0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b,
7236 + 0x0000935b},
7237 + {0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b,
7238 + 0x0000935b},
7239 + {0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b,
7240 + 0x0000935b},
7241 + {0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b,
7242 + 0x0000935b},
7243 + {0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b,
7244 + 0x0000935b},
7245 + {0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b,
7246 + 0x0000935b},
7247 + {0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b,
7248 + 0x0000935b},
7249 + {0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7250 + 0x0000935b},
7251 + {0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7252 + 0x0000935b},
7253 + {0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7254 + 0x0000935b},
7255 + {0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7256 + 0x0000935b},
7257 + {0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7258 + 0x0000935b},
7259 + {0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7260 + 0x0000935b},
7261 + {0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7262 + 0x0000935b},
7263 + {0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7264 + 0x0000935b},
7265 + {0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7266 + 0x0000935b},
7267 + {0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7268 + 0x0000935b},
7269 + {0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7270 + 0x0000935b},
7271 + {0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7272 + 0x0000935b},
7273 + {0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7274 + 0x0000935b},
7275 + {0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7276 + 0x0000935b},
7277 + {0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7278 + 0x0000935b},
7279 + {0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7280 + 0x0000935b},
7281 + {0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7282 + 0x0000935b},
7283 + {0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7284 + 0x0000935b},
7285 + {0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7286 + 0x0000935b},
7287 + {0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7288 + 0x0000935b},
7289 + {0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7290 + 0x0000935b},
7291 + {0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7292 + 0x0000935b},
7293 + {0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7294 + 0x0000935b},
7295 + {0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7296 + 0x0000935b},
7297 + {0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7298 + 0x0000935b},
7299 + {0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b,
7300 + 0x0000935b},
7301 + {0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a,
7302 + 0x0000105a},
7303 + {0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a,
7304 + 0x0000105a},
7305 +};
7306 +
7307 +static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
7308 + {0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652,
7309 + 0x0a1aa652},
7310 + {0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce,
7311 + 0x050739ce},
7312 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7313 + 0x00000000},
7314 + {0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002,
7315 + 0x00004002},
7316 + {0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008,
7317 + 0x00007008},
7318 + {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010,
7319 + 0x0000c010},
7320 + {0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012,
7321 + 0x00010012},
7322 + {0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014,
7323 + 0x00013014},
7324 + {0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a,
7325 + 0x0001820a},
7326 + {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211,
7327 + 0x0001b211},
7328 + {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213,
7329 + 0x0001e213},
7330 + {0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411,
7331 + 0x00022411},
7332 + {0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413,
7333 + 0x00025413},
7334 + {0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811,
7335 + 0x00029811},
7336 + {0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813,
7337 + 0x0002c813},
7338 + {0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14,
7339 + 0x00030a14},
7340 + {0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50,
7341 + 0x00035a50},
7342 + {0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c,
7343 + 0x00039c4c},
7344 + {0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a,
7345 + 0x0003de8a},
7346 + {0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92,
7347 + 0x00042e92},
7348 + {0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2,
7349 + 0x00046ed2},
7350 + {0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5,
7351 + 0x0004bed5},
7352 + {0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54,
7353 + 0x0004ff54},
7354 + {0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5,
7355 + 0x00055fd5},
7356 + {0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff,
7357 + 0x00198eff},
7358 + {0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff,
7359 + 0x00198eff},
7360 + {0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000,
7361 + 0x00172000},
7362 + {0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000,
7363 + 0x00172000},
7364 + {0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480,
7365 + 0xf258a480},
7366 + {0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480,
7367 + 0xf258a480},
7368 +};
7369 +
7370 +static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
7371 + {0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652,
7372 + 0x0a1aa652},
7373 + {0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce,
7374 + 0x050701ce},
7375 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7376 + 0x00000000},
7377 + {0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002,
7378 + 0x00003002},
7379 + {0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009,
7380 + 0x00008009},
7381 + {0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b,
7382 + 0x0000b00b},
7383 + {0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012,
7384 + 0x0000e012},
7385 + {0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048,
7386 + 0x00012048},
7387 + {0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a,
7388 + 0x0001604a},
7389 + {0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211,
7390 + 0x0001a211},
7391 + {0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213,
7392 + 0x0001e213},
7393 + {0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b,
7394 + 0x0002121b},
7395 + {0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412,
7396 + 0x00024412},
7397 + {0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414,
7398 + 0x00028414},
7399 + {0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a,
7400 + 0x0002b44a},
7401 + {0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649,
7402 + 0x00030649},
7403 + {0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b,
7404 + 0x0003364b},
7405 + {0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49,
7406 + 0x00038a49},
7407 + {0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48,
7408 + 0x0003be48},
7409 + {0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a,
7410 + 0x0003ee4a},
7411 + {0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88,
7412 + 0x00042e88},
7413 + {0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a,
7414 + 0x00046e8a},
7415 + {0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9,
7416 + 0x00049ec9},
7417 + {0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42,
7418 + 0x0004bf42},
7419 + {0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff,
7420 + 0x0019beff},
7421 + {0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff,
7422 + 0x0019beff},
7423 + {0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000,
7424 + 0x00392000},
7425 + {0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000,
7426 + 0x00392000},
7427 + {0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480,
7428 + 0x92592480},
7429 + {0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480,
7430 + 0x92592480},
7431 +};
7432 +
7433 +static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
7434 + {0x00004040, 0x9248fd00},
7435 + {0x00004040, 0x24924924},
7436 + {0x00004040, 0xa8000019},
7437 + {0x00004040, 0x13160820},
7438 + {0x00004040, 0xe5980560},
7439 + {0x00004040, 0xc01dcffc},
7440 + {0x00004040, 0x1aaabe41},
7441 + {0x00004040, 0xbe105554},
7442 + {0x00004040, 0x00043007},
7443 + {0x00004044, 0x00000000},
7444 +};
7445 +
7446 +static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
7447 + {0x00004040, 0x9248fd00},
7448 + {0x00004040, 0x24924924},
7449 + {0x00004040, 0xa8000019},
7450 + {0x00004040, 0x13160820},
7451 + {0x00004040, 0xe5980560},
7452 + {0x00004040, 0xc01dcffd},
7453 + {0x00004040, 0x1aaabe41},
7454 + {0x00004040, 0xbe105554},
7455 + {0x00004040, 0x00043007},
7456 + {0x00004044, 0x00000000},
7457 +};
7458 +
7459 +/* AR9285 Revsion 10*/
7460 +static const u_int32_t ar9285Modes_9285[][6] = {
7461 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
7462 + 0x000001e0},
7463 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
7464 + 0x000001e0},
7465 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
7466 + 0x00001180},
7467 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7468 + 0x00000008},
7469 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
7470 + 0x06e006e0},
7471 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
7472 + 0x0988004f},
7473 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440,
7474 + 0x00006880},
7475 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
7476 + 0x00000303},
7477 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
7478 + 0x02020200},
7479 + {0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
7480 + 0x00000e0e},
7481 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
7482 + 0x0a020001},
7483 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
7484 + 0x00000e0e},
7485 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
7486 + 0x00000007},
7487 + {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e,
7488 + 0x206a012e},
7489 + {0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020,
7490 + 0x037216a0},
7491 + {0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e,
7492 + 0x00001059},
7493 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
7494 + 0x6d4000e2},
7495 + {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e,
7496 + 0x7ec84d2e},
7497 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e,
7498 + 0x3139605e},
7499 + {0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20,
7500 + 0x00058d18},
7501 + {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00,
7502 + 0x0001ce00},
7503 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
7504 + 0x5ac640d0},
7505 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
7506 + 0x06903881},
7507 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
7508 + 0x000007d0},
7509 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
7510 + 0x00000016},
7511 + {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d,
7512 + 0xd00a800d},
7513 + {0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020,
7514 + 0xdfbc1010},
7515 + {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7516 + 0x00000000},
7517 + {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7518 + 0x00000000},
7519 + {0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c,
7520 + 0x00cf4d1c},
7521 + {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00,
7522 + 0x00000c00},
7523 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
7524 + 0x05eea6d4},
7525 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
7526 + 0x06336f77},
7527 + {0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329,
7528 + 0x60f65329},
7529 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
7530 + 0x08f186c8},
7531 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
7532 + 0x00046384},
7533 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7534 + 0x00000000},
7535 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
7536 + 0x00000000},
7537 + {0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084,
7538 + 0x00000000},
7539 + {0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088,
7540 + 0x00000000},
7541 + {0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c,
7542 + 0x00000000},
7543 + {0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100,
7544 + 0x00000000},
7545 + {0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104,
7546 + 0x00000000},
7547 + {0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108,
7548 + 0x00000000},
7549 + {0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c,
7550 + 0x00000000},
7551 + {0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110,
7552 + 0x00000000},
7553 + {0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114,
7554 + 0x00000000},
7555 + {0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180,
7556 + 0x00000000},
7557 + {0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184,
7558 + 0x00000000},
7559 + {0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188,
7560 + 0x00000000},
7561 + {0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c,
7562 + 0x00000000},
7563 + {0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190,
7564 + 0x00000000},
7565 + {0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194,
7566 + 0x00000000},
7567 + {0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0,
7568 + 0x00000000},
7569 + {0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c,
7570 + 0x00000000},
7571 + {0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8,
7572 + 0x00000000},
7573 + {0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284,
7574 + 0x00000000},
7575 + {0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288,
7576 + 0x00000000},
7577 + {0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220,
7578 + 0x00000000},
7579 + {0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290,
7580 + 0x00000000},
7581 + {0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300,
7582 + 0x00000000},
7583 + {0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304,
7584 + 0x00000000},
7585 + {0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308,
7586 + 0x00000000},
7587 + {0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c,
7588 + 0x00000000},
7589 + {0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380,
7590 + 0x00000000},
7591 + {0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384,
7592 + 0x00000000},
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7961 + {0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce,
7962 + 0x00000000},
7963 + {0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2,
7964 + 0x00000000},
7965 + {0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6,
7966 + 0x00000000},
7967 + {0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3,
7968 + 0x00000000},
7969 + {0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb,
7970 + 0x00000000},
7971 + {0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7972 + 0x00000000},
7973 + {0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7974 + 0x00000000},
7975 + {0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7976 + 0x00000000},
7977 + {0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7978 + 0x00000000},
7979 + {0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7980 + 0x00000000},
7981 + {0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7982 + 0x00000000},
7983 + {0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7984 + 0x00000000},
7985 + {0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7986 + 0x00000000},
7987 + {0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7988 + 0x00000000},
7989 + {0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7990 + 0x00000000},
7991 + {0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7992 + 0x00000000},
7993 + {0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7994 + 0x00000000},
7995 + {0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7996 + 0x00000000},
7997 + {0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
7998 + 0x00000000},
7999 + {0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8000 + 0x00000000},
8001 + {0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8002 + 0x00000000},
8003 + {0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8004 + 0x00000000},
8005 + {0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8006 + 0x00000000},
8007 + {0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8008 + 0x00000000},
8009 + {0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8010 + 0x00000000},
8011 + {0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8012 + 0x00000000},
8013 + {0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8014 + 0x00000000},
8015 + {0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8016 + 0x00000000},
8017 + {0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8018 + 0x00000000},
8019 + {0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8020 + 0x00000000},
8021 + {0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8022 + 0x00000000},
8023 + {0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8024 + 0x00000000},
8025 + {0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8026 + 0x00000000},
8027 + {0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8028 + 0x00000000},
8029 + {0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8030 + 0x00000000},
8031 + {0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8032 + 0x00000000},
8033 + {0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8034 + 0x00000000},
8035 + {0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8036 + 0x00000000},
8037 + {0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8038 + 0x00000000},
8039 + {0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8040 + 0x00000000},
8041 + {0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8042 + 0x00000000},
8043 + {0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8044 + 0x00000000},
8045 + {0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8046 + 0x00000000},
8047 + {0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3,
8048 + 0x00000000},
8049 + {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004,
8050 + 0x00000004},
8051 + {0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000,
8052 + 0x0001f000},
8053 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
8054 + 0x1883800a},
8055 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
8056 + 0x00000000},
8057 + {0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000,
8058 + 0x001da000},
8059 + {0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652,
8060 + 0x0a82a652},
8061 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8062 + 0x00000000},
8063 + {0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201,
8064 + 0x00000000},
8065 + {0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408,
8066 + 0x00000000},
8067 + {0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a,
8068 + 0x00000000},
8069 + {0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818,
8070 + 0x00000000},
8071 + {0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858,
8072 + 0x00000000},
8073 + {0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859,
8074 + 0x00000000},
8075 + {0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b,
8076 + 0x00000000},
8077 + {0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a,
8078 + 0x00000000},
8079 + {0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b,
8080 + 0x00000000},
8081 + {0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c,
8082 + 0x00000000},
8083 + {0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d,
8084 + 0x00000000},
8085 + {0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e,
8086 + 0x00000000},
8087 + {0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de,
8088 + 0x00000000},
8089 + {0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e,
8090 + 0x00000000},
8091 + {0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e,
8092 + 0x00000000},
8093 + {0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df,
8094 + 0x00000000},
8095 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
8096 + 0x00000000},
8097 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
8098 + 0x7999aa0e},
8099 +};
8100 +
8101 +static const u_int32_t ar9285Common_9285[][2] = {
8102 + {0x0000000c, 0x00000000},
8103 + {0x00000030, 0x00020045},
8104 + {0x00000034, 0x00000005},
8105 + {0x00000040, 0x00000000},
8106 + {0x00000044, 0x00000008},
8107 + {0x00000048, 0x00000008},
8108 + {0x0000004c, 0x00000010},
8109 + {0x00000050, 0x00000000},
8110 + {0x00000054, 0x0000001f},
8111 + {0x00000800, 0x00000000},
8112 + {0x00000804, 0x00000000},
8113 + {0x00000808, 0x00000000},
8114 + {0x0000080c, 0x00000000},
8115 + {0x00000810, 0x00000000},
8116 + {0x00000814, 0x00000000},
8117 + {0x00000818, 0x00000000},
8118 + {0x0000081c, 0x00000000},
8119 + {0x00000820, 0x00000000},
8120 + {0x00000824, 0x00000000},
8121 + {0x00001040, 0x002ffc0f},
8122 + {0x00001044, 0x002ffc0f},
8123 + {0x00001048, 0x002ffc0f},
8124 + {0x0000104c, 0x002ffc0f},
8125 + {0x00001050, 0x002ffc0f},
8126 + {0x00001054, 0x002ffc0f},
8127 + {0x00001058, 0x002ffc0f},
8128 + {0x0000105c, 0x002ffc0f},
8129 + {0x00001060, 0x002ffc0f},
8130 + {0x00001064, 0x002ffc0f},
8131 + {0x00001230, 0x00000000},
8132 + {0x00001270, 0x00000000},
8133 + {0x00001038, 0x00000000},
8134 + {0x00001078, 0x00000000},
8135 + {0x000010b8, 0x00000000},
8136 + {0x000010f8, 0x00000000},
8137 + {0x00001138, 0x00000000},
8138 + {0x00001178, 0x00000000},
8139 + {0x000011b8, 0x00000000},
8140 + {0x000011f8, 0x00000000},
8141 + {0x00001238, 0x00000000},
8142 + {0x00001278, 0x00000000},
8143 + {0x000012b8, 0x00000000},
8144 + {0x000012f8, 0x00000000},
8145 + {0x00001338, 0x00000000},
8146 + {0x00001378, 0x00000000},
8147 + {0x000013b8, 0x00000000},
8148 + {0x000013f8, 0x00000000},
8149 + {0x00001438, 0x00000000},
8150 + {0x00001478, 0x00000000},
8151 + {0x000014b8, 0x00000000},
8152 + {0x000014f8, 0x00000000},
8153 + {0x00001538, 0x00000000},
8154 + {0x00001578, 0x00000000},
8155 + {0x000015b8, 0x00000000},
8156 + {0x000015f8, 0x00000000},
8157 + {0x00001638, 0x00000000},
8158 + {0x00001678, 0x00000000},
8159 + {0x000016b8, 0x00000000},
8160 + {0x000016f8, 0x00000000},
8161 + {0x00001738, 0x00000000},
8162 + {0x00001778, 0x00000000},
8163 + {0x000017b8, 0x00000000},
8164 + {0x000017f8, 0x00000000},
8165 + {0x0000103c, 0x00000000},
8166 + {0x0000107c, 0x00000000},
8167 + {0x000010bc, 0x00000000},
8168 + {0x000010fc, 0x00000000},
8169 + {0x0000113c, 0x00000000},
8170 + {0x0000117c, 0x00000000},
8171 + {0x000011bc, 0x00000000},
8172 + {0x000011fc, 0x00000000},
8173 + {0x0000123c, 0x00000000},
8174 + {0x0000127c, 0x00000000},
8175 + {0x000012bc, 0x00000000},
8176 + {0x000012fc, 0x00000000},
8177 + {0x0000133c, 0x00000000},
8178 + {0x0000137c, 0x00000000},
8179 + {0x000013bc, 0x00000000},
8180 + {0x000013fc, 0x00000000},
8181 + {0x0000143c, 0x00000000},
8182 + {0x0000147c, 0x00000000},
8183 + {0x00004030, 0x00000002},
8184 + {0x0000403c, 0x00000002},
8185 + {0x00004024, 0x0000001f},
8186 + {0x00004060, 0x00000000},
8187 + {0x00004064, 0x00000000},
8188 + {0x00007010, 0x00000031},
8189 + {0x00007034, 0x00000002},
8190 + {0x00007038, 0x000004c2},
8191 + {0x00008004, 0x00000000},
8192 + {0x00008008, 0x00000000},
8193 + {0x0000800c, 0x00000000},
8194 + {0x00008018, 0x00000700},
8195 + {0x00008020, 0x00000000},
8196 + {0x00008038, 0x00000000},
8197 + {0x0000803c, 0x00000000},
8198 + {0x00008048, 0x00000000},
8199 + {0x00008054, 0x00000000},
8200 + {0x00008058, 0x00000000},
8201 + {0x0000805c, 0x000fc78f},
8202 + {0x00008060, 0x0000000f},
8203 + {0x00008064, 0x00000000},
8204 + {0x00008070, 0x00000000},
8205 + {0x000080c0, 0x2a80001a},
8206 + {0x000080c4, 0x05dc01e0},
8207 + {0x000080c8, 0x1f402710},
8208 + {0x000080cc, 0x01f40000},
8209 + {0x000080d0, 0x00001e00},
8210 + {0x000080d4, 0x00000000},
8211 + {0x000080d8, 0x00400000},
8212 + {0x000080e0, 0xffffffff},
8213 + {0x000080e4, 0x0000ffff},
8214 + {0x000080e8, 0x003f3f3f},
8215 + {0x000080ec, 0x00000000},
8216 + {0x000080f0, 0x00000000},
8217 + {0x000080f4, 0x00000000},
8218 + {0x000080f8, 0x00000000},
8219 + {0x000080fc, 0x00020000},
8220 + {0x00008100, 0x00020000},
8221 + {0x00008104, 0x00000001},
8222 + {0x00008108, 0x00000052},
8223 + {0x0000810c, 0x00000000},
8224 + {0x00008110, 0x00000168},
8225 + {0x00008118, 0x000100aa},
8226 + {0x0000811c, 0x00003210},
8227 + {0x00008120, 0x08f04800},
8228 + {0x00008124, 0x00000000},
8229 + {0x00008128, 0x00000000},
8230 + {0x0000812c, 0x00000000},
8231 + {0x00008130, 0x00000000},
8232 + {0x00008134, 0x00000000},
8233 + {0x00008138, 0x00000000},
8234 + {0x0000813c, 0x00000000},
8235 + {0x00008144, 0x00000000},
8236 + {0x00008168, 0x00000000},
8237 + {0x0000816c, 0x00000000},
8238 + {0x00008170, 0x32143320},
8239 + {0x00008174, 0xfaa4fa50},
8240 + {0x00008178, 0x00000100},
8241 + {0x0000817c, 0x00000000},
8242 + {0x000081c0, 0x00000000},
8243 + {0x000081d0, 0x00003210},
8244 + {0x000081ec, 0x00000000},
8245 + {0x000081f0, 0x00000000},
8246 + {0x000081f4, 0x00000000},
8247 + {0x000081f8, 0x00000000},
8248 + {0x000081fc, 0x00000000},
8249 + {0x00008200, 0x00000000},
8250 + {0x00008204, 0x00000000},
8251 + {0x00008208, 0x00000000},
8252 + {0x0000820c, 0x00000000},
8253 + {0x00008210, 0x00000000},
8254 + {0x00008214, 0x00000000},
8255 + {0x00008218, 0x00000000},
8256 + {0x0000821c, 0x00000000},
8257 + {0x00008220, 0x00000000},
8258 + {0x00008224, 0x00000000},
8259 + {0x00008228, 0x00000000},
8260 + {0x0000822c, 0x00000000},
8261 + {0x00008230, 0x00000000},
8262 + {0x00008234, 0x00000000},
8263 + {0x00008238, 0x00000000},
8264 + {0x0000823c, 0x00000000},
8265 + {0x00008240, 0x00100000},
8266 + {0x00008244, 0x0010f400},
8267 + {0x00008248, 0x00000100},
8268 + {0x0000824c, 0x0001e800},
8269 + {0x00008250, 0x00000000},
8270 + {0x00008254, 0x00000000},
8271 + {0x00008258, 0x00000000},
8272 + {0x0000825c, 0x400000ff},
8273 + {0x00008260, 0x00080922},
8274 + {0x00008264, 0xa8a00010},
8275 + {0x00008270, 0x00000000},
8276 + {0x00008274, 0x40000000},
8277 + {0x00008278, 0x003e4180},
8278 + {0x0000827c, 0x00000000},
8279 + {0x00008284, 0x0000002c},
8280 + {0x00008288, 0x0000002c},
8281 + {0x0000828c, 0x00000000},
8282 + {0x00008294, 0x00000000},
8283 + {0x00008298, 0x00000000},
8284 + {0x0000829c, 0x00000000},
8285 + {0x00008300, 0x00000040},
8286 + {0x00008314, 0x00000000},
8287 + {0x00008328, 0x00000000},
8288 + {0x0000832c, 0x00000001},
8289 + {0x00008330, 0x00000302},
8290 + {0x00008334, 0x00000e00},
8291 + {0x00008338, 0x00000000},
8292 + {0x0000833c, 0x00000000},
8293 + {0x00008340, 0x00010380},
8294 + {0x00008344, 0x00481043},
8295 + {0x00009808, 0x00000000},
8296 + {0x0000980c, 0xafe68e30},
8297 + {0x00009810, 0xfd14e000},
8298 + {0x00009814, 0x9c0a9f6b},
8299 + {0x0000981c, 0x00000000},
8300 + {0x0000982c, 0x0000a000},
8301 + {0x00009830, 0x00000000},
8302 + {0x0000983c, 0x00200400},
8303 + {0x0000984c, 0x0040233c},
8304 + {0x00009854, 0x00000044},
8305 + {0x00009900, 0x00000000},
8306 + {0x00009904, 0x00000000},
8307 + {0x00009908, 0x00000000},
8308 + {0x0000990c, 0x00000000},
8309 + {0x00009910, 0x01002310},
8310 + {0x0000991c, 0x10000fff},
8311 + {0x00009920, 0x04900000},
8312 + {0x00009928, 0x00000001},
8313 + {0x0000992c, 0x00000004},
8314 + {0x00009934, 0x1e1f2022},
8315 + {0x00009938, 0x0a0b0c0d},
8316 + {0x0000993c, 0x00000000},
8317 + {0x00009940, 0x14750604},
8318 + {0x00009948, 0x9280c00a},
8319 + {0x0000994c, 0x00020028},
8320 + {0x00009954, 0x5f3ca3de},
8321 + {0x00009958, 0x2108ecff},
8322 + {0x00009968, 0x000003ce},
8323 + {0x00009970, 0x1927b515},
8324 + {0x00009974, 0x00000000},
8325 + {0x00009978, 0x00000001},
8326 + {0x0000997c, 0x00000000},
8327 + {0x00009980, 0x00000000},
8328 + {0x00009984, 0x00000000},
8329 + {0x00009988, 0x00000000},
8330 + {0x0000998c, 0x00000000},
8331 + {0x00009990, 0x00000000},
8332 + {0x00009994, 0x00000000},
8333 + {0x00009998, 0x00000000},
8334 + {0x0000999c, 0x00000000},
8335 + {0x000099a0, 0x00000000},
8336 + {0x000099a4, 0x00000001},
8337 + {0x000099a8, 0x201fff00},
8338 + {0x000099ac, 0x2def0a00},
8339 + {0x000099b0, 0x03051000},
8340 + {0x000099b4, 0x00000820},
8341 + {0x000099dc, 0x00000000},
8342 + {0x000099e0, 0x00000000},
8343 + {0x000099e4, 0xaaaaaaaa},
8344 + {0x000099e8, 0x3c466478},
8345 + {0x000099ec, 0x0cc80caa},
8346 + {0x000099f0, 0x00000000},
8347 + {0x0000a208, 0x803e6788},
8348 + {0x0000a210, 0x4080a333},
8349 + {0x0000a214, 0x00206c10},
8350 + {0x0000a218, 0x009c4060},
8351 + {0x0000a220, 0x01834061},
8352 + {0x0000a224, 0x00000400},
8353 + {0x0000a228, 0x000003b5},
8354 + {0x0000a22c, 0x00000000},
8355 + {0x0000a234, 0x20202020},
8356 + {0x0000a238, 0x20202020},
8357 + {0x0000a244, 0x00000000},
8358 + {0x0000a248, 0xfffffffc},
8359 + {0x0000a24c, 0x00000000},
8360 + {0x0000a254, 0x00000000},
8361 + {0x0000a258, 0x0ccb5380},
8362 + {0x0000a25c, 0x15151501},
8363 + {0x0000a260, 0xdfa90f01},
8364 + {0x0000a268, 0x00000000},
8365 + {0x0000a26c, 0x0ebae9e6},
8366 + {0x0000d270, 0x0d820820},
8367 + {0x0000a278, 0x39ce739c},
8368 + {0x0000a27c, 0x050e039c},
8369 + {0x0000d35c, 0x07ffffef},
8370 + {0x0000d360, 0x0fffffe7},
8371 + {0x0000d364, 0x17ffffe5},
8372 + {0x0000d368, 0x1fffffe4},
8373 + {0x0000d36c, 0x37ffffe3},
8374 + {0x0000d370, 0x3fffffe3},
8375 + {0x0000d374, 0x57ffffe3},
8376 + {0x0000d378, 0x5fffffe2},
8377 + {0x0000d37c, 0x7fffffe2},
8378 + {0x0000d380, 0x7f3c7bba},
8379 + {0x0000d384, 0xf3307ff0},
8380 + {0x0000a388, 0x0c000000},
8381 + {0x0000a38c, 0x20202020},
8382 + {0x0000a390, 0x20202020},
8383 + {0x0000a394, 0x39ce739c},
8384 + {0x0000a398, 0x0000039c},
8385 + {0x0000a39c, 0x00000001},
8386 + {0x0000a3a0, 0x00000000},
8387 + {0x0000a3a4, 0x00000000},
8388 + {0x0000a3a8, 0x00000000},
8389 + {0x0000a3ac, 0x00000000},
8390 + {0x0000a3b0, 0x00000000},
8391 + {0x0000a3b4, 0x00000000},
8392 + {0x0000a3b8, 0x00000000},
8393 + {0x0000a3bc, 0x00000000},
8394 + {0x0000a3c0, 0x00000000},
8395 + {0x0000a3c4, 0x00000000},
8396 + {0x0000a3cc, 0x20202020},
8397 + {0x0000a3d0, 0x20202020},
8398 + {0x0000a3d4, 0x20202020},
8399 + {0x0000a3dc, 0x39ce739c},
8400 + {0x0000a3e0, 0x0000039c},
8401 + {0x0000a3e4, 0x00000000},
8402 + {0x0000a3e8, 0x18c43433},
8403 + {0x0000a3ec, 0x00f70081},
8404 + {0x00007800, 0x00140000},
8405 + {0x00007804, 0x0e4548d8},
8406 + {0x00007808, 0x54214514},
8407 + {0x0000780c, 0x02025820},
8408 + {0x00007810, 0x71c0d388},
8409 + {0x00007814, 0x924934a8},
8410 + {0x0000781c, 0x00000000},
8411 + {0x00007820, 0x00000c04},
8412 + {0x00007824, 0x00d86fff},
8413 + {0x00007828, 0x26d2491b},
8414 + {0x0000782c, 0x6e36d97b},
8415 + {0x00007830, 0xedb6d96c},
8416 + {0x00007834, 0x71400086},
8417 + {0x00007838, 0xfac68800},
8418 + {0x0000783c, 0x0001fffe},
8419 + {0x00007840, 0xffeb1a20},
8420 + {0x00007844, 0x000c0db6},
8421 + {0x00007848, 0x6db61b6f},
8422 + {0x0000784c, 0x6d9b66db},
8423 + {0x00007850, 0x6d8c6dba},
8424 + {0x00007854, 0x00040000},
8425 + {0x00007858, 0xdb003012},
8426 + {0x0000785c, 0x04924914},
8427 + {0x00007860, 0x21084210},
8428 + {0x00007864, 0xf7d7ffde},
8429 + {0x00007868, 0xc2034080},
8430 + {0x0000786c, 0x48609eb4},
8431 + {0x00007870, 0x10142c00},
8432 +};
8433 +
8434 +static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
8435 + {0x00004040, 0x9248fd00},
8436 + {0x00004040, 0x24924924},
8437 + {0x00004040, 0xa8000019},
8438 + {0x00004040, 0x13160820},
8439 + {0x00004040, 0xe5980560},
8440 + {0x00004040, 0xc01dcffd},
8441 + {0x00004040, 0x1aaabe41},
8442 + {0x00004040, 0xbe105554},
8443 + {0x00004040, 0x00043007},
8444 + {0x00004044, 0x00000000},
8445 +};
8446 +
8447 +static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
8448 + {0x00004040, 0x9248fd00},
8449 + {0x00004040, 0x24924924},
8450 + {0x00004040, 0xa8000019},
8451 + {0x00004040, 0x13160820},
8452 + {0x00004040, 0xe5980560},
8453 + {0x00004040, 0xc01dcffc},
8454 + {0x00004040, 0x1aaabe41},
8455 + {0x00004040, 0xbe105554},
8456 + {0x00004040, 0x00043007},
8457 + {0x00004044, 0x00000000},
8458 +};
8459 +
8460 +/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
8461 +static const u_int32_t ar9285Modes_9285_1_2[][6] = {
8462 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
8463 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
8464 + 0x000001e0},
8465 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
8466 + 0x000001e0},
8467 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
8468 + 0x00001180},
8469 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8470 + 0x00000008},
8471 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
8472 + 0x06e006e0},
8473 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
8474 + 0x0988004f},
8475 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440,
8476 + 0x00006880},
8477 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
8478 + 0x00000303},
8479 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
8480 + 0x02020200},
8481 + {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e,
8482 + 0x01000e0e},
8483 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
8484 + 0x0a020001},
8485 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
8486 + 0x00000e0e},
8487 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
8488 + 0x00000007},
8489 + {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e,
8490 + 0x206a012e},
8491 + {0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620,
8492 + 0x037216a0},
8493 + {0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053,
8494 + 0x00001059},
8495 + {0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053,
8496 + 0x00001059},
8497 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
8498 + 0x6d4000e2},
8499 + {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e,
8500 + 0x7ec84d2e},
8501 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e,
8502 + 0x3139605e},
8503 + {0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20,
8504 + 0x00058d18},
8505 + {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00,
8506 + 0x0001ce00},
8507 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
8508 + 0x5ac640d0},
8509 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
8510 + 0x06903881},
8511 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
8512 + 0x000007d0},
8513 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
8514 + 0x00000016},
8515 + {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d,
8516 + 0xd00a800d},
8517 + {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020,
8518 + 0xffbc1010},
8519 + {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8520 + 0x00000000},
8521 + {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8522 + 0x00000000},
8523 + {0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c,
8524 + 0x0000421c},
8525 + {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00,
8526 + 0x00000c00},
8527 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
8528 + 0x05eea6d4},
8529 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
8530 + 0x06336f77},
8531 + {0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f,
8532 + 0x6af6532f},
8533 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
8534 + 0x08f186c8},
8535 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
8536 + 0x00046384},
8537 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8538 + 0x00000000},
8539 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
8540 + 0x00000000},
8541 + {0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084,
8542 + 0x00000000},
8543 + {0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088,
8544 + 0x00000000},
8545 + {0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c,
8546 + 0x00000000},
8547 + {0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100,
8548 + 0x00000000},
8549 + {0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104,
8550 + 0x00000000},
8551 + {0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108,
8552 + 0x00000000},
8553 + {0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c,
8554 + 0x00000000},
8555 + {0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110,
8556 + 0x00000000},
8557 + {0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114,
8558 + 0x00000000},
8559 + {0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180,
8560 + 0x00000000},
8561 + {0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184,
8562 + 0x00000000},
8563 + {0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188,
8564 + 0x00000000},
8565 + {0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c,
8566 + 0x00000000},
8567 + {0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190,
8568 + 0x00000000},
8569 + {0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194,
8570 + 0x00000000},
8571 + {0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0,
8572 + 0x00000000},
8573 + {0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c,
8574 + 0x00000000},
8575 + {0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8,
8576 + 0x00000000},
8577 + {0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284,
8578 + 0x00000000},
8579 + {0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288,
8580 + 0x00000000},
8581 + {0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224,
8582 + 0x00000000},
8583 + {0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290,
8584 + 0x00000000},
8585 + {0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300,
8586 + 0x00000000},
8587 + {0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304,
8588 + 0x00000000},
8589 + {0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308,
8590 + 0x00000000},
8591 + {0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c,
8592 + 0x00000000},
8593 + {0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380,
8594 + 0x00000000},
8595 + {0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384,
8596 + 0x00000000},
8597 + {0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700,
8598 + 0x00000000},
8599 + {0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704,
8600 + 0x00000000},
8601 + {0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708,
8602 + 0x00000000},
8603 + {0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c,
8604 + 0x00000000},
8605 + {0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780,
8606 + 0x00000000},
8607 + {0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784,
8608 + 0x00000000},
8609 + {0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00,
8610 + 0x00000000},
8611 + {0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04,
8612 + 0x00000000},
8613 + {0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08,
8614 + 0x00000000},
8615 + {0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c,
8616 + 0x00000000},
8617 + {0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80,
8618 + 0x00000000},
8619 + {0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84,
8620 + 0x00000000},
8621 + {0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88,
8622 + 0x00000000},
8623 + {0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c,
8624 + 0x00000000},
8625 + {0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90,
8626 + 0x00000000},
8627 + {0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80,
8628 + 0x00000000},
8629 + {0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84,
8630 + 0x00000000},
8631 + {0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88,
8632 + 0x00000000},
8633 + {0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c,
8634 + 0x00000000},
8635 + {0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90,
8636 + 0x00000000},
8637 + {0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c,
8638 + 0x00000000},
8639 + {0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310,
8640 + 0x00000000},
8641 + {0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384,
8642 + 0x00000000},
8643 + {0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388,
8644 + 0x00000000},
8645 + {0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324,
8646 + 0x00000000},
8647 + {0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704,
8648 + 0x00000000},
8649 + {0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4,
8650 + 0x00000000},
8651 + {0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8,
8652 + 0x00000000},
8653 + {0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710,
8654 + 0x00000000},
8655 + {0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714,
8656 + 0x00000000},
8657 + {0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720,
8658 + 0x00000000},
8659 + {0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724,
8660 + 0x00000000},
8661 + {0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728,
8662 + 0x00000000},
8663 + {0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c,
8664 + 0x00000000},
8665 + {0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0,
8666 + 0x00000000},
8667 + {0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4,
8668 + 0x00000000},
8669 + {0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8,
8670 + 0x00000000},
8671 + {0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0,
8672 + 0x00000000},
8673 + {0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4,
8674 + 0x00000000},
8675 + {0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8,
8676 + 0x00000000},
8677 + {0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5,
8678 + 0x00000000},
8679 + {0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9,
8680 + 0x00000000},
8681 + {0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad,
8682 + 0x00000000},
8683 + {0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1,
8684 + 0x00000000},
8685 + {0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5,
8686 + 0x00000000},
8687 + {0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9,
8688 + 0x00000000},
8689 + {0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5,
8690 + 0x00000000},
8691 + {0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9,
8692 + 0x00000000},
8693 + {0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1,
8694 + 0x00000000},
8695 + {0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5,
8696 + 0x00000000},
8697 + {0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9,
8698 + 0x00000000},
8699 + {0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6,
8700 + 0x00000000},
8701 + {0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca,
8702 + 0x00000000},
8703 + {0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce,
8704 + 0x00000000},
8705 + {0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2,
8706 + 0x00000000},
8707 + {0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6,
8708 + 0x00000000},
8709 + {0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3,
8710 + 0x00000000},
8711 + {0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7,
8712 + 0x00000000},
8713 + {0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb,
8714 + 0x00000000},
8715 + {0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf,
8716 + 0x00000000},
8717 + {0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7,
8718 + 0x00000000},
8719 + {0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8720 + 0x00000000},
8721 + {0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8722 + 0x00000000},
8723 + {0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8724 + 0x00000000},
8725 + {0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8726 + 0x00000000},
8727 + {0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8728 + 0x00000000},
8729 + {0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8730 + 0x00000000},
8731 + {0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8732 + 0x00000000},
8733 + {0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8734 + 0x00000000},
8735 + {0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8736 + 0x00000000},
8737 + {0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8738 + 0x00000000},
8739 + {0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8740 + 0x00000000},
8741 + {0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8742 + 0x00000000},
8743 + {0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8744 + 0x00000000},
8745 + {0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8746 + 0x00000000},
8747 + {0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8748 + 0x00000000},
8749 + {0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8750 + 0x00000000},
8751 + {0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8752 + 0x00000000},
8753 + {0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8754 + 0x00000000},
8755 + {0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8756 + 0x00000000},
8757 + {0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8758 + 0x00000000},
8759 + {0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8760 + 0x00000000},
8761 + {0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8762 + 0x00000000},
8763 + {0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8764 + 0x00000000},
8765 + {0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8766 + 0x00000000},
8767 + {0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8768 + 0x00000000},
8769 + {0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8770 + 0x00000000},
8771 + {0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8772 + 0x00000000},
8773 + {0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8774 + 0x00000000},
8775 + {0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8776 + 0x00000000},
8777 + {0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8778 + 0x00000000},
8779 + {0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8780 + 0x00000000},
8781 + {0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8782 + 0x00000000},
8783 + {0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8784 + 0x00000000},
8785 + {0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8786 + 0x00000000},
8787 + {0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8788 + 0x00000000},
8789 + {0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8790 + 0x00000000},
8791 + {0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8792 + 0x00000000},
8793 + {0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8794 + 0x00000000},
8795 + {0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8796 + 0x00000000},
8797 + {0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084,
8798 + 0x00000000},
8799 + {0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088,
8800 + 0x00000000},
8801 + {0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c,
8802 + 0x00000000},
8803 + {0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100,
8804 + 0x00000000},
8805 + {0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104,
8806 + 0x00000000},
8807 + {0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108,
8808 + 0x00000000},
8809 + {0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c,
8810 + 0x00000000},
8811 + {0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110,
8812 + 0x00000000},
8813 + {0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114,
8814 + 0x00000000},
8815 + {0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180,
8816 + 0x00000000},
8817 + {0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184,
8818 + 0x00000000},
8819 + {0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188,
8820 + 0x00000000},
8821 + {0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c,
8822 + 0x00000000},
8823 + {0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190,
8824 + 0x00000000},
8825 + {0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194,
8826 + 0x00000000},
8827 + {0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0,
8828 + 0x00000000},
8829 + {0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c,
8830 + 0x00000000},
8831 + {0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8,
8832 + 0x00000000},
8833 + {0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284,
8834 + 0x00000000},
8835 + {0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288,
8836 + 0x00000000},
8837 + {0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224,
8838 + 0x00000000},
8839 + {0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290,
8840 + 0x00000000},
8841 + {0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300,
8842 + 0x00000000},
8843 + {0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304,
8844 + 0x00000000},
8845 + {0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308,
8846 + 0x00000000},
8847 + {0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c,
8848 + 0x00000000},
8849 + {0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380,
8850 + 0x00000000},
8851 + {0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384,
8852 + 0x00000000},
8853 + {0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700,
8854 + 0x00000000},
8855 + {0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704,
8856 + 0x00000000},
8857 + {0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708,
8858 + 0x00000000},
8859 + {0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c,
8860 + 0x00000000},
8861 + {0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780,
8862 + 0x00000000},
8863 + {0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784,
8864 + 0x00000000},
8865 + {0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00,
8866 + 0x00000000},
8867 + {0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04,
8868 + 0x00000000},
8869 + {0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08,
8870 + 0x00000000},
8871 + {0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c,
8872 + 0x00000000},
8873 + {0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80,
8874 + 0x00000000},
8875 + {0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84,
8876 + 0x00000000},
8877 + {0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88,
8878 + 0x00000000},
8879 + {0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c,
8880 + 0x00000000},
8881 + {0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90,
8882 + 0x00000000},
8883 + {0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80,
8884 + 0x00000000},
8885 + {0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84,
8886 + 0x00000000},
8887 + {0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88,
8888 + 0x00000000},
8889 + {0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c,
8890 + 0x00000000},
8891 + {0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90,
8892 + 0x00000000},
8893 + {0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c,
8894 + 0x00000000},
8895 + {0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310,
8896 + 0x00000000},
8897 + {0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384,
8898 + 0x00000000},
8899 + {0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388,
8900 + 0x00000000},
8901 + {0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324,
8902 + 0x00000000},
8903 + {0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704,
8904 + 0x00000000},
8905 + {0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4,
8906 + 0x00000000},
8907 + {0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8,
8908 + 0x00000000},
8909 + {0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710,
8910 + 0x00000000},
8911 + {0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714,
8912 + 0x00000000},
8913 + {0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720,
8914 + 0x00000000},
8915 + {0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724,
8916 + 0x00000000},
8917 + {0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728,
8918 + 0x00000000},
8919 + {0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c,
8920 + 0x00000000},
8921 + {0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0,
8922 + 0x00000000},
8923 + {0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4,
8924 + 0x00000000},
8925 + {0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8,
8926 + 0x00000000},
8927 + {0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0,
8928 + 0x00000000},
8929 + {0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4,
8930 + 0x00000000},
8931 + {0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8,
8932 + 0x00000000},
8933 + {0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5,
8934 + 0x00000000},
8935 + {0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9,
8936 + 0x00000000},
8937 + {0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad,
8938 + 0x00000000},
8939 + {0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1,
8940 + 0x00000000},
8941 + {0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5,
8942 + 0x00000000},
8943 + {0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9,
8944 + 0x00000000},
8945 + {0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5,
8946 + 0x00000000},
8947 + {0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9,
8948 + 0x00000000},
8949 + {0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1,
8950 + 0x00000000},
8951 + {0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5,
8952 + 0x00000000},
8953 + {0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9,
8954 + 0x00000000},
8955 + {0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6,
8956 + 0x00000000},
8957 + {0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca,
8958 + 0x00000000},
8959 + {0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce,
8960 + 0x00000000},
8961 + {0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2,
8962 + 0x00000000},
8963 + {0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6,
8964 + 0x00000000},
8965 + {0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3,
8966 + 0x00000000},
8967 + {0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7,
8968 + 0x00000000},
8969 + {0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb,
8970 + 0x00000000},
8971 + {0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf,
8972 + 0x00000000},
8973 + {0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7,
8974 + 0x00000000},
8975 + {0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8976 + 0x00000000},
8977 + {0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8978 + 0x00000000},
8979 + {0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8980 + 0x00000000},
8981 + {0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8982 + 0x00000000},
8983 + {0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8984 + 0x00000000},
8985 + {0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8986 + 0x00000000},
8987 + {0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8988 + 0x00000000},
8989 + {0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8990 + 0x00000000},
8991 + {0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8992 + 0x00000000},
8993 + {0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8994 + 0x00000000},
8995 + {0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8996 + 0x00000000},
8997 + {0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
8998 + 0x00000000},
8999 + {0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9000 + 0x00000000},
9001 + {0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9002 + 0x00000000},
9003 + {0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9004 + 0x00000000},
9005 + {0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9006 + 0x00000000},
9007 + {0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9008 + 0x00000000},
9009 + {0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9010 + 0x00000000},
9011 + {0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9012 + 0x00000000},
9013 + {0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9014 + 0x00000000},
9015 + {0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9016 + 0x00000000},
9017 + {0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9018 + 0x00000000},
9019 + {0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9020 + 0x00000000},
9021 + {0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9022 + 0x00000000},
9023 + {0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9024 + 0x00000000},
9025 + {0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9026 + 0x00000000},
9027 + {0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9028 + 0x00000000},
9029 + {0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9030 + 0x00000000},
9031 + {0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9032 + 0x00000000},
9033 + {0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9034 + 0x00000000},
9035 + {0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9036 + 0x00000000},
9037 + {0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9038 + 0x00000000},
9039 + {0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9040 + 0x00000000},
9041 + {0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9042 + 0x00000000},
9043 + {0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9044 + 0x00000000},
9045 + {0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9046 + 0x00000000},
9047 + {0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9048 + 0x00000000},
9049 + {0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9050 + 0x00000000},
9051 + {0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
9052 + 0x00000000},
9053 + {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004,
9054 + 0x00000004},
9055 + {0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000,
9056 + 0x0001f000},
9057 + {0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000,
9058 + 0x0001f000},
9059 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
9060 + 0x1883800a},
9061 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
9062 + 0x00000000},
9063 + {0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000,
9064 + 0x0004a000},
9065 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
9066 + 0x7999aa0e},
9067 +};
9068 +
9069 +static const u_int32_t ar9285Common_9285_1_2[][2] = {
9070 + {0x0000000c, 0x00000000},
9071 + {0x00000030, 0x00020045},
9072 + {0x00000034, 0x00000005},
9073 + {0x00000040, 0x00000000},
9074 + {0x00000044, 0x00000008},
9075 + {0x00000048, 0x00000008},
9076 + {0x0000004c, 0x00000010},
9077 + {0x00000050, 0x00000000},
9078 + {0x00000054, 0x0000001f},
9079 + {0x00000800, 0x00000000},
9080 + {0x00000804, 0x00000000},
9081 + {0x00000808, 0x00000000},
9082 + {0x0000080c, 0x00000000},
9083 + {0x00000810, 0x00000000},
9084 + {0x00000814, 0x00000000},
9085 + {0x00000818, 0x00000000},
9086 + {0x0000081c, 0x00000000},
9087 + {0x00000820, 0x00000000},
9088 + {0x00000824, 0x00000000},
9089 + {0x00001040, 0x002ffc0f},
9090 + {0x00001044, 0x002ffc0f},
9091 + {0x00001048, 0x002ffc0f},
9092 + {0x0000104c, 0x002ffc0f},
9093 + {0x00001050, 0x002ffc0f},
9094 + {0x00001054, 0x002ffc0f},
9095 + {0x00001058, 0x002ffc0f},
9096 + {0x0000105c, 0x002ffc0f},
9097 + {0x00001060, 0x002ffc0f},
9098 + {0x00001064, 0x002ffc0f},
9099 + {0x00001230, 0x00000000},
9100 + {0x00001270, 0x00000000},
9101 + {0x00001038, 0x00000000},
9102 + {0x00001078, 0x00000000},
9103 + {0x000010b8, 0x00000000},
9104 + {0x000010f8, 0x00000000},
9105 + {0x00001138, 0x00000000},
9106 + {0x00001178, 0x00000000},
9107 + {0x000011b8, 0x00000000},
9108 + {0x000011f8, 0x00000000},
9109 + {0x00001238, 0x00000000},
9110 + {0x00001278, 0x00000000},
9111 + {0x000012b8, 0x00000000},
9112 + {0x000012f8, 0x00000000},
9113 + {0x00001338, 0x00000000},
9114 + {0x00001378, 0x00000000},
9115 + {0x000013b8, 0x00000000},
9116 + {0x000013f8, 0x00000000},
9117 + {0x00001438, 0x00000000},
9118 + {0x00001478, 0x00000000},
9119 + {0x000014b8, 0x00000000},
9120 + {0x000014f8, 0x00000000},
9121 + {0x00001538, 0x00000000},
9122 + {0x00001578, 0x00000000},
9123 + {0x000015b8, 0x00000000},
9124 + {0x000015f8, 0x00000000},
9125 + {0x00001638, 0x00000000},
9126 + {0x00001678, 0x00000000},
9127 + {0x000016b8, 0x00000000},
9128 + {0x000016f8, 0x00000000},
9129 + {0x00001738, 0x00000000},
9130 + {0x00001778, 0x00000000},
9131 + {0x000017b8, 0x00000000},
9132 + {0x000017f8, 0x00000000},
9133 + {0x0000103c, 0x00000000},
9134 + {0x0000107c, 0x00000000},
9135 + {0x000010bc, 0x00000000},
9136 + {0x000010fc, 0x00000000},
9137 + {0x0000113c, 0x00000000},
9138 + {0x0000117c, 0x00000000},
9139 + {0x000011bc, 0x00000000},
9140 + {0x000011fc, 0x00000000},
9141 + {0x0000123c, 0x00000000},
9142 + {0x0000127c, 0x00000000},
9143 + {0x000012bc, 0x00000000},
9144 + {0x000012fc, 0x00000000},
9145 + {0x0000133c, 0x00000000},
9146 + {0x0000137c, 0x00000000},
9147 + {0x000013bc, 0x00000000},
9148 + {0x000013fc, 0x00000000},
9149 + {0x0000143c, 0x00000000},
9150 + {0x0000147c, 0x00000000},
9151 + {0x00004030, 0x00000002},
9152 + {0x0000403c, 0x00000002},
9153 + {0x00004024, 0x0000001f},
9154 + {0x00004060, 0x00000000},
9155 + {0x00004064, 0x00000000},
9156 + {0x00007010, 0x00000031},
9157 + {0x00007034, 0x00000002},
9158 + {0x00007038, 0x000004c2},
9159 + {0x00008004, 0x00000000},
9160 + {0x00008008, 0x00000000},
9161 + {0x0000800c, 0x00000000},
9162 + {0x00008018, 0x00000700},
9163 + {0x00008020, 0x00000000},
9164 + {0x00008038, 0x00000000},
9165 + {0x0000803c, 0x00000000},
9166 + {0x00008048, 0x00000000},
9167 + {0x00008054, 0x00000000},
9168 + {0x00008058, 0x00000000},
9169 + {0x0000805c, 0x000fc78f},
9170 + {0x00008060, 0x0000000f},
9171 + {0x00008064, 0x00000000},
9172 + {0x00008070, 0x00000000},
9173 + {0x000080c0, 0x2a80001a},
9174 + {0x000080c4, 0x05dc01e0},
9175 + {0x000080c8, 0x1f402710},
9176 + {0x000080cc, 0x01f40000},
9177 + {0x000080d0, 0x00001e00},
9178 + {0x000080d4, 0x00000000},
9179 + {0x000080d8, 0x00400000},
9180 + {0x000080e0, 0xffffffff},
9181 + {0x000080e4, 0x0000ffff},
9182 + {0x000080e8, 0x003f3f3f},
9183 + {0x000080ec, 0x00000000},
9184 + {0x000080f0, 0x00000000},
9185 + {0x000080f4, 0x00000000},
9186 + {0x000080f8, 0x00000000},
9187 + {0x000080fc, 0x00020000},
9188 + {0x00008100, 0x00020000},
9189 + {0x00008104, 0x00000001},
9190 + {0x00008108, 0x00000052},
9191 + {0x0000810c, 0x00000000},
9192 + {0x00008110, 0x00000168},
9193 + {0x00008118, 0x000100aa},
9194 + {0x0000811c, 0x00003210},
9195 + {0x00008120, 0x08f04810},
9196 + {0x00008124, 0x00000000},
9197 + {0x00008128, 0x00000000},
9198 + {0x0000812c, 0x00000000},
9199 + {0x00008130, 0x00000000},
9200 + {0x00008134, 0x00000000},
9201 + {0x00008138, 0x00000000},
9202 + {0x0000813c, 0x00000000},
9203 + {0x00008144, 0xffffffff},
9204 + {0x00008168, 0x00000000},
9205 + {0x0000816c, 0x00000000},
9206 + {0x00008170, 0x32143320},
9207 + {0x00008174, 0xfaa4fa50},
9208 + {0x00008178, 0x00000100},
9209 + {0x0000817c, 0x00000000},
9210 + {0x000081c0, 0x00000000},
9211 + {0x000081d0, 0x0000320a},
9212 + {0x000081ec, 0x00000000},
9213 + {0x000081f0, 0x00000000},
9214 + {0x000081f4, 0x00000000},
9215 + {0x000081f8, 0x00000000},
9216 + {0x000081fc, 0x00000000},
9217 + {0x00008200, 0x00000000},
9218 + {0x00008204, 0x00000000},
9219 + {0x00008208, 0x00000000},
9220 + {0x0000820c, 0x00000000},
9221 + {0x00008210, 0x00000000},
9222 + {0x00008214, 0x00000000},
9223 + {0x00008218, 0x00000000},
9224 + {0x0000821c, 0x00000000},
9225 + {0x00008220, 0x00000000},
9226 + {0x00008224, 0x00000000},
9227 + {0x00008228, 0x00000000},
9228 + {0x0000822c, 0x00000000},
9229 + {0x00008230, 0x00000000},
9230 + {0x00008234, 0x00000000},
9231 + {0x00008238, 0x00000000},
9232 + {0x0000823c, 0x00000000},
9233 + {0x00008240, 0x00100000},
9234 + {0x00008244, 0x0010f400},
9235 + {0x00008248, 0x00000100},
9236 + {0x0000824c, 0x0001e800},
9237 + {0x00008250, 0x00000000},
9238 + {0x00008254, 0x00000000},
9239 + {0x00008258, 0x00000000},
9240 + {0x0000825c, 0x400000ff},
9241 + {0x00008260, 0x00080922},
9242 + {0x00008264, 0x88a00010},
9243 + {0x00008270, 0x00000000},
9244 + {0x00008274, 0x40000000},
9245 + {0x00008278, 0x003e4180},
9246 + {0x0000827c, 0x00000000},
9247 + {0x00008284, 0x0000002c},
9248 + {0x00008288, 0x0000002c},
9249 + {0x0000828c, 0x00000000},
9250 + {0x00008294, 0x00000000},
9251 + {0x00008298, 0x00000000},
9252 + {0x0000829c, 0x00000000},
9253 + {0x00008300, 0x00000040},
9254 + {0x00008314, 0x00000000},
9255 + {0x00008328, 0x00000000},
9256 + {0x0000832c, 0x00000001},
9257 + {0x00008330, 0x00000302},
9258 + {0x00008334, 0x00000e00},
9259 + {0x00008338, 0x00ff0000},
9260 + {0x0000833c, 0x00000000},
9261 + {0x00008340, 0x00010380},
9262 + {0x00008344, 0x00481043},
9263 + {0x00009808, 0x00000000},
9264 + {0x0000980c, 0xafe68e30},
9265 + {0x00009810, 0xfd14e000},
9266 + {0x00009814, 0x9c0a9f6b},
9267 + {0x0000981c, 0x00000000},
9268 + {0x0000982c, 0x0000a000},
9269 + {0x00009830, 0x00000000},
9270 + {0x0000983c, 0x00200400},
9271 + {0x0000984c, 0x0040233c},
9272 + {0x00009854, 0x00000044},
9273 + {0x00009900, 0x00000000},
9274 + {0x00009904, 0x00000000},
9275 + {0x00009908, 0x00000000},
9276 + {0x0000990c, 0x00000000},
9277 + {0x00009910, 0x01002310},
9278 + {0x0000991c, 0x10000fff},
9279 + {0x00009920, 0x04900000},
9280 + {0x00009928, 0x00000001},
9281 + {0x0000992c, 0x00000004},
9282 + {0x00009934, 0x1e1f2022},
9283 + {0x00009938, 0x0a0b0c0d},
9284 + {0x0000993c, 0x00000000},
9285 + {0x00009940, 0x14750604},
9286 + {0x00009948, 0x9280c00a},
9287 + {0x0000994c, 0x00020028},
9288 + {0x00009954, 0x5f3ca3de},
9289 + {0x00009958, 0x2108ecff},
9290 + {0x00009968, 0x000003ce},
9291 + {0x00009970, 0x192bb514},
9292 + {0x00009974, 0x00000000},
9293 + {0x00009978, 0x00000001},
9294 + {0x0000997c, 0x00000000},
9295 + {0x00009980, 0x00000000},
9296 + {0x00009984, 0x00000000},
9297 + {0x00009988, 0x00000000},
9298 + {0x0000998c, 0x00000000},
9299 + {0x00009990, 0x00000000},
9300 + {0x00009994, 0x00000000},
9301 + {0x00009998, 0x00000000},
9302 + {0x0000999c, 0x00000000},
9303 + {0x000099a0, 0x00000000},
9304 + {0x000099a4, 0x00000001},
9305 + {0x000099a8, 0x201fff00},
9306 + {0x000099ac, 0x2def0400},
9307 + {0x000099b0, 0x03051000},
9308 + {0x000099b4, 0x00000820},
9309 + {0x000099dc, 0x00000000},
9310 + {0x000099e0, 0x00000000},
9311 + {0x000099e4, 0xaaaaaaaa},
9312 + {0x000099e8, 0x3c466478},
9313 + {0x000099ec, 0x0cc80caa},
9314 + {0x000099f0, 0x00000000},
9315 + {0x0000a208, 0x803e68c8},
9316 + {0x0000a210, 0x4080a333},
9317 + {0x0000a214, 0x00206c10},
9318 + {0x0000a218, 0x009c4060},
9319 + {0x0000a220, 0x01834061},
9320 + {0x0000a224, 0x00000400},
9321 + {0x0000a228, 0x000003b5},
9322 + {0x0000a22c, 0x00000000},
9323 + {0x0000a234, 0x20202020},
9324 + {0x0000a238, 0x20202020},
9325 + {0x0000a244, 0x00000000},
9326 + {0x0000a248, 0xfffffffc},
9327 + {0x0000a24c, 0x00000000},
9328 + {0x0000a254, 0x00000000},
9329 + {0x0000a258, 0x0ccb5380},
9330 + {0x0000a25c, 0x15151501},
9331 + {0x0000a260, 0xdfa90f01},
9332 + {0x0000a268, 0x00000000},
9333 + {0x0000a26c, 0x0ebae9e6},
9334 + {0x0000d270, 0x0d820820},
9335 + {0x0000d35c, 0x07ffffef},
9336 + {0x0000d360, 0x0fffffe7},
9337 + {0x0000d364, 0x17ffffe5},
9338 + {0x0000d368, 0x1fffffe4},
9339 + {0x0000d36c, 0x37ffffe3},
9340 + {0x0000d370, 0x3fffffe3},
9341 + {0x0000d374, 0x57ffffe3},
9342 + {0x0000d378, 0x5fffffe2},
9343 + {0x0000d37c, 0x7fffffe2},
9344 + {0x0000d380, 0x7f3c7bba},
9345 + {0x0000d384, 0xf3307ff0},
9346 + {0x0000a388, 0x0c000000},
9347 + {0x0000a38c, 0x20202020},
9348 + {0x0000a390, 0x20202020},
9349 + {0x0000a39c, 0x00000001},
9350 + {0x0000a3a0, 0x00000000},
9351 + {0x0000a3a4, 0x00000000},
9352 + {0x0000a3a8, 0x00000000},
9353 + {0x0000a3ac, 0x00000000},
9354 + {0x0000a3b0, 0x00000000},
9355 + {0x0000a3b4, 0x00000000},
9356 + {0x0000a3b8, 0x00000000},
9357 + {0x0000a3bc, 0x00000000},
9358 + {0x0000a3c0, 0x00000000},
9359 + {0x0000a3c4, 0x00000000},
9360 + {0x0000a3cc, 0x20202020},
9361 + {0x0000a3d0, 0x20202020},
9362 + {0x0000a3d4, 0x20202020},
9363 + {0x0000a3e4, 0x00000000},
9364 + {0x0000a3e8, 0x18c43433},
9365 + {0x0000a3ec, 0x00f70081},
9366 + {0x00007800, 0x00140000},
9367 + {0x00007804, 0x0e4548d8},
9368 + {0x00007808, 0x54214514},
9369 + {0x0000780c, 0x02025830},
9370 + {0x00007810, 0x71c0d388},
9371 + {0x0000781c, 0x00000000},
9372 + {0x00007824, 0x00d86fff},
9373 + {0x0000782c, 0x6e36d97b},
9374 + {0x00007834, 0x71400087},
9375 + {0x00007844, 0x000c0db6},
9376 + {0x00007848, 0x6db6246f},
9377 + {0x0000784c, 0x6d9b66db},
9378 + {0x00007850, 0x6d8c6dba},
9379 + {0x00007854, 0x00040000},
9380 + {0x00007858, 0xdb003012},
9381 + {0x0000785c, 0x04924914},
9382 + {0x00007860, 0x21084210},
9383 + {0x00007864, 0xf7d7ffde},
9384 + {0x00007868, 0xc2034080},
9385 + {0x00007870, 0x10142c00},
9386 +};
9387 +
9388 +static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
9389 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9390 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9391 + 0x00000000},
9392 + {0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200,
9393 + 0x00000000},
9394 + {0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201,
9395 + 0x00000000},
9396 + {0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240,
9397 + 0x00000000},
9398 + {0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241,
9399 + 0x00000000},
9400 + {0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600,
9401 + 0x00000000},
9402 + {0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800,
9403 + 0x00000000},
9404 + {0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802,
9405 + 0x00000000},
9406 + {0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805,
9407 + 0x00000000},
9408 + {0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80,
9409 + 0x00000000},
9410 + {0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00,
9411 + 0x00000000},
9412 + {0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40,
9413 + 0x00000000},
9414 + {0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80,
9415 + 0x00000000},
9416 + {0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82,
9417 + 0x00000000},
9418 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
9419 + 0x00000000},
9420 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
9421 + 0x00000000},
9422 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9423 + 0x00000000},
9424 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9425 + 0x00000000},
9426 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9427 + 0x00000000},
9428 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9429 + 0x00000000},
9430 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9431 + 0x00000000},
9432 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9433 + 0x00000000},
9434 + {0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8,
9435 + 0x924934a8},
9436 + {0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b,
9437 + 0x26d2491b},
9438 + {0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e,
9439 + 0xedb6d96e},
9440 + {0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803,
9441 + 0xfac68803},
9442 + {0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe,
9443 + 0x0001fffe},
9444 + {0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20,
9445 + 0xffeb1a20},
9446 + {0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe,
9447 + 0x08609ebe},
9448 + {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00,
9449 + 0x00000c00},
9450 + {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652,
9451 + 0x0a22a652},
9452 + {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9453 + 0x0e739ce7},
9454 + {0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7,
9455 + 0x050380e7},
9456 + {0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9457 + 0x0e739ce7},
9458 + {0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7,
9459 + 0x000000e7},
9460 + {0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9461 + 0x0e739ce7},
9462 + {0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7,
9463 + 0x000000e7},
9464 +};
9465 +
9466 +static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
9467 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9468 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9469 + 0x00000000},
9470 + {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200,
9471 + 0x00000000},
9472 + {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208,
9473 + 0x00000000},
9474 + {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608,
9475 + 0x00000000},
9476 + {0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618,
9477 + 0x00000000},
9478 + {0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9,
9479 + 0x00000000},
9480 + {0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710,
9481 + 0x00000000},
9482 + {0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718,
9483 + 0x00000000},
9484 + {0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758,
9485 + 0x00000000},
9486 + {0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a,
9487 + 0x00000000},
9488 + {0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c,
9489 + 0x00000000},
9490 + {0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e,
9491 + 0x00000000},
9492 + {0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f,
9493 + 0x00000000},
9494 + {0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df,
9495 + 0x00000000},
9496 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
9497 + 0x00000000},
9498 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
9499 + 0x00000000},
9500 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9501 + 0x00000000},
9502 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9503 + 0x00000000},
9504 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9505 + 0x00000000},
9506 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9507 + 0x00000000},
9508 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9509 + 0x00000000},
9510 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9511 + 0x00000000},
9512 + {0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8,
9513 + 0x924934a8},
9514 + {0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b,
9515 + 0x26d2491b},
9516 + {0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e,
9517 + 0xedb6d96e},
9518 + {0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801,
9519 + 0xfac68801},
9520 + {0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe,
9521 + 0x0001fffe},
9522 + {0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20,
9523 + 0xffeb1a20},
9524 + {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4,
9525 + 0x48609eb4},
9526 + {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04,
9527 + 0x00000c04},
9528 + {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652,
9529 + 0x0a22a652},
9530 + {0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9531 + 0x39ce739c},
9532 + {0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c,
9533 + 0x050e039c},
9534 + {0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9535 + 0x39ce739c},
9536 + {0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c,
9537 + 0x0000039c},
9538 + {0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9539 + 0x39ce739c},
9540 + {0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c,
9541 + 0x0000039c},
9542 +};
9543 +
9544 +static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
9545 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9546 + 0x00000000},
9547 + {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200,
9548 + 0x00000000},
9549 + {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208,
9550 + 0x00000000},
9551 + {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608,
9552 + 0x00000000},
9553 + {0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618,
9554 + 0x00000000},
9555 + {0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9,
9556 + 0x00000000},
9557 + {0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710,
9558 + 0x00000000},
9559 + {0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718,
9560 + 0x00000000},
9561 + {0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758,
9562 + 0x00000000},
9563 + {0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a,
9564 + 0x00000000},
9565 + {0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c,
9566 + 0x00000000},
9567 + {0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e,
9568 + 0x00000000},
9569 + {0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f,
9570 + 0x00000000},
9571 + {0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df,
9572 + 0x00000000},
9573 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
9574 + 0x00000000},
9575 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
9576 + 0x00000000},
9577 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9578 + 0x00000000},
9579 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9580 + 0x00000000},
9581 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9582 + 0x00000000},
9583 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9584 + 0x00000000},
9585 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9586 + 0x00000000},
9587 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9588 + 0x00000000},
9589 + {0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8,
9590 + 0x92497ca8},
9591 + {0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b,
9592 + 0x4ad2491b},
9593 + {0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e,
9594 + 0xedb6dbae},
9595 + {0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441,
9596 + 0xdac71441},
9597 + {0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe,
9598 + 0x2481f6fe},
9599 + {0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c,
9600 + 0xba5f638c},
9601 + {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4,
9602 + 0x48609eb4},
9603 + {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04,
9604 + 0x00000c04},
9605 + {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652,
9606 + 0x0a22a652},
9607 + {0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9608 + 0x39ce739c},
9609 + {0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c,
9610 + 0x050e039c},
9611 + {0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9612 + 0x39ce739c},
9613 + {0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c,
9614 + 0x0000039c},
9615 + {0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c,
9616 + 0x39ce739c},
9617 + {0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c,
9618 + 0x0000039c},
9619 +};
9620 +
9621 +static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
9622 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9623 + 0x00000000},
9624 + {0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200,
9625 + 0x00000000},
9626 + {0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201,
9627 + 0x00000000},
9628 + {0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240,
9629 + 0x00000000},
9630 + {0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241,
9631 + 0x00000000},
9632 + {0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600,
9633 + 0x00000000},
9634 + {0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800,
9635 + 0x00000000},
9636 + {0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802,
9637 + 0x00000000},
9638 + {0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805,
9639 + 0x00000000},
9640 + {0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80,
9641 + 0x00000000},
9642 + {0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00,
9643 + 0x00000000},
9644 + {0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40,
9645 + 0x00000000},
9646 + {0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80,
9647 + 0x00000000},
9648 + {0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82,
9649 + 0x00000000},
9650 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
9651 + 0x00000000},
9652 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
9653 + 0x00000000},
9654 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9655 + 0x00000000},
9656 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9657 + 0x00000000},
9658 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9659 + 0x00000000},
9660 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9661 + 0x00000000},
9662 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9663 + 0x00000000},
9664 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
9665 + 0x00000000},
9666 + {0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8,
9667 + 0x92497ca8},
9668 + {0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b,
9669 + 0x4ad2491b},
9670 + {0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e,
9671 + 0xedb6da6e},
9672 + {0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443,
9673 + 0xdac71443},
9674 + {0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe,
9675 + 0x2481f6fe},
9676 + {0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c,
9677 + 0xba5f638c},
9678 + {0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe,
9679 + 0x08609ebe},
9680 + {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00,
9681 + 0x00000c00},
9682 + {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652,
9683 + 0x0a22a652},
9684 + {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9685 + 0x0e739ce7},
9686 + {0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7,
9687 + 0x050380e7},
9688 + {0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9689 + 0x0e739ce7},
9690 + {0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7,
9691 + 0x000000e7},
9692 + {0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
9693 + 0x0e739ce7},
9694 + {0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7,
9695 + 0x000000e7},
9696 +};
9697 +
9698 +static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
9699 + {0x00004040, 0x9248fd00},
9700 + {0x00004040, 0x24924924},
9701 + {0x00004040, 0xa8000019},
9702 + {0x00004040, 0x13160820},
9703 + {0x00004040, 0xe5980560},
9704 + {0x00004040, 0xc01dcffd},
9705 + {0x00004040, 0x1aaabe41},
9706 + {0x00004040, 0xbe105554},
9707 + {0x00004040, 0x00043007},
9708 + {0x00004044, 0x00000000},
9709 +};
9710 +
9711 +static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
9712 + {0x00004040, 0x9248fd00},
9713 + {0x00004040, 0x24924924},
9714 + {0x00004040, 0xa8000019},
9715 + {0x00004040, 0x13160820},
9716 + {0x00004040, 0xe5980560},
9717 + {0x00004040, 0xc01dcffc},
9718 + {0x00004040, 0x1aaabe41},
9719 + {0x00004040, 0xbe105554},
9720 + {0x00004040, 0x00043007},
9721 + {0x00004044, 0x00000000},
9722 +};
9723 +
9724 +/* AR9287 Revision 10 */
9725 +static const u_int32_t ar9287Modes_9287_1_0[][6] = {
9726 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
9727 + {0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160,
9728 + 0x000001e0},
9729 + {0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c,
9730 + 0x000001e0},
9731 + {0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38,
9732 + 0x00001180},
9733 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9734 + 0x00000008},
9735 + {0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00,
9736 + 0x06e006e0},
9737 + {0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b,
9738 + 0x0988004f},
9739 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810,
9740 + 0x08f04810},
9741 + {0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a,
9742 + 0x0000320a},
9743 + {0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440,
9744 + 0x00006880},
9745 + {0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300,
9746 + 0x00000303},
9747 + {0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200,
9748 + 0x02020200},
9749 + {0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e,
9750 + 0x01000e0e},
9751 + {0x00009828, 0x00000000, 0x00000000, 0x0a020001, 0x0a020001,
9752 + 0x0a020001},
9753 + {0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e,
9754 + 0x00000e0e},
9755 + {0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007,
9756 + 0x00000007},
9757 + {0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e,
9758 + 0x206a012e},
9759 + {0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0,
9760 + 0x037216a0},
9761 + {0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2,
9762 + 0x6c4000e2},
9763 + {0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e,
9764 + 0x7ec84d2e},
9765 + {0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e,
9766 + 0x31395d5e},
9767 + {0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20,
9768 + 0x00058d18},
9769 + {0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00,
9770 + 0x0001ce00},
9771 + {0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0,
9772 + 0x5ac640d0},
9773 + {0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881,
9774 + 0x06903881},
9775 + {0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898,
9776 + 0x000007d0},
9777 + {0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b,
9778 + 0x00000016},
9779 + {0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d,
9780 + 0xd00a8a0d},
9781 + {0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010,
9782 + 0xefbc1010},
9783 + {0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010,
9784 + 0x00000010},
9785 + {0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010,
9786 + 0x00000010},
9787 + {0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210,
9788 + 0x00000210},
9789 + {0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce,
9790 + 0x000003ce},
9791 + {0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c,
9792 + 0x0000001c},
9793 + {0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00,
9794 + 0x00000c00},
9795 + {0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4,
9796 + 0x05eea6d4},
9797 + {0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444,
9798 + 0x00000444},
9799 + {0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9800 + 0x00000000},
9801 + {0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9802 + 0x00000000},
9803 + {0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a,
9804 + 0x1883800a},
9805 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
9806 + 0x00000000},
9807 + {0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000,
9808 + 0x0004a000},
9809 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
9810 + 0x7999aa0e},
9811 + {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9812 + 0x00000000},
9813 +};
9814 +
9815 +static const u_int32_t ar9287Common_9287_1_0[][2] = {
9816 + {0x0000000c, 0x00000000},
9817 + {0x00000030, 0x00020015},
9818 + {0x00000034, 0x00000005},
9819 + {0x00000040, 0x00000000},
9820 + {0x00000044, 0x00000008},
9821 + {0x00000048, 0x00000008},
9822 + {0x0000004c, 0x00000010},
9823 + {0x00000050, 0x00000000},
9824 + {0x00000054, 0x0000001f},
9825 + {0x00000800, 0x00000000},
9826 + {0x00000804, 0x00000000},
9827 + {0x00000808, 0x00000000},
9828 + {0x0000080c, 0x00000000},
9829 + {0x00000810, 0x00000000},
9830 + {0x00000814, 0x00000000},
9831 + {0x00000818, 0x00000000},
9832 + {0x0000081c, 0x00000000},
9833 + {0x00000820, 0x00000000},
9834 + {0x00000824, 0x00000000},
9835 + {0x00001040, 0x002ffc0f},
9836 + {0x00001044, 0x002ffc0f},
9837 + {0x00001048, 0x002ffc0f},
9838 + {0x0000104c, 0x002ffc0f},
9839 + {0x00001050, 0x002ffc0f},
9840 + {0x00001054, 0x002ffc0f},
9841 + {0x00001058, 0x002ffc0f},
9842 + {0x0000105c, 0x002ffc0f},
9843 + {0x00001060, 0x002ffc0f},
9844 + {0x00001064, 0x002ffc0f},
9845 + {0x00001230, 0x00000000},
9846 + {0x00001270, 0x00000000},
9847 + {0x00001038, 0x00000000},
9848 + {0x00001078, 0x00000000},
9849 + {0x000010b8, 0x00000000},
9850 + {0x000010f8, 0x00000000},
9851 + {0x00001138, 0x00000000},
9852 + {0x00001178, 0x00000000},
9853 + {0x000011b8, 0x00000000},
9854 + {0x000011f8, 0x00000000},
9855 + {0x00001238, 0x00000000},
9856 + {0x00001278, 0x00000000},
9857 + {0x000012b8, 0x00000000},
9858 + {0x000012f8, 0x00000000},
9859 + {0x00001338, 0x00000000},
9860 + {0x00001378, 0x00000000},
9861 + {0x000013b8, 0x00000000},
9862 + {0x000013f8, 0x00000000},
9863 + {0x00001438, 0x00000000},
9864 + {0x00001478, 0x00000000},
9865 + {0x000014b8, 0x00000000},
9866 + {0x000014f8, 0x00000000},
9867 + {0x00001538, 0x00000000},
9868 + {0x00001578, 0x00000000},
9869 + {0x000015b8, 0x00000000},
9870 + {0x000015f8, 0x00000000},
9871 + {0x00001638, 0x00000000},
9872 + {0x00001678, 0x00000000},
9873 + {0x000016b8, 0x00000000},
9874 + {0x000016f8, 0x00000000},
9875 + {0x00001738, 0x00000000},
9876 + {0x00001778, 0x00000000},
9877 + {0x000017b8, 0x00000000},
9878 + {0x000017f8, 0x00000000},
9879 + {0x0000103c, 0x00000000},
9880 + {0x0000107c, 0x00000000},
9881 + {0x000010bc, 0x00000000},
9882 + {0x000010fc, 0x00000000},
9883 + {0x0000113c, 0x00000000},
9884 + {0x0000117c, 0x00000000},
9885 + {0x000011bc, 0x00000000},
9886 + {0x000011fc, 0x00000000},
9887 + {0x0000123c, 0x00000000},
9888 + {0x0000127c, 0x00000000},
9889 + {0x000012bc, 0x00000000},
9890 + {0x000012fc, 0x00000000},
9891 + {0x0000133c, 0x00000000},
9892 + {0x0000137c, 0x00000000},
9893 + {0x000013bc, 0x00000000},
9894 + {0x000013fc, 0x00000000},
9895 + {0x0000143c, 0x00000000},
9896 + {0x0000147c, 0x00000000},
9897 + {0x00004030, 0x00000002},
9898 + {0x0000403c, 0x00000002},
9899 + {0x00004024, 0x0000001f},
9900 + {0x00004060, 0x00000000},
9901 + {0x00004064, 0x00000000},
9902 + {0x00007010, 0x00000033},
9903 + {0x00007020, 0x00000000},
9904 + {0x00007034, 0x00000002},
9905 + {0x00007038, 0x000004c2},
9906 + {0x00008004, 0x00000000},
9907 + {0x00008008, 0x00000000},
9908 + {0x0000800c, 0x00000000},
9909 + {0x00008018, 0x00000700},
9910 + {0x00008020, 0x00000000},
9911 + {0x00008038, 0x00000000},
9912 + {0x0000803c, 0x00000000},
9913 + {0x00008048, 0x40000000},
9914 + {0x00008054, 0x00000000},
9915 + {0x00008058, 0x00000000},
9916 + {0x0000805c, 0x000fc78f},
9917 + {0x00008060, 0x0000000f},
9918 + {0x00008064, 0x00000000},
9919 + {0x00008070, 0x00000000},
9920 + {0x000080c0, 0x2a80001a},
9921 + {0x000080c4, 0x05dc01e0},
9922 + {0x000080c8, 0x1f402710},
9923 + {0x000080cc, 0x01f40000},
9924 + {0x000080d0, 0x00001e00},
9925 + {0x000080d4, 0x00000000},
9926 + {0x000080d8, 0x00400000},
9927 + {0x000080e0, 0xffffffff},
9928 + {0x000080e4, 0x0000ffff},
9929 + {0x000080e8, 0x003f3f3f},
9930 + {0x000080ec, 0x00000000},
9931 + {0x000080f0, 0x00000000},
9932 + {0x000080f4, 0x00000000},
9933 + {0x000080f8, 0x00000000},
9934 + {0x000080fc, 0x00020000},
9935 + {0x00008100, 0x00020000},
9936 + {0x00008104, 0x00000001},
9937 + {0x00008108, 0x00000052},
9938 + {0x0000810c, 0x00000000},
9939 + {0x00008110, 0x00000168},
9940 + {0x00008118, 0x000100aa},
9941 + {0x0000811c, 0x00003210},
9942 + {0x00008124, 0x00000000},
9943 + {0x00008128, 0x00000000},
9944 + {0x0000812c, 0x00000000},
9945 + {0x00008130, 0x00000000},
9946 + {0x00008134, 0x00000000},
9947 + {0x00008138, 0x00000000},
9948 + {0x0000813c, 0x00000000},
9949 + {0x00008144, 0xffffffff},
9950 + {0x00008168, 0x00000000},
9951 + {0x0000816c, 0x00000000},
9952 + {0x00008170, 0x18487320},
9953 + {0x00008174, 0xfaa4fa50},
9954 + {0x00008178, 0x00000100},
9955 + {0x0000817c, 0x00000000},
9956 + {0x000081c0, 0x00000000},
9957 + {0x000081c4, 0x00000000},
9958 + {0x000081d4, 0x00000000},
9959 + {0x000081ec, 0x00000000},
9960 + {0x000081f0, 0x00000000},
9961 + {0x000081f4, 0x00000000},
9962 + {0x000081f8, 0x00000000},
9963 + {0x000081fc, 0x00000000},
9964 + {0x00008200, 0x00000000},
9965 + {0x00008204, 0x00000000},
9966 + {0x00008208, 0x00000000},
9967 + {0x0000820c, 0x00000000},
9968 + {0x00008210, 0x00000000},
9969 + {0x00008214, 0x00000000},
9970 + {0x00008218, 0x00000000},
9971 + {0x0000821c, 0x00000000},
9972 + {0x00008220, 0x00000000},
9973 + {0x00008224, 0x00000000},
9974 + {0x00008228, 0x00000000},
9975 + {0x0000822c, 0x00000000},
9976 + {0x00008230, 0x00000000},
9977 + {0x00008234, 0x00000000},
9978 + {0x00008238, 0x00000000},
9979 + {0x0000823c, 0x00000000},
9980 + {0x00008240, 0x00100000},
9981 + {0x00008244, 0x0010f400},
9982 + {0x00008248, 0x00000100},
9983 + {0x0000824c, 0x0001e800},
9984 + {0x00008250, 0x00000000},
9985 + {0x00008254, 0x00000000},
9986 + {0x00008258, 0x00000000},
9987 + {0x0000825c, 0x400000ff},
9988 + {0x00008260, 0x00080922},
9989 + {0x00008264, 0xa8a00010},
9990 + {0x00008270, 0x00000000},
9991 + {0x00008274, 0x40000000},
9992 + {0x00008278, 0x003e4180},
9993 + {0x0000827c, 0x00000000},
9994 + {0x00008284, 0x0000002c},
9995 + {0x00008288, 0x0000002c},
9996 + {0x0000828c, 0x000000ff},
9997 + {0x00008294, 0x00000000},
9998 + {0x00008298, 0x00000000},
9999 + {0x0000829c, 0x00000000},
10000 + {0x00008300, 0x00000040},
10001 + {0x00008314, 0x00000000},
10002 + {0x00008328, 0x00000000},
10003 + {0x0000832c, 0x00000007},
10004 + {0x00008330, 0x00000302},
10005 + {0x00008334, 0x00000e00},
10006 + {0x00008338, 0x00ff0000},
10007 + {0x0000833c, 0x00000000},
10008 + {0x00008340, 0x000107ff},
10009 + {0x00008344, 0x01c81043},
10010 + {0x00008360, 0xffffffff},
10011 + {0x00008364, 0xffffffff},
10012 + {0x00008368, 0x00000000},
10013 + {0x00008370, 0x00000000},
10014 + {0x00008374, 0x000000ff},
10015 + {0x00008378, 0x00000000},
10016 + {0x0000837c, 0x00000000},
10017 + {0x00008380, 0xffffffff},
10018 + {0x00008384, 0xffffffff},
10019 + {0x00008390, 0x0fffffff},
10020 + {0x00008394, 0x0fffffff},
10021 + {0x00008398, 0x00000000},
10022 + {0x0000839c, 0x00000000},
10023 + {0x000083a0, 0x00000000},
10024 + {0x00009808, 0x00000000},
10025 + {0x0000980c, 0xafe68e30},
10026 + {0x00009810, 0xfd14e000},
10027 + {0x00009814, 0x9c0a9f6b},
10028 + {0x0000981c, 0x00000000},
10029 + {0x0000982c, 0x0000a000},
10030 + {0x00009830, 0x00000000},
10031 + {0x0000983c, 0x00200400},
10032 + {0x0000984c, 0x0040233c},
10033 + {0x0000a84c, 0x0040233c},
10034 + {0x00009854, 0x00000044},
10035 + {0x00009900, 0x00000000},
10036 + {0x00009904, 0x00000000},
10037 + {0x00009908, 0x00000000},
10038 + {0x0000990c, 0x00000000},
10039 + {0x00009910, 0x10002310},
10040 + {0x0000991c, 0x10000fff},
10041 + {0x00009920, 0x04900000},
10042 + {0x0000a920, 0x04900000},
10043 + {0x00009928, 0x00000001},
10044 + {0x0000992c, 0x00000004},
10045 + {0x00009930, 0x00000000},
10046 + {0x0000a930, 0x00000000},
10047 + {0x00009934, 0x1e1f2022},
10048 + {0x00009938, 0x0a0b0c0d},
10049 + {0x0000993c, 0x00000000},
10050 + {0x00009948, 0x9280c00a},
10051 + {0x0000994c, 0x00020028},
10052 + {0x00009954, 0x5f3ca3de},
10053 + {0x00009958, 0x0108ecff},
10054 + {0x00009940, 0x14750604},
10055 + {0x0000c95c, 0x004b6a8e},
10056 + {0x00009970, 0x990bb515},
10057 + {0x00009974, 0x00000000},
10058 + {0x00009978, 0x00000001},
10059 + {0x0000997c, 0x00000000},
10060 + {0x000099a0, 0x00000000},
10061 + {0x000099a4, 0x00000001},
10062 + {0x000099a8, 0x201fff00},
10063 + {0x000099ac, 0x0c6f0000},
10064 + {0x000099b0, 0x03051000},
10065 + {0x000099b4, 0x00000820},
10066 + {0x000099c4, 0x06336f77},
10067 + {0x000099c8, 0x6af65329},
10068 + {0x000099cc, 0x08f186c8},
10069 + {0x000099d0, 0x00046384},
10070 + {0x000099dc, 0x00000000},
10071 + {0x000099e0, 0x00000000},
10072 + {0x000099e4, 0xaaaaaaaa},
10073 + {0x000099e8, 0x3c466478},
10074 + {0x000099ec, 0x0cc80caa},
10075 + {0x000099f0, 0x00000000},
10076 + {0x000099fc, 0x00001042},
10077 + {0x0000a1f4, 0x00fffeff},
10078 + {0x0000a1f8, 0x00f5f9ff},
10079 + {0x0000a1fc, 0xb79f6427},
10080 + {0x0000a208, 0x803e4788},
10081 + {0x0000a210, 0x4080a333},
10082 + {0x0000a214, 0x40206c10},
10083 + {0x0000a218, 0x009c4060},
10084 + {0x0000a220, 0x01834061},
10085 + {0x0000a224, 0x00000400},
10086 + {0x0000a228, 0x000003b5},
10087 + {0x0000a22c, 0x233f7180},
10088 + {0x0000a234, 0x20202020},
10089 + {0x0000a238, 0x20202020},
10090 + {0x0000a23c, 0x13c889af},
10091 + {0x0000a240, 0x38490a20},
10092 + {0x0000a244, 0x00000000},
10093 + {0x0000a248, 0xfffffffc},
10094 + {0x0000a24c, 0x00000000},
10095 + {0x0000a254, 0x00000000},
10096 + {0x0000a258, 0x0cdbd380},
10097 + {0x0000a25c, 0x0f0f0f01},
10098 + {0x0000a260, 0xdfa91f01},
10099 + {0x0000a264, 0x00418a11},
10100 + {0x0000b264, 0x00418a11},
10101 + {0x0000a268, 0x00000000},
10102 + {0x0000a26c, 0x0e79e5c6},
10103 + {0x0000b26c, 0x0e79e5c6},
10104 + {0x0000d270, 0x00820820},
10105 + {0x0000a278, 0x1ce739ce},
10106 + {0x0000a27c, 0x050701ce},
10107 + {0x0000d35c, 0x07ffffef},
10108 + {0x0000d360, 0x0fffffe7},
10109 + {0x0000d364, 0x17ffffe5},
10110 + {0x0000d368, 0x1fffffe4},
10111 + {0x0000d36c, 0x37ffffe3},
10112 + {0x0000d370, 0x3fffffe3},
10113 + {0x0000d374, 0x57ffffe3},
10114 + {0x0000d378, 0x5fffffe2},
10115 + {0x0000d37c, 0x7fffffe2},
10116 + {0x0000d380, 0x7f3c7bba},
10117 + {0x0000d384, 0xf3307ff0},
10118 + {0x0000a388, 0x0c000000},
10119 + {0x0000a38c, 0x20202020},
10120 + {0x0000a390, 0x20202020},
10121 + {0x0000a394, 0x1ce739ce},
10122 + {0x0000a398, 0x000001ce},
10123 + {0x0000b398, 0x000001ce},
10124 + {0x0000a39c, 0x00000001},
10125 + {0x0000a3c8, 0x00000246},
10126 + {0x0000a3cc, 0x20202020},
10127 + {0x0000a3d0, 0x20202020},
10128 + {0x0000a3d4, 0x20202020},
10129 + {0x0000a3dc, 0x1ce739ce},
10130 + {0x0000a3e0, 0x000001ce},
10131 + {0x0000a3e4, 0x00000000},
10132 + {0x0000a3e8, 0x18c43433},
10133 + {0x0000a3ec, 0x00f70081},
10134 + {0x0000a3f0, 0x01036a1e},
10135 + {0x0000a3f4, 0x00000000},
10136 + {0x0000b3f4, 0x00000000},
10137 + {0x0000a7d8, 0x00000001},
10138 + {0x00007800, 0x00000800},
10139 + {0x00007804, 0x6c35ffb0},
10140 + {0x00007808, 0x6db6c000},
10141 + {0x0000780c, 0x6db6cb30},
10142 + {0x00007810, 0x6db6cb6c},
10143 + {0x00007814, 0x0501e200},
10144 + {0x00007818, 0x0094128d},
10145 + {0x0000781c, 0x976ee392},
10146 + {0x00007820, 0xf75ff6fc},
10147 + {0x00007824, 0x00040000},
10148 + {0x00007828, 0xdb003012},
10149 + {0x0000782c, 0x04924914},
10150 + {0x00007830, 0x21084210},
10151 + {0x00007834, 0x00140000},
10152 + {0x00007838, 0x0e4548d8},
10153 + {0x0000783c, 0x54214514},
10154 + {0x00007840, 0x02025820},
10155 + {0x00007844, 0x71c0d388},
10156 + {0x00007848, 0x934934a8},
10157 + {0x00007850, 0x00000000},
10158 + {0x00007854, 0x00000800},
10159 + {0x00007858, 0x6c35ffb0},
10160 + {0x0000785c, 0x6db6c000},
10161 + {0x00007860, 0x6db6cb2c},
10162 + {0x00007864, 0x6db6cb6c},
10163 + {0x00007868, 0x0501e200},
10164 + {0x0000786c, 0x0094128d},
10165 + {0x00007870, 0x976ee392},
10166 + {0x00007874, 0xf75ff6fc},
10167 + {0x00007878, 0x00040000},
10168 + {0x0000787c, 0xdb003012},
10169 + {0x00007880, 0x04924914},
10170 + {0x00007884, 0x21084210},
10171 + {0x00007888, 0x001b6db0},
10172 + {0x0000788c, 0x00376b63},
10173 + {0x00007890, 0x06db6db6},
10174 + {0x00007894, 0x006d8000},
10175 + {0x00007898, 0x48100000},
10176 + {0x0000789c, 0x00000000},
10177 + {0x000078a0, 0x08000000},
10178 + {0x000078a4, 0x0007ffd8},
10179 + {0x000078a8, 0x0007ffd8},
10180 + {0x000078ac, 0x001c0020},
10181 + {0x000078b0, 0x000611eb},
10182 + {0x000078b4, 0x40008080},
10183 + {0x000078b8, 0x2a850160},
10184 +};
10185 +
10186 +static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
10187 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
10188 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10189 + 0x00000000},
10190 + {0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002,
10191 + 0x00004002},
10192 + {0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004,
10193 + 0x00008004},
10194 + {0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a,
10195 + 0x0000c00a},
10196 + {0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c,
10197 + 0x0001000c},
10198 + {0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b,
10199 + 0x0001420b},
10200 + {0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a,
10201 + 0x0001824a},
10202 + {0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a,
10203 + 0x0001c44a},
10204 + {0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a,
10205 + 0x0002064a},
10206 + {0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a,
10207 + 0x0002484a},
10208 + {0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a,
10209 + 0x00028a4a},
10210 + {0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a,
10211 + 0x0002cc4a},
10212 + {0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a,
10213 + 0x00030e4a},
10214 + {0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a,
10215 + 0x00034e8a},
10216 + {0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c,
10217 + 0x00038e8c},
10218 + {0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc,
10219 + 0x0003cecc},
10220 + {0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4,
10221 + 0x00040ed4},
10222 + {0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc,
10223 + 0x00044edc},
10224 + {0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede,
10225 + 0x00048ede},
10226 + {0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e,
10227 + 0x0004cf1e},
10228 + {0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e,
10229 + 0x00050f5e},
10230 + {0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e,
10231 + 0x00054f9e},
10232 + {0x0000a780, 0x00000000, 0x00000000, 0x00000060, 0x00000060,
10233 + 0x00000060},
10234 + {0x0000a784, 0x00000000, 0x00000000, 0x00004062, 0x00004062,
10235 + 0x00004062},
10236 + {0x0000a788, 0x00000000, 0x00000000, 0x00008064, 0x00008064,
10237 + 0x00008064},
10238 + {0x0000a78c, 0x00000000, 0x00000000, 0x0000c0a4, 0x0000c0a4,
10239 + 0x0000c0a4},
10240 + {0x0000a790, 0x00000000, 0x00000000, 0x000100b0, 0x000100b0,
10241 + 0x000100b0},
10242 + {0x0000a794, 0x00000000, 0x00000000, 0x000140b2, 0x000140b2,
10243 + 0x000140b2},
10244 + {0x0000a798, 0x00000000, 0x00000000, 0x000180b4, 0x000180b4,
10245 + 0x000180b4},
10246 + {0x0000a79c, 0x00000000, 0x00000000, 0x0001c0f4, 0x0001c0f4,
10247 + 0x0001c0f4},
10248 + {0x0000a7a0, 0x00000000, 0x00000000, 0x00020134, 0x00020134,
10249 + 0x00020134},
10250 + {0x0000a7a4, 0x00000000, 0x00000000, 0x000240fe, 0x000240fe,
10251 + 0x000240fe},
10252 + {0x0000a7a8, 0x00000000, 0x00000000, 0x0002813e, 0x0002813e,
10253 + 0x0002813e},
10254 + {0x0000a7ac, 0x00000000, 0x00000000, 0x0002c17e, 0x0002c17e,
10255 + 0x0002c17e},
10256 + {0x0000a7b0, 0x00000000, 0x00000000, 0x000301be, 0x000301be,
10257 + 0x000301be},
10258 + {0x0000a7b4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10259 + 0x000341fe},
10260 + {0x0000a7b8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10261 + 0x000341fe},
10262 + {0x0000a7bc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10263 + 0x000341fe},
10264 + {0x0000a7c0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10265 + 0x000341fe},
10266 + {0x0000a7c4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10267 + 0x000341fe},
10268 + {0x0000a7c8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10269 + 0x000341fe},
10270 + {0x0000a7cc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10271 + 0x000341fe},
10272 + {0x0000a7d0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10273 + 0x000341fe},
10274 + {0x0000a7d4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe,
10275 + 0x000341fe},
10276 + {0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000,
10277 + 0x0a1aa000},
10278 +};
10279 +
10280 +static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
10281 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
10282 + {0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120,
10283 + 0x0000a120},
10284 + {0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124,
10285 + 0x0000a124},
10286 + {0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128,
10287 + 0x0000a128},
10288 + {0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c,
10289 + 0x0000a12c},
10290 + {0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130,
10291 + 0x0000a130},
10292 + {0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194,
10293 + 0x0000a194},
10294 + {0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198,
10295 + 0x0000a198},
10296 + {0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c,
10297 + 0x0000a20c},
10298 + {0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210,
10299 + 0x0000a210},
10300 + {0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284,
10301 + 0x0000a284},
10302 + {0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288,
10303 + 0x0000a288},
10304 + {0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c,
10305 + 0x0000a28c},
10306 + {0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290,
10307 + 0x0000a290},
10308 + {0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294,
10309 + 0x0000a294},
10310 + {0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0,
10311 + 0x0000a2a0},
10312 + {0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4,
10313 + 0x0000a2a4},
10314 + {0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8,
10315 + 0x0000a2a8},
10316 + {0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac,
10317 + 0x0000a2ac},
10318 + {0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0,
10319 + 0x0000a2b0},
10320 + {0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4,
10321 + 0x0000a2b4},
10322 + {0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8,
10323 + 0x0000a2b8},
10324 + {0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4,
10325 + 0x0000a2c4},
10326 + {0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708,
10327 + 0x0000a708},
10328 + {0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c,
10329 + 0x0000a70c},
10330 + {0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710,
10331 + 0x0000a710},
10332 + {0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04,
10333 + 0x0000ab04},
10334 + {0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08,
10335 + 0x0000ab08},
10336 + {0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c,
10337 + 0x0000ab0c},
10338 + {0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10,
10339 + 0x0000ab10},
10340 + {0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14,
10341 + 0x0000ab14},
10342 + {0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18,
10343 + 0x0000ab18},
10344 + {0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c,
10345 + 0x0000ab8c},
10346 + {0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90,
10347 + 0x0000ab90},
10348 + {0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94,
10349 + 0x0000ab94},
10350 + {0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98,
10351 + 0x0000ab98},
10352 + {0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4,
10353 + 0x0000aba4},
10354 + {0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8,
10355 + 0x0000aba8},
10356 + {0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04,
10357 + 0x0000cb04},
10358 + {0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08,
10359 + 0x0000cb08},
10360 + {0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c,
10361 + 0x0000cb0c},
10362 + {0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10,
10363 + 0x0000cb10},
10364 + {0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14,
10365 + 0x0000cb14},
10366 + {0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18,
10367 + 0x0000cb18},
10368 + {0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c,
10369 + 0x0000cb8c},
10370 + {0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90,
10371 + 0x0000cb90},
10372 + {0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18,
10373 + 0x0000cf18},
10374 + {0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24,
10375 + 0x0000cf24},
10376 + {0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28,
10377 + 0x0000cf28},
10378 + {0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314,
10379 + 0x0000d314},
10380 + {0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318,
10381 + 0x0000d318},
10382 + {0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c,
10383 + 0x0000d38c},
10384 + {0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390,
10385 + 0x0000d390},
10386 + {0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394,
10387 + 0x0000d394},
10388 + {0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398,
10389 + 0x0000d398},
10390 + {0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4,
10391 + 0x0000d3a4},
10392 + {0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8,
10393 + 0x0000d3a8},
10394 + {0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac,
10395 + 0x0000d3ac},
10396 + {0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0,
10397 + 0x0000d3b0},
10398 + {0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380,
10399 + 0x0000f380},
10400 + {0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384,
10401 + 0x0000f384},
10402 + {0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388,
10403 + 0x0000f388},
10404 + {0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710,
10405 + 0x0000f710},
10406 + {0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714,
10407 + 0x0000f714},
10408 + {0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718,
10409 + 0x0000f718},
10410 + {0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10,
10411 + 0x0000fb10},
10412 + {0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14,
10413 + 0x0000fb14},
10414 + {0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18,
10415 + 0x0000fb18},
10416 + {0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c,
10417 + 0x0000fb8c},
10418 + {0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90,
10419 + 0x0000fb90},
10420 + {0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94,
10421 + 0x0000fb94},
10422 + {0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c,
10423 + 0x0000ff8c},
10424 + {0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90,
10425 + 0x0000ff90},
10426 + {0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94,
10427 + 0x0000ff94},
10428 + {0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0,
10429 + 0x0000ffa0},
10430 + {0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4,
10431 + 0x0000ffa4},
10432 + {0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8,
10433 + 0x0000ffa8},
10434 + {0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac,
10435 + 0x0000ffac},
10436 + {0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0,
10437 + 0x0000ffb0},
10438 + {0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4,
10439 + 0x0000ffb4},
10440 + {0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1,
10441 + 0x0000ffa1},
10442 + {0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5,
10443 + 0x0000ffa5},
10444 + {0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9,
10445 + 0x0000ffa9},
10446 + {0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad,
10447 + 0x0000ffad},
10448 + {0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1,
10449 + 0x0000ffb1},
10450 + {0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5,
10451 + 0x0000ffb5},
10452 + {0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9,
10453 + 0x0000ffb9},
10454 + {0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5,
10455 + 0x0000ffc5},
10456 + {0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9,
10457 + 0x0000ffc9},
10458 + {0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd,
10459 + 0x0000ffcd},
10460 + {0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1,
10461 + 0x0000ffd1},
10462 + {0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5,
10463 + 0x0000ffd5},
10464 + {0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2,
10465 + 0x0000ffc2},
10466 + {0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6,
10467 + 0x0000ffc6},
10468 + {0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca,
10469 + 0x0000ffca},
10470 + {0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce,
10471 + 0x0000ffce},
10472 + {0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2,
10473 + 0x0000ffd2},
10474 + {0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6,
10475 + 0x0000ffd6},
10476 + {0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda,
10477 + 0x0000ffda},
10478 + {0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7,
10479 + 0x0000ffc7},
10480 + {0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb,
10481 + 0x0000ffcb},
10482 + {0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf,
10483 + 0x0000ffcf},
10484 + {0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3,
10485 + 0x0000ffd3},
10486 + {0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7,
10487 + 0x0000ffd7},
10488 + {0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10489 + 0x0000ffdb},
10490 + {0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10491 + 0x0000ffdb},
10492 + {0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10493 + 0x0000ffdb},
10494 + {0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10495 + 0x0000ffdb},
10496 + {0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10497 + 0x0000ffdb},
10498 + {0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10499 + 0x0000ffdb},
10500 + {0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10501 + 0x0000ffdb},
10502 + {0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10503 + 0x0000ffdb},
10504 + {0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10505 + 0x0000ffdb},
10506 + {0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10507 + 0x0000ffdb},
10508 + {0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10509 + 0x0000ffdb},
10510 + {0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10511 + 0x0000ffdb},
10512 + {0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10513 + 0x0000ffdb},
10514 + {0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10515 + 0x0000ffdb},
10516 + {0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10517 + 0x0000ffdb},
10518 + {0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10519 + 0x0000ffdb},
10520 + {0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10521 + 0x0000ffdb},
10522 + {0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10523 + 0x0000ffdb},
10524 + {0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10525 + 0x0000ffdb},
10526 + {0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10527 + 0x0000ffdb},
10528 + {0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10529 + 0x0000ffdb},
10530 + {0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10531 + 0x0000ffdb},
10532 + {0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10533 + 0x0000ffdb},
10534 + {0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10535 + 0x0000ffdb},
10536 + {0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10537 + 0x0000ffdb},
10538 + {0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120,
10539 + 0x0000a120},
10540 + {0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124,
10541 + 0x0000a124},
10542 + {0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128,
10543 + 0x0000a128},
10544 + {0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c,
10545 + 0x0000a12c},
10546 + {0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130,
10547 + 0x0000a130},
10548 + {0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194,
10549 + 0x0000a194},
10550 + {0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198,
10551 + 0x0000a198},
10552 + {0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c,
10553 + 0x0000a20c},
10554 + {0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210,
10555 + 0x0000a210},
10556 + {0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284,
10557 + 0x0000a284},
10558 + {0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288,
10559 + 0x0000a288},
10560 + {0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c,
10561 + 0x0000a28c},
10562 + {0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290,
10563 + 0x0000a290},
10564 + {0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294,
10565 + 0x0000a294},
10566 + {0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0,
10567 + 0x0000a2a0},
10568 + {0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4,
10569 + 0x0000a2a4},
10570 + {0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8,
10571 + 0x0000a2a8},
10572 + {0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac,
10573 + 0x0000a2ac},
10574 + {0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0,
10575 + 0x0000a2b0},
10576 + {0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4,
10577 + 0x0000a2b4},
10578 + {0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8,
10579 + 0x0000a2b8},
10580 + {0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4,
10581 + 0x0000a2c4},
10582 + {0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708,
10583 + 0x0000a708},
10584 + {0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c,
10585 + 0x0000a70c},
10586 + {0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710,
10587 + 0x0000a710},
10588 + {0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04,
10589 + 0x0000ab04},
10590 + {0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08,
10591 + 0x0000ab08},
10592 + {0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c,
10593 + 0x0000ab0c},
10594 + {0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10,
10595 + 0x0000ab10},
10596 + {0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14,
10597 + 0x0000ab14},
10598 + {0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18,
10599 + 0x0000ab18},
10600 + {0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c,
10601 + 0x0000ab8c},
10602 + {0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90,
10603 + 0x0000ab90},
10604 + {0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94,
10605 + 0x0000ab94},
10606 + {0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98,
10607 + 0x0000ab98},
10608 + {0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4,
10609 + 0x0000aba4},
10610 + {0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8,
10611 + 0x0000aba8},
10612 + {0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04,
10613 + 0x0000cb04},
10614 + {0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08,
10615 + 0x0000cb08},
10616 + {0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c,
10617 + 0x0000cb0c},
10618 + {0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10,
10619 + 0x0000cb10},
10620 + {0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14,
10621 + 0x0000cb14},
10622 + {0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18,
10623 + 0x0000cb18},
10624 + {0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c,
10625 + 0x0000cb8c},
10626 + {0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90,
10627 + 0x0000cb90},
10628 + {0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18,
10629 + 0x0000cf18},
10630 + {0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24,
10631 + 0x0000cf24},
10632 + {0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28,
10633 + 0x0000cf28},
10634 + {0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314,
10635 + 0x0000d314},
10636 + {0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318,
10637 + 0x0000d318},
10638 + {0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c,
10639 + 0x0000d38c},
10640 + {0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390,
10641 + 0x0000d390},
10642 + {0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394,
10643 + 0x0000d394},
10644 + {0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398,
10645 + 0x0000d398},
10646 + {0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4,
10647 + 0x0000d3a4},
10648 + {0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8,
10649 + 0x0000d3a8},
10650 + {0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac,
10651 + 0x0000d3ac},
10652 + {0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0,
10653 + 0x0000d3b0},
10654 + {0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380,
10655 + 0x0000f380},
10656 + {0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384,
10657 + 0x0000f384},
10658 + {0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388,
10659 + 0x0000f388},
10660 + {0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710,
10661 + 0x0000f710},
10662 + {0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714,
10663 + 0x0000f714},
10664 + {0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718,
10665 + 0x0000f718},
10666 + {0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10,
10667 + 0x0000fb10},
10668 + {0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14,
10669 + 0x0000fb14},
10670 + {0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18,
10671 + 0x0000fb18},
10672 + {0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c,
10673 + 0x0000fb8c},
10674 + {0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90,
10675 + 0x0000fb90},
10676 + {0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94,
10677 + 0x0000fb94},
10678 + {0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c,
10679 + 0x0000ff8c},
10680 + {0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90,
10681 + 0x0000ff90},
10682 + {0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94,
10683 + 0x0000ff94},
10684 + {0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0,
10685 + 0x0000ffa0},
10686 + {0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4,
10687 + 0x0000ffa4},
10688 + {0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8,
10689 + 0x0000ffa8},
10690 + {0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac,
10691 + 0x0000ffac},
10692 + {0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0,
10693 + 0x0000ffb0},
10694 + {0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4,
10695 + 0x0000ffb4},
10696 + {0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1,
10697 + 0x0000ffa1},
10698 + {0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5,
10699 + 0x0000ffa5},
10700 + {0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9,
10701 + 0x0000ffa9},
10702 + {0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad,
10703 + 0x0000ffad},
10704 + {0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1,
10705 + 0x0000ffb1},
10706 + {0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5,
10707 + 0x0000ffb5},
10708 + {0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9,
10709 + 0x0000ffb9},
10710 + {0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5,
10711 + 0x0000ffc5},
10712 + {0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9,
10713 + 0x0000ffc9},
10714 + {0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd,
10715 + 0x0000ffcd},
10716 + {0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1,
10717 + 0x0000ffd1},
10718 + {0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5,
10719 + 0x0000ffd5},
10720 + {0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2,
10721 + 0x0000ffc2},
10722 + {0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6,
10723 + 0x0000ffc6},
10724 + {0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca,
10725 + 0x0000ffca},
10726 + {0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce,
10727 + 0x0000ffce},
10728 + {0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2,
10729 + 0x0000ffd2},
10730 + {0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6,
10731 + 0x0000ffd6},
10732 + {0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda,
10733 + 0x0000ffda},
10734 + {0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7,
10735 + 0x0000ffc7},
10736 + {0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb,
10737 + 0x0000ffcb},
10738 + {0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf,
10739 + 0x0000ffcf},
10740 + {0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3,
10741 + 0x0000ffd3},
10742 + {0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7,
10743 + 0x0000ffd7},
10744 + {0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10745 + 0x0000ffdb},
10746 + {0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10747 + 0x0000ffdb},
10748 + {0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10749 + 0x0000ffdb},
10750 + {0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10751 + 0x0000ffdb},
10752 + {0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10753 + 0x0000ffdb},
10754 + {0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10755 + 0x0000ffdb},
10756 + {0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10757 + 0x0000ffdb},
10758 + {0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10759 + 0x0000ffdb},
10760 + {0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10761 + 0x0000ffdb},
10762 + {0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10763 + 0x0000ffdb},
10764 + {0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10765 + 0x0000ffdb},
10766 + {0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10767 + 0x0000ffdb},
10768 + {0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10769 + 0x0000ffdb},
10770 + {0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10771 + 0x0000ffdb},
10772 + {0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10773 + 0x0000ffdb},
10774 + {0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10775 + 0x0000ffdb},
10776 + {0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10777 + 0x0000ffdb},
10778 + {0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10779 + 0x0000ffdb},
10780 + {0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10781 + 0x0000ffdb},
10782 + {0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10783 + 0x0000ffdb},
10784 + {0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10785 + 0x0000ffdb},
10786 + {0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10787 + 0x0000ffdb},
10788 + {0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10789 + 0x0000ffdb},
10790 + {0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10791 + 0x0000ffdb},
10792 + {0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
10793 + 0x0000ffdb},
10794 + {0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067,
10795 + 0x00001067},
10796 + {0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067,
10797 + 0x00001067},
10798 +};
10799 +
10800 +static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
10801 + {0x00004040, 0x9248fd00},
10802 + {0x00004040, 0x24924924},
10803 + {0x00004040, 0xa8000019},
10804 + {0x00004040, 0x13160820},
10805 + {0x00004040, 0xe5980560},
10806 + {0x00004040, 0xc01dcffd},
10807 + {0x00004040, 0x1aaabe41},
10808 + {0x00004040, 0xbe105554},
10809 + {0x00004040, 0x00043007},
10810 + {0x00004044, 0x00000000},
10811 +};
10812 +
10813 +static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
10814 + {0x00004040, 0x9248fd00},
10815 + {0x00004040, 0x24924924},
10816 + {0x00004040, 0xa8000019},
10817 + {0x00004040, 0x13160820},
10818 + {0x00004040, 0xe5980560},
10819 + {0x00004040, 0xc01dcffc},
10820 + {0x00004040, 0x1aaabe41},
10821 + {0x00004040, 0xbe105554},
10822 + {0x00004040, 0x00043007},
10823 + {0x00004044, 0x00000000},
10824 +};
10825 +
10826 +/* AR9287 Revision 11 */
10827 +
10828 +static const u_int32_t ar9287Modes_9287_1_1[][6] = {
10829 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
10830 + {0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160,
10831 + 0x000001e0},
10832 + {0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c,
10833 + 0x000001e0},
10834 + {0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38,
10835 + 0x00001180},
10836 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10837 + 0x00000008},
10838 + {0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00,
10839 + 0x06e006e0},
10840 + {0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b,
10841 + 0x0988004f},
10842 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810,
10843 + 0x08f04810},
10844 + {0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a,
10845 + 0x0000320a},
10846 + {0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440,
10847 + 0x00006880},
10848 + {0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300,
10849 + 0x00000303},
10850 + {0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200,
10851 + 0x02020200},
10852 + {0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e,
10853 + 0x01000e0e},
10854 + {0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001,
10855 + 0x3a020001},
10856 + {0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e,
10857 + 0x00000e0e},
10858 + {0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007,
10859 + 0x00000007},
10860 + {0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e,
10861 + 0x206a012e},
10862 + {0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0,
10863 + 0x037216a0},
10864 + {0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2,
10865 + 0x6c4000e2},
10866 + {0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e,
10867 + 0x7ec84d2e},
10868 + {0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e,
10869 + 0x31395d5e},
10870 + {0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20,
10871 + 0x00058d18},
10872 + {0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00,
10873 + 0x0001ce00},
10874 + {0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0,
10875 + 0x5ac640d0},
10876 + {0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881,
10877 + 0x06903881},
10878 + {0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898,
10879 + 0x000007d0},
10880 + {0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b,
10881 + 0x00000016},
10882 + {0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d,
10883 + 0xd00a8a0d},
10884 + {0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010,
10885 + 0xefbc1010},
10886 + {0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010,
10887 + 0x00000010},
10888 + {0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010,
10889 + 0x00000010},
10890 + {0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210,
10891 + 0x00000210},
10892 + {0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce,
10893 + 0x000003ce},
10894 + {0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c,
10895 + 0x0000001c},
10896 + {0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00,
10897 + 0x00000c00},
10898 + {0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4,
10899 + 0x05eea6d4},
10900 + {0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444,
10901 + 0x00000444},
10902 + {0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10903 + 0x00000000},
10904 + {0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10905 + 0x00000000},
10906 + {0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a,
10907 + 0x1883800a},
10908 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
10909 + 0x00000000},
10910 + {0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000,
10911 + 0x0004a000},
10912 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
10913 + 0x7999aa0e},
10914 + {0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10915 + 0x00000000},
10916 +};
10917 +
10918 +static const u_int32_t ar9287Common_9287_1_1[][2] = {
10919 + {0x0000000c, 0x00000000},
10920 + {0x00000030, 0x00020015},
10921 + {0x00000034, 0x00000005},
10922 + {0x00000040, 0x00000000},
10923 + {0x00000044, 0x00000008},
10924 + {0x00000048, 0x00000008},
10925 + {0x0000004c, 0x00000010},
10926 + {0x00000050, 0x00000000},
10927 + {0x00000054, 0x0000001f},
10928 + {0x00000800, 0x00000000},
10929 + {0x00000804, 0x00000000},
10930 + {0x00000808, 0x00000000},
10931 + {0x0000080c, 0x00000000},
10932 + {0x00000810, 0x00000000},
10933 + {0x00000814, 0x00000000},
10934 + {0x00000818, 0x00000000},
10935 + {0x0000081c, 0x00000000},
10936 + {0x00000820, 0x00000000},
10937 + {0x00000824, 0x00000000},
10938 + {0x00001040, 0x002ffc0f},
10939 + {0x00001044, 0x002ffc0f},
10940 + {0x00001048, 0x002ffc0f},
10941 + {0x0000104c, 0x002ffc0f},
10942 + {0x00001050, 0x002ffc0f},
10943 + {0x00001054, 0x002ffc0f},
10944 + {0x00001058, 0x002ffc0f},
10945 + {0x0000105c, 0x002ffc0f},
10946 + {0x00001060, 0x002ffc0f},
10947 + {0x00001064, 0x002ffc0f},
10948 + {0x00001230, 0x00000000},
10949 + {0x00001270, 0x00000000},
10950 + {0x00001038, 0x00000000},
10951 + {0x00001078, 0x00000000},
10952 + {0x000010b8, 0x00000000},
10953 + {0x000010f8, 0x00000000},
10954 + {0x00001138, 0x00000000},
10955 + {0x00001178, 0x00000000},
10956 + {0x000011b8, 0x00000000},
10957 + {0x000011f8, 0x00000000},
10958 + {0x00001238, 0x00000000},
10959 + {0x00001278, 0x00000000},
10960 + {0x000012b8, 0x00000000},
10961 + {0x000012f8, 0x00000000},
10962 + {0x00001338, 0x00000000},
10963 + {0x00001378, 0x00000000},
10964 + {0x000013b8, 0x00000000},
10965 + {0x000013f8, 0x00000000},
10966 + {0x00001438, 0x00000000},
10967 + {0x00001478, 0x00000000},
10968 + {0x000014b8, 0x00000000},
10969 + {0x000014f8, 0x00000000},
10970 + {0x00001538, 0x00000000},
10971 + {0x00001578, 0x00000000},
10972 + {0x000015b8, 0x00000000},
10973 + {0x000015f8, 0x00000000},
10974 + {0x00001638, 0x00000000},
10975 + {0x00001678, 0x00000000},
10976 + {0x000016b8, 0x00000000},
10977 + {0x000016f8, 0x00000000},
10978 + {0x00001738, 0x00000000},
10979 + {0x00001778, 0x00000000},
10980 + {0x000017b8, 0x00000000},
10981 + {0x000017f8, 0x00000000},
10982 + {0x0000103c, 0x00000000},
10983 + {0x0000107c, 0x00000000},
10984 + {0x000010bc, 0x00000000},
10985 + {0x000010fc, 0x00000000},
10986 + {0x0000113c, 0x00000000},
10987 + {0x0000117c, 0x00000000},
10988 + {0x000011bc, 0x00000000},
10989 + {0x000011fc, 0x00000000},
10990 + {0x0000123c, 0x00000000},
10991 + {0x0000127c, 0x00000000},
10992 + {0x000012bc, 0x00000000},
10993 + {0x000012fc, 0x00000000},
10994 + {0x0000133c, 0x00000000},
10995 + {0x0000137c, 0x00000000},
10996 + {0x000013bc, 0x00000000},
10997 + {0x000013fc, 0x00000000},
10998 + {0x0000143c, 0x00000000},
10999 + {0x0000147c, 0x00000000},
11000 + {0x00004030, 0x00000002},
11001 + {0x0000403c, 0x00000002},
11002 + {0x00004024, 0x0000001f},
11003 + {0x00004060, 0x00000000},
11004 + {0x00004064, 0x00000000},
11005 + {0x00007010, 0x00000033},
11006 + {0x00007020, 0x00000000},
11007 + {0x00007034, 0x00000002},
11008 + {0x00007038, 0x000004c2},
11009 + {0x00008004, 0x00000000},
11010 + {0x00008008, 0x00000000},
11011 + {0x0000800c, 0x00000000},
11012 + {0x00008018, 0x00000700},
11013 + {0x00008020, 0x00000000},
11014 + {0x00008038, 0x00000000},
11015 + {0x0000803c, 0x00000000},
11016 + {0x00008048, 0x40000000},
11017 + {0x00008054, 0x00000000},
11018 + {0x00008058, 0x00000000},
11019 + {0x0000805c, 0x000fc78f},
11020 + {0x00008060, 0x0000000f},
11021 + {0x00008064, 0x00000000},
11022 + {0x00008070, 0x00000000},
11023 + {0x000080c0, 0x2a80001a},
11024 + {0x000080c4, 0x05dc01e0},
11025 + {0x000080c8, 0x1f402710},
11026 + {0x000080cc, 0x01f40000},
11027 + {0x000080d0, 0x00001e00},
11028 + {0x000080d4, 0x00000000},
11029 + {0x000080d8, 0x00400000},
11030 + {0x000080e0, 0xffffffff},
11031 + {0x000080e4, 0x0000ffff},
11032 + {0x000080e8, 0x003f3f3f},
11033 + {0x000080ec, 0x00000000},
11034 + {0x000080f0, 0x00000000},
11035 + {0x000080f4, 0x00000000},
11036 + {0x000080f8, 0x00000000},
11037 + {0x000080fc, 0x00020000},
11038 + {0x00008100, 0x00020000},
11039 + {0x00008104, 0x00000001},
11040 + {0x00008108, 0x00000052},
11041 + {0x0000810c, 0x00000000},
11042 + {0x00008110, 0x00000168},
11043 + {0x00008118, 0x000100aa},
11044 + {0x0000811c, 0x00003210},
11045 + {0x00008124, 0x00000000},
11046 + {0x00008128, 0x00000000},
11047 + {0x0000812c, 0x00000000},
11048 + {0x00008130, 0x00000000},
11049 + {0x00008134, 0x00000000},
11050 + {0x00008138, 0x00000000},
11051 + {0x0000813c, 0x00000000},
11052 + {0x00008144, 0xffffffff},
11053 + {0x00008168, 0x00000000},
11054 + {0x0000816c, 0x00000000},
11055 + {0x00008170, 0x18487320},
11056 + {0x00008174, 0xfaa4fa50},
11057 + {0x00008178, 0x00000100},
11058 + {0x0000817c, 0x00000000},
11059 + {0x000081c0, 0x00000000},
11060 + {0x000081c4, 0x00000000},
11061 + {0x000081d4, 0x00000000},
11062 + {0x000081ec, 0x00000000},
11063 + {0x000081f0, 0x00000000},
11064 + {0x000081f4, 0x00000000},
11065 + {0x000081f8, 0x00000000},
11066 + {0x000081fc, 0x00000000},
11067 + {0x00008200, 0x00000000},
11068 + {0x00008204, 0x00000000},
11069 + {0x00008208, 0x00000000},
11070 + {0x0000820c, 0x00000000},
11071 + {0x00008210, 0x00000000},
11072 + {0x00008214, 0x00000000},
11073 + {0x00008218, 0x00000000},
11074 + {0x0000821c, 0x00000000},
11075 + {0x00008220, 0x00000000},
11076 + {0x00008224, 0x00000000},
11077 + {0x00008228, 0x00000000},
11078 + {0x0000822c, 0x00000000},
11079 + {0x00008230, 0x00000000},
11080 + {0x00008234, 0x00000000},
11081 + {0x00008238, 0x00000000},
11082 + {0x0000823c, 0x00000000},
11083 + {0x00008240, 0x00100000},
11084 + {0x00008244, 0x0010f400},
11085 + {0x00008248, 0x00000100},
11086 + {0x0000824c, 0x0001e800},
11087 + {0x00008250, 0x00000000},
11088 + {0x00008254, 0x00000000},
11089 + {0x00008258, 0x00000000},
11090 + {0x0000825c, 0x400000ff},
11091 + {0x00008260, 0x00080922},
11092 + {0x00008264, 0x88a00010},
11093 + {0x00008270, 0x00000000},
11094 + {0x00008274, 0x40000000},
11095 + {0x00008278, 0x003e4180},
11096 + {0x0000827c, 0x00000000},
11097 + {0x00008284, 0x0000002c},
11098 + {0x00008288, 0x0000002c},
11099 + {0x0000828c, 0x000000ff},
11100 + {0x00008294, 0x00000000},
11101 + {0x00008298, 0x00000000},
11102 + {0x0000829c, 0x00000000},
11103 + {0x00008300, 0x00000040},
11104 + {0x00008314, 0x00000000},
11105 + {0x00008328, 0x00000000},
11106 + {0x0000832c, 0x00000007},
11107 + {0x00008330, 0x00000302},
11108 + {0x00008334, 0x00000e00},
11109 + {0x00008338, 0x00ff0000},
11110 + {0x0000833c, 0x00000000},
11111 + {0x00008340, 0x000107ff},
11112 + {0x00008344, 0x01c81043},
11113 + {0x00008360, 0xffffffff},
11114 + {0x00008364, 0xffffffff},
11115 + {0x00008368, 0x00000000},
11116 + {0x00008370, 0x00000000},
11117 + {0x00008374, 0x000000ff},
11118 + {0x00008378, 0x00000000},
11119 + {0x0000837c, 0x00000000},
11120 + {0x00008380, 0xffffffff},
11121 + {0x00008384, 0xffffffff},
11122 + {0x00008390, 0x0fffffff},
11123 + {0x00008394, 0x0fffffff},
11124 + {0x00008398, 0x00000000},
11125 + {0x0000839c, 0x00000000},
11126 + {0x000083a0, 0x00000000},
11127 + {0x00009808, 0x00000000},
11128 + {0x0000980c, 0xafe68e30},
11129 + {0x00009810, 0xfd14e000},
11130 + {0x00009814, 0x9c0a9f6b},
11131 + {0x0000981c, 0x00000000},
11132 + {0x0000982c, 0x0000a000},
11133 + {0x00009830, 0x00000000},
11134 + {0x0000983c, 0x00200400},
11135 + {0x0000984c, 0x0040233c},
11136 + {0x0000a84c, 0x0040233c},
11137 + {0x00009854, 0x00000044},
11138 + {0x00009900, 0x00000000},
11139 + {0x00009904, 0x00000000},
11140 + {0x00009908, 0x00000000},
11141 + {0x0000990c, 0x00000000},
11142 + {0x00009910, 0x10002310},
11143 + {0x0000991c, 0x10000fff},
11144 + {0x00009920, 0x04900000},
11145 + {0x0000a920, 0x04900000},
11146 + {0x00009928, 0x00000001},
11147 + {0x0000992c, 0x00000004},
11148 + {0x00009930, 0x00000000},
11149 + {0x0000a930, 0x00000000},
11150 + {0x00009934, 0x1e1f2022},
11151 + {0x00009938, 0x0a0b0c0d},
11152 + {0x0000993c, 0x00000000},
11153 + {0x00009948, 0x9280c00a},
11154 + {0x0000994c, 0x00020028},
11155 + {0x00009954, 0x5f3ca3de},
11156 + {0x00009958, 0x0108ecff},
11157 + {0x00009940, 0x14750604},
11158 + {0x0000c95c, 0x004b6a8e},
11159 + {0x00009970, 0x990bb514},
11160 + {0x00009974, 0x00000000},
11161 + {0x00009978, 0x00000001},
11162 + {0x0000997c, 0x00000000},
11163 + {0x000099a0, 0x00000000},
11164 + {0x000099a4, 0x00000001},
11165 + {0x000099a8, 0x201fff00},
11166 + {0x000099ac, 0x0c6f0000},
11167 + {0x000099b0, 0x03051000},
11168 + {0x000099b4, 0x00000820},
11169 + {0x000099c4, 0x06336f77},
11170 + {0x000099c8, 0x6af6532f},
11171 + {0x000099cc, 0x08f186c8},
11172 + {0x000099d0, 0x00046384},
11173 + {0x000099dc, 0x00000000},
11174 + {0x000099e0, 0x00000000},
11175 + {0x000099e4, 0xaaaaaaaa},
11176 + {0x000099e8, 0x3c466478},
11177 + {0x000099ec, 0x0cc80caa},
11178 + {0x000099f0, 0x00000000},
11179 + {0x000099fc, 0x00001042},
11180 + {0x0000a208, 0x803e4788},
11181 + {0x0000a210, 0x4080a333},
11182 + {0x0000a214, 0x40206c10},
11183 + {0x0000a218, 0x009c4060},
11184 + {0x0000a220, 0x01834061},
11185 + {0x0000a224, 0x00000400},
11186 + {0x0000a228, 0x000003b5},
11187 + {0x0000a22c, 0x233f7180},
11188 + {0x0000a234, 0x20202020},
11189 + {0x0000a238, 0x20202020},
11190 + {0x0000a23c, 0x13c889af},
11191 + {0x0000a240, 0x38490a20},
11192 + {0x0000a244, 0x00000000},
11193 + {0x0000a248, 0xfffffffc},
11194 + {0x0000a24c, 0x00000000},
11195 + {0x0000a254, 0x00000000},
11196 + {0x0000a258, 0x0cdbd380},
11197 + {0x0000a25c, 0x0f0f0f01},
11198 + {0x0000a260, 0xdfa91f01},
11199 + {0x0000a264, 0x00418a11},
11200 + {0x0000b264, 0x00418a11},
11201 + {0x0000a268, 0x00000000},
11202 + {0x0000a26c, 0x0e79e5c6},
11203 + {0x0000b26c, 0x0e79e5c6},
11204 + {0x0000d270, 0x00820820},
11205 + {0x0000a278, 0x1ce739ce},
11206 + {0x0000a27c, 0x050701ce},
11207 + {0x0000d35c, 0x07ffffef},
11208 + {0x0000d360, 0x0fffffe7},
11209 + {0x0000d364, 0x17ffffe5},
11210 + {0x0000d368, 0x1fffffe4},
11211 + {0x0000d36c, 0x37ffffe3},
11212 + {0x0000d370, 0x3fffffe3},
11213 + {0x0000d374, 0x57ffffe3},
11214 + {0x0000d378, 0x5fffffe2},
11215 + {0x0000d37c, 0x7fffffe2},
11216 + {0x0000d380, 0x7f3c7bba},
11217 + {0x0000d384, 0xf3307ff0},
11218 + {0x0000a388, 0x0c000000},
11219 + {0x0000a38c, 0x20202020},
11220 + {0x0000a390, 0x20202020},
11221 + {0x0000a394, 0x1ce739ce},
11222 + {0x0000a398, 0x000001ce},
11223 + {0x0000b398, 0x000001ce},
11224 + {0x0000a39c, 0x00000001},
11225 + {0x0000a3c8, 0x00000246},
11226 + {0x0000a3cc, 0x20202020},
11227 + {0x0000a3d0, 0x20202020},
11228 + {0x0000a3d4, 0x20202020},
11229 + {0x0000a3dc, 0x1ce739ce},
11230 + {0x0000a3e0, 0x000001ce},
11231 + {0x0000a3e4, 0x00000000},
11232 + {0x0000a3e8, 0x18c43433},
11233 + {0x0000a3ec, 0x00f70081},
11234 + {0x0000a3f0, 0x01036a1e},
11235 + {0x0000a3f4, 0x00000000},
11236 + {0x0000b3f4, 0x00000000},
11237 + {0x0000a7d8, 0x000003f1},
11238 + {0x00007800, 0x00000800},
11239 + {0x00007804, 0x6c35ffd2},
11240 + {0x00007808, 0x6db6c000},
11241 + {0x0000780c, 0x6db6cb30},
11242 + {0x00007810, 0x6db6cb6c},
11243 + {0x00007814, 0x0501e200},
11244 + {0x00007818, 0x0094128d},
11245 + {0x0000781c, 0x976ee392},
11246 + {0x00007820, 0xf75ff6fc},
11247 + {0x00007824, 0x00040000},
11248 + {0x00007828, 0xdb003012},
11249 + {0x0000782c, 0x04924914},
11250 + {0x00007830, 0x21084210},
11251 + {0x00007834, 0x00140000},
11252 + {0x00007838, 0x0e4548d8},
11253 + {0x0000783c, 0x54214514},
11254 + {0x00007840, 0x02025830},
11255 + {0x00007844, 0x71c0d388},
11256 + {0x00007848, 0x934934a8},
11257 + {0x00007850, 0x00000000},
11258 + {0x00007854, 0x00000800},
11259 + {0x00007858, 0x6c35ffd2},
11260 + {0x0000785c, 0x6db6c000},
11261 + {0x00007860, 0x6db6cb30},
11262 + {0x00007864, 0x6db6cb6c},
11263 + {0x00007868, 0x0501e200},
11264 + {0x0000786c, 0x0094128d},
11265 + {0x00007870, 0x976ee392},
11266 + {0x00007874, 0xf75ff6fc},
11267 + {0x00007878, 0x00040000},
11268 + {0x0000787c, 0xdb003012},
11269 + {0x00007880, 0x04924914},
11270 + {0x00007884, 0x21084210},
11271 + {0x00007888, 0x001b6db0},
11272 + {0x0000788c, 0x00376b63},
11273 + {0x00007890, 0x06db6db6},
11274 + {0x00007894, 0x006d8000},
11275 + {0x00007898, 0x48100000},
11276 + {0x0000789c, 0x00000000},
11277 + {0x000078a0, 0x08000000},
11278 + {0x000078a4, 0x0007ffd8},
11279 + {0x000078a8, 0x0007ffd8},
11280 + {0x000078ac, 0x001c0020},
11281 + {0x000078b0, 0x00060aeb},
11282 + {0x000078b4, 0x40008080},
11283 + {0x000078b8, 0x2a850160},
11284 +};
11285 +
11286 +/*
11287 + * For Japanese regulatory requirements, 2484 MHz requires the following three
11288 + * registers be programmed differently from the channel between 2412 and 2472 MHz.
11289 + */
11290 +static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
11291 + {0x0000a1f4, 0x00fffeff},
11292 + {0x0000a1f8, 0x00f5f9ff},
11293 + {0x0000a1fc, 0xb79f6427},
11294 +};
11295 +
11296 +static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
11297 + {0x0000a1f4, 0x00000000},
11298 + {0x0000a1f8, 0xefff0301},
11299 + {0x0000a1fc, 0xca9228ee},
11300 +};
11301 +
11302 +static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
11303 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
11304 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
11305 + 0x00000000},
11306 + {0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002,
11307 + 0x00004002},
11308 + {0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004,
11309 + 0x00008004},
11310 + {0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a,
11311 + 0x0000c00a},
11312 + {0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c,
11313 + 0x0001000c},
11314 + {0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b,
11315 + 0x0001420b},
11316 + {0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a,
11317 + 0x0001824a},
11318 + {0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a,
11319 + 0x0001c44a},
11320 + {0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a,
11321 + 0x0002064a},
11322 + {0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a,
11323 + 0x0002484a},
11324 + {0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a,
11325 + 0x00028a4a},
11326 + {0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a,
11327 + 0x0002cc4a},
11328 + {0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a,
11329 + 0x00030e4a},
11330 + {0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a,
11331 + 0x00034e8a},
11332 + {0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c,
11333 + 0x00038e8c},
11334 + {0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc,
11335 + 0x0003cecc},
11336 + {0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4,
11337 + 0x00040ed4},
11338 + {0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc,
11339 + 0x00044edc},
11340 + {0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede,
11341 + 0x00048ede},
11342 + {0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e,
11343 + 0x0004cf1e},
11344 + {0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e,
11345 + 0x00050f5e},
11346 + {0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e,
11347 + 0x00054f9e},
11348 + {0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062,
11349 + 0x00000062},
11350 + {0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064,
11351 + 0x00004064},
11352 + {0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4,
11353 + 0x000080a4},
11354 + {0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa,
11355 + 0x0000c0aa},
11356 + {0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac,
11357 + 0x000100ac},
11358 + {0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4,
11359 + 0x000140b4},
11360 + {0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4,
11361 + 0x000180f4},
11362 + {0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134,
11363 + 0x0001c134},
11364 + {0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174,
11365 + 0x00020174},
11366 + {0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c,
11367 + 0x0002417c},
11368 + {0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e,
11369 + 0x0002817e},
11370 + {0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be,
11371 + 0x0002c1be},
11372 + {0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11373 + 0x000301fe},
11374 + {0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11375 + 0x000301fe},
11376 + {0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11377 + 0x000301fe},
11378 + {0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11379 + 0x000301fe},
11380 + {0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11381 + 0x000301fe},
11382 + {0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11383 + 0x000301fe},
11384 + {0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11385 + 0x000301fe},
11386 + {0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11387 + 0x000301fe},
11388 + {0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11389 + 0x000301fe},
11390 + {0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe,
11391 + 0x000301fe},
11392 + {0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000,
11393 + 0x0a1aa000},
11394 +};
11395 +
11396 +static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
11397 + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
11398 + {0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120,
11399 + 0x0000a120},
11400 + {0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124,
11401 + 0x0000a124},
11402 + {0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128,
11403 + 0x0000a128},
11404 + {0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c,
11405 + 0x0000a12c},
11406 + {0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130,
11407 + 0x0000a130},
11408 + {0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194,
11409 + 0x0000a194},
11410 + {0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198,
11411 + 0x0000a198},
11412 + {0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c,
11413 + 0x0000a20c},
11414 + {0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210,
11415 + 0x0000a210},
11416 + {0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284,
11417 + 0x0000a284},
11418 + {0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288,
11419 + 0x0000a288},
11420 + {0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c,
11421 + 0x0000a28c},
11422 + {0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290,
11423 + 0x0000a290},
11424 + {0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294,
11425 + 0x0000a294},
11426 + {0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0,
11427 + 0x0000a2a0},
11428 + {0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4,
11429 + 0x0000a2a4},
11430 + {0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8,
11431 + 0x0000a2a8},
11432 + {0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac,
11433 + 0x0000a2ac},
11434 + {0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0,
11435 + 0x0000a2b0},
11436 + {0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4,
11437 + 0x0000a2b4},
11438 + {0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8,
11439 + 0x0000a2b8},
11440 + {0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4,
11441 + 0x0000a2c4},
11442 + {0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708,
11443 + 0x0000a708},
11444 + {0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c,
11445 + 0x0000a70c},
11446 + {0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710,
11447 + 0x0000a710},
11448 + {0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04,
11449 + 0x0000ab04},
11450 + {0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08,
11451 + 0x0000ab08},
11452 + {0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c,
11453 + 0x0000ab0c},
11454 + {0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10,
11455 + 0x0000ab10},
11456 + {0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14,
11457 + 0x0000ab14},
11458 + {0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18,
11459 + 0x0000ab18},
11460 + {0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c,
11461 + 0x0000ab8c},
11462 + {0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90,
11463 + 0x0000ab90},
11464 + {0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94,
11465 + 0x0000ab94},
11466 + {0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98,
11467 + 0x0000ab98},
11468 + {0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4,
11469 + 0x0000aba4},
11470 + {0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8,
11471 + 0x0000aba8},
11472 + {0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04,
11473 + 0x0000cb04},
11474 + {0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08,
11475 + 0x0000cb08},
11476 + {0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c,
11477 + 0x0000cb0c},
11478 + {0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10,
11479 + 0x0000cb10},
11480 + {0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14,
11481 + 0x0000cb14},
11482 + {0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18,
11483 + 0x0000cb18},
11484 + {0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c,
11485 + 0x0000cb8c},
11486 + {0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90,
11487 + 0x0000cb90},
11488 + {0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18,
11489 + 0x0000cf18},
11490 + {0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24,
11491 + 0x0000cf24},
11492 + {0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28,
11493 + 0x0000cf28},
11494 + {0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314,
11495 + 0x0000d314},
11496 + {0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318,
11497 + 0x0000d318},
11498 + {0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c,
11499 + 0x0000d38c},
11500 + {0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390,
11501 + 0x0000d390},
11502 + {0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394,
11503 + 0x0000d394},
11504 + {0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398,
11505 + 0x0000d398},
11506 + {0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4,
11507 + 0x0000d3a4},
11508 + {0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8,
11509 + 0x0000d3a8},
11510 + {0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac,
11511 + 0x0000d3ac},
11512 + {0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0,
11513 + 0x0000d3b0},
11514 + {0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380,
11515 + 0x0000f380},
11516 + {0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384,
11517 + 0x0000f384},
11518 + {0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388,
11519 + 0x0000f388},
11520 + {0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710,
11521 + 0x0000f710},
11522 + {0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714,
11523 + 0x0000f714},
11524 + {0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718,
11525 + 0x0000f718},
11526 + {0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10,
11527 + 0x0000fb10},
11528 + {0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14,
11529 + 0x0000fb14},
11530 + {0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18,
11531 + 0x0000fb18},
11532 + {0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c,
11533 + 0x0000fb8c},
11534 + {0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90,
11535 + 0x0000fb90},
11536 + {0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94,
11537 + 0x0000fb94},
11538 + {0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c,
11539 + 0x0000ff8c},
11540 + {0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90,
11541 + 0x0000ff90},
11542 + {0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94,
11543 + 0x0000ff94},
11544 + {0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0,
11545 + 0x0000ffa0},
11546 + {0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4,
11547 + 0x0000ffa4},
11548 + {0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8,
11549 + 0x0000ffa8},
11550 + {0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac,
11551 + 0x0000ffac},
11552 + {0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0,
11553 + 0x0000ffb0},
11554 + {0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4,
11555 + 0x0000ffb4},
11556 + {0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1,
11557 + 0x0000ffa1},
11558 + {0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5,
11559 + 0x0000ffa5},
11560 + {0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9,
11561 + 0x0000ffa9},
11562 + {0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad,
11563 + 0x0000ffad},
11564 + {0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1,
11565 + 0x0000ffb1},
11566 + {0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5,
11567 + 0x0000ffb5},
11568 + {0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9,
11569 + 0x0000ffb9},
11570 + {0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5,
11571 + 0x0000ffc5},
11572 + {0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9,
11573 + 0x0000ffc9},
11574 + {0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd,
11575 + 0x0000ffcd},
11576 + {0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1,
11577 + 0x0000ffd1},
11578 + {0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5,
11579 + 0x0000ffd5},
11580 + {0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2,
11581 + 0x0000ffc2},
11582 + {0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6,
11583 + 0x0000ffc6},
11584 + {0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca,
11585 + 0x0000ffca},
11586 + {0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce,
11587 + 0x0000ffce},
11588 + {0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2,
11589 + 0x0000ffd2},
11590 + {0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6,
11591 + 0x0000ffd6},
11592 + {0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda,
11593 + 0x0000ffda},
11594 + {0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7,
11595 + 0x0000ffc7},
11596 + {0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb,
11597 + 0x0000ffcb},
11598 + {0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf,
11599 + 0x0000ffcf},
11600 + {0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3,
11601 + 0x0000ffd3},
11602 + {0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7,
11603 + 0x0000ffd7},
11604 + {0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11605 + 0x0000ffdb},
11606 + {0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11607 + 0x0000ffdb},
11608 + {0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11609 + 0x0000ffdb},
11610 + {0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11611 + 0x0000ffdb},
11612 + {0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11613 + 0x0000ffdb},
11614 + {0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11615 + 0x0000ffdb},
11616 + {0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11617 + 0x0000ffdb},
11618 + {0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11619 + 0x0000ffdb},
11620 + {0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11621 + 0x0000ffdb},
11622 + {0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11623 + 0x0000ffdb},
11624 + {0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11625 + 0x0000ffdb},
11626 + {0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11627 + 0x0000ffdb},
11628 + {0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11629 + 0x0000ffdb},
11630 + {0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11631 + 0x0000ffdb},
11632 + {0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11633 + 0x0000ffdb},
11634 + {0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11635 + 0x0000ffdb},
11636 + {0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11637 + 0x0000ffdb},
11638 + {0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11639 + 0x0000ffdb},
11640 + {0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11641 + 0x0000ffdb},
11642 + {0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11643 + 0x0000ffdb},
11644 + {0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11645 + 0x0000ffdb},
11646 + {0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11647 + 0x0000ffdb},
11648 + {0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11649 + 0x0000ffdb},
11650 + {0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11651 + 0x0000ffdb},
11652 + {0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11653 + 0x0000ffdb},
11654 + {0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120,
11655 + 0x0000a120},
11656 + {0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124,
11657 + 0x0000a124},
11658 + {0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128,
11659 + 0x0000a128},
11660 + {0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c,
11661 + 0x0000a12c},
11662 + {0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130,
11663 + 0x0000a130},
11664 + {0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194,
11665 + 0x0000a194},
11666 + {0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198,
11667 + 0x0000a198},
11668 + {0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c,
11669 + 0x0000a20c},
11670 + {0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210,
11671 + 0x0000a210},
11672 + {0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284,
11673 + 0x0000a284},
11674 + {0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288,
11675 + 0x0000a288},
11676 + {0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c,
11677 + 0x0000a28c},
11678 + {0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290,
11679 + 0x0000a290},
11680 + {0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294,
11681 + 0x0000a294},
11682 + {0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0,
11683 + 0x0000a2a0},
11684 + {0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4,
11685 + 0x0000a2a4},
11686 + {0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8,
11687 + 0x0000a2a8},
11688 + {0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac,
11689 + 0x0000a2ac},
11690 + {0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0,
11691 + 0x0000a2b0},
11692 + {0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4,
11693 + 0x0000a2b4},
11694 + {0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8,
11695 + 0x0000a2b8},
11696 + {0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4,
11697 + 0x0000a2c4},
11698 + {0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708,
11699 + 0x0000a708},
11700 + {0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c,
11701 + 0x0000a70c},
11702 + {0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710,
11703 + 0x0000a710},
11704 + {0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04,
11705 + 0x0000ab04},
11706 + {0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08,
11707 + 0x0000ab08},
11708 + {0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c,
11709 + 0x0000ab0c},
11710 + {0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10,
11711 + 0x0000ab10},
11712 + {0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14,
11713 + 0x0000ab14},
11714 + {0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18,
11715 + 0x0000ab18},
11716 + {0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c,
11717 + 0x0000ab8c},
11718 + {0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90,
11719 + 0x0000ab90},
11720 + {0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94,
11721 + 0x0000ab94},
11722 + {0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98,
11723 + 0x0000ab98},
11724 + {0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4,
11725 + 0x0000aba4},
11726 + {0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8,
11727 + 0x0000aba8},
11728 + {0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04,
11729 + 0x0000cb04},
11730 + {0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08,
11731 + 0x0000cb08},
11732 + {0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c,
11733 + 0x0000cb0c},
11734 + {0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10,
11735 + 0x0000cb10},
11736 + {0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14,
11737 + 0x0000cb14},
11738 + {0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18,
11739 + 0x0000cb18},
11740 + {0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c,
11741 + 0x0000cb8c},
11742 + {0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90,
11743 + 0x0000cb90},
11744 + {0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18,
11745 + 0x0000cf18},
11746 + {0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24,
11747 + 0x0000cf24},
11748 + {0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28,
11749 + 0x0000cf28},
11750 + {0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314,
11751 + 0x0000d314},
11752 + {0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318,
11753 + 0x0000d318},
11754 + {0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c,
11755 + 0x0000d38c},
11756 + {0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390,
11757 + 0x0000d390},
11758 + {0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394,
11759 + 0x0000d394},
11760 + {0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398,
11761 + 0x0000d398},
11762 + {0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4,
11763 + 0x0000d3a4},
11764 + {0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8,
11765 + 0x0000d3a8},
11766 + {0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac,
11767 + 0x0000d3ac},
11768 + {0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0,
11769 + 0x0000d3b0},
11770 + {0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380,
11771 + 0x0000f380},
11772 + {0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384,
11773 + 0x0000f384},
11774 + {0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388,
11775 + 0x0000f388},
11776 + {0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710,
11777 + 0x0000f710},
11778 + {0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714,
11779 + 0x0000f714},
11780 + {0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718,
11781 + 0x0000f718},
11782 + {0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10,
11783 + 0x0000fb10},
11784 + {0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14,
11785 + 0x0000fb14},
11786 + {0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18,
11787 + 0x0000fb18},
11788 + {0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c,
11789 + 0x0000fb8c},
11790 + {0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90,
11791 + 0x0000fb90},
11792 + {0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94,
11793 + 0x0000fb94},
11794 + {0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c,
11795 + 0x0000ff8c},
11796 + {0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90,
11797 + 0x0000ff90},
11798 + {0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94,
11799 + 0x0000ff94},
11800 + {0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0,
11801 + 0x0000ffa0},
11802 + {0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4,
11803 + 0x0000ffa4},
11804 + {0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8,
11805 + 0x0000ffa8},
11806 + {0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac,
11807 + 0x0000ffac},
11808 + {0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0,
11809 + 0x0000ffb0},
11810 + {0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4,
11811 + 0x0000ffb4},
11812 + {0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1,
11813 + 0x0000ffa1},
11814 + {0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5,
11815 + 0x0000ffa5},
11816 + {0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9,
11817 + 0x0000ffa9},
11818 + {0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad,
11819 + 0x0000ffad},
11820 + {0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1,
11821 + 0x0000ffb1},
11822 + {0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5,
11823 + 0x0000ffb5},
11824 + {0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9,
11825 + 0x0000ffb9},
11826 + {0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5,
11827 + 0x0000ffc5},
11828 + {0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9,
11829 + 0x0000ffc9},
11830 + {0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd,
11831 + 0x0000ffcd},
11832 + {0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1,
11833 + 0x0000ffd1},
11834 + {0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5,
11835 + 0x0000ffd5},
11836 + {0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2,
11837 + 0x0000ffc2},
11838 + {0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6,
11839 + 0x0000ffc6},
11840 + {0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca,
11841 + 0x0000ffca},
11842 + {0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce,
11843 + 0x0000ffce},
11844 + {0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2,
11845 + 0x0000ffd2},
11846 + {0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6,
11847 + 0x0000ffd6},
11848 + {0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda,
11849 + 0x0000ffda},
11850 + {0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7,
11851 + 0x0000ffc7},
11852 + {0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb,
11853 + 0x0000ffcb},
11854 + {0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf,
11855 + 0x0000ffcf},
11856 + {0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3,
11857 + 0x0000ffd3},
11858 + {0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7,
11859 + 0x0000ffd7},
11860 + {0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11861 + 0x0000ffdb},
11862 + {0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11863 + 0x0000ffdb},
11864 + {0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11865 + 0x0000ffdb},
11866 + {0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11867 + 0x0000ffdb},
11868 + {0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11869 + 0x0000ffdb},
11870 + {0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11871 + 0x0000ffdb},
11872 + {0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11873 + 0x0000ffdb},
11874 + {0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11875 + 0x0000ffdb},
11876 + {0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11877 + 0x0000ffdb},
11878 + {0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11879 + 0x0000ffdb},
11880 + {0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11881 + 0x0000ffdb},
11882 + {0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11883 + 0x0000ffdb},
11884 + {0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11885 + 0x0000ffdb},
11886 + {0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11887 + 0x0000ffdb},
11888 + {0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11889 + 0x0000ffdb},
11890 + {0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11891 + 0x0000ffdb},
11892 + {0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11893 + 0x0000ffdb},
11894 + {0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11895 + 0x0000ffdb},
11896 + {0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11897 + 0x0000ffdb},
11898 + {0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11899 + 0x0000ffdb},
11900 + {0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11901 + 0x0000ffdb},
11902 + {0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11903 + 0x0000ffdb},
11904 + {0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11905 + 0x0000ffdb},
11906 + {0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11907 + 0x0000ffdb},
11908 + {0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb,
11909 + 0x0000ffdb},
11910 + {0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067,
11911 + 0x00001067},
11912 + {0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067,
11913 + 0x00001067},
11914 +};
11915 +
11916 +static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
11917 + {0x00004040, 0x9248fd00},
11918 + {0x00004040, 0x24924924},
11919 + {0x00004040, 0xa8000019},
11920 + {0x00004040, 0x13160820},
11921 + {0x00004040, 0xe5980560},
11922 + {0x00004040, 0xc01dcffd},
11923 + {0x00004040, 0x1aaabe41},
11924 + {0x00004040, 0xbe105554},
11925 + {0x00004040, 0x00043007},
11926 + {0x00004044, 0x00000000},
11927 +};
11928 +
11929 +static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
11930 + {0x00004040, 0x9248fd00},
11931 + {0x00004040, 0x24924924},
11932 + {0x00004040, 0xa8000019},
11933 + {0x00004040, 0x13160820},
11934 + {0x00004040, 0xe5980560},
11935 + {0x00004040, 0xc01dcffc},
11936 + {0x00004040, 0x1aaabe41},
11937 + {0x00004040, 0xbe105554},
11938 + {0x00004040, 0x00043007},
11939 + {0x00004044, 0x00000000},
11940 +};
11941 +
11942 +/* AR9271 initialization values automaticaly created: 06/04/09 */
11943 +static const u_int32_t ar9271Modes_9271[][6] = {
11944 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160,
11945 + 0x000001e0},
11946 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c,
11947 + 0x000001e0},
11948 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38,
11949 + 0x00001180},
11950 + {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
11951 + 0x00000008},
11952 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00,
11953 + 0x06e006e0},
11954 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b,
11955 + 0x0988004f},
11956 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440,
11957 + 0x00006880},
11958 + {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300,
11959 + 0x00000303},
11960 + {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200,
11961 + 0x02020200},
11962 + {0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e,
11963 + 0x01000e0e},
11964 + {0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001,
11965 + 0x3a020001},
11966 + {0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e,
11967 + 0x00000e0e},
11968 + {0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007,
11969 + 0x00000007},
11970 + {0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e,
11971 + 0x206a012e},
11972 + {0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620,
11973 + 0x037216a0},
11974 + {0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053,
11975 + 0x00001059},
11976 + {0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053,
11977 + 0x00001059},
11978 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
11979 + 0x6d4000e2},
11980 + {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e,
11981 + 0x7ec84d2e},
11982 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e,
11983 + 0x3139605e},
11984 + {0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18,
11985 + 0x00058d18},
11986 + {0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00,
11987 + 0x0001ce00},
11988 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
11989 + 0x5ac640d0},
11990 + {0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881,
11991 + 0x06903881},
11992 + {0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310,
11993 + 0x30002310},
11994 + {0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898,
11995 + 0x000007d0},
11996 + {0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b,
11997 + 0x00000016},
11998 + {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d,
11999 + 0xd00a800d},
12000 + {0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020,
12001 + 0xffbc1010},
12002 + {0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12003 + 0x00000000},
12004 + {0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12005 + 0x00000000},
12006 + {0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c,
12007 + 0x0000421c},
12008 + {0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00,
12009 + 0x00000c00},
12010 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
12011 + 0x05eea6d4},
12012 + {0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77,
12013 + 0x06336f77},
12014 + {0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f,
12015 + 0x6af6532f},
12016 + {0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8,
12017 + 0x08f186c8},
12018 + {0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384,
12019 + 0x00046384},
12020 + {0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12021 + 0x00000000},
12022 + {0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12023 + 0x00000000},
12024 + {0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084,
12025 + 0x00000000},
12026 + {0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088,
12027 + 0x00000000},
12028 + {0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c,
12029 + 0x00000000},
12030 + {0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100,
12031 + 0x00000000},
12032 + {0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104,
12033 + 0x00000000},
12034 + {0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108,
12035 + 0x00000000},
12036 + {0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c,
12037 + 0x00000000},
12038 + {0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110,
12039 + 0x00000000},
12040 + {0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114,
12041 + 0x00000000},
12042 + {0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180,
12043 + 0x00000000},
12044 + {0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184,
12045 + 0x00000000},
12046 + {0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188,
12047 + 0x00000000},
12048 + {0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c,
12049 + 0x00000000},
12050 + {0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190,
12051 + 0x00000000},
12052 + {0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194,
12053 + 0x00000000},
12054 + {0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0,
12055 + 0x00000000},
12056 + {0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c,
12057 + 0x00000000},
12058 + {0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8,
12059 + 0x00000000},
12060 + {0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284,
12061 + 0x00000000},
12062 + {0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288,
12063 + 0x00000000},
12064 + {0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224,
12065 + 0x00000000},
12066 + {0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290,
12067 + 0x00000000},
12068 + {0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300,
12069 + 0x00000000},
12070 + {0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304,
12071 + 0x00000000},
12072 + {0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308,
12073 + 0x00000000},
12074 + {0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c,
12075 + 0x00000000},
12076 + {0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380,
12077 + 0x00000000},
12078 + {0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384,
12079 + 0x00000000},
12080 + {0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700,
12081 + 0x00000000},
12082 + {0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704,
12083 + 0x00000000},
12084 + {0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708,
12085 + 0x00000000},
12086 + {0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c,
12087 + 0x00000000},
12088 + {0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780,
12089 + 0x00000000},
12090 + {0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784,
12091 + 0x00000000},
12092 + {0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00,
12093 + 0x00000000},
12094 + {0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04,
12095 + 0x00000000},
12096 + {0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08,
12097 + 0x00000000},
12098 + {0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c,
12099 + 0x00000000},
12100 + {0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80,
12101 + 0x00000000},
12102 + {0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84,
12103 + 0x00000000},
12104 + {0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88,
12105 + 0x00000000},
12106 + {0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c,
12107 + 0x00000000},
12108 + {0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90,
12109 + 0x00000000},
12110 + {0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80,
12111 + 0x00000000},
12112 + {0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84,
12113 + 0x00000000},
12114 + {0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88,
12115 + 0x00000000},
12116 + {0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c,
12117 + 0x00000000},
12118 + {0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90,
12119 + 0x00000000},
12120 + {0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c,
12121 + 0x00000000},
12122 + {0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310,
12123 + 0x00000000},
12124 + {0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384,
12125 + 0x00000000},
12126 + {0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388,
12127 + 0x00000000},
12128 + {0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324,
12129 + 0x00000000},
12130 + {0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704,
12131 + 0x00000000},
12132 + {0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4,
12133 + 0x00000000},
12134 + {0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8,
12135 + 0x00000000},
12136 + {0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710,
12137 + 0x00000000},
12138 + {0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714,
12139 + 0x00000000},
12140 + {0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720,
12141 + 0x00000000},
12142 + {0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724,
12143 + 0x00000000},
12144 + {0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728,
12145 + 0x00000000},
12146 + {0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c,
12147 + 0x00000000},
12148 + {0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0,
12149 + 0x00000000},
12150 + {0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4,
12151 + 0x00000000},
12152 + {0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8,
12153 + 0x00000000},
12154 + {0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0,
12155 + 0x00000000},
12156 + {0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4,
12157 + 0x00000000},
12158 + {0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8,
12159 + 0x00000000},
12160 + {0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5,
12161 + 0x00000000},
12162 + {0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9,
12163 + 0x00000000},
12164 + {0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad,
12165 + 0x00000000},
12166 + {0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1,
12167 + 0x00000000},
12168 + {0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5,
12169 + 0x00000000},
12170 + {0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9,
12171 + 0x00000000},
12172 + {0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5,
12173 + 0x00000000},
12174 + {0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9,
12175 + 0x00000000},
12176 + {0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1,
12177 + 0x00000000},
12178 + {0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5,
12179 + 0x00000000},
12180 + {0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9,
12181 + 0x00000000},
12182 + {0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6,
12183 + 0x00000000},
12184 + {0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca,
12185 + 0x00000000},
12186 + {0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce,
12187 + 0x00000000},
12188 + {0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2,
12189 + 0x00000000},
12190 + {0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6,
12191 + 0x00000000},
12192 + {0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3,
12193 + 0x00000000},
12194 + {0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7,
12195 + 0x00000000},
12196 + {0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb,
12197 + 0x00000000},
12198 + {0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf,
12199 + 0x00000000},
12200 + {0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7,
12201 + 0x00000000},
12202 + {0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12203 + 0x00000000},
12204 + {0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12205 + 0x00000000},
12206 + {0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12207 + 0x00000000},
12208 + {0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12209 + 0x00000000},
12210 + {0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12211 + 0x00000000},
12212 + {0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12213 + 0x00000000},
12214 + {0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12215 + 0x00000000},
12216 + {0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12217 + 0x00000000},
12218 + {0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12219 + 0x00000000},
12220 + {0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12221 + 0x00000000},
12222 + {0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12223 + 0x00000000},
12224 + {0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12225 + 0x00000000},
12226 + {0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12227 + 0x00000000},
12228 + {0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12229 + 0x00000000},
12230 + {0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12231 + 0x00000000},
12232 + {0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12233 + 0x00000000},
12234 + {0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12235 + 0x00000000},
12236 + {0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12237 + 0x00000000},
12238 + {0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12239 + 0x00000000},
12240 + {0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12241 + 0x00000000},
12242 + {0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12243 + 0x00000000},
12244 + {0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12245 + 0x00000000},
12246 + {0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12247 + 0x00000000},
12248 + {0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12249 + 0x00000000},
12250 + {0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12251 + 0x00000000},
12252 + {0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12253 + 0x00000000},
12254 + {0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12255 + 0x00000000},
12256 + {0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12257 + 0x00000000},
12258 + {0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12259 + 0x00000000},
12260 + {0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12261 + 0x00000000},
12262 + {0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12263 + 0x00000000},
12264 + {0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12265 + 0x00000000},
12266 + {0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12267 + 0x00000000},
12268 + {0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12269 + 0x00000000},
12270 + {0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12271 + 0x00000000},
12272 + {0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12273 + 0x00000000},
12274 + {0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12275 + 0x00000000},
12276 + {0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12277 + 0x00000000},
12278 + {0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12279 + 0x00000000},
12280 + {0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084,
12281 + 0x00000000},
12282 + {0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088,
12283 + 0x00000000},
12284 + {0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c,
12285 + 0x00000000},
12286 + {0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100,
12287 + 0x00000000},
12288 + {0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104,
12289 + 0x00000000},
12290 + {0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108,
12291 + 0x00000000},
12292 + {0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c,
12293 + 0x00000000},
12294 + {0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110,
12295 + 0x00000000},
12296 + {0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114,
12297 + 0x00000000},
12298 + {0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180,
12299 + 0x00000000},
12300 + {0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184,
12301 + 0x00000000},
12302 + {0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188,
12303 + 0x00000000},
12304 + {0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c,
12305 + 0x00000000},
12306 + {0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190,
12307 + 0x00000000},
12308 + {0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194,
12309 + 0x00000000},
12310 + {0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0,
12311 + 0x00000000},
12312 + {0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c,
12313 + 0x00000000},
12314 + {0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8,
12315 + 0x00000000},
12316 + {0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284,
12317 + 0x00000000},
12318 + {0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288,
12319 + 0x00000000},
12320 + {0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224,
12321 + 0x00000000},
12322 + {0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290,
12323 + 0x00000000},
12324 + {0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300,
12325 + 0x00000000},
12326 + {0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304,
12327 + 0x00000000},
12328 + {0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308,
12329 + 0x00000000},
12330 + {0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c,
12331 + 0x00000000},
12332 + {0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380,
12333 + 0x00000000},
12334 + {0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384,
12335 + 0x00000000},
12336 + {0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700,
12337 + 0x00000000},
12338 + {0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704,
12339 + 0x00000000},
12340 + {0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708,
12341 + 0x00000000},
12342 + {0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c,
12343 + 0x00000000},
12344 + {0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780,
12345 + 0x00000000},
12346 + {0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784,
12347 + 0x00000000},
12348 + {0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00,
12349 + 0x00000000},
12350 + {0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04,
12351 + 0x00000000},
12352 + {0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08,
12353 + 0x00000000},
12354 + {0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c,
12355 + 0x00000000},
12356 + {0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80,
12357 + 0x00000000},
12358 + {0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84,
12359 + 0x00000000},
12360 + {0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88,
12361 + 0x00000000},
12362 + {0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c,
12363 + 0x00000000},
12364 + {0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90,
12365 + 0x00000000},
12366 + {0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80,
12367 + 0x00000000},
12368 + {0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84,
12369 + 0x00000000},
12370 + {0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88,
12371 + 0x00000000},
12372 + {0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c,
12373 + 0x00000000},
12374 + {0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90,
12375 + 0x00000000},
12376 + {0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c,
12377 + 0x00000000},
12378 + {0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310,
12379 + 0x00000000},
12380 + {0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384,
12381 + 0x00000000},
12382 + {0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388,
12383 + 0x00000000},
12384 + {0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324,
12385 + 0x00000000},
12386 + {0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704,
12387 + 0x00000000},
12388 + {0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4,
12389 + 0x00000000},
12390 + {0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8,
12391 + 0x00000000},
12392 + {0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710,
12393 + 0x00000000},
12394 + {0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714,
12395 + 0x00000000},
12396 + {0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720,
12397 + 0x00000000},
12398 + {0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724,
12399 + 0x00000000},
12400 + {0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728,
12401 + 0x00000000},
12402 + {0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c,
12403 + 0x00000000},
12404 + {0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0,
12405 + 0x00000000},
12406 + {0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4,
12407 + 0x00000000},
12408 + {0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8,
12409 + 0x00000000},
12410 + {0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0,
12411 + 0x00000000},
12412 + {0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4,
12413 + 0x00000000},
12414 + {0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8,
12415 + 0x00000000},
12416 + {0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5,
12417 + 0x00000000},
12418 + {0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9,
12419 + 0x00000000},
12420 + {0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad,
12421 + 0x00000000},
12422 + {0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1,
12423 + 0x00000000},
12424 + {0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5,
12425 + 0x00000000},
12426 + {0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9,
12427 + 0x00000000},
12428 + {0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5,
12429 + 0x00000000},
12430 + {0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9,
12431 + 0x00000000},
12432 + {0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1,
12433 + 0x00000000},
12434 + {0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5,
12435 + 0x00000000},
12436 + {0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9,
12437 + 0x00000000},
12438 + {0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6,
12439 + 0x00000000},
12440 + {0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca,
12441 + 0x00000000},
12442 + {0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce,
12443 + 0x00000000},
12444 + {0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2,
12445 + 0x00000000},
12446 + {0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6,
12447 + 0x00000000},
12448 + {0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3,
12449 + 0x00000000},
12450 + {0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7,
12451 + 0x00000000},
12452 + {0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb,
12453 + 0x00000000},
12454 + {0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf,
12455 + 0x00000000},
12456 + {0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7,
12457 + 0x00000000},
12458 + {0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12459 + 0x00000000},
12460 + {0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12461 + 0x00000000},
12462 + {0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12463 + 0x00000000},
12464 + {0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12465 + 0x00000000},
12466 + {0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12467 + 0x00000000},
12468 + {0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12469 + 0x00000000},
12470 + {0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12471 + 0x00000000},
12472 + {0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12473 + 0x00000000},
12474 + {0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12475 + 0x00000000},
12476 + {0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12477 + 0x00000000},
12478 + {0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12479 + 0x00000000},
12480 + {0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12481 + 0x00000000},
12482 + {0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12483 + 0x00000000},
12484 + {0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12485 + 0x00000000},
12486 + {0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12487 + 0x00000000},
12488 + {0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12489 + 0x00000000},
12490 + {0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12491 + 0x00000000},
12492 + {0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12493 + 0x00000000},
12494 + {0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12495 + 0x00000000},
12496 + {0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12497 + 0x00000000},
12498 + {0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12499 + 0x00000000},
12500 + {0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12501 + 0x00000000},
12502 + {0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12503 + 0x00000000},
12504 + {0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12505 + 0x00000000},
12506 + {0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12507 + 0x00000000},
12508 + {0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12509 + 0x00000000},
12510 + {0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12511 + 0x00000000},
12512 + {0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12513 + 0x00000000},
12514 + {0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12515 + 0x00000000},
12516 + {0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12517 + 0x00000000},
12518 + {0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12519 + 0x00000000},
12520 + {0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12521 + 0x00000000},
12522 + {0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12523 + 0x00000000},
12524 + {0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12525 + 0x00000000},
12526 + {0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12527 + 0x00000000},
12528 + {0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12529 + 0x00000000},
12530 + {0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12531 + 0x00000000},
12532 + {0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12533 + 0x00000000},
12534 + {0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db,
12535 + 0x00000000},
12536 + {0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004,
12537 + 0x00000004},
12538 + {0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000,
12539 + 0x0001f000},
12540 + {0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000,
12541 + 0x0001f000},
12542 + {0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a,
12543 + 0x1883800a},
12544 + {0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108,
12545 + 0x00000000},
12546 + {0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000,
12547 + 0x0004a000},
12548 + {0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e,
12549 + 0x7999aa0e},
12550 +};
12551 +
12552 +static const u_int32_t ar9271Common_9271[][2] = {
12553 + {0x0000000c, 0x00000000},
12554 + {0x00000030, 0x00020045},
12555 + {0x00000034, 0x00000005},
12556 + {0x00000040, 0x00000000},
12557 + {0x00000044, 0x00000008},
12558 + {0x00000048, 0x00000008},
12559 + {0x0000004c, 0x00000010},
12560 + {0x00000050, 0x00000000},
12561 + {0x00000054, 0x0000001f},
12562 + {0x00000800, 0x00000000},
12563 + {0x00000804, 0x00000000},
12564 + {0x00000808, 0x00000000},
12565 + {0x0000080c, 0x00000000},
12566 + {0x00000810, 0x00000000},
12567 + {0x00000814, 0x00000000},
12568 + {0x00000818, 0x00000000},
12569 + {0x0000081c, 0x00000000},
12570 + {0x00000820, 0x00000000},
12571 + {0x00000824, 0x00000000},
12572 + {0x00001040, 0x002ffc0f},
12573 + {0x00001044, 0x002ffc0f},
12574 + {0x00001048, 0x002ffc0f},
12575 + {0x0000104c, 0x002ffc0f},
12576 + {0x00001050, 0x002ffc0f},
12577 + {0x00001054, 0x002ffc0f},
12578 + {0x00001058, 0x002ffc0f},
12579 + {0x0000105c, 0x002ffc0f},
12580 + {0x00001060, 0x002ffc0f},
12581 + {0x00001064, 0x002ffc0f},
12582 + {0x00001230, 0x00000000},
12583 + {0x00001270, 0x00000000},
12584 + {0x00001038, 0x00000000},
12585 + {0x00001078, 0x00000000},
12586 + {0x000010b8, 0x00000000},
12587 + {0x000010f8, 0x00000000},
12588 + {0x00001138, 0x00000000},
12589 + {0x00001178, 0x00000000},
12590 + {0x000011b8, 0x00000000},
12591 + {0x000011f8, 0x00000000},
12592 + {0x00001238, 0x00000000},
12593 + {0x00001278, 0x00000000},
12594 + {0x000012b8, 0x00000000},
12595 + {0x000012f8, 0x00000000},
12596 + {0x00001338, 0x00000000},
12597 + {0x00001378, 0x00000000},
12598 + {0x000013b8, 0x00000000},
12599 + {0x000013f8, 0x00000000},
12600 + {0x00001438, 0x00000000},
12601 + {0x00001478, 0x00000000},
12602 + {0x000014b8, 0x00000000},
12603 + {0x000014f8, 0x00000000},
12604 + {0x00001538, 0x00000000},
12605 + {0x00001578, 0x00000000},
12606 + {0x000015b8, 0x00000000},
12607 + {0x000015f8, 0x00000000},
12608 + {0x00001638, 0x00000000},
12609 + {0x00001678, 0x00000000},
12610 + {0x000016b8, 0x00000000},
12611 + {0x000016f8, 0x00000000},
12612 + {0x00001738, 0x00000000},
12613 + {0x00001778, 0x00000000},
12614 + {0x000017b8, 0x00000000},
12615 + {0x000017f8, 0x00000000},
12616 + {0x0000103c, 0x00000000},
12617 + {0x0000107c, 0x00000000},
12618 + {0x000010bc, 0x00000000},
12619 + {0x000010fc, 0x00000000},
12620 + {0x0000113c, 0x00000000},
12621 + {0x0000117c, 0x00000000},
12622 + {0x000011bc, 0x00000000},
12623 + {0x000011fc, 0x00000000},
12624 + {0x0000123c, 0x00000000},
12625 + {0x0000127c, 0x00000000},
12626 + {0x000012bc, 0x00000000},
12627 + {0x000012fc, 0x00000000},
12628 + {0x0000133c, 0x00000000},
12629 + {0x0000137c, 0x00000000},
12630 + {0x000013bc, 0x00000000},
12631 + {0x000013fc, 0x00000000},
12632 + {0x0000143c, 0x00000000},
12633 + {0x0000147c, 0x00000000},
12634 + {0x00004030, 0x00000002},
12635 + {0x0000403c, 0x00000002},
12636 + {0x00004024, 0x0000001f},
12637 + {0x00004060, 0x00000000},
12638 + {0x00004064, 0x00000000},
12639 + {0x00008004, 0x00000000},
12640 + {0x00008008, 0x00000000},
12641 + {0x0000800c, 0x00000000},
12642 + {0x00008018, 0x00000700},
12643 + {0x00008020, 0x00000000},
12644 + {0x00008038, 0x00000000},
12645 + {0x0000803c, 0x00000000},
12646 + {0x00008048, 0x00000000},
12647 + {0x00008054, 0x00000000},
12648 + {0x00008058, 0x00000000},
12649 + {0x0000805c, 0x000fc78f},
12650 + {0x00008060, 0x0000000f},
12651 + {0x00008064, 0x00000000},
12652 + {0x00008070, 0x00000000},
12653 + {0x000080b0, 0x00000000},
12654 + {0x000080b4, 0x00000000},
12655 + {0x000080b8, 0x00000000},
12656 + {0x000080bc, 0x00000000},
12657 + {0x000080c0, 0x2a80001a},
12658 + {0x000080c4, 0x05dc01e0},
12659 + {0x000080c8, 0x1f402710},
12660 + {0x000080cc, 0x01f40000},
12661 + {0x000080d0, 0x00001e00},
12662 + {0x000080d4, 0x00000000},
12663 + {0x000080d8, 0x00400000},
12664 + {0x000080e0, 0xffffffff},
12665 + {0x000080e4, 0x0000ffff},
12666 + {0x000080e8, 0x003f3f3f},
12667 + {0x000080ec, 0x00000000},
12668 + {0x000080f0, 0x00000000},
12669 + {0x000080f4, 0x00000000},
12670 + {0x000080f8, 0x00000000},
12671 + {0x000080fc, 0x00020000},
12672 + {0x00008100, 0x00020000},
12673 + {0x00008104, 0x00000001},
12674 + {0x00008108, 0x00000052},
12675 + {0x0000810c, 0x00000000},
12676 + {0x00008110, 0x00000168},
12677 + {0x00008118, 0x000100aa},
12678 + {0x0000811c, 0x00003210},
12679 + {0x00008120, 0x08f04810},
12680 + {0x00008124, 0x00000000},
12681 + {0x00008128, 0x00000000},
12682 + {0x0000812c, 0x00000000},
12683 + {0x00008130, 0x00000000},
12684 + {0x00008134, 0x00000000},
12685 + {0x00008138, 0x00000000},
12686 + {0x0000813c, 0x00000000},
12687 + {0x00008144, 0xffffffff},
12688 + {0x00008168, 0x00000000},
12689 + {0x0000816c, 0x00000000},
12690 + {0x00008170, 0x32143320},
12691 + {0x00008174, 0xfaa4fa50},
12692 + {0x00008178, 0x00000100},
12693 + {0x0000817c, 0x00000000},
12694 + {0x000081c0, 0x00000000},
12695 + {0x000081d0, 0x0000320a},
12696 + {0x000081ec, 0x00000000},
12697 + {0x000081f0, 0x00000000},
12698 + {0x000081f4, 0x00000000},
12699 + {0x000081f8, 0x00000000},
12700 + {0x000081fc, 0x00000000},
12701 + {0x00008200, 0x00000000},
12702 + {0x00008204, 0x00000000},
12703 + {0x00008208, 0x00000000},
12704 + {0x0000820c, 0x00000000},
12705 + {0x00008210, 0x00000000},
12706 + {0x00008214, 0x00000000},
12707 + {0x00008218, 0x00000000},
12708 + {0x0000821c, 0x00000000},
12709 + {0x00008220, 0x00000000},
12710 + {0x00008224, 0x00000000},
12711 + {0x00008228, 0x00000000},
12712 + {0x0000822c, 0x00000000},
12713 + {0x00008230, 0x00000000},
12714 + {0x00008234, 0x00000000},
12715 + {0x00008238, 0x00000000},
12716 + {0x0000823c, 0x00000000},
12717 + {0x00008240, 0x00100000},
12718 + {0x00008244, 0x0010f400},
12719 + {0x00008248, 0x00000100},
12720 + {0x0000824c, 0x0001e800},
12721 + {0x00008250, 0x00000000},
12722 + {0x00008254, 0x00000000},
12723 + {0x00008258, 0x00000000},
12724 + {0x0000825c, 0x400000ff},
12725 + {0x00008260, 0x00080922},
12726 + {0x00008264, 0xa8a00010},
12727 + {0x00008270, 0x00000000},
12728 + {0x00008274, 0x40000000},
12729 + {0x00008278, 0x003e4180},
12730 + {0x0000827c, 0x00000000},
12731 + {0x00008284, 0x0000002c},
12732 + {0x00008288, 0x0000002c},
12733 + {0x0000828c, 0x00000000},
12734 + {0x00008294, 0x00000000},
12735 + {0x00008298, 0x00000000},
12736 + {0x0000829c, 0x00000000},
12737 + {0x00008300, 0x00000040},
12738 + {0x00008314, 0x00000000},
12739 + {0x00008328, 0x00000000},
12740 + {0x0000832c, 0x00000001},
12741 + {0x00008330, 0x00000302},
12742 + {0x00008334, 0x00000e00},
12743 + {0x00008338, 0x00ff0000},
12744 + {0x0000833c, 0x00000000},
12745 + {0x00008340, 0x00010380},
12746 + {0x00008344, 0x00581043},
12747 + {0x00007010, 0x00000030},
12748 + {0x00007034, 0x00000002},
12749 + {0x00007038, 0x000004c2},
12750 + {0x00007800, 0x00140000},
12751 + {0x00007804, 0x0e4548d8},
12752 + {0x00007808, 0x54214514},
12753 + {0x0000780c, 0x02025820},
12754 + {0x00007810, 0x71c0d388},
12755 + {0x00007814, 0x924934a8},
12756 + {0x0000781c, 0x00000000},
12757 + {0x00007828, 0x66964300},
12758 + {0x0000782c, 0x8db6d961},
12759 + {0x00007830, 0x8db6d96c},
12760 + {0x00007834, 0x6140008b},
12761 + {0x0000783c, 0x72ee0a72},
12762 + {0x00007840, 0xbbfffffc},
12763 + {0x00007844, 0x000c0db6},
12764 + {0x00007848, 0x6db61b6f},
12765 + {0x0000784c, 0x6d9b66db},
12766 + {0x00007850, 0x6d8c6dba},
12767 + {0x00007854, 0x00040000},
12768 + {0x00007858, 0xdb003012},
12769 + {0x0000785c, 0x04924914},
12770 + {0x00007860, 0x21084210},
12771 + {0x00007864, 0xf7d7ffde},
12772 + {0x00007868, 0xc2034080},
12773 + {0x00007870, 0x10142c00},
12774 + {0x00009808, 0x00000000},
12775 + {0x0000980c, 0xafe68e30},
12776 + {0x00009810, 0xfd14e000},
12777 + {0x00009814, 0x9c0a9f6b},
12778 + {0x0000981c, 0x00000000},
12779 + {0x0000982c, 0x0000a000},
12780 + {0x00009830, 0x00000000},
12781 + {0x0000983c, 0x00200400},
12782 + {0x0000984c, 0x0040233c},
12783 + {0x00009854, 0x00000044},
12784 + {0x00009900, 0x00000000},
12785 + {0x00009904, 0x00000000},
12786 + {0x00009908, 0x00000000},
12787 + {0x0000990c, 0x00000000},
12788 + {0x0000991c, 0x10000fff},
12789 + {0x00009920, 0x04900000},
12790 + {0x00009928, 0x00000001},
12791 + {0x0000992c, 0x00000004},
12792 + {0x00009934, 0x1e1f2022},
12793 + {0x00009938, 0x0a0b0c0d},
12794 + {0x0000993c, 0x00000000},
12795 + {0x00009940, 0x14750604},
12796 + {0x00009948, 0x9280c00a},
12797 + {0x0000994c, 0x00020028},
12798 + {0x00009954, 0x5f3ca3de},
12799 + {0x00009958, 0x0108ecff},
12800 + {0x00009968, 0x000003ce},
12801 + {0x00009970, 0x192bb514},
12802 + {0x00009974, 0x00000000},
12803 + {0x00009978, 0x00000001},
12804 + {0x0000997c, 0x00000000},
12805 + {0x00009980, 0x00000000},
12806 + {0x00009984, 0x00000000},
12807 + {0x00009988, 0x00000000},
12808 + {0x0000998c, 0x00000000},
12809 + {0x00009990, 0x00000000},
12810 + {0x00009994, 0x00000000},
12811 + {0x00009998, 0x00000000},
12812 + {0x0000999c, 0x00000000},
12813 + {0x000099a0, 0x00000000},
12814 + {0x000099a4, 0x00000001},
12815 + {0x000099a8, 0x201fff00},
12816 + {0x000099ac, 0x2def0400},
12817 + {0x000099b0, 0x03051000},
12818 + {0x000099b4, 0x00000820},
12819 + {0x000099dc, 0x00000000},
12820 + {0x000099e0, 0x00000000},
12821 + {0x000099e4, 0xaaaaaaaa},
12822 + {0x000099e8, 0x3c466478},
12823 + {0x000099ec, 0x0cc80caa},
12824 + {0x000099f0, 0x00000000},
12825 + {0x0000a208, 0x803e68c8},
12826 + {0x0000a210, 0x4080a333},
12827 + {0x0000a214, 0x00206c10},
12828 + {0x0000a218, 0x009c4060},
12829 + {0x0000a220, 0x01834061},
12830 + {0x0000a224, 0x00000400},
12831 + {0x0000a228, 0x000003b5},
12832 + {0x0000a22c, 0x00000000},
12833 + {0x0000a234, 0x20202020},
12834 + {0x0000a238, 0x20202020},
12835 + {0x0000a244, 0x00000000},
12836 + {0x0000a248, 0xfffffffc},
12837 + {0x0000a24c, 0x00000000},
12838 + {0x0000a254, 0x00000000},
12839 + {0x0000a258, 0x0ccb5380},
12840 + {0x0000a25c, 0x15151501},
12841 + {0x0000a260, 0xdfa90f01},
12842 + {0x0000a268, 0x00000000},
12843 + {0x0000a26c, 0x0ebae9e6},
12844 + {0x0000a388, 0x0c000000},
12845 + {0x0000a38c, 0x20202020},
12846 + {0x0000a390, 0x20202020},
12847 + {0x0000a39c, 0x00000001},
12848 + {0x0000a3a0, 0x00000000},
12849 + {0x0000a3a4, 0x00000000},
12850 + {0x0000a3a8, 0x00000000},
12851 + {0x0000a3ac, 0x00000000},
12852 + {0x0000a3b0, 0x00000000},
12853 + {0x0000a3b4, 0x00000000},
12854 + {0x0000a3b8, 0x00000000},
12855 + {0x0000a3bc, 0x00000000},
12856 + {0x0000a3c0, 0x00000000},
12857 + {0x0000a3c4, 0x00000000},
12858 + {0x0000a3cc, 0x20202020},
12859 + {0x0000a3d0, 0x20202020},
12860 + {0x0000a3d4, 0x20202020},
12861 + {0x0000a3e4, 0x00000000},
12862 + {0x0000a3e8, 0x18c43433},
12863 + {0x0000a3ec, 0x00f70081},
12864 + {0x0000a3f0, 0x01036a2f},
12865 + {0x0000a3f4, 0x00000000},
12866 + {0x0000d270, 0x0d820820},
12867 + {0x0000d35c, 0x07ffffef},
12868 + {0x0000d360, 0x0fffffe7},
12869 + {0x0000d364, 0x17ffffe5},
12870 + {0x0000d368, 0x1fffffe4},
12871 + {0x0000d36c, 0x37ffffe3},
12872 + {0x0000d370, 0x3fffffe3},
12873 + {0x0000d374, 0x57ffffe3},
12874 + {0x0000d378, 0x5fffffe2},
12875 + {0x0000d37c, 0x7fffffe2},
12876 + {0x0000d380, 0x7f3c7bba},
12877 + {0x0000d384, 0xf3307ff0},
12878 +};
12879 +
12880 +static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = {
12881 + {0x0000a1f4, 0x00fffeff},
12882 + {0x0000a1f8, 0x00f5f9ff},
12883 + {0x0000a1fc, 0xb79f6427},
12884 +};
12885 +
12886 +static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
12887 + {0x0000a1f4, 0x00000000},
12888 + {0x0000a1f8, 0xefff0301},
12889 + {0x0000a1fc, 0xca9228ee},
12890 +};
12891 +
12892 +static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
12893 + {0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311,
12894 + 0x30002311},
12895 + {0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001,
12896 + 0x0a020001},
12897 +};
12898 +
12899 +static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
12900 + {0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2,
12901 + 0x6d4000e2},
12902 + {0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e,
12903 + 0x3139605e},
12904 + {0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e,
12905 + 0x7ec84d2e},
12906 + {0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881,
12907 + 0x06903881},
12908 + {0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0,
12909 + 0x5ac640d0},
12910 + {0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8,
12911 + 0x803e68c8},
12912 + {0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d,
12913 + 0xd00a800d},
12914 + {0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4,
12915 + 0x05eea6d4},
12916 +};
12917 +
12918 +static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
12919 + {0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12920 + 0x00000000},
12921 + {0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200,
12922 + 0x00000000},
12923 + {0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208,
12924 + 0x00000000},
12925 + {0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608,
12926 + 0x00000000},
12927 + {0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610,
12928 + 0x00000000},
12929 + {0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0,
12930 + 0x00000000},
12931 + {0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758,
12932 + 0x00000000},
12933 + {0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759,
12934 + 0x00000000},
12935 + {0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a,
12936 + 0x00000000},
12937 + {0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c,
12938 + 0x00000000},
12939 + {0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e,
12940 + 0x00000000},
12941 + {0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f,
12942 + 0x00000000},
12943 + {0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df,
12944 + 0x00000000},
12945 + {0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de,
12946 + 0x00000000},
12947 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
12948 + 0x00000000},
12949 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
12950 + 0x00000000},
12951 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12952 + 0x00000000},
12953 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12954 + 0x00000000},
12955 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12956 + 0x00000000},
12957 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12958 + 0x00000000},
12959 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12960 + 0x00000000},
12961 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
12962 + 0x00000000},
12963 + {0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029,
12964 + 0x00000029},
12965 + {0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff,
12966 + 0x00d8abff},
12967 + {0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4,
12968 + 0x48609eb4},
12969 + {0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04,
12970 + 0x00000c04},
12971 + {0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652,
12972 + 0x0a22a652},
12973 + {0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd,
12974 + 0x3bdef7bd},
12975 + {0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd,
12976 + 0x050e83bd},
12977 + {0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd,
12978 + 0x3bdef7bd},
12979 + {0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd,
12980 + 0x000003bd},
12981 + {0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd,
12982 + 0x3bdef7bd},
12983 + {0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd,
12984 + 0x000003bd},
12985 +};
12986 +
12987 +static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
12988 + {0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000,
12989 + 0x00000000},
12990 + {0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200,
12991 + 0x00000000},
12992 + {0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201,
12993 + 0x00000000},
12994 + {0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240,
12995 + 0x00000000},
12996 + {0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241,
12997 + 0x00000000},
12998 + {0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600,
12999 + 0x00000000},
13000 + {0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800,
13001 + 0x00000000},
13002 + {0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802,
13003 + 0x00000000},
13004 + {0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805,
13005 + 0x00000000},
13006 + {0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41,
13007 + 0x00000000},
13008 + {0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00,
13009 + 0x00000000},
13010 + {0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40,
13011 + 0x00000000},
13012 + {0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80,
13013 + 0x00000000},
13014 + {0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de,
13015 + 0x00000000},
13016 + {0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e,
13017 + 0x00000000},
13018 + {0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e,
13019 + 0x00000000},
13020 + {0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13021 + 0x00000000},
13022 + {0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13023 + 0x00000000},
13024 + {0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13025 + 0x00000000},
13026 + {0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13027 + 0x00000000},
13028 + {0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13029 + 0x00000000},
13030 + {0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df,
13031 + 0x00000000},
13032 + {0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b,
13033 + 0x0000002b},
13034 + {0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff,
13035 + 0x00d8a7ff},
13036 + {0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba,
13037 + 0x08609eb6},
13038 + {0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00,
13039 + 0x00000c00},
13040 + {0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a212652, 0x0a212652,
13041 + 0x0a22a652},
13042 + {0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7,
13043 + 0x0e739ce7},
13044 + {0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063,
13045 + 0x05018063},
13046 + {0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63,
13047 + 0x06318c63},
13048 + {0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063,
13049 + 0x00000063},
13050 + {0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63,
13051 + 0x06318c63},
13052 + {0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063,
13053 + 0x00000063},
13054 +};
13055 +
13056 +#endif /* INITVALS_9002_10_H */
13057 --- /dev/null
13058 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
13059 @@ -0,0 +1,474 @@
13060 +/*
13061 + * Copyright (c) 2008-2010 Atheros Communications Inc.
13062 + *
13063 + * Permission to use, copy, modify, and/or distribute this software for any
13064 + * purpose with or without fee is hereby granted, provided that the above
13065 + * copyright notice and this permission notice appear in all copies.
13066 + *
13067 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13068 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13069 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13070 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13071 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13072 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
13073 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13074 + */
13075 +
13076 +#include "hw.h"
13077 +
13078 +static void ar9002_hw_rx_enable(struct ath_hw *ah)
13079 +{
13080 + REG_WRITE(ah, AR_CR, AR_CR_RXE);
13081 +}
13082 +
13083 +static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
13084 +{
13085 + ((struct ath_desc*) ds)->ds_link = ds_link;
13086 +}
13087 +
13088 +static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
13089 +{
13090 + *ds_link = &((struct ath_desc *)ds)->ds_link;
13091 +}
13092 +
13093 +static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
13094 +{
13095 + u32 isr = 0;
13096 + u32 mask2 = 0;
13097 + struct ath9k_hw_capabilities *pCap = &ah->caps;
13098 + u32 sync_cause = 0;
13099 + bool fatal_int = false;
13100 + struct ath_common *common = ath9k_hw_common(ah);
13101 +
13102 + if (!AR_SREV_9100(ah)) {
13103 + if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
13104 + if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
13105 + == AR_RTC_STATUS_ON) {
13106 + isr = REG_READ(ah, AR_ISR);
13107 + }
13108 + }
13109 +
13110 + sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
13111 + AR_INTR_SYNC_DEFAULT;
13112 +
13113 + *masked = 0;
13114 +
13115 + if (!isr && !sync_cause)
13116 + return false;
13117 + } else {
13118 + *masked = 0;
13119 + isr = REG_READ(ah, AR_ISR);
13120 + }
13121 +
13122 + if (isr) {
13123 + if (isr & AR_ISR_BCNMISC) {
13124 + u32 isr2;
13125 + isr2 = REG_READ(ah, AR_ISR_S2);
13126 + if (isr2 & AR_ISR_S2_TIM)
13127 + mask2 |= ATH9K_INT_TIM;
13128 + if (isr2 & AR_ISR_S2_DTIM)
13129 + mask2 |= ATH9K_INT_DTIM;
13130 + if (isr2 & AR_ISR_S2_DTIMSYNC)
13131 + mask2 |= ATH9K_INT_DTIMSYNC;
13132 + if (isr2 & (AR_ISR_S2_CABEND))
13133 + mask2 |= ATH9K_INT_CABEND;
13134 + if (isr2 & AR_ISR_S2_GTT)
13135 + mask2 |= ATH9K_INT_GTT;
13136 + if (isr2 & AR_ISR_S2_CST)
13137 + mask2 |= ATH9K_INT_CST;
13138 + if (isr2 & AR_ISR_S2_TSFOOR)
13139 + mask2 |= ATH9K_INT_TSFOOR;
13140 + }
13141 +
13142 + isr = REG_READ(ah, AR_ISR_RAC);
13143 + if (isr == 0xffffffff) {
13144 + *masked = 0;
13145 + return false;
13146 + }
13147 +
13148 + *masked = isr & ATH9K_INT_COMMON;
13149 +
13150 + if (ah->config.rx_intr_mitigation) {
13151 + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
13152 + *masked |= ATH9K_INT_RX;
13153 + }
13154 +
13155 + if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
13156 + *masked |= ATH9K_INT_RX;
13157 + if (isr &
13158 + (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
13159 + AR_ISR_TXEOL)) {
13160 + u32 s0_s, s1_s;
13161 +
13162 + *masked |= ATH9K_INT_TX;
13163 +
13164 + s0_s = REG_READ(ah, AR_ISR_S0_S);
13165 + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
13166 + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
13167 +
13168 + s1_s = REG_READ(ah, AR_ISR_S1_S);
13169 + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
13170 + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
13171 + }
13172 +
13173 + if (isr & AR_ISR_RXORN) {
13174 + ath_print(common, ATH_DBG_INTERRUPT,
13175 + "receive FIFO overrun interrupt\n");
13176 + }
13177 +
13178 + if (!AR_SREV_9100(ah)) {
13179 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
13180 + u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
13181 + if (isr5 & AR_ISR_S5_TIM_TIMER)
13182 + *masked |= ATH9K_INT_TIM_TIMER;
13183 + }
13184 + }
13185 +
13186 + *masked |= mask2;
13187 + }
13188 +
13189 + if (AR_SREV_9100(ah))
13190 + return true;
13191 +
13192 + if (isr & AR_ISR_GENTMR) {
13193 + u32 s5_s;
13194 +
13195 + s5_s = REG_READ(ah, AR_ISR_S5_S);
13196 + if (isr & AR_ISR_GENTMR) {
13197 + ah->intr_gen_timer_trigger =
13198 + MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
13199 +
13200 + ah->intr_gen_timer_thresh =
13201 + MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
13202 +
13203 + if (ah->intr_gen_timer_trigger)
13204 + *masked |= ATH9K_INT_GENTIMER;
13205 +
13206 + }
13207 + }
13208 +
13209 + if (sync_cause) {
13210 + fatal_int =
13211 + (sync_cause &
13212 + (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
13213 + ? true : false;
13214 +
13215 + if (fatal_int) {
13216 + if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
13217 + ath_print(common, ATH_DBG_ANY,
13218 + "received PCI FATAL interrupt\n");
13219 + }
13220 + if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
13221 + ath_print(common, ATH_DBG_ANY,
13222 + "received PCI PERR interrupt\n");
13223 + }
13224 + *masked |= ATH9K_INT_FATAL;
13225 + }
13226 + if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
13227 + ath_print(common, ATH_DBG_INTERRUPT,
13228 + "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
13229 + REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
13230 + REG_WRITE(ah, AR_RC, 0);
13231 + *masked |= ATH9K_INT_FATAL;
13232 + }
13233 + if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
13234 + ath_print(common, ATH_DBG_INTERRUPT,
13235 + "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
13236 + }
13237 +
13238 + REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
13239 + (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
13240 + }
13241 + return true;
13242 +}
13243 +
13244 +static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
13245 + bool is_firstseg, bool is_lastseg,
13246 + const void *ds0, dma_addr_t buf_addr,
13247 + unsigned int qcu)
13248 +{
13249 + struct ar5416_desc *ads = AR5416DESC(ds);
13250 +
13251 + ads->ds_data = buf_addr;
13252 +
13253 + if (is_firstseg) {
13254 + ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
13255 + } else if (is_lastseg) {
13256 + ads->ds_ctl0 = 0;
13257 + ads->ds_ctl1 = seglen;
13258 + ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
13259 + ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
13260 + } else {
13261 + ads->ds_ctl0 = 0;
13262 + ads->ds_ctl1 = seglen | AR_TxMore;
13263 + ads->ds_ctl2 = 0;
13264 + ads->ds_ctl3 = 0;
13265 + }
13266 + ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
13267 + ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
13268 + ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
13269 + ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
13270 + ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
13271 +}
13272 +
13273 +static void ar9002_hw_clear_txdesc(struct ath_hw *ah, void *ds)
13274 +{
13275 + struct ar5416_desc *ads = AR5416DESC(ds);
13276 +
13277 + ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
13278 + ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
13279 + ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
13280 + ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
13281 + ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
13282 +}
13283 +
13284 +static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
13285 + struct ath_tx_status *ts)
13286 +{
13287 + struct ar5416_desc *ads = AR5416DESC(ds);
13288 +
13289 + if ((ads->ds_txstatus9 & AR_TxDone) == 0)
13290 + return -EINPROGRESS;
13291 +
13292 + ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
13293 + ts->ts_tstamp = ads->AR_SendTimestamp;
13294 + ts->ts_status = 0;
13295 + ts->ts_flags = 0;
13296 +
13297 + if (ads->ds_txstatus1 & AR_FrmXmitOK)
13298 + ts->ts_status |= ATH9K_TX_ACKED;
13299 + if (ads->ds_txstatus1 & AR_ExcessiveRetries)
13300 + ts->ts_status |= ATH9K_TXERR_XRETRY;
13301 + if (ads->ds_txstatus1 & AR_Filtered)
13302 + ts->ts_status |= ATH9K_TXERR_FILT;
13303 + if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
13304 + ts->ts_status |= ATH9K_TXERR_FIFO;
13305 + ath9k_hw_updatetxtriglevel(ah, true);
13306 + }
13307 + if (ads->ds_txstatus9 & AR_TxOpExceeded)
13308 + ts->ts_status |= ATH9K_TXERR_XTXOP;
13309 + if (ads->ds_txstatus1 & AR_TxTimerExpired)
13310 + ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
13311 +
13312 + if (ads->ds_txstatus1 & AR_DescCfgErr)
13313 + ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
13314 + if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
13315 + ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
13316 + ath9k_hw_updatetxtriglevel(ah, true);
13317 + }
13318 + if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
13319 + ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
13320 + ath9k_hw_updatetxtriglevel(ah, true);
13321 + }
13322 + if (ads->ds_txstatus0 & AR_TxBaStatus) {
13323 + ts->ts_flags |= ATH9K_TX_BA;
13324 + ts->ba_low = ads->AR_BaBitmapLow;
13325 + ts->ba_high = ads->AR_BaBitmapHigh;
13326 + }
13327 +
13328 + ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
13329 + switch (ts->ts_rateindex) {
13330 + case 0:
13331 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
13332 + break;
13333 + case 1:
13334 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
13335 + break;
13336 + case 2:
13337 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
13338 + break;
13339 + case 3:
13340 + ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
13341 + break;
13342 + }
13343 +
13344 + ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
13345 + ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
13346 + ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
13347 + ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
13348 + ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
13349 + ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
13350 + ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
13351 + ts->evm0 = ads->AR_TxEVM0;
13352 + ts->evm1 = ads->AR_TxEVM1;
13353 + ts->evm2 = ads->AR_TxEVM2;
13354 + ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
13355 + ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
13356 + ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
13357 + ts->ts_antenna = 0;
13358 +
13359 + return 0;
13360 +}
13361 +
13362 +static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
13363 + u32 pktLen, enum ath9k_pkt_type type,
13364 + u32 txPower, u32 keyIx,
13365 + enum ath9k_key_type keyType, u32 flags)
13366 +{
13367 + struct ar5416_desc *ads = AR5416DESC(ds);
13368 +
13369 +
13370 + txPower += ah->txpower_indexoffset;
13371 + if (txPower > 63)
13372 + txPower = 63;
13373 +
13374 + ads->ds_ctl0 = (pktLen & AR_FrameLen)
13375 + | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
13376 + | SM(txPower, AR_XmitPower)
13377 + | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
13378 + | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
13379 + | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
13380 + | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
13381 +
13382 + ads->ds_ctl1 =
13383 + (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
13384 + | SM(type, AR_FrameType)
13385 + | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
13386 + | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
13387 + | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
13388 +
13389 + ads->ds_ctl6 = SM(keyType, AR_EncrType);
13390 +
13391 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
13392 + ads->ds_ctl8 = 0;
13393 + ads->ds_ctl9 = 0;
13394 + ads->ds_ctl10 = 0;
13395 + ads->ds_ctl11 = 0;
13396 + }
13397 +}
13398 +
13399 +static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
13400 + void *lastds,
13401 + u32 durUpdateEn, u32 rtsctsRate,
13402 + u32 rtsctsDuration,
13403 + struct ath9k_11n_rate_series series[],
13404 + u32 nseries, u32 flags)
13405 +{
13406 + struct ar5416_desc *ads = AR5416DESC(ds);
13407 + struct ar5416_desc *last_ads = AR5416DESC(lastds);
13408 + u32 ds_ctl0;
13409 +
13410 + if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
13411 + ds_ctl0 = ads->ds_ctl0;
13412 +
13413 + if (flags & ATH9K_TXDESC_RTSENA) {
13414 + ds_ctl0 &= ~AR_CTSEnable;
13415 + ds_ctl0 |= AR_RTSEnable;
13416 + } else {
13417 + ds_ctl0 &= ~AR_RTSEnable;
13418 + ds_ctl0 |= AR_CTSEnable;
13419 + }
13420 +
13421 + ads->ds_ctl0 = ds_ctl0;
13422 + } else {
13423 + ads->ds_ctl0 =
13424 + (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
13425 + }
13426 +
13427 + ads->ds_ctl2 = set11nTries(series, 0)
13428 + | set11nTries(series, 1)
13429 + | set11nTries(series, 2)
13430 + | set11nTries(series, 3)
13431 + | (durUpdateEn ? AR_DurUpdateEna : 0)
13432 + | SM(0, AR_BurstDur);
13433 +
13434 + ads->ds_ctl3 = set11nRate(series, 0)
13435 + | set11nRate(series, 1)
13436 + | set11nRate(series, 2)
13437 + | set11nRate(series, 3);
13438 +
13439 + ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
13440 + | set11nPktDurRTSCTS(series, 1);
13441 +
13442 + ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
13443 + | set11nPktDurRTSCTS(series, 3);
13444 +
13445 + ads->ds_ctl7 = set11nRateFlags(series, 0)
13446 + | set11nRateFlags(series, 1)
13447 + | set11nRateFlags(series, 2)
13448 + | set11nRateFlags(series, 3)
13449 + | SM(rtsctsRate, AR_RTSCTSRate);
13450 + last_ads->ds_ctl2 = ads->ds_ctl2;
13451 + last_ads->ds_ctl3 = ads->ds_ctl3;
13452 +}
13453 +
13454 +static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
13455 + u32 aggrLen)
13456 +{
13457 + struct ar5416_desc *ads = AR5416DESC(ds);
13458 +
13459 + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
13460 + ads->ds_ctl6 &= ~AR_AggrLen;
13461 + ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
13462 +}
13463 +
13464 +static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
13465 + u32 numDelims)
13466 +{
13467 + struct ar5416_desc *ads = AR5416DESC(ds);
13468 + unsigned int ctl6;
13469 +
13470 + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
13471 +
13472 + ctl6 = ads->ds_ctl6;
13473 + ctl6 &= ~AR_PadDelim;
13474 + ctl6 |= SM(numDelims, AR_PadDelim);
13475 + ads->ds_ctl6 = ctl6;
13476 +}
13477 +
13478 +static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
13479 +{
13480 + struct ar5416_desc *ads = AR5416DESC(ds);
13481 +
13482 + ads->ds_ctl1 |= AR_IsAggr;
13483 + ads->ds_ctl1 &= ~AR_MoreAggr;
13484 + ads->ds_ctl6 &= ~AR_PadDelim;
13485 +}
13486 +
13487 +static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
13488 +{
13489 + struct ar5416_desc *ads = AR5416DESC(ds);
13490 +
13491 + ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
13492 +}
13493 +
13494 +static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
13495 + u32 burstDuration)
13496 +{
13497 + struct ar5416_desc *ads = AR5416DESC(ds);
13498 +
13499 + ads->ds_ctl2 &= ~AR_BurstDur;
13500 + ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
13501 +}
13502 +
13503 +static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
13504 + u32 vmf)
13505 +{
13506 + struct ar5416_desc *ads = AR5416DESC(ds);
13507 +
13508 + if (vmf)
13509 + ads->ds_ctl0 |= AR_VirtMoreFrag;
13510 + else
13511 + ads->ds_ctl0 &= ~AR_VirtMoreFrag;
13512 +}
13513 +
13514 +void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
13515 +{
13516 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
13517 +
13518 + ops->rx_enable = ar9002_hw_rx_enable;
13519 + ops->set_desc_link = ar9002_hw_set_desc_link;
13520 + ops->get_desc_link = ar9002_hw_get_desc_link;
13521 + ops->get_isr = ar9002_hw_get_isr;
13522 + ops->fill_txdesc = ar9002_hw_fill_txdesc;
13523 + ops->clear_txdesc = ar9002_hw_clear_txdesc;
13524 + ops->proc_txdesc = ar9002_hw_proc_txdesc;
13525 + ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
13526 + ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
13527 + ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
13528 + ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
13529 + ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
13530 + ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
13531 + ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
13532 + ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
13533 +}
13534 --- /dev/null
13535 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
13536 @@ -0,0 +1,601 @@
13537 +/*
13538 + * Copyright (c) 2008-2010 Atheros Communications Inc.
13539 + *
13540 + * Permission to use, copy, modify, and/or distribute this software for any
13541 + * purpose with or without fee is hereby granted, provided that the above
13542 + * copyright notice and this permission notice appear in all copies.
13543 + *
13544 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13545 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13546 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13547 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13548 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13549 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
13550 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13551 + */
13552 +
13553 +/**
13554 + * DOC: Programming Atheros 802.11n analog front end radios
13555 + *
13556 + * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
13557 + * devices have either an external AR2133 analog front end radio for single
13558 + * band 2.4 GHz communication or an AR5133 analog front end radio for dual
13559 + * band 2.4 GHz / 5 GHz communication.
13560 + *
13561 + * All devices after the AR5416 and AR5418 family starting with the AR9280
13562 + * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
13563 + * into a single-chip and require less programming.
13564 + *
13565 + * The following single-chips exist with a respective embedded radio:
13566 + *
13567 + * AR9280 - 11n dual-band 2x2 MIMO for PCIe
13568 + * AR9281 - 11n single-band 1x2 MIMO for PCIe
13569 + * AR9285 - 11n single-band 1x1 for PCIe
13570 + * AR9287 - 11n single-band 2x2 MIMO for PCIe
13571 + *
13572 + * AR9220 - 11n dual-band 2x2 MIMO for PCI
13573 + * AR9223 - 11n single-band 2x2 MIMO for PCI
13574 + *
13575 + * AR9287 - 11n single-band 1x1 MIMO for USB
13576 + */
13577 +
13578 +#include "hw.h"
13579 +#include "ar9002_phy.h"
13580 +
13581 +/**
13582 + * ar9002_hw_set_channel - set channel on single-chip device
13583 + * @ah: atheros hardware structure
13584 + * @chan:
13585 + *
13586 + * This is the function to change channel on single-chip devices, that is
13587 + * all devices after ar9280.
13588 + *
13589 + * This function takes the channel value in MHz and sets
13590 + * hardware channel value. Assumes writes have been enabled to analog bus.
13591 + *
13592 + * Actual Expression,
13593 + *
13594 + * For 2GHz channel,
13595 + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
13596 + * (freq_ref = 40MHz)
13597 + *
13598 + * For 5GHz channel,
13599 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
13600 + * (freq_ref = 40MHz/(24>>amodeRefSel))
13601 + */
13602 +static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
13603 +{
13604 + u16 bMode, fracMode, aModeRefSel = 0;
13605 + u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
13606 + struct chan_centers centers;
13607 + u32 refDivA = 24;
13608 +
13609 + ath9k_hw_get_channel_centers(ah, chan, &centers);
13610 + freq = centers.synth_center;
13611 +
13612 + reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
13613 + reg32 &= 0xc0000000;
13614 +
13615 + if (freq < 4800) { /* 2 GHz, fractional mode */
13616 + u32 txctl;
13617 + int regWrites = 0;
13618 +
13619 + bMode = 1;
13620 + fracMode = 1;
13621 + aModeRefSel = 0;
13622 + channelSel = CHANSEL_2G(freq);
13623 +
13624 + if (AR_SREV_9287_11_OR_LATER(ah)) {
13625 + if (freq == 2484) {
13626 + /* Enable channel spreading for channel 14 */
13627 + REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
13628 + 1, regWrites);
13629 + } else {
13630 + REG_WRITE_ARRAY(&ah->iniCckfirNormal,
13631 + 1, regWrites);
13632 + }
13633 + } else {
13634 + txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
13635 + if (freq == 2484) {
13636 + /* Enable channel spreading for channel 14 */
13637 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
13638 + txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
13639 + } else {
13640 + REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
13641 + txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
13642 + }
13643 + }
13644 + } else {
13645 + bMode = 0;
13646 + fracMode = 0;
13647 +
13648 + switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
13649 + case 0:
13650 + if ((freq % 20) == 0) {
13651 + aModeRefSel = 3;
13652 + } else if ((freq % 10) == 0) {
13653 + aModeRefSel = 2;
13654 + }
13655 + if (aModeRefSel)
13656 + break;
13657 + case 1:
13658 + default:
13659 + aModeRefSel = 0;
13660 + /*
13661 + * Enable 2G (fractional) mode for channels
13662 + * which are 5MHz spaced.
13663 + */
13664 + fracMode = 1;
13665 + refDivA = 1;
13666 + channelSel = CHANSEL_5G(freq);
13667 +
13668 + /* RefDivA setting */
13669 + REG_RMW_FIELD(ah, AR_AN_SYNTH9,
13670 + AR_AN_SYNTH9_REFDIVA, refDivA);
13671 +
13672 + }
13673 +
13674 + if (!fracMode) {
13675 + ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
13676 + channelSel = ndiv & 0x1ff;
13677 + channelFrac = (ndiv & 0xfffffe00) * 2;
13678 + channelSel = (channelSel << 17) | channelFrac;
13679 + }
13680 + }
13681 +
13682 + reg32 = reg32 |
13683 + (bMode << 29) |
13684 + (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
13685 +
13686 + REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
13687 +
13688 + ah->curchan = chan;
13689 + ah->curchan_rad_index = -1;
13690 +
13691 + return 0;
13692 +}
13693 +
13694 +/**
13695 + * ar9002_hw_spur_mitigate - convert baseband spur frequency
13696 + * @ah: atheros hardware structure
13697 + * @chan:
13698 + *
13699 + * For single-chip solutions. Converts to baseband spur frequency given the
13700 + * input channel frequency and compute register settings below.
13701 + */
13702 +static void ar9002_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
13703 +{
13704 + int bb_spur = AR_NO_SPUR;
13705 + int freq;
13706 + int bin, cur_bin;
13707 + int bb_spur_off, spur_subchannel_sd;
13708 + int spur_freq_sd;
13709 + int spur_delta_phase;
13710 + int denominator;
13711 + int upper, lower, cur_vit_mask;
13712 + int tmp, newVal;
13713 + int i;
13714 + int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
13715 + AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
13716 + };
13717 + int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
13718 + AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
13719 + };
13720 + int inc[4] = { 0, 100, 0, 0 };
13721 + struct chan_centers centers;
13722 +
13723 + int8_t mask_m[123];
13724 + int8_t mask_p[123];
13725 + int8_t mask_amt;
13726 + int tmp_mask;
13727 + int cur_bb_spur;
13728 + bool is2GHz = IS_CHAN_2GHZ(chan);
13729 +
13730 + memset(&mask_m, 0, sizeof(int8_t) * 123);
13731 + memset(&mask_p, 0, sizeof(int8_t) * 123);
13732 +
13733 + ath9k_hw_get_channel_centers(ah, chan, &centers);
13734 + freq = centers.synth_center;
13735 +
13736 + ah->config.spurmode = SPUR_ENABLE_EEPROM;
13737 + for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
13738 + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
13739 +
13740 + if (is2GHz)
13741 + cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
13742 + else
13743 + cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
13744 +
13745 + if (AR_NO_SPUR == cur_bb_spur)
13746 + break;
13747 + cur_bb_spur = cur_bb_spur - freq;
13748 +
13749 + if (IS_CHAN_HT40(chan)) {
13750 + if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
13751 + (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
13752 + bb_spur = cur_bb_spur;
13753 + break;
13754 + }
13755 + } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
13756 + (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
13757 + bb_spur = cur_bb_spur;
13758 + break;
13759 + }
13760 + }
13761 +
13762 + if (AR_NO_SPUR == bb_spur) {
13763 + REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
13764 + AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
13765 + return;
13766 + } else {
13767 + REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
13768 + AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
13769 + }
13770 +
13771 + bin = bb_spur * 320;
13772 +
13773 + tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
13774 +
13775 + newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
13776 + AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
13777 + AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
13778 + AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
13779 + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
13780 +
13781 + newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
13782 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
13783 + AR_PHY_SPUR_REG_MASK_RATE_SELECT |
13784 + AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
13785 + SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
13786 + REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
13787 +
13788 + if (IS_CHAN_HT40(chan)) {
13789 + if (bb_spur < 0) {
13790 + spur_subchannel_sd = 1;
13791 + bb_spur_off = bb_spur + 10;
13792 + } else {
13793 + spur_subchannel_sd = 0;
13794 + bb_spur_off = bb_spur - 10;
13795 + }
13796 + } else {
13797 + spur_subchannel_sd = 0;
13798 + bb_spur_off = bb_spur;
13799 + }
13800 +
13801 + if (IS_CHAN_HT40(chan))
13802 + spur_delta_phase =
13803 + ((bb_spur * 262144) /
13804 + 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
13805 + else
13806 + spur_delta_phase =
13807 + ((bb_spur * 524288) /
13808 + 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
13809 +
13810 + denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
13811 + spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
13812 +
13813 + newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
13814 + SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
13815 + SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
13816 + REG_WRITE(ah, AR_PHY_TIMING11, newVal);
13817 +
13818 + newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
13819 + REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
13820 +
13821 + cur_bin = -6000;
13822 + upper = bin + 100;
13823 + lower = bin - 100;
13824 +
13825 + for (i = 0; i < 4; i++) {
13826 + int pilot_mask = 0;
13827 + int chan_mask = 0;
13828 + int bp = 0;
13829 + for (bp = 0; bp < 30; bp++) {
13830 + if ((cur_bin > lower) && (cur_bin < upper)) {
13831 + pilot_mask = pilot_mask | 0x1 << bp;
13832 + chan_mask = chan_mask | 0x1 << bp;
13833 + }
13834 + cur_bin += 100;
13835 + }
13836 + cur_bin += inc[i];
13837 + REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
13838 + REG_WRITE(ah, chan_mask_reg[i], chan_mask);
13839 + }
13840 +
13841 + cur_vit_mask = 6100;
13842 + upper = bin + 120;
13843 + lower = bin - 120;
13844 +
13845 + for (i = 0; i < 123; i++) {
13846 + if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
13847 +
13848 + /* workaround for gcc bug #37014 */
13849 + volatile int tmp_v = abs(cur_vit_mask - bin);
13850 +
13851 + if (tmp_v < 75)
13852 + mask_amt = 1;
13853 + else
13854 + mask_amt = 0;
13855 + if (cur_vit_mask < 0)
13856 + mask_m[abs(cur_vit_mask / 100)] = mask_amt;
13857 + else
13858 + mask_p[cur_vit_mask / 100] = mask_amt;
13859 + }
13860 + cur_vit_mask -= 100;
13861 + }
13862 +
13863 + tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
13864 + | (mask_m[48] << 26) | (mask_m[49] << 24)
13865 + | (mask_m[50] << 22) | (mask_m[51] << 20)
13866 + | (mask_m[52] << 18) | (mask_m[53] << 16)
13867 + | (mask_m[54] << 14) | (mask_m[55] << 12)
13868 + | (mask_m[56] << 10) | (mask_m[57] << 8)
13869 + | (mask_m[58] << 6) | (mask_m[59] << 4)
13870 + | (mask_m[60] << 2) | (mask_m[61] << 0);
13871 + REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
13872 + REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
13873 +
13874 + tmp_mask = (mask_m[31] << 28)
13875 + | (mask_m[32] << 26) | (mask_m[33] << 24)
13876 + | (mask_m[34] << 22) | (mask_m[35] << 20)
13877 + | (mask_m[36] << 18) | (mask_m[37] << 16)
13878 + | (mask_m[48] << 14) | (mask_m[39] << 12)
13879 + | (mask_m[40] << 10) | (mask_m[41] << 8)
13880 + | (mask_m[42] << 6) | (mask_m[43] << 4)
13881 + | (mask_m[44] << 2) | (mask_m[45] << 0);
13882 + REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
13883 + REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
13884 +
13885 + tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
13886 + | (mask_m[18] << 26) | (mask_m[18] << 24)
13887 + | (mask_m[20] << 22) | (mask_m[20] << 20)
13888 + | (mask_m[22] << 18) | (mask_m[22] << 16)
13889 + | (mask_m[24] << 14) | (mask_m[24] << 12)
13890 + | (mask_m[25] << 10) | (mask_m[26] << 8)
13891 + | (mask_m[27] << 6) | (mask_m[28] << 4)
13892 + | (mask_m[29] << 2) | (mask_m[30] << 0);
13893 + REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
13894 + REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
13895 +
13896 + tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
13897 + | (mask_m[2] << 26) | (mask_m[3] << 24)
13898 + | (mask_m[4] << 22) | (mask_m[5] << 20)
13899 + | (mask_m[6] << 18) | (mask_m[7] << 16)
13900 + | (mask_m[8] << 14) | (mask_m[9] << 12)
13901 + | (mask_m[10] << 10) | (mask_m[11] << 8)
13902 + | (mask_m[12] << 6) | (mask_m[13] << 4)
13903 + | (mask_m[14] << 2) | (mask_m[15] << 0);
13904 + REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
13905 + REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
13906 +
13907 + tmp_mask = (mask_p[15] << 28)
13908 + | (mask_p[14] << 26) | (mask_p[13] << 24)
13909 + | (mask_p[12] << 22) | (mask_p[11] << 20)
13910 + | (mask_p[10] << 18) | (mask_p[9] << 16)
13911 + | (mask_p[8] << 14) | (mask_p[7] << 12)
13912 + | (mask_p[6] << 10) | (mask_p[5] << 8)
13913 + | (mask_p[4] << 6) | (mask_p[3] << 4)
13914 + | (mask_p[2] << 2) | (mask_p[1] << 0);
13915 + REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
13916 + REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
13917 +
13918 + tmp_mask = (mask_p[30] << 28)
13919 + | (mask_p[29] << 26) | (mask_p[28] << 24)
13920 + | (mask_p[27] << 22) | (mask_p[26] << 20)
13921 + | (mask_p[25] << 18) | (mask_p[24] << 16)
13922 + | (mask_p[23] << 14) | (mask_p[22] << 12)
13923 + | (mask_p[21] << 10) | (mask_p[20] << 8)
13924 + | (mask_p[19] << 6) | (mask_p[18] << 4)
13925 + | (mask_p[17] << 2) | (mask_p[16] << 0);
13926 + REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
13927 + REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
13928 +
13929 + tmp_mask = (mask_p[45] << 28)
13930 + | (mask_p[44] << 26) | (mask_p[43] << 24)
13931 + | (mask_p[42] << 22) | (mask_p[41] << 20)
13932 + | (mask_p[40] << 18) | (mask_p[39] << 16)
13933 + | (mask_p[38] << 14) | (mask_p[37] << 12)
13934 + | (mask_p[36] << 10) | (mask_p[35] << 8)
13935 + | (mask_p[34] << 6) | (mask_p[33] << 4)
13936 + | (mask_p[32] << 2) | (mask_p[31] << 0);
13937 + REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
13938 + REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
13939 +
13940 + tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
13941 + | (mask_p[59] << 26) | (mask_p[58] << 24)
13942 + | (mask_p[57] << 22) | (mask_p[56] << 20)
13943 + | (mask_p[55] << 18) | (mask_p[54] << 16)
13944 + | (mask_p[53] << 14) | (mask_p[52] << 12)
13945 + | (mask_p[51] << 10) | (mask_p[50] << 8)
13946 + | (mask_p[49] << 6) | (mask_p[48] << 4)
13947 + | (mask_p[47] << 2) | (mask_p[46] << 0);
13948 + REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
13949 + REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
13950 +}
13951 +
13952 +static void ar9002_olc_init(struct ath_hw *ah)
13953 +{
13954 + u32 i;
13955 +
13956 + if (!OLC_FOR_AR9280_20_LATER)
13957 + return;
13958 +
13959 + if (OLC_FOR_AR9287_10_LATER) {
13960 + REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
13961 + AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
13962 + ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
13963 + AR9287_AN_TXPC0_TXPCMODE,
13964 + AR9287_AN_TXPC0_TXPCMODE_S,
13965 + AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
13966 + udelay(100);
13967 + } else {
13968 + for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
13969 + ah->originalGain[i] =
13970 + MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
13971 + AR_PHY_TX_GAIN);
13972 + ah->PDADCdelta = 0;
13973 + }
13974 +}
13975 +
13976 +static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
13977 + struct ath9k_channel *chan)
13978 +{
13979 + u32 pll;
13980 +
13981 + pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
13982 +
13983 + if (chan && IS_CHAN_HALF_RATE(chan))
13984 + pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
13985 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
13986 + pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
13987 +
13988 + if (chan && IS_CHAN_5GHZ(chan)) {
13989 + pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
13990 +
13991 +
13992 + if (AR_SREV_9280_20(ah)) {
13993 + if (((chan->channel % 20) == 0)
13994 + || ((chan->channel % 10) == 0))
13995 + pll = 0x2850;
13996 + else
13997 + pll = 0x142c;
13998 + }
13999 + } else {
14000 + pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
14001 + }
14002 +
14003 + return pll;
14004 +}
14005 +
14006 +static void ar9002_hw_do_getnf(struct ath_hw *ah,
14007 + int16_t nfarray[NUM_NF_READINGS])
14008 +{
14009 + struct ath_common *common = ath9k_hw_common(ah);
14010 + int16_t nf;
14011 +
14012 + nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
14013 +
14014 + if (nf & 0x100)
14015 + nf = 0 - ((nf ^ 0x1ff) + 1);
14016 + ath_print(common, ATH_DBG_CALIBRATE,
14017 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
14018 +
14019 + if (AR_SREV_9271(ah) && (nf >= -114))
14020 + nf = -116;
14021 +
14022 + nfarray[0] = nf;
14023 +
14024 + if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
14025 + nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
14026 + AR9280_PHY_CH1_MINCCA_PWR);
14027 +
14028 + if (nf & 0x100)
14029 + nf = 0 - ((nf ^ 0x1ff) + 1);
14030 + ath_print(common, ATH_DBG_CALIBRATE,
14031 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
14032 + nfarray[1] = nf;
14033 + }
14034 +
14035 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
14036 + if (nf & 0x100)
14037 + nf = 0 - ((nf ^ 0x1ff) + 1);
14038 + ath_print(common, ATH_DBG_CALIBRATE,
14039 + "NF calibrated [ext] [chain 0] is %d\n", nf);
14040 +
14041 + if (AR_SREV_9271(ah) && (nf >= -114))
14042 + nf = -116;
14043 +
14044 + nfarray[3] = nf;
14045 +
14046 + if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
14047 + nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
14048 + AR9280_PHY_CH1_EXT_MINCCA_PWR);
14049 +
14050 + if (nf & 0x100)
14051 + nf = 0 - ((nf ^ 0x1ff) + 1);
14052 + ath_print(common, ATH_DBG_CALIBRATE,
14053 + "NF calibrated [ext] [chain 1] is %d\n", nf);
14054 + nfarray[4] = nf;
14055 + }
14056 +}
14057 +
14058 +static void ar9002_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
14059 +{
14060 + struct ath9k_nfcal_hist *h;
14061 + int i, j;
14062 + int32_t val;
14063 + const u32 ar5416_cca_regs[6] = {
14064 + AR_PHY_CCA,
14065 + AR_PHY_CH1_CCA,
14066 + AR_PHY_CH2_CCA,
14067 + AR_PHY_EXT_CCA,
14068 + AR_PHY_CH1_EXT_CCA,
14069 + AR_PHY_CH2_EXT_CCA
14070 + };
14071 + u8 chainmask, rx_chain_status;
14072 +
14073 + rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
14074 + if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
14075 + chainmask = 0x9;
14076 + else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
14077 + if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
14078 + chainmask = 0x1B;
14079 + else
14080 + chainmask = 0x09;
14081 + } else {
14082 + if (rx_chain_status & 0x4)
14083 + chainmask = 0x3F;
14084 + else if (rx_chain_status & 0x2)
14085 + chainmask = 0x1B;
14086 + else
14087 + chainmask = 0x09;
14088 + }
14089 +
14090 + h = ah->nfCalHist;
14091 +
14092 + for (i = 0; i < NUM_NF_READINGS; i++) {
14093 + if (chainmask & (1 << i)) {
14094 + val = REG_READ(ah, ar5416_cca_regs[i]);
14095 + val &= 0xFFFFFE00;
14096 + val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
14097 + REG_WRITE(ah, ar5416_cca_regs[i], val);
14098 + }
14099 + }
14100 +
14101 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
14102 + AR_PHY_AGC_CONTROL_ENABLE_NF);
14103 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
14104 + AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
14105 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
14106 +
14107 + for (j = 0; j < 5; j++) {
14108 + if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
14109 + AR_PHY_AGC_CONTROL_NF) == 0)
14110 + break;
14111 + udelay(50);
14112 + }
14113 +
14114 + for (i = 0; i < NUM_NF_READINGS; i++) {
14115 + if (chainmask & (1 << i)) {
14116 + val = REG_READ(ah, ar5416_cca_regs[i]);
14117 + val &= 0xFFFFFE00;
14118 + val |= (((u32) (-50) << 1) & 0x1ff);
14119 + REG_WRITE(ah, ar5416_cca_regs[i], val);
14120 + }
14121 + }
14122 +}
14123 +
14124 +void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
14125 +{
14126 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
14127 +
14128 + priv_ops->set_rf_regs = NULL;
14129 + priv_ops->rf_alloc_ext_banks = NULL;
14130 + priv_ops->rf_free_ext_banks = NULL;
14131 + priv_ops->rf_set_freq = ar9002_hw_set_channel;
14132 + priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
14133 + priv_ops->olc_init = ar9002_olc_init;
14134 + priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
14135 + priv_ops->do_getnf = ar9002_hw_do_getnf;
14136 + priv_ops->loadnf = ar9002_hw_loadnf;
14137 +}
14138 --- /dev/null
14139 +++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
14140 @@ -0,0 +1,572 @@
14141 +/*
14142 + * Copyright (c) 2008-2010 Atheros Communications Inc.
14143 + *
14144 + * Permission to use, copy, modify, and/or distribute this software for any
14145 + * purpose with or without fee is hereby granted, provided that the above
14146 + * copyright notice and this permission notice appear in all copies.
14147 + *
14148 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14149 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14150 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14151 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14152 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14153 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14154 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14155 + */
14156 +#ifndef AR9002_PHY_H
14157 +#define AR9002_PHY_H
14158 +
14159 +#define AR_PHY_TEST 0x9800
14160 +#define PHY_AGC_CLR 0x10000000
14161 +#define RFSILENT_BB 0x00002000
14162 +
14163 +#define AR_PHY_TURBO 0x9804
14164 +#define AR_PHY_FC_TURBO_MODE 0x00000001
14165 +#define AR_PHY_FC_TURBO_SHORT 0x00000002
14166 +#define AR_PHY_FC_DYN2040_EN 0x00000004
14167 +#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
14168 +#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
14169 +/* For 25 MHz channel spacing -- not used but supported by hw */
14170 +#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
14171 +#define AR_PHY_FC_HT_EN 0x00000040
14172 +#define AR_PHY_FC_SHORT_GI_40 0x00000080
14173 +#define AR_PHY_FC_WALSH 0x00000100
14174 +#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
14175 +#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
14176 +
14177 +#define AR_PHY_TEST2 0x9808
14178 +
14179 +#define AR_PHY_TIMING2 0x9810
14180 +#define AR_PHY_TIMING3 0x9814
14181 +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
14182 +#define AR_PHY_TIMING3_DSC_MAN_S 17
14183 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
14184 +#define AR_PHY_TIMING3_DSC_EXP_S 13
14185 +
14186 +#define AR_PHY_CHIP_ID_REV_0 0x80
14187 +#define AR_PHY_CHIP_ID_REV_1 0x81
14188 +#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
14189 +
14190 +#define AR_PHY_ACTIVE 0x981C
14191 +#define AR_PHY_ACTIVE_EN 0x00000001
14192 +#define AR_PHY_ACTIVE_DIS 0x00000000
14193 +
14194 +#define AR_PHY_RF_CTL2 0x9824
14195 +#define AR_PHY_TX_END_DATA_START 0x000000FF
14196 +#define AR_PHY_TX_END_DATA_START_S 0
14197 +#define AR_PHY_TX_END_PA_ON 0x0000FF00
14198 +#define AR_PHY_TX_END_PA_ON_S 8
14199 +
14200 +#define AR_PHY_RF_CTL3 0x9828
14201 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
14202 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
14203 +
14204 +#define AR_PHY_ADC_CTL 0x982C
14205 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
14206 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
14207 +#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
14208 +#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
14209 +#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
14210 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
14211 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
14212 +
14213 +#define AR_PHY_ADC_SERIAL_CTL 0x9830
14214 +#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
14215 +#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
14216 +
14217 +#define AR_PHY_RF_CTL4 0x9834
14218 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
14219 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
14220 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
14221 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
14222 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
14223 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
14224 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
14225 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
14226 +
14227 +#define AR_PHY_TSTDAC_CONST 0x983c
14228 +
14229 +#define AR_PHY_SETTLING 0x9844
14230 +#define AR_PHY_SETTLING_SWITCH 0x00003F80
14231 +#define AR_PHY_SETTLING_SWITCH_S 7
14232 +
14233 +#define AR_PHY_RXGAIN 0x9848
14234 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
14235 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
14236 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
14237 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
14238 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
14239 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
14240 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
14241 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
14242 +
14243 +#define AR_PHY_DESIRED_SZ 0x9850
14244 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
14245 +#define AR_PHY_DESIRED_SZ_ADC_S 0
14246 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
14247 +#define AR_PHY_DESIRED_SZ_PGA_S 8
14248 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
14249 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
14250 +
14251 +#define AR_PHY_FIND_SIG 0x9858
14252 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
14253 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12
14254 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
14255 +#define AR_PHY_FIND_SIG_FIRPWR_S 18
14256 +
14257 +#define AR_PHY_AGC_CTL1 0x985C
14258 +#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
14259 +#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
14260 +#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
14261 +#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
14262 +
14263 +#define AR_PHY_CCA 0x9864
14264 +#define AR_PHY_MINCCA_PWR 0x0FF80000
14265 +#define AR_PHY_MINCCA_PWR_S 19
14266 +#define AR_PHY_CCA_THRESH62 0x0007F000
14267 +#define AR_PHY_CCA_THRESH62_S 12
14268 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000
14269 +#define AR9280_PHY_MINCCA_PWR_S 20
14270 +#define AR9280_PHY_CCA_THRESH62 0x000FF000
14271 +#define AR9280_PHY_CCA_THRESH62_S 12
14272 +
14273 +#define AR_PHY_SFCORR_LOW 0x986C
14274 +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
14275 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
14276 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
14277 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
14278 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
14279 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
14280 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
14281 +
14282 +#define AR_PHY_SFCORR 0x9868
14283 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
14284 +#define AR_PHY_SFCORR_M2COUNT_THR_S 0
14285 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
14286 +#define AR_PHY_SFCORR_M1_THRESH_S 17
14287 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
14288 +#define AR_PHY_SFCORR_M2_THRESH_S 24
14289 +
14290 +#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
14291 +#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
14292 +#define AR_PHY_SYNTH_CONTROL 0x9874
14293 +#define AR_PHY_SLEEP_SCAL 0x9878
14294 +
14295 +#define AR_PHY_PLL_CTL 0x987c
14296 +#define AR_PHY_PLL_CTL_40 0xaa
14297 +#define AR_PHY_PLL_CTL_40_5413 0x04
14298 +#define AR_PHY_PLL_CTL_44 0xab
14299 +#define AR_PHY_PLL_CTL_44_2133 0xeb
14300 +#define AR_PHY_PLL_CTL_40_2133 0xea
14301 +
14302 +#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
14303 +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
14304 +#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
14305 +#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
14306 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
14307 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
14308 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
14309 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
14310 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
14311 +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
14312 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
14313 +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
14314 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
14315 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
14316 +
14317 +#define AR_PHY_RX_DELAY 0x9914
14318 +#define AR_PHY_SEARCH_START_DELAY 0x9918
14319 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
14320 +
14321 +#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
14322 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
14323 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
14324 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
14325 +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
14326 +#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
14327 +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
14328 +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
14329 +#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
14330 +
14331 +#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
14332 +#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
14333 +#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
14334 +#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
14335 +
14336 +#define AR_PHY_TIMING5 0x9924
14337 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
14338 +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
14339 +
14340 +#define AR_PHY_POWER_TX_RATE1 0x9934
14341 +#define AR_PHY_POWER_TX_RATE2 0x9938
14342 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c
14343 +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
14344 +
14345 +#define AR_PHY_FRAME_CTL 0x9944
14346 +#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
14347 +#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
14348 +
14349 +#define AR_PHY_TXPWRADJ 0x994C
14350 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
14351 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
14352 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
14353 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
14354 +
14355 +#define AR_PHY_RADAR_EXT 0x9940
14356 +#define AR_PHY_RADAR_EXT_ENA 0x00004000
14357 +
14358 +#define AR_PHY_RADAR_0 0x9954
14359 +#define AR_PHY_RADAR_0_ENA 0x00000001
14360 +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
14361 +#define AR_PHY_RADAR_0_INBAND 0x0000003e
14362 +#define AR_PHY_RADAR_0_INBAND_S 1
14363 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
14364 +#define AR_PHY_RADAR_0_PRSSI_S 6
14365 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
14366 +#define AR_PHY_RADAR_0_HEIGHT_S 12
14367 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
14368 +#define AR_PHY_RADAR_0_RRSSI_S 18
14369 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
14370 +#define AR_PHY_RADAR_0_FIRPWR_S 24
14371 +
14372 +#define AR_PHY_RADAR_1 0x9958
14373 +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
14374 +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
14375 +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
14376 +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
14377 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
14378 +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
14379 +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
14380 +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
14381 +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
14382 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
14383 +#define AR_PHY_RADAR_1_MAXLEN_S 0
14384 +
14385 +#define AR_PHY_SWITCH_CHAIN_0 0x9960
14386 +#define AR_PHY_SWITCH_COM 0x9964
14387 +
14388 +#define AR_PHY_SIGMA_DELTA 0x996C
14389 +#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
14390 +#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
14391 +#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
14392 +#define AR_PHY_SIGMA_DELTA_FILT2_S 3
14393 +#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
14394 +#define AR_PHY_SIGMA_DELTA_FILT1_S 8
14395 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
14396 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
14397 +
14398 +#define AR_PHY_RESTART 0x9970
14399 +#define AR_PHY_RESTART_DIV_GC 0x001C0000
14400 +#define AR_PHY_RESTART_DIV_GC_S 18
14401 +
14402 +#define AR_PHY_RFBUS_REQ 0x997C
14403 +#define AR_PHY_RFBUS_REQ_EN 0x00000001
14404 +
14405 +#define AR_PHY_TIMING7 0x9980
14406 +#define AR_PHY_TIMING8 0x9984
14407 +#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
14408 +#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
14409 +
14410 +#define AR_PHY_BIN_MASK2_1 0x9988
14411 +#define AR_PHY_BIN_MASK2_2 0x998c
14412 +#define AR_PHY_BIN_MASK2_3 0x9990
14413 +#define AR_PHY_BIN_MASK2_4 0x9994
14414 +
14415 +#define AR_PHY_BIN_MASK_1 0x9900
14416 +#define AR_PHY_BIN_MASK_2 0x9904
14417 +#define AR_PHY_BIN_MASK_3 0x9908
14418 +
14419 +#define AR_PHY_MASK_CTL 0x990c
14420 +
14421 +#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
14422 +#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
14423 +
14424 +#define AR_PHY_TIMING9 0x9998
14425 +#define AR_PHY_TIMING10 0x999c
14426 +#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
14427 +#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
14428 +
14429 +#define AR_PHY_TIMING11 0x99a0
14430 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
14431 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
14432 +#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
14433 +#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
14434 +
14435 +#define AR_PHY_RX_CHAINMASK 0x99a4
14436 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
14437 +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
14438 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
14439 +
14440 +#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
14441 +#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
14442 +#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
14443 +#define AR_PHY_9285_ANT_DIV_CTL_S 24
14444 +#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
14445 +#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
14446 +#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
14447 +#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
14448 +#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
14449 +#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
14450 +#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
14451 +#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
14452 +#define AR_PHY_9285_ANT_DIV_LNA1 2
14453 +#define AR_PHY_9285_ANT_DIV_LNA2 1
14454 +#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
14455 +#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
14456 +#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
14457 +#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
14458 +
14459 +#define AR_PHY_EXT_CCA0 0x99b8
14460 +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
14461 +#define AR_PHY_EXT_CCA0_THRESH62_S 0
14462 +
14463 +#define AR_PHY_EXT_CCA 0x99bc
14464 +#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
14465 +#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
14466 +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
14467 +#define AR_PHY_EXT_CCA_THRESH62_S 16
14468 +#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
14469 +#define AR_PHY_EXT_MINCCA_PWR_S 23
14470 +#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
14471 +#define AR9280_PHY_EXT_MINCCA_PWR_S 16
14472 +
14473 +#define AR_PHY_SFCORR_EXT 0x99c0
14474 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
14475 +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
14476 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
14477 +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
14478 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
14479 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
14480 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
14481 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
14482 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
14483 +
14484 +#define AR_PHY_HALFGI 0x99D0
14485 +#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
14486 +#define AR_PHY_HALFGI_DSC_MAN_S 4
14487 +#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
14488 +#define AR_PHY_HALFGI_DSC_EXP_S 0
14489 +
14490 +#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
14491 +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
14492 +
14493 +#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
14494 +
14495 +#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
14496 +#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
14497 +
14498 +#define AR_PHY_M_SLEEP 0x99f0
14499 +#define AR_PHY_REFCLKDLY 0x99f4
14500 +#define AR_PHY_REFCLKPD 0x99f8
14501 +
14502 +#define AR_PHY_CALMODE 0x99f0
14503 +
14504 +#define AR_PHY_CALMODE_IQ 0x00000000
14505 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
14506 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
14507 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
14508 +
14509 +#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
14510 +#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
14511 +#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
14512 +#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
14513 +
14514 +#define AR_PHY_CURRENT_RSSI 0x9c1c
14515 +#define AR9280_PHY_CURRENT_RSSI 0x9c3c
14516 +
14517 +#define AR_PHY_RFBUS_GRANT 0x9C20
14518 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001
14519 +
14520 +#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
14521 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
14522 +
14523 +#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
14524 +
14525 +#define AR_PHY_MODE 0xA200
14526 +#define AR_PHY_MODE_ASYNCFIFO 0x80
14527 +#define AR_PHY_MODE_AR2133 0x08
14528 +#define AR_PHY_MODE_AR5111 0x00
14529 +#define AR_PHY_MODE_AR5112 0x08
14530 +#define AR_PHY_MODE_DYNAMIC 0x04
14531 +#define AR_PHY_MODE_RF2GHZ 0x02
14532 +#define AR_PHY_MODE_RF5GHZ 0x00
14533 +#define AR_PHY_MODE_CCK 0x01
14534 +#define AR_PHY_MODE_OFDM 0x00
14535 +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
14536 +
14537 +#define AR_PHY_CCK_TX_CTRL 0xA204
14538 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
14539 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
14540 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
14541 +
14542 +#define AR_PHY_CCK_DETECT 0xA208
14543 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
14544 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
14545 +/* [12:6] settling time for antenna switch */
14546 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
14547 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
14548 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
14549 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
14550 +
14551 +#define AR_PHY_GAIN_2GHZ 0xA20C
14552 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
14553 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
14554 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
14555 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
14556 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
14557 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
14558 +
14559 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
14560 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
14561 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
14562 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
14563 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
14564 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
14565 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
14566 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
14567 +
14568 +#define AR_PHY_CCK_RXCTRL4 0xA21C
14569 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
14570 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
14571 +
14572 +#define AR_PHY_DAG_CTRLCCK 0xA228
14573 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
14574 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
14575 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
14576 +
14577 +#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
14578 +#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
14579 +
14580 +#define AR_PHY_POWER_TX_RATE3 0xA234
14581 +#define AR_PHY_POWER_TX_RATE4 0xA238
14582 +
14583 +#define AR_PHY_SCRM_SEQ_XR 0xA23C
14584 +#define AR_PHY_HEADER_DETECT_XR 0xA240
14585 +#define AR_PHY_CHIRP_DETECTED_XR 0xA244
14586 +#define AR_PHY_BLUETOOTH 0xA254
14587 +
14588 +#define AR_PHY_TPCRG1 0xA258
14589 +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
14590 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
14591 +
14592 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
14593 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
14594 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
14595 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
14596 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
14597 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
14598 +
14599 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
14600 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
14601 +
14602 +#define AR_PHY_TX_PWRCTRL4 0xa264
14603 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
14604 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
14605 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
14606 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
14607 +
14608 +#define AR_PHY_TX_PWRCTRL6_0 0xa270
14609 +#define AR_PHY_TX_PWRCTRL6_1 0xb270
14610 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
14611 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
14612 +
14613 +#define AR_PHY_TX_PWRCTRL7 0xa274
14614 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
14615 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
14616 +
14617 +#define AR_PHY_TX_PWRCTRL9 0xa27C
14618 +#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
14619 +#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
14620 +#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
14621 +#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
14622 +
14623 +#define AR_PHY_TX_GAIN_TBL1 0xa300
14624 +#define AR_PHY_TX_GAIN 0x0007F000
14625 +#define AR_PHY_TX_GAIN_S 12
14626 +
14627 +#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
14628 +#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
14629 +#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
14630 +#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
14631 +
14632 +#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
14633 +#define AR_PHY_MASK2_M_31_45 0xa3a4
14634 +#define AR_PHY_MASK2_M_16_30 0xa3a8
14635 +#define AR_PHY_MASK2_M_00_15 0xa3ac
14636 +#define AR_PHY_MASK2_P_15_01 0xa3b8
14637 +#define AR_PHY_MASK2_P_30_16 0xa3bc
14638 +#define AR_PHY_MASK2_P_45_31 0xa3c0
14639 +#define AR_PHY_MASK2_P_61_45 0xa3c4
14640 +#define AR_PHY_SPUR_REG 0x994c
14641 +
14642 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
14643 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
14644 +
14645 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
14646 +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
14647 +#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
14648 +#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
14649 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
14650 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
14651 +
14652 +#define AR_PHY_PILOT_MASK_01_30 0xa3b0
14653 +#define AR_PHY_PILOT_MASK_31_60 0xa3b4
14654 +
14655 +#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
14656 +#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
14657 +
14658 +#define AR_PHY_ANALOG_SWAP 0xa268
14659 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
14660 +
14661 +#define AR_PHY_TPCRG5 0xA26C
14662 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
14663 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
14664 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
14665 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
14666 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
14667 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
14668 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
14669 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
14670 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
14671 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
14672 +
14673 +/* Carrier leak calibration control, do it after AGC calibration */
14674 +#define AR_PHY_CL_CAL_CTL 0xA358
14675 +#define AR_PHY_CL_CAL_ENABLE 0x00000002
14676 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
14677 +
14678 +#define AR_PHY_POWER_TX_RATE5 0xA38C
14679 +#define AR_PHY_POWER_TX_RATE6 0xA390
14680 +
14681 +#define AR_PHY_CAL_CHAINMASK 0xA39C
14682 +
14683 +#define AR_PHY_POWER_TX_SUB 0xA3C8
14684 +#define AR_PHY_POWER_TX_RATE7 0xA3CC
14685 +#define AR_PHY_POWER_TX_RATE8 0xA3D0
14686 +#define AR_PHY_POWER_TX_RATE9 0xA3D4
14687 +
14688 +#define AR_PHY_XPA_CFG 0xA3D8
14689 +#define AR_PHY_FORCE_XPA_CFG 0x000000001
14690 +#define AR_PHY_FORCE_XPA_CFG_S 0
14691 +
14692 +#define AR_PHY_CH1_CCA 0xa864
14693 +#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
14694 +#define AR_PHY_CH1_MINCCA_PWR_S 19
14695 +#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
14696 +#define AR9280_PHY_CH1_MINCCA_PWR_S 20
14697 +
14698 +#define AR_PHY_CH2_CCA 0xb864
14699 +#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
14700 +#define AR_PHY_CH2_MINCCA_PWR_S 19
14701 +
14702 +#define AR_PHY_CH1_EXT_CCA 0xa9bc
14703 +#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
14704 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
14705 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
14706 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
14707 +
14708 +#define AR_PHY_CH2_EXT_CCA 0xb9bc
14709 +#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
14710 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
14711 +
14712 +#endif
14713 --- /dev/null
14714 +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
14715 @@ -0,0 +1,798 @@
14716 +/*
14717 + * Copyright (c) 2010 Atheros Communications Inc.
14718 + *
14719 + * Permission to use, copy, modify, and/or distribute this software for any
14720 + * purpose with or without fee is hereby granted, provided that the above
14721 + * copyright notice and this permission notice appear in all copies.
14722 + *
14723 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14724 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14725 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14726 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14727 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14728 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14729 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14730 + */
14731 +
14732 +#include "hw.h"
14733 +#include "hw-ops.h"
14734 +#include "ar9003_phy.h"
14735 +
14736 +static void ar9003_hw_setup_calibration(struct ath_hw *ah,
14737 + struct ath9k_cal_list *currCal)
14738 +{
14739 + struct ath_common *common = ath9k_hw_common(ah);
14740 +
14741 + /* Select calibration to run */
14742 + switch(currCal->calData->calType) {
14743 + case IQ_MISMATCH_CAL:
14744 + /*
14745 + * Start calibration with
14746 + * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
14747 + */
14748 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
14749 + AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
14750 + currCal->calData->calCountMax);
14751 + REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
14752 +
14753 + ath_print(common, ATH_DBG_CALIBRATE,
14754 + "starting IQ Mismatch Calibration\n");
14755 +
14756 + /* Kick-off cal */
14757 + REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
14758 + break;
14759 + case TEMP_COMP_CAL:
14760 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
14761 + AR_PHY_65NM_CH0_THERM_LOCAL, 1);
14762 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
14763 + AR_PHY_65NM_CH0_THERM_START, 1);
14764 +
14765 + ath_print(common, ATH_DBG_CALIBRATE,
14766 + "starting Temperature Compensation Calibration\n");
14767 + break;
14768 + case ADC_DC_INIT_CAL:
14769 + case ADC_GAIN_CAL:
14770 + case ADC_DC_CAL:
14771 + /* Not yet */
14772 + break;
14773 + }
14774 +}
14775 +
14776 +/*
14777 + * Generic calibration routine.
14778 + * Recalibrate the lower PHY chips to account for temperature/environment
14779 + * changes.
14780 + */
14781 +static bool ar9003_hw_per_calibration(struct ath_hw *ah,
14782 + struct ath9k_channel *ichan,
14783 + u8 rxchainmask,
14784 + struct ath9k_cal_list *currCal)
14785 +{
14786 + /* Cal is assumed not done until explicitly set below */
14787 + bool iscaldone = false;
14788 +
14789 + /* Calibration in progress. */
14790 + if (currCal->calState == CAL_RUNNING) {
14791 + /* Check to see if it has finished. */
14792 + if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
14793 + /*
14794 + * Accumulate cal measures for active chains
14795 + */
14796 + currCal->calData->calCollect(ah);
14797 + ah->cal_samples++;
14798 +
14799 + if (ah->cal_samples >=
14800 + currCal->calData->calNumSamples) {
14801 + unsigned int i, numChains = 0;
14802 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
14803 + if (rxchainmask & (1 << i))
14804 + numChains++;
14805 + }
14806 +
14807 + /*
14808 + * Process accumulated data
14809 + */
14810 + currCal->calData->calPostProc(ah, numChains);
14811 +
14812 + /* Calibration has finished. */
14813 + ichan->CalValid |= currCal->calData->calType;
14814 + currCal->calState = CAL_DONE;
14815 + iscaldone = true;
14816 + } else {
14817 + /*
14818 + * Set-up collection of another sub-sample until we
14819 + * get desired number
14820 + */
14821 + ar9003_hw_setup_calibration(ah, currCal);
14822 + }
14823 + }
14824 + } else if (!(ichan->CalValid & currCal->calData->calType)) {
14825 + /* If current cal is marked invalid in channel, kick it off */
14826 + ath9k_hw_reset_calibration(ah, currCal);
14827 + }
14828 +
14829 + return iscaldone;
14830 +}
14831 +
14832 +static bool ar9003_hw_calibrate(struct ath_hw *ah,
14833 + struct ath9k_channel *chan,
14834 + u8 rxchainmask,
14835 + bool longcal)
14836 +{
14837 + bool iscaldone = true;
14838 + struct ath9k_cal_list *currCal = ah->cal_list_curr;
14839 +
14840 + /*
14841 + * For given calibration:
14842 + * 1. Call generic cal routine
14843 + * 2. When this cal is done (isCalDone) if we have more cals waiting
14844 + * (eg after reset), mask this to upper layers by not propagating
14845 + * isCalDone if it is set to TRUE.
14846 + * Instead, change isCalDone to FALSE and setup the waiting cal(s)
14847 + * to be run.
14848 + */
14849 + if (currCal &&
14850 + (currCal->calState == CAL_RUNNING ||
14851 + currCal->calState == CAL_WAITING)) {
14852 + iscaldone = ar9003_hw_per_calibration(ah, chan,
14853 + rxchainmask, currCal);
14854 + if (iscaldone) {
14855 + ah->cal_list_curr = currCal = currCal->calNext;
14856 +
14857 + if (currCal->calState == CAL_WAITING) {
14858 + iscaldone = false;
14859 + ath9k_hw_reset_calibration(ah, currCal);
14860 + }
14861 + }
14862 + }
14863 +
14864 + /* Do NF cal only at longer intervals */
14865 + if (longcal) {
14866 + /*
14867 + * Load the NF from history buffer of the current channel.
14868 + * NF is slow time-variant, so it is OK to use a historical value.
14869 + */
14870 + ath9k_hw_loadnf(ah, ah->curchan);
14871 +
14872 + /* start NF calibration, without updating BB NF register */
14873 + ath9k_hw_start_nfcal(ah);
14874 + }
14875 +
14876 + return iscaldone;
14877 +}
14878 +
14879 +static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
14880 +{
14881 + int i;
14882 +
14883 + /* Accumulate IQ cal measures for active chains */
14884 + for (i = 0; i < AR5416_MAX_CHAINS; i++) {
14885 + ah->totalPowerMeasI[i] +=
14886 + REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
14887 + ah->totalPowerMeasQ[i] +=
14888 + REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
14889 + ah->totalIqCorrMeas[i] +=
14890 + (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
14891 + ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
14892 + "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
14893 + ah->cal_samples, i, ah->totalPowerMeasI[i],
14894 + ah->totalPowerMeasQ[i],
14895 + ah->totalIqCorrMeas[i]);
14896 + }
14897 +}
14898 +
14899 +static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
14900 +{
14901 + struct ath_common *common = ath9k_hw_common(ah);
14902 + u32 powerMeasQ, powerMeasI, iqCorrMeas;
14903 + u32 qCoffDenom, iCoffDenom;
14904 + int32_t qCoff, iCoff;
14905 + int iqCorrNeg, i;
14906 + const u_int32_t offset_array[3] = {
14907 + AR_PHY_RX_IQCAL_CORR_B0,
14908 + AR_PHY_RX_IQCAL_CORR_B1,
14909 + AR_PHY_RX_IQCAL_CORR_B2,
14910 + };
14911 +
14912 + for (i = 0; i < numChains; i++) {
14913 + powerMeasI = ah->totalPowerMeasI[i];
14914 + powerMeasQ = ah->totalPowerMeasQ[i];
14915 + iqCorrMeas = ah->totalIqCorrMeas[i];
14916 +
14917 + ath_print(common, ATH_DBG_CALIBRATE,
14918 + "Starting IQ Cal and Correction for Chain %d\n",
14919 + i);
14920 +
14921 + ath_print(common, ATH_DBG_CALIBRATE,
14922 + "Orignal: Chn %diq_corr_meas = 0x%08x\n",
14923 + i, ah->totalIqCorrMeas[i]);
14924 +
14925 + iqCorrNeg = 0;
14926 +
14927 + if (iqCorrMeas > 0x80000000) {
14928 + iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
14929 + iqCorrNeg = 1;
14930 + }
14931 +
14932 + ath_print(common, ATH_DBG_CALIBRATE,
14933 + "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
14934 + ath_print(common, ATH_DBG_CALIBRATE,
14935 + "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
14936 + ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
14937 + iqCorrNeg);
14938 +
14939 + iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
14940 + qCoffDenom = powerMeasQ / 64;
14941 +
14942 + if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
14943 + iCoff = iqCorrMeas / iCoffDenom;
14944 + qCoff = powerMeasI / qCoffDenom - 64;
14945 + ath_print(common, ATH_DBG_CALIBRATE,
14946 + "Chn %d iCoff = 0x%08x\n", i, iCoff);
14947 + ath_print(common, ATH_DBG_CALIBRATE,
14948 + "Chn %d qCoff = 0x%08x\n", i, qCoff);
14949 +
14950 + /* Force bounds on iCoff */
14951 + if (iCoff >= 63)
14952 + iCoff = 63;
14953 + else if (iCoff <= -63)
14954 + iCoff = -63;
14955 +
14956 + /* Negate iCoff if iqCorrNeg == 0 */
14957 + if (iqCorrNeg == 0x0)
14958 + iCoff = -iCoff;
14959 +
14960 + /* Force bounds on qCoff */
14961 + if (qCoff >= 63)
14962 + qCoff = 63;
14963 + else if (qCoff <= -63)
14964 + qCoff = -63;
14965 +
14966 + iCoff = iCoff & 0x7f;
14967 + qCoff = qCoff & 0x7f;
14968 +
14969 + ath_print(common, ATH_DBG_CALIBRATE,
14970 + "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
14971 + i, iCoff, qCoff);
14972 + ath_print(common, ATH_DBG_CALIBRATE,
14973 + "Register offset (0x%04x) "
14974 + "before update = 0x%x\n",
14975 + offset_array[i],
14976 + REG_READ(ah, offset_array[i]));
14977 +
14978 + REG_RMW_FIELD(ah, offset_array[i],
14979 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
14980 + iCoff);
14981 + REG_RMW_FIELD(ah, offset_array[i],
14982 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
14983 + qCoff);
14984 + ath_print(common, ATH_DBG_CALIBRATE,
14985 + "Register offset (0x%04x) QI COFF "
14986 + "(bitfields 0x%08x) after update = 0x%x\n",
14987 + offset_array[i],
14988 + AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
14989 + REG_READ(ah, offset_array[i]));
14990 + ath_print(common, ATH_DBG_CALIBRATE,
14991 + "Register offset (0x%04x) QQ COFF "
14992 + "(bitfields 0x%08x) after update = 0x%x\n",
14993 + offset_array[i], AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
14994 + REG_READ(ah, offset_array[i]));
14995 +
14996 + ath_print(common, ATH_DBG_CALIBRATE,
14997 + "IQ Cal and Correction done for Chain %d\n",
14998 + i);
14999 + }
15000 + }
15001 +
15002 + REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
15003 + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
15004 + ath_print(common, ATH_DBG_CALIBRATE,
15005 + "IQ Cal and Correction (offset 0x%04x) enabled "
15006 + "(bit position 0x%08x). New Value 0x%08x\n",
15007 + (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
15008 + AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
15009 + REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
15010 +}
15011 +
15012 +static const struct ath9k_percal_data iq_cal_single_sample = {
15013 + IQ_MISMATCH_CAL,
15014 + MIN_CAL_SAMPLES,
15015 + PER_MAX_LOG_COUNT,
15016 + ar9003_hw_iqcal_collect,
15017 + ar9003_hw_iqcalibrate
15018 +};
15019 +
15020 +static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
15021 +{
15022 + ah->iq_caldata.calData = &iq_cal_single_sample;
15023 + ah->supp_cals = IQ_MISMATCH_CAL;
15024 +}
15025 +
15026 +static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
15027 + enum ath9k_cal_types calType)
15028 +{
15029 + switch (calType & ah->supp_cals) {
15030 + case IQ_MISMATCH_CAL:
15031 + /*
15032 + * XXX: Run IQ Mismatch for non-CCK only
15033 + * Note that CHANNEL_B is never set though.
15034 + */
15035 + return true;
15036 + case ADC_GAIN_CAL:
15037 + case ADC_DC_CAL:
15038 + return false;
15039 + case TEMP_COMP_CAL:
15040 + return true;
15041 + }
15042 +
15043 + return false;
15044 +}
15045 +
15046 +/*
15047 + * solve 4x4 linear equation used in loopback iq cal.
15048 + */
15049 +static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
15050 + s32 sin_2phi_1,
15051 + s32 cos_2phi_1,
15052 + s32 sin_2phi_2,
15053 + s32 cos_2phi_2,
15054 + s32 mag_a0_d0,
15055 + s32 phs_a0_d0,
15056 + s32 mag_a1_d0,
15057 + s32 phs_a1_d0,
15058 + s32 solved_eq[])
15059 +{
15060 + s32 f1 = cos_2phi_1 - cos_2phi_2,
15061 + f3 = sin_2phi_1 - sin_2phi_2,
15062 + f2;
15063 + s32 mag_tx, phs_tx, mag_rx, phs_rx;
15064 + const s32 result_shift = 1 << 15;
15065 + struct ath_common *common = ath9k_hw_common(ah);
15066 +
15067 + f2 = (f1 * f1 + f3 * f3) / result_shift;
15068 +
15069 + if (!f2) {
15070 + ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
15071 + return false;
15072 + }
15073 +
15074 + /* mag mismatch, tx */
15075 + mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
15076 + /* phs mismatch, tx */
15077 + phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
15078 +
15079 + mag_tx = (mag_tx / f2);
15080 + phs_tx = (phs_tx / f2);
15081 +
15082 + /* mag mismatch, rx */
15083 + mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
15084 + result_shift;
15085 + /* phs mismatch, rx */
15086 + phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
15087 + result_shift;
15088 +
15089 + solved_eq[0] = mag_tx;
15090 + solved_eq[1] = phs_tx;
15091 + solved_eq[2] = mag_rx;
15092 + solved_eq[3] = phs_rx;
15093 +
15094 + return true;
15095 +}
15096 +
15097 +static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
15098 +{
15099 + s32 abs_i = abs(in_re),
15100 + abs_q = abs(in_im),
15101 + max_abs, min_abs;
15102 +
15103 + if (abs_i > abs_q) {
15104 + max_abs = abs_i;
15105 + min_abs = abs_q;
15106 + } else {
15107 + max_abs = abs_q;
15108 + min_abs = abs_i;
15109 + }
15110 +
15111 + return (max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4));
15112 +}
15113 +
15114 +#define DELPT 32
15115 +
15116 +static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
15117 + s32 chain_idx,
15118 + const s32 iq_res[],
15119 + s32 iqc_coeff[])
15120 +{
15121 + s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
15122 + i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
15123 + i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
15124 + i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
15125 + s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
15126 + phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
15127 + sin_2phi_1, cos_2phi_1,
15128 + sin_2phi_2, cos_2phi_2;
15129 + s32 mag_tx, phs_tx, mag_rx, phs_rx;
15130 + s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
15131 + q_q_coff, q_i_coff;
15132 + const s32 res_scale = 1 << 15;
15133 + const s32 delpt_shift = 1 << 8;
15134 + s32 mag1, mag2;
15135 + struct ath_common *common = ath9k_hw_common(ah);
15136 +
15137 + i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
15138 + i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
15139 + iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
15140 +
15141 + if (i2_m_q2_a0_d0 > 0x800)
15142 + i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
15143 +
15144 + if (i2_p_q2_a0_d0 > 0x800)
15145 + i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
15146 +
15147 + if (iq_corr_a0_d0 > 0x800)
15148 + iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
15149 +
15150 + i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
15151 + i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
15152 + iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
15153 +
15154 + if (i2_m_q2_a0_d1 > 0x800)
15155 + i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
15156 +
15157 + if (i2_p_q2_a0_d1 > 0x800)
15158 + i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1);
15159 +
15160 + if (iq_corr_a0_d1 > 0x800)
15161 + iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
15162 +
15163 + i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
15164 + i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
15165 + iq_corr_a1_d0 = iq_res[4] & 0xfff;
15166 +
15167 + if (i2_m_q2_a1_d0 > 0x800)
15168 + i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
15169 +
15170 + if (i2_p_q2_a1_d0 > 0x800)
15171 + i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
15172 +
15173 + if (iq_corr_a1_d0 > 0x800)
15174 + iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
15175 +
15176 + i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
15177 + i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
15178 + iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
15179 +
15180 + if (i2_m_q2_a1_d1 > 0x800)
15181 + i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
15182 +
15183 + if (i2_p_q2_a1_d1 > 0x800)
15184 + i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
15185 +
15186 + if (iq_corr_a1_d1 > 0x800)
15187 + iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
15188 +
15189 + if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
15190 + (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
15191 + ath_print(common, ATH_DBG_CALIBRATE,
15192 + "Divide by 0:\na0_d0=%d\n"
15193 + "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
15194 + i2_p_q2_a0_d0, i2_p_q2_a0_d1,
15195 + i2_p_q2_a1_d0, i2_p_q2_a1_d1);
15196 + return false;
15197 + }
15198 +
15199 + mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
15200 + phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
15201 +
15202 + mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
15203 + phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
15204 +
15205 + mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
15206 + phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
15207 +
15208 + mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
15209 + phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
15210 +
15211 + /* w/o analog phase shift */
15212 + sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
15213 + /* w/o analog phase shift */
15214 + cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
15215 + /* w/ analog phase shift */
15216 + sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
15217 + /* w/ analog phase shift */
15218 + cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
15219 +
15220 + /*
15221 + * force sin^2 + cos^2 = 1;
15222 + * find magnitude by approximation
15223 + */
15224 + mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
15225 + mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
15226 +
15227 + if ((mag1 == 0) || (mag2 == 0)) {
15228 + ath_print(common, ATH_DBG_CALIBRATE,
15229 + "Divide by 0: mag1=%d, mag2=%d\n",
15230 + mag1, mag2);
15231 + return false;
15232 + }
15233 +
15234 + /* normalization sin and cos by mag */
15235 + sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
15236 + cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
15237 + sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
15238 + cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
15239 +
15240 + /* calculate IQ mismatch */
15241 + if (!ar9003_hw_solve_iq_cal(ah,
15242 + sin_2phi_1, cos_2phi_1,
15243 + sin_2phi_2, cos_2phi_2,
15244 + mag_a0_d0, phs_a0_d0,
15245 + mag_a1_d0,
15246 + phs_a1_d0, solved_eq)) {
15247 + ath_print(common, ATH_DBG_CALIBRATE,
15248 + "Call to ar9003_hw_solve_iq_cal() failed.\n");
15249 + return false;
15250 + }
15251 +
15252 + mag_tx = solved_eq[0];
15253 + phs_tx = solved_eq[1];
15254 + mag_rx = solved_eq[2];
15255 + phs_rx = solved_eq[3];
15256 +
15257 + ath_print(common, ATH_DBG_CALIBRATE,
15258 + "chain %d: mag mismatch=%d phase mismatch=%d\n",
15259 + chain_idx, mag_tx/res_scale, phs_tx/res_scale);
15260 +
15261 + if (res_scale == mag_tx) {
15262 + ath_print(common, ATH_DBG_CALIBRATE,
15263 + "Divide by 0: mag_tx=%d, res_scale=%d\n",
15264 + mag_tx, res_scale);
15265 + return false;
15266 + }
15267 +
15268 + /* calculate and quantize Tx IQ correction factor */
15269 + mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
15270 + phs_corr_tx = -phs_tx;
15271 +
15272 + q_q_coff = (mag_corr_tx * 128 / res_scale);
15273 + q_i_coff = (phs_corr_tx * 256 / res_scale);
15274 +
15275 + ath_print(common, ATH_DBG_CALIBRATE,
15276 + "tx chain %d: mag corr=%d phase corr=%d\n",
15277 + chain_idx, q_q_coff, q_i_coff);
15278 +
15279 + if (q_i_coff < -63)
15280 + q_i_coff = -63;
15281 + if (q_i_coff > 63)
15282 + q_i_coff = 63;
15283 + if (q_q_coff < -63)
15284 + q_q_coff = -63;
15285 + if (q_q_coff > 63)
15286 + q_q_coff = 63;
15287 +
15288 + iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
15289 +
15290 + ath_print(common, ATH_DBG_CALIBRATE,
15291 + "tx chain %d: iq corr coeff=%x\n",
15292 + chain_idx, iqc_coeff[0]);
15293 +
15294 + if (-mag_rx == res_scale) {
15295 + ath_print(common, ATH_DBG_CALIBRATE,
15296 + "Divide by 0: mag_rx=%d, res_scale=%d\n",
15297 + mag_rx, res_scale);
15298 + return false;
15299 + }
15300 +
15301 + /* calculate and quantize Rx IQ correction factors */
15302 + mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
15303 + phs_corr_rx = -phs_rx;
15304 +
15305 + q_q_coff = (mag_corr_rx * 128 / res_scale);
15306 + q_i_coff = (phs_corr_rx * 256 / res_scale);
15307 +
15308 + ath_print(common, ATH_DBG_CALIBRATE,
15309 + "rx chain %d: mag corr=%d phase corr=%d\n",
15310 + chain_idx, q_q_coff, q_i_coff);
15311 +
15312 + if (q_i_coff < -63)
15313 + q_i_coff = -63;
15314 + if (q_i_coff > 63)
15315 + q_i_coff = 63;
15316 + if (q_q_coff < -63)
15317 + q_q_coff = -63;
15318 + if (q_q_coff > 63)
15319 + q_q_coff = 63;
15320 +
15321 + iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
15322 +
15323 + ath_print(common, ATH_DBG_CALIBRATE,
15324 + "rx chain %d: iq corr coeff=%x\n",
15325 + chain_idx, iqc_coeff[1]);
15326 +
15327 + return true;
15328 +}
15329 +
15330 +static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
15331 +{
15332 + struct ath_common *common = ath9k_hw_common(ah);
15333 + const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
15334 + AR_PHY_TX_IQCAL_STATUS_B0,
15335 + AR_PHY_TX_IQCAL_STATUS_B1,
15336 + AR_PHY_TX_IQCAL_STATUS_B2,
15337 + };
15338 + const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
15339 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
15340 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
15341 + AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
15342 + };
15343 + const u32 rx_corr[AR9300_MAX_CHAINS] = {
15344 + AR_PHY_RX_IQCAL_CORR_B0,
15345 + AR_PHY_RX_IQCAL_CORR_B1,
15346 + AR_PHY_RX_IQCAL_CORR_B2,
15347 + };
15348 + const u_int32_t chan_info_tab[] = {
15349 + AR_PHY_CHAN_INFO_TAB_0,
15350 + AR_PHY_CHAN_INFO_TAB_1,
15351 + AR_PHY_CHAN_INFO_TAB_2,
15352 + };
15353 + s32 iq_res[6];
15354 + s32 iqc_coeff[2];
15355 + s32 i, j;
15356 + u32 num_chains = 0;
15357 +
15358 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
15359 + if (ah->txchainmask & (1 << i))
15360 + num_chains++;
15361 + }
15362 +
15363 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
15364 + AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
15365 + DELPT);
15366 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
15367 + AR_PHY_TX_IQCAL_START_DO_CAL,
15368 + AR_PHY_TX_IQCAL_START_DO_CAL);
15369 +
15370 + if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
15371 + AR_PHY_TX_IQCAL_START_DO_CAL,
15372 + 0, AH_WAIT_TIMEOUT)) {
15373 + ath_print(common, ATH_DBG_CALIBRATE,
15374 + "Tx IQ Cal not complete.\n");
15375 + goto TX_IQ_CAL_FAILED;
15376 + }
15377 +
15378 + for (i = 0; i < num_chains; i++) {
15379 + ath_print(common, ATH_DBG_CALIBRATE,
15380 + "Doing Tx IQ Cal for chain %d.\n", i);
15381 +
15382 + if (REG_READ(ah, txiqcal_status[i]) &
15383 + AR_PHY_TX_IQCAL_STATUS_FAILED) {
15384 + ath_print(common, ATH_DBG_CALIBRATE,
15385 + "Tx IQ Cal failed for chain %d.\n", i);
15386 + goto TX_IQ_CAL_FAILED;
15387 + }
15388 +
15389 + for (j = 0; j < 3; j++) {
15390 + u_int8_t idx = 2 * j,
15391 + offset = 4 * j;
15392 +
15393 + REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
15394 + AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
15395 +
15396 + /* 32 bits */
15397 + iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
15398 +
15399 + REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
15400 + AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
15401 +
15402 + /* 16 bits */
15403 + iq_res[idx+1] = 0xffff & REG_READ(ah, chan_info_tab[i] + offset);
15404 +
15405 + ath_print(common, ATH_DBG_CALIBRATE,
15406 + "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
15407 + idx, iq_res[idx], idx+1, iq_res[idx+1]);
15408 + }
15409 +
15410 + if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
15411 + ath_print(common, ATH_DBG_CALIBRATE,
15412 + "Failed in calculation of IQ correction.\n");
15413 + goto TX_IQ_CAL_FAILED;
15414 + }
15415 +
15416 + ath_print(common, ATH_DBG_CALIBRATE,
15417 + "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
15418 + iqc_coeff[0], iqc_coeff[1]);
15419 +
15420 + REG_RMW_FIELD(ah, tx_corr_coeff[i],
15421 + AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
15422 + iqc_coeff[0]);
15423 + REG_RMW_FIELD(ah, rx_corr[i],
15424 + AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
15425 + iqc_coeff[1] >> 7);
15426 + REG_RMW_FIELD(ah, rx_corr[i],
15427 + AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
15428 + iqc_coeff[1]);
15429 + }
15430 +
15431 + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
15432 + AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
15433 + REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
15434 + AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
15435 +
15436 + return;
15437 +
15438 +TX_IQ_CAL_FAILED:
15439 + ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
15440 + return;
15441 +}
15442 +
15443 +static bool ar9003_hw_init_cal(struct ath_hw *ah,
15444 + struct ath9k_channel *chan)
15445 +{
15446 + struct ath_common *common = ath9k_hw_common(ah);
15447 +
15448 + /*
15449 + * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
15450 + * running AGC/TxIQ cals
15451 + */
15452 + ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
15453 +
15454 + /* Calibrate the AGC */
15455 + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
15456 + REG_READ(ah, AR_PHY_AGC_CONTROL) |
15457 + AR_PHY_AGC_CONTROL_CAL);
15458 +
15459 + /* Poll for offset calibration complete */
15460 + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
15461 + 0, AH_WAIT_TIMEOUT)) {
15462 + ath_print(common, ATH_DBG_CALIBRATE,
15463 + "offset calibration failed to "
15464 + "complete in 1ms; noisy environment?\n");
15465 + return false;
15466 + }
15467 +
15468 + /* Do Tx IQ Calibration */
15469 + ar9003_hw_tx_iq_cal(ah);
15470 +
15471 + /* Revert chainmasks to their original values before NF cal */
15472 + ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
15473 +
15474 + /* Initialize list pointers */
15475 + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
15476 +
15477 + if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
15478 + INIT_CAL(&ah->iq_caldata);
15479 + INSERT_CAL(ah, &ah->iq_caldata);
15480 + ath_print(common, ATH_DBG_CALIBRATE,
15481 + "enabling IQ Calibration.\n");
15482 + }
15483 +
15484 + if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) {
15485 + INIT_CAL(&ah->tempCompCalData);
15486 + INSERT_CAL(ah, &ah->tempCompCalData);
15487 + ath_print(common, ATH_DBG_CALIBRATE,
15488 + "enabling Temperature Compensation Calibration.\n");
15489 + }
15490 +
15491 + /* Initialize current pointer to first element in list */
15492 + ah->cal_list_curr = ah->cal_list;
15493 +
15494 + if (ah->cal_list_curr)
15495 + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
15496 +
15497 + chan->CalValid = 0;
15498 +
15499 + return true;
15500 +}
15501 +
15502 +void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
15503 +{
15504 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
15505 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
15506 +
15507 + priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
15508 + priv_ops->init_cal = ar9003_hw_init_cal;
15509 + priv_ops->setup_calibration = ar9003_hw_setup_calibration;
15510 + priv_ops->iscal_supported = ar9003_hw_iscal_supported;
15511 +
15512 + ops->calibrate = ar9003_hw_calibrate;
15513 +}
15514 --- /dev/null
15515 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
15516 @@ -0,0 +1,1841 @@
15517 +/*
15518 + * Copyright (c) 2010 Atheros Communications Inc.
15519 + *
15520 + * Permission to use, copy, modify, and/or distribute this software for any
15521 + * purpose with or without fee is hereby granted, provided that the above
15522 + * copyright notice and this permission notice appear in all copies.
15523 + *
15524 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15525 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15526 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15527 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15528 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15529 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15530 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15531 + */
15532 +
15533 +#include "hw.h"
15534 +#include "ar9003_phy.h"
15535 +#include "ar9003_eeprom.h"
15536 +
15537 +#define COMP_HDR_LEN 4
15538 +#define COMP_CKSUM_LEN 2
15539 +
15540 +#define AR_CH0_TOP (0x00016288)
15541 +#define AR_CH0_TOP_XPABIASLVL (0x3)
15542 +#define AR_CH0_TOP_XPABIASLVL_S (8)
15543 +
15544 +#define AR_CH0_THERM (0x00016290)
15545 +#define AR_CH0_THERM_SPARE (0x3f)
15546 +#define AR_CH0_THERM_SPARE_S (0)
15547 +
15548 +#define AR_SWITCH_TABLE_COM_ALL (0xffff)
15549 +#define AR_SWITCH_TABLE_COM_ALL_S (0)
15550 +
15551 +#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
15552 +#define AR_SWITCH_TABLE_COM2_ALL_S (0)
15553 +
15554 +#define AR_SWITCH_TABLE_ALL (0xfff)
15555 +#define AR_SWITCH_TABLE_ALL_S (0)
15556 +
15557 +static const struct ar9300_eeprom ar9300_default = {
15558 + .eepromVersion = 2,
15559 + .templateVersion = 2,
15560 + .macAddr = {1, 2, 3, 4, 5, 6},
15561 + .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15562 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
15563 + .baseEepHeader = {
15564 + .regDmn = {0, 0x1f},
15565 + .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
15566 + .opCapFlags = {
15567 + .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
15568 + .eepMisc = 0,
15569 + },
15570 + .rfSilent = 0,
15571 + .blueToothOptions = 0,
15572 + .deviceCap = 0,
15573 + .deviceType = 5, /* takes lower byte in eeprom location */
15574 + .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
15575 + .params_for_tuning_caps = {0, 0},
15576 + .featureEnable = 0x0c,
15577 + /*
15578 + * bit0 - enable tx temp comp - disabled
15579 + * bit1 - enable tx volt comp - disabled
15580 + * bit2 - enable fastClock - enabled
15581 + * bit3 - enable doubling - enabled
15582 + * bit4 - enable internal regulator - disabled
15583 + */
15584 + .miscConfiguration = 0, /* bit0 - turn down drivestrength */
15585 + .eepromWriteEnableGpio = 3,
15586 + .wlanDisableGpio = 0,
15587 + .wlanLedGpio = 8,
15588 + .rxBandSelectGpio = 0xff,
15589 + .txrxgain = 0,
15590 + .swreg = 0,
15591 + },
15592 + .modalHeader2G = {
15593 + /* ar9300_modal_eep_header 2g */
15594 + /* 4 idle,t1,t2,b(4 bits per setting) */
15595 + .antCtrlCommon = 0x110,
15596 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
15597 + .antCtrlCommon2 = 0x22222,
15598 +
15599 + /*
15600 + * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
15601 + * rx1, rx12, b (2 bits each)
15602 + */
15603 + .antCtrlChain = {0x150, 0x150, 0x150},
15604 +
15605 + /*
15606 + * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
15607 + * for ar9280 (0xa20c/b20c 5:0)
15608 + */
15609 + .xatten1DB = {0, 0, 0},
15610 +
15611 + /*
15612 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
15613 + * for ar9280 (0xa20c/b20c 16:12
15614 + */
15615 + .xatten1Margin = {0, 0, 0},
15616 + .tempSlope = 36,
15617 + .voltSlope = 0,
15618 +
15619 + /*
15620 + * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
15621 + * channels in usual fbin coding format
15622 + */
15623 + .spurChans = {0, 0, 0, 0, 0},
15624 +
15625 + /*
15626 + * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
15627 + * if the register is per chain
15628 + */
15629 + .noiseFloorThreshCh = {-1, 0, 0},
15630 + .ob = {1, 1, 1},/* 3 chain */
15631 + .db_stage2 = {1, 1, 1}, /* 3 chain */
15632 + .db_stage3 = {0, 0, 0},
15633 + .db_stage4 = {0, 0, 0},
15634 + .xpaBiasLvl = 0,
15635 + .txFrameToDataStart = 0x0e,
15636 + .txFrameToPaOn = 0x0e,
15637 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
15638 + .antennaGain = 0,
15639 + .switchSettling = 0x2c,
15640 + .adcDesiredSize = -30,
15641 + .txEndToXpaOff = 0,
15642 + .txEndToRxOn = 0x2,
15643 + .txFrameToXpaOn = 0xe,
15644 + .thresh62 = 28,
15645 + .futureModal = { /* [32] */
15646 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15647 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
15648 + },
15649 + },
15650 + .calFreqPier2G = {
15651 + FREQ2FBIN(2412, 1),
15652 + FREQ2FBIN(2437, 1),
15653 + FREQ2FBIN(2472, 1),
15654 + },
15655 + /* ar9300_cal_data_per_freq_op_loop 2g */
15656 + .calPierData2G = {
15657 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
15658 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
15659 + {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}},
15660 + },
15661 + .calTarget_freqbin_Cck = {
15662 + FREQ2FBIN(2412, 1),
15663 + FREQ2FBIN(2484, 1),
15664 + },
15665 + .calTarget_freqbin_2G = {
15666 + FREQ2FBIN(2412, 1),
15667 + FREQ2FBIN(2437, 1),
15668 + FREQ2FBIN(2472, 1)
15669 + },
15670 + .calTarget_freqbin_2GHT20 = {
15671 + FREQ2FBIN(2412, 1),
15672 + FREQ2FBIN(2437, 1),
15673 + FREQ2FBIN(2472, 1)
15674 + },
15675 + .calTarget_freqbin_2GHT40 = {
15676 + FREQ2FBIN(2412, 1),
15677 + FREQ2FBIN(2437, 1),
15678 + FREQ2FBIN(2472, 1)
15679 + },
15680 + .calTargetPowerCck = {
15681 + /* 1L-5L,5S,11L,11S */
15682 + {{36, 36, 36, 36}},
15683 + {{36, 36, 36, 36}},
15684 + },
15685 + .calTargetPower2G = {
15686 + /* 6-24,36,48,54 */
15687 + {{32, 32, 28, 24}},
15688 + {{32, 32, 28, 24}},
15689 + {{32, 32, 28, 24}},
15690 + },
15691 + .calTargetPower2GHT20 = {
15692 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15693 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15694 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15695 + },
15696 + .calTargetPower2GHT40 = {
15697 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15698 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15699 + {{32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20}},
15700 + },
15701 + .ctlIndex_2G = {
15702 + 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
15703 + 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
15704 + },
15705 + .ctl_freqbin_2G = {
15706 + {
15707 + FREQ2FBIN(2412, 1),
15708 + FREQ2FBIN(2417, 1),
15709 + FREQ2FBIN(2457, 1),
15710 + FREQ2FBIN(2462, 1)
15711 + },
15712 + {
15713 + FREQ2FBIN(2412, 1),
15714 + FREQ2FBIN(2417, 1),
15715 + FREQ2FBIN(2462, 1),
15716 + 0xFF,
15717 + },
15718 +
15719 + {
15720 + FREQ2FBIN(2412, 1),
15721 + FREQ2FBIN(2417, 1),
15722 + FREQ2FBIN(2462, 1),
15723 + 0xFF,
15724 + },
15725 + {
15726 + FREQ2FBIN(2422, 1),
15727 + FREQ2FBIN(2427, 1),
15728 + FREQ2FBIN(2447, 1),
15729 + FREQ2FBIN(2452, 1)
15730 + },
15731 +
15732 + {
15733 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15734 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15735 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15736 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
15737 + },
15738 +
15739 + {
15740 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15741 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15742 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15743 + 0,
15744 + },
15745 +
15746 + {
15747 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15748 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15749 + FREQ2FBIN(2472, 1),
15750 + 0,
15751 + },
15752 +
15753 + {
15754 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
15755 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
15756 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
15757 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
15758 + },
15759 +
15760 + {
15761 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15762 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15763 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15764 + },
15765 +
15766 + {
15767 + /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15768 + /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15769 + /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15770 + 0
15771 + },
15772 +
15773 + {
15774 + /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
15775 + /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
15776 + /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
15777 + 0
15778 + },
15779 +
15780 + {
15781 + /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
15782 + /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
15783 + /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
15784 + /* Data[11].ctlEdges[3].bChannel */
15785 + FREQ2FBIN(2462, 1),
15786 + }
15787 + },
15788 + .ctlPowerData_2G = {
15789 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15790 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15791 + {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
15792 +
15793 + {{{60, 1}, {60, 0}, {0, 0}, {0, 0}}},
15794 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15795 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15796 +
15797 + {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
15798 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15799 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15800 +
15801 + {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
15802 + {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
15803 + },
15804 + .modalHeader5G = {
15805 + /* 4 idle,t1,t2,b (4 bits per setting) */
15806 + .antCtrlCommon = 0x110,
15807 + /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
15808 + .antCtrlCommon2 = 0x22222,
15809 + /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
15810 + .antCtrlChain = {
15811 + 0x000, 0x000, 0x000,
15812 + },
15813 + /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
15814 + .xatten1DB = {0, 0, 0},
15815 +
15816 + /*
15817 + * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
15818 + * for merlin (0xa20c/b20c 16:12
15819 + */
15820 + .xatten1Margin = {0, 0, 0},
15821 + .tempSlope = 68,
15822 + .voltSlope = 0,
15823 + /* spurChans spur channels in usual fbin coding format */
15824 + .spurChans = {0, 0, 0, 0, 0},
15825 + /* noiseFloorThreshCh Check if the register is per chain */
15826 + .noiseFloorThreshCh = {-1, 0, 0},
15827 + .ob = {3, 3, 3}, /* 3 chain */
15828 + .db_stage2 = {3, 3, 3}, /* 3 chain */
15829 + .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
15830 + .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
15831 + .xpaBiasLvl = 0,
15832 + .txFrameToDataStart = 0x0e,
15833 + .txFrameToPaOn = 0x0e,
15834 + .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
15835 + .antennaGain = 0,
15836 + .switchSettling = 0x2d,
15837 + .adcDesiredSize = -30,
15838 + .txEndToXpaOff = 0,
15839 + .txEndToRxOn = 0x2,
15840 + .txFrameToXpaOn = 0xe,
15841 + .thresh62 = 28,
15842 + .futureModal = {
15843 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15844 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
15845 + },
15846 + },
15847 + .calFreqPier5G = {
15848 + FREQ2FBIN(5180, 0),
15849 + FREQ2FBIN(5220, 0),
15850 + FREQ2FBIN(5320, 0),
15851 + FREQ2FBIN(5400, 0),
15852 + FREQ2FBIN(5500, 0),
15853 + FREQ2FBIN(5600, 0),
15854 + FREQ2FBIN(5725, 0),
15855 + FREQ2FBIN(5825, 0)
15856 + },
15857 + .calPierData5G = {
15858 + {
15859 + {0, 0, 0, 0, 0},
15860 + {0, 0, 0, 0, 0},
15861 + {0, 0, 0, 0, 0},
15862 + {0, 0, 0, 0, 0},
15863 + {0, 0, 0, 0, 0},
15864 + {0, 0, 0, 0, 0},
15865 + {0, 0, 0, 0, 0},
15866 + {0, 0, 0, 0, 0},
15867 + },
15868 + {
15869 + {0, 0, 0, 0, 0},
15870 + {0, 0, 0, 0, 0},
15871 + {0, 0, 0, 0, 0},
15872 + {0, 0, 0, 0, 0},
15873 + {0, 0, 0, 0, 0},
15874 + {0, 0, 0, 0, 0},
15875 + {0, 0, 0, 0, 0},
15876 + {0, 0, 0, 0, 0},
15877 + },
15878 + {
15879 + {0, 0, 0, 0, 0},
15880 + {0, 0, 0, 0, 0},
15881 + {0, 0, 0, 0, 0},
15882 + {0, 0, 0, 0, 0},
15883 + {0, 0, 0, 0, 0},
15884 + {0, 0, 0, 0, 0},
15885 + {0, 0, 0, 0, 0},
15886 + {0, 0, 0, 0, 0},
15887 + },
15888 +
15889 + },
15890 + .calTarget_freqbin_5G = {
15891 + FREQ2FBIN(5180, 0),
15892 + FREQ2FBIN(5220, 0),
15893 + FREQ2FBIN(5320, 0),
15894 + FREQ2FBIN(5400, 0),
15895 + FREQ2FBIN(5500, 0),
15896 + FREQ2FBIN(5600, 0),
15897 + FREQ2FBIN(5725, 0),
15898 + FREQ2FBIN(5825, 0)
15899 + },
15900 + .calTarget_freqbin_5GHT20 = {
15901 + FREQ2FBIN(5180, 0),
15902 + FREQ2FBIN(5240, 0),
15903 + FREQ2FBIN(5320, 0),
15904 + FREQ2FBIN(5500, 0),
15905 + FREQ2FBIN(5700, 0),
15906 + FREQ2FBIN(5745, 0),
15907 + FREQ2FBIN(5725, 0),
15908 + FREQ2FBIN(5825, 0)
15909 + },
15910 + .calTarget_freqbin_5GHT40 = {
15911 + FREQ2FBIN(5180, 0),
15912 + FREQ2FBIN(5240, 0),
15913 + FREQ2FBIN(5320, 0),
15914 + FREQ2FBIN(5500, 0),
15915 + FREQ2FBIN(5700, 0),
15916 + FREQ2FBIN(5745, 0),
15917 + FREQ2FBIN(5725, 0),
15918 + FREQ2FBIN(5825, 0)
15919 + },
15920 + .calTargetPower5G = {
15921 + /* 6-24,36,48,54 */
15922 + {{20, 20, 20, 10}},
15923 + {{20, 20, 20, 10}},
15924 + {{20, 20, 20, 10}},
15925 + {{20, 20, 20, 10}},
15926 + {{20, 20, 20, 10}},
15927 + {{20, 20, 20, 10}},
15928 + {{20, 20, 20, 10}},
15929 + {{20, 20, 20, 10}},
15930 + },
15931 + .calTargetPower5GHT20 = {
15932 + /*
15933 + * 0_8_16,1-3_9-11_17-19,
15934 + * 4,5,6,7,12,13,14,15,20,21,22,23
15935 + */
15936 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15937 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15938 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15939 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15940 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15941 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15942 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15943 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15944 + },
15945 + .calTargetPower5GHT40 = {
15946 + /*
15947 + * 0_8_16,1-3_9-11_17-19,
15948 + * 4,5,6,7,12,13,14,15,20,21,22,23
15949 + */
15950 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15951 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15952 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15953 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15954 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15955 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15956 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15957 + {{20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0}},
15958 + },
15959 + .ctlIndex_5G = {
15960 + 0x10, 0x16, 0x18, 0x40, 0x46,
15961 + 0x48, 0x30, 0x36, 0x38
15962 + },
15963 + .ctl_freqbin_5G = {
15964 + {
15965 + /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
15966 + /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
15967 + /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
15968 + /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
15969 + /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
15970 + /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
15971 + /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
15972 + /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
15973 + },
15974 + {
15975 + /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
15976 + /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
15977 + /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
15978 + /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
15979 + /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
15980 + /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
15981 + /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
15982 + /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
15983 + },
15984 +
15985 + {
15986 + /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
15987 + /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
15988 + /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
15989 + /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
15990 + /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
15991 + /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
15992 + /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
15993 + /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
15994 + },
15995 +
15996 + {
15997 + /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
15998 + /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
15999 + /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
16000 + /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
16001 + /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
16002 + /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
16003 + /* Data[3].ctlEdges[6].bChannel */ 0xFF,
16004 + /* Data[3].ctlEdges[7].bChannel */ 0xFF,
16005 + },
16006 +
16007 + {
16008 + /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16009 + /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
16010 + /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
16011 + /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
16012 + /* Data[4].ctlEdges[4].bChannel */ 0xFF,
16013 + /* Data[4].ctlEdges[5].bChannel */ 0xFF,
16014 + /* Data[4].ctlEdges[6].bChannel */ 0xFF,
16015 + /* Data[4].ctlEdges[7].bChannel */ 0xFF,
16016 + },
16017 +
16018 + {
16019 + /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
16020 + /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
16021 + /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
16022 + /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
16023 + /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
16024 + /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
16025 + /* Data[5].ctlEdges[6].bChannel */ 0xFF,
16026 + /* Data[5].ctlEdges[7].bChannel */ 0xFF
16027 + },
16028 +
16029 + {
16030 + /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16031 + /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
16032 + /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
16033 + /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
16034 + /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
16035 + /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
16036 + /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
16037 + /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
16038 + },
16039 +
16040 + {
16041 + /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
16042 + /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
16043 + /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
16044 + /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
16045 + /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
16046 + /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
16047 + /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
16048 + /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
16049 + },
16050 +
16051 + {
16052 + /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
16053 + /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
16054 + /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
16055 + /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
16056 + /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
16057 + /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
16058 + /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
16059 + /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
16060 + }
16061 + },
16062 + .ctlPowerData_5G = {
16063 + {
16064 + {
16065 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16066 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
16067 + }
16068 + },
16069 + {
16070 + {
16071 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16072 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
16073 + }
16074 + },
16075 + {
16076 + {
16077 + {60, 0}, {60, 1}, {60, 0}, {60, 1},
16078 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16079 + }
16080 + },
16081 + {
16082 + {
16083 + {60, 0}, {60, 1}, {60, 1}, {60, 0},
16084 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
16085 + }
16086 + },
16087 + {
16088 + {
16089 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
16090 + {60, 0}, {60, 0}, {60, 0}, {60, 0},
16091 + }
16092 + },
16093 + {
16094 + {
16095 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16096 + {60, 1}, {60, 0}, {60, 0}, {60, 0},
16097 + }
16098 + },
16099 + {
16100 + {
16101 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16102 + {60, 1}, {60, 1}, {60, 1}, {60, 1},
16103 + }
16104 + },
16105 + {
16106 + {
16107 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
16108 + {60, 1}, {60, 1}, {60, 1}, {60, 0},
16109 + }
16110 + },
16111 + {
16112 + {
16113 + {60, 1}, {60, 0}, {60, 1}, {60, 1},
16114 + {60, 1}, {60, 1}, {60, 0}, {60, 1},
16115 + }
16116 + },
16117 + }
16118 +};
16119 +
16120 +static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
16121 +{
16122 + return 0;
16123 +}
16124 +
16125 +static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
16126 + enum eeprom_param param)
16127 +{
16128 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16129 + struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
16130 +
16131 + switch (param) {
16132 + case EEP_MAC_LSW:
16133 + return eep->macAddr[0] << 8 | eep->macAddr[1];
16134 + case EEP_MAC_MID:
16135 + return eep->macAddr[2] << 8 | eep->macAddr[3];
16136 + case EEP_MAC_MSW:
16137 + return eep->macAddr[4] << 8 | eep->macAddr[5];
16138 + case EEP_REG_0:
16139 + return pBase->regDmn[0];
16140 + case EEP_REG_1:
16141 + return pBase->regDmn[1];
16142 + case EEP_OP_CAP:
16143 + return pBase->deviceCap;
16144 + case EEP_OP_MODE:
16145 + return pBase->opCapFlags.opFlags;
16146 + case EEP_RF_SILENT:
16147 + return pBase->rfSilent;
16148 + case EEP_TX_MASK:
16149 + return (pBase->txrxMask >> 4) & 0xf;
16150 + case EEP_RX_MASK:
16151 + return pBase->txrxMask & 0xf;
16152 + case EEP_DRIVE_STRENGTH:
16153 +#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
16154 + return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
16155 + case EEP_INTERNAL_REGULATOR:
16156 + /* Bit 4 is internal regulator flag */
16157 + return ((pBase->featureEnable & 0x10) >> 4);
16158 + case EEP_SWREG:
16159 + return (pBase->swreg);
16160 + default:
16161 + return 0;
16162 + }
16163 +}
16164 +
16165 +#ifdef __BIG_ENDIAN
16166 +static void ar9300_swap_eeprom(struct ar9300_eeprom *eep)
16167 +{
16168 + u32 dword;
16169 + u16 word;
16170 + int i;
16171 +
16172 + word = swab16(eep->baseEepHeader.regDmn[0]);
16173 + eep->baseEepHeader.regDmn[0] = word;
16174 +
16175 + word = swab16(eep->baseEepHeader.regDmn[1]);
16176 + eep->baseEepHeader.regDmn[1] = word;
16177 +
16178 + dword = swab32(eep->modalHeader2G.antCtrlCommon);
16179 + eep->modalHeader2G.antCtrlCommon = dword;
16180 +
16181 + dword = swab32(eep->modalHeader2G.antCtrlCommon2);
16182 + eep->modalHeader2G.antCtrlCommon2 = dword;
16183 +
16184 + dword = swab32(eep->modalHeader5G.antCtrlCommon);
16185 + eep->modalHeader5G.antCtrlCommon = dword;
16186 +
16187 + dword = swab32(eep->modalHeader5G.antCtrlCommon2);
16188 + eep->modalHeader5G.antCtrlCommon2 = dword;
16189 +
16190 + for (i = 0; i < AR9300_MAX_CHAINS; i++) {
16191 + word = swab16(eep->modalHeader2G.antCtrlChain[i]);
16192 + eep->modalHeader2G.antCtrlChain[i] = word;
16193 +
16194 + word = swab16(eep->modalHeader5G.antCtrlChain[i]);
16195 + eep->modalHeader5G.antCtrlChain[i] = word;
16196 + }
16197 +}
16198 +#endif
16199 +
16200 +static bool ar9300_hw_read_eeprom(struct ath_hw *ah,
16201 + long address, u8 * buffer, int many)
16202 +{
16203 + int i;
16204 + u8 value[2];
16205 + unsigned long eepAddr;
16206 + unsigned long byteAddr;
16207 + u16 *svalue;
16208 + struct ath_common *common = ath9k_hw_common(ah);
16209 +
16210 + if ((address < 0) || ((address + many) > AR9300_EEPROM_SIZE - 1)) {
16211 + ath_print(common, ATH_DBG_EEPROM,
16212 + "eeprom address not in range \n");
16213 + return false;
16214 + }
16215 +
16216 + for (i = 0; i < many; i++) {
16217 + eepAddr = (u16) (address + i) / 2;
16218 + byteAddr = (u16) (address + i) % 2;
16219 + svalue = (u16 *) value;
16220 + if (!ath9k_hw_nvram_read(common, eepAddr, svalue)) {
16221 + ath_print(common, ATH_DBG_EEPROM,
16222 + "unable to read eeprom region\n");
16223 + return false;
16224 + }
16225 + *svalue = le16_to_cpu(*svalue);
16226 + buffer[i] = value[byteAddr];
16227 + }
16228 +
16229 + return true;
16230 +}
16231 +
16232 +static bool ar9300_read_eeprom(struct ath_hw *ah,
16233 + int address, u8 * buffer, int many)
16234 +{
16235 + int it;
16236 +
16237 + for (it = 0; it < many; it++)
16238 + if (!ar9300_hw_read_eeprom(ah, (address - it), (buffer + it), 1))
16239 + return false;
16240 + return true;
16241 +}
16242 +
16243 +static void ar9300_comp_hdr_unpack(u8 * best, int *code, int *reference,
16244 + int *length, int *major, int *minor)
16245 +{
16246 + unsigned long value[4];
16247 +
16248 + value[0] = best[0];
16249 + value[1] = best[1];
16250 + value[2] = best[2];
16251 + value[3] = best[3];
16252 + *code = ((value[0] >> 5) & 0x0007);
16253 + *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
16254 + *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
16255 + *major = (value[2] & 0x000f);
16256 + *minor = (value[3] & 0x00ff);
16257 +}
16258 +
16259 +static u16 ar9300_comp_cksum(u8 * data, int dsize)
16260 +{
16261 + int it, checksum = 0;
16262 +
16263 + for (it = 0; it < dsize; it++) {
16264 + checksum += data[it];
16265 + checksum &= 0xffff;
16266 + }
16267 +
16268 + return checksum;
16269 +}
16270 +
16271 +static bool ar9300_uncompress_block(struct ath_hw *ah,
16272 + u8 *mptr,
16273 + int mdataSize,
16274 + u8 *block,
16275 + int size)
16276 +{
16277 + int it;
16278 + int spot;
16279 + int offset;
16280 + int length;
16281 + struct ath_common *common = ath9k_hw_common(ah);
16282 +
16283 + spot = 0;
16284 +
16285 + for (it = 0; it < size; it += (length+2)) {
16286 + offset = block[it];
16287 + offset &= 0xff;
16288 + spot += offset;
16289 + length = block[it+1];
16290 + length &= 0xff;
16291 +
16292 + if (length > 0 && spot >= 0 && spot+length < mdataSize) {
16293 + ath_print(common, ATH_DBG_EEPROM,
16294 + "Restore at %d: spot=%d offset=%d length=%d\n",
16295 + it, spot, offset, length);
16296 + memcpy(&mptr[spot],&block[it+2],length);
16297 + spot += length;
16298 + } else if (length > 0) {
16299 + ath_print(common, ATH_DBG_EEPROM,
16300 + "Bad restore at %d: spot=%d offset=%d length=%d\n",
16301 + it, spot, offset, length);
16302 + return false;
16303 + }
16304 + }
16305 + return true;
16306 +}
16307 +
16308 +static int ar9300_compress_decision(struct ath_hw *ah,
16309 + int it,
16310 + int code,
16311 + int reference,
16312 + u8 * mptr,
16313 + u8 * word, int length, int mdata_size)
16314 +{
16315 + struct ath_common *common = ath9k_hw_common(ah);
16316 + u8 *dptr;
16317 +
16318 + switch (code) {
16319 + case _CompressNone:
16320 + if (length != mdata_size) {
16321 + ath_print(common, ATH_DBG_EEPROM,
16322 + "EEPROM structure size mismatch"
16323 + "memory=%d eeprom=%d\n", mdata_size, length);
16324 + return -1;
16325 + }
16326 + memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
16327 + ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
16328 + " uncompressed, length %d\n", it, length);
16329 + break;
16330 + case _CompressBlock:
16331 + if (reference == 0) {
16332 + dptr = mptr;
16333 + } else {
16334 + if (reference != 2) {
16335 + ath_print(common, ATH_DBG_EEPROM,
16336 + "cant find reference eeprom"
16337 + "struct %d\n", reference);
16338 + return -1;
16339 + }
16340 + memcpy(mptr, &ar9300_default, mdata_size);
16341 + }
16342 + ath_print(common, ATH_DBG_EEPROM,
16343 + "restore eeprom %d: block, reference %d,"
16344 + " length %d\n", it, reference, length);
16345 + ar9300_uncompress_block(ah, mptr, mdata_size,
16346 + (u8 *) (word + COMP_HDR_LEN), length);
16347 + break;
16348 + default:
16349 + ath_print(common, ATH_DBG_EEPROM, "unknown compression"
16350 + " code %d\n", code);
16351 + return -1;
16352 + }
16353 + return 0;
16354 +}
16355 +
16356 +/*
16357 + * Read the configuration data from the eeprom.
16358 + * The data can be put in any specified memory buffer.
16359 + *
16360 + * Returns -1 on error.
16361 + * Returns address of next memory location on success.
16362 + */
16363 +static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
16364 + u8 * mptr, int mdata_size)
16365 +{
16366 +#define MDEFAULT 15
16367 +#define MSTATE 100
16368 + int cptr;
16369 + u8 *word;
16370 + int code;
16371 + int reference, length, major, minor;
16372 + int osize;
16373 + int it;
16374 + u16 checksum, mchecksum;
16375 + struct ath_common *common = ath9k_hw_common(ah);
16376 +
16377 + word = kzalloc(2048, GFP_KERNEL);
16378 + if (!word)
16379 + return -1;
16380 +
16381 + memcpy(mptr, &ar9300_default, mdata_size);
16382 +
16383 + cptr = AR9300_BASE_ADDR;
16384 + for (it = 0; it < MSTATE; it++) {
16385 + if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
16386 + goto fail;
16387 +
16388 + if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
16389 + word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
16390 + && word[2] == 0xff && word[3] == 0xff))
16391 + break;
16392 +
16393 + ar9300_comp_hdr_unpack(word, &code, &reference,
16394 + &length, &major, &minor);
16395 + ath_print(common, ATH_DBG_EEPROM,
16396 + "Found block at %x: code=%d ref=%d"
16397 + "length=%d major=%d minor=%d\n", cptr, code,
16398 + reference, length, major, minor);
16399 + if (length >= 1024) {
16400 + ath_print(common, ATH_DBG_EEPROM,
16401 + "Skipping bad header\n");
16402 + cptr -= COMP_HDR_LEN;
16403 + continue;
16404 + }
16405 +
16406 + osize = length;
16407 + ar9300_read_eeprom(ah, cptr, word,
16408 + COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
16409 + checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
16410 + mchecksum = word[COMP_HDR_LEN + osize] |
16411 + (word[COMP_HDR_LEN + osize + 1] << 8);
16412 + ath_print(common, ATH_DBG_EEPROM,
16413 + "checksum %x %x\n", checksum, mchecksum);
16414 + if (checksum == mchecksum) {
16415 + ar9300_compress_decision(ah, it, code, reference, mptr,
16416 + word, length, mdata_size);
16417 + } else {
16418 + ath_print(common, ATH_DBG_EEPROM,
16419 + "skipping block with bad checksum\n");
16420 + }
16421 + cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
16422 + }
16423 +
16424 + kfree(word);
16425 + return cptr;
16426 +
16427 +fail:
16428 + kfree(word);
16429 + return -1;
16430 +}
16431 +
16432 +/*
16433 + * Restore the configuration structure by reading the eeprom.
16434 + * This function destroys any existing in-memory structure
16435 + * content.
16436 + */
16437 +static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
16438 +{
16439 + u8 *mptr = NULL;
16440 + int mdata_size;
16441 +
16442 + mptr = (u8 *) & ah->eeprom.ar9300_eep;
16443 + mdata_size = sizeof(struct ar9300_eeprom);
16444 +
16445 + if (mptr && mdata_size > 0) {
16446 + /* At this point, mptr points to the eeprom data structure
16447 + * in it's "default" state. If this is big endian, swap the
16448 + * data structures back to "little endian"
16449 + */
16450 + /* First swap, default to Little Endian */
16451 +#ifdef __BIG_ENDIAN
16452 + ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
16453 +#endif
16454 + if (ar9300_eeprom_restore_internal(ah, mptr, mdata_size) >= 0)
16455 + return true;
16456 +
16457 + /* Second Swap, back to Big Endian */
16458 +#ifdef __BIG_ENDIAN
16459 + ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
16460 +#endif
16461 + }
16462 + return false;
16463 +}
16464 +
16465 +/* XXX: review hardware docs */
16466 +static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
16467 +{
16468 + return ah->eeprom.ar9300_eep.eepromVersion;
16469 +}
16470 +
16471 +/* XXX: could be read from the eepromVersion, not sure yet */
16472 +static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
16473 +{
16474 + return 0;
16475 +}
16476 +
16477 +static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
16478 + enum ieee80211_band freq_band)
16479 +{
16480 + return 1;
16481 +}
16482 +
16483 +static u16 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
16484 + struct ath9k_channel *chan)
16485 +{
16486 + return -EINVAL;
16487 +}
16488 +
16489 +static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
16490 +{
16491 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16492 +
16493 + if (is2ghz)
16494 + return eep->modalHeader2G.xpaBiasLvl;
16495 + else
16496 + return eep->modalHeader5G.xpaBiasLvl;
16497 +}
16498 +
16499 +static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
16500 +{
16501 + int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
16502 + REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
16503 + REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
16504 + ((bias >> 2) & 0x3));
16505 +}
16506 +
16507 +static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
16508 +{
16509 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16510 +
16511 + if (is2ghz)
16512 + return eep->modalHeader2G.antCtrlCommon;
16513 + else
16514 + return eep->modalHeader5G.antCtrlCommon;
16515 +}
16516 +
16517 +static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
16518 +{
16519 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16520 +
16521 + if (is2ghz)
16522 + return eep->modalHeader2G.antCtrlCommon2;
16523 + else
16524 + return eep->modalHeader5G.antCtrlCommon2;
16525 +}
16526 +
16527 +static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, bool is2ghz)
16528 +{
16529 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16530 +
16531 + if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
16532 + if (is2ghz)
16533 + return eep->modalHeader2G.antCtrlChain[chain];
16534 + else
16535 + return eep->modalHeader5G.antCtrlChain[chain];
16536 + }
16537 +
16538 + return 0;
16539 +}
16540 +
16541 +static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
16542 +{
16543 + u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
16544 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
16545 +
16546 + value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
16547 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
16548 +
16549 + value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
16550 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
16551 +
16552 + value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
16553 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
16554 +
16555 + value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
16556 + REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
16557 +}
16558 +
16559 +static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
16560 +{
16561 + int drive_strength;
16562 + unsigned long reg;
16563 +
16564 + drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
16565 +
16566 + if (!drive_strength)
16567 + return;
16568 +
16569 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
16570 + reg &= ~0x00ffffc0;
16571 + reg |= 0x5 << 21;
16572 + reg |= 0x5 << 18;
16573 + reg |= 0x5 << 15;
16574 + reg |= 0x5 << 12;
16575 + reg |= 0x5 << 9;
16576 + reg |= 0x5 << 6;
16577 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
16578 +
16579 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
16580 + reg &= ~0xffffffe0;
16581 + reg |= 0x5 << 29;
16582 + reg |= 0x5 << 26;
16583 + reg |= 0x5 << 23;
16584 + reg |= 0x5 << 20;
16585 + reg |= 0x5 << 17;
16586 + reg |= 0x5 << 14;
16587 + reg |= 0x5 << 11;
16588 + reg |= 0x5 << 8;
16589 + reg |= 0x5 << 5;
16590 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
16591 +
16592 + reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
16593 + reg &= ~0xff800000;
16594 + reg |= 0x5 << 29;
16595 + reg |= 0x5 << 26;
16596 + reg |= 0x5 << 23;
16597 + REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
16598 +}
16599 +
16600 +static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
16601 +{
16602 + int internal_regulator =
16603 + ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
16604 +
16605 + if (internal_regulator) {
16606 + /* Internal regulator is ON. Write swreg register. */
16607 + int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
16608 + REG_WRITE(ah, AR_RTC_REG_CONTROL1,
16609 + REG_READ(ah, AR_RTC_REG_CONTROL1) &
16610 + (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
16611 + REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
16612 + /* Set REG_CONTROL1.SWREG_PROGRAM */
16613 + REG_WRITE(ah, AR_RTC_REG_CONTROL1,
16614 + REG_READ(ah,
16615 + AR_RTC_REG_CONTROL1) |
16616 + AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
16617 + } else {
16618 + REG_WRITE(ah, AR_RTC_SLEEP_CLK,
16619 + (REG_READ(ah,
16620 + AR_RTC_SLEEP_CLK) |
16621 + AR_RTC_FORCE_SWREG_PRD));
16622 + }
16623 +}
16624 +
16625 +static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
16626 + struct ath9k_channel *chan)
16627 +{
16628 + ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
16629 + ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
16630 + ar9003_hw_drive_strength_apply(ah);
16631 + ar9003_hw_internal_regulator_apply(ah);
16632 +}
16633 +
16634 +static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
16635 + struct ath9k_channel *chan)
16636 +{
16637 +}
16638 +
16639 +/*
16640 + * Returns the interpolated y value corresponding to the specified x value
16641 + * from the np ordered pairs of data (px,py).
16642 + * The pairs do not have to be in any order.
16643 + * If the specified x value is less than any of the px,
16644 + * the returned y value is equal to the py for the lowest px.
16645 + * If the specified x value is greater than any of the px,
16646 + * the returned y value is equal to the py for the highest px.
16647 + */
16648 +static int ar9003_hw_power_interpolate(int32_t x,
16649 + int32_t * px, int32_t * py, u_int16_t np)
16650 +{
16651 + int ip = 0;
16652 + int lx = 0, ly = 0, lhave = 0;
16653 + int hx = 0, hy = 0, hhave = 0;
16654 + int dx = 0;
16655 + int y = 0;
16656 +
16657 + lhave = 0;
16658 + hhave = 0;
16659 +
16660 + /* identify best lower and higher x calibration measurement */
16661 + for (ip = 0; ip < np; ip++) {
16662 + dx = x - px[ip];
16663 +
16664 + /* this measurement is higher than our desired x */
16665 + if (dx <= 0) {
16666 + if (!hhave || dx > (x - hx)) {
16667 + /* new best higher x measurement */
16668 + hx = px[ip];
16669 + hy = py[ip];
16670 + hhave = 1;
16671 + }
16672 + }
16673 + /* this measurement is lower than our desired x */
16674 + if (dx >= 0) {
16675 + if (!lhave || dx < (x - lx)) {
16676 + /* new best lower x measurement */
16677 + lx = px[ip];
16678 + ly = py[ip];
16679 + lhave = 1;
16680 + }
16681 + }
16682 + }
16683 +
16684 + /* the low x is good */
16685 + if (lhave) {
16686 + /* so is the high x */
16687 + if (hhave) {
16688 + /* they're the same, so just pick one */
16689 + if (hx == lx)
16690 + y = ly;
16691 + else /* interpolate */
16692 + y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
16693 + } else /* only low is good, use it */
16694 + y = ly;
16695 + } else if (hhave) /* only high is good, use it */
16696 + y = hy;
16697 + else /* nothing is good,this should never happen unless np=0, ???? */
16698 + y = -(1 << 30);
16699 + return y;
16700 +}
16701 +
16702 +static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
16703 + u16 rateIndex, u16 freq, bool is2GHz)
16704 +{
16705 + u16 numPiers, i;
16706 + s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
16707 + s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
16708 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16709 + struct cal_tgt_pow_legacy *pEepromTargetPwr;
16710 + u8 *pFreqBin;
16711 +
16712 + if (is2GHz) {
16713 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
16714 + pEepromTargetPwr = eep->calTargetPower2G;
16715 + pFreqBin = eep->calTarget_freqbin_2G;
16716 + } else {
16717 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
16718 + pEepromTargetPwr = eep->calTargetPower5G;
16719 + pFreqBin = eep->calTarget_freqbin_5G;
16720 + }
16721 +
16722 + /*
16723 + * create array of channels and targetpower from
16724 + * targetpower piers stored on eeprom
16725 + */
16726 + for (i = 0; i < numPiers; i++) {
16727 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
16728 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
16729 + }
16730 +
16731 + /* interpolate to get target power for given frequency */
16732 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
16733 + freqArray,
16734 + targetPowerArray, numPiers));
16735 +}
16736 +
16737 +static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
16738 + u16 rateIndex,
16739 + u16 freq, bool is2GHz)
16740 +{
16741 + u16 numPiers, i;
16742 + s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
16743 + s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
16744 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16745 + struct cal_tgt_pow_ht *pEepromTargetPwr;
16746 + u8 *pFreqBin;
16747 +
16748 + if (is2GHz) {
16749 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
16750 + pEepromTargetPwr = eep->calTargetPower2GHT20;
16751 + pFreqBin = eep->calTarget_freqbin_2GHT20;
16752 + } else {
16753 + numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
16754 + pEepromTargetPwr = eep->calTargetPower5GHT20;
16755 + pFreqBin = eep->calTarget_freqbin_5GHT20;
16756 + }
16757 +
16758 + /*
16759 + * create array of channels and targetpower
16760 + * from targetpower piers stored on eeprom
16761 + */
16762 + for (i = 0; i < numPiers; i++) {
16763 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
16764 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
16765 + }
16766 +
16767 + /* interpolate to get target power for given frequency */
16768 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
16769 + freqArray,
16770 + targetPowerArray, numPiers));
16771 +}
16772 +
16773 +static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
16774 + u16 rateIndex,
16775 + u16 freq, bool is2GHz)
16776 +{
16777 + u16 numPiers, i;
16778 + s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
16779 + s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
16780 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16781 + struct cal_tgt_pow_ht *pEepromTargetPwr;
16782 + u8 *pFreqBin;
16783 +
16784 + if (is2GHz) {
16785 + numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
16786 + pEepromTargetPwr = eep->calTargetPower2GHT40;
16787 + pFreqBin = eep->calTarget_freqbin_2GHT40;
16788 + } else {
16789 + numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
16790 + pEepromTargetPwr = eep->calTargetPower5GHT40;
16791 + pFreqBin = eep->calTarget_freqbin_5GHT40;
16792 + }
16793 +
16794 + /*
16795 + * create array of channels and targetpower from
16796 + * targetpower piers stored on eeprom
16797 + */
16798 + for (i = 0; i < numPiers; i++) {
16799 + freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
16800 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
16801 + }
16802 +
16803 + /* interpolate to get target power for given frequency */
16804 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
16805 + freqArray,
16806 + targetPowerArray, numPiers));
16807 +}
16808 +
16809 +static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
16810 + u16 rateIndex, u16 freq)
16811 +{
16812 + u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
16813 + s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
16814 + s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
16815 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
16816 + struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
16817 + u8 *pFreqBin = eep->calTarget_freqbin_Cck;
16818 +
16819 + /*
16820 + * create array of channels and targetpower from
16821 + * targetpower piers stored on eeprom
16822 + */
16823 + for (i = 0; i < numPiers; i++) {
16824 + freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
16825 + targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
16826 + }
16827 +
16828 + /* interpolate to get target power for given frequency */
16829 + return ((u8) ar9003_hw_power_interpolate((s32) freq,
16830 + freqArray,
16831 + targetPowerArray, numPiers));
16832 +}
16833 +
16834 +/* Set tx power registers to array of values passed in */
16835 +static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
16836 +{
16837 +#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
16838 + /* make sure forced gain is not set */
16839 + REG_WRITE(ah, 0xa458, 0);
16840 +
16841 + /* Write the OFDM power per rate set */
16842 +
16843 + /* 6 (LSB), 9, 12, 18 (MSB) */
16844 + REG_WRITE(ah, 0xa3c0,
16845 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
16846 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
16847 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
16848 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
16849 +
16850 + /* 24 (LSB), 36, 48, 54 (MSB) */
16851 + REG_WRITE(ah, 0xa3c4,
16852 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
16853 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
16854 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
16855 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
16856 +
16857 + /* Write the CCK power per rate set */
16858 +
16859 + /* 1L (LSB), reserved, 2L, 2S (MSB) */
16860 + REG_WRITE(ah, 0xa3c8,
16861 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
16862 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
16863 + // POW_SM(txPowerTimes2, 8) | /* this is reserved for AR9003 */
16864 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
16865 +
16866 + /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
16867 + REG_WRITE(ah, 0xa3cc,
16868 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
16869 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
16870 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
16871 + POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
16872 + );
16873 +
16874 + /* Write the HT20 power per rate set */
16875 +
16876 + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
16877 + REG_WRITE(ah, 0xa3d0,
16878 + POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
16879 + POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
16880 + POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
16881 + POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
16882 + );
16883 +
16884 + /* 6 (LSB), 7, 12, 13 (MSB) */
16885 + REG_WRITE(ah, 0xa3d4,
16886 + POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
16887 + POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
16888 + POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
16889 + POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
16890 + );
16891 +
16892 + /* 14 (LSB), 15, 20, 21 */
16893 + REG_WRITE(ah, 0xa3e4,
16894 + POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
16895 + POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
16896 + POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
16897 + POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
16898 + );
16899 +
16900 + /* Mixed HT20 and HT40 rates */
16901 +
16902 + /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
16903 + REG_WRITE(ah, 0xa3e8,
16904 + POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
16905 + POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
16906 + POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
16907 + POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
16908 + );
16909 +
16910 + /* Write the HT40 power per rate set */
16911 + // correct PAR difference between HT40 and HT20/LEGACY
16912 + /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
16913 + REG_WRITE(ah, 0xa3d8,
16914 + POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
16915 + POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
16916 + POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
16917 + POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
16918 + );
16919 +
16920 + /* 6 (LSB), 7, 12, 13 (MSB) */
16921 + REG_WRITE(ah, 0xa3dc,
16922 + POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
16923 + POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
16924 + POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
16925 + POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
16926 + );
16927 +
16928 + /* 14 (LSB), 15, 20, 21 */
16929 + REG_WRITE(ah, 0xa3ec,
16930 + POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
16931 + POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
16932 + POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
16933 + POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
16934 + );
16935 +
16936 + return 0;
16937 +#undef POW_SM
16938 +}
16939 +
16940 +static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq)
16941 +{
16942 + u8 targetPowerValT2[ar9300RateSize];
16943 + /* XXX: hard code for now, need to get from eeprom struct */
16944 + u8 ht40PowerIncForPdadc = 0;
16945 + bool is2GHz = false;
16946 + unsigned int i = 0;
16947 + struct ath_common *common = ath9k_hw_common(ah);
16948 +
16949 + if (freq < 4000)
16950 + is2GHz = true;
16951 +
16952 + targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
16953 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
16954 + is2GHz);
16955 + targetPowerValT2[ALL_TARGET_LEGACY_36] =
16956 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
16957 + is2GHz);
16958 + targetPowerValT2[ALL_TARGET_LEGACY_48] =
16959 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
16960 + is2GHz);
16961 + targetPowerValT2[ALL_TARGET_LEGACY_54] =
16962 + ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
16963 + is2GHz);
16964 + targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
16965 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
16966 + freq);
16967 + targetPowerValT2[ALL_TARGET_LEGACY_5S] =
16968 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
16969 + targetPowerValT2[ALL_TARGET_LEGACY_11L] =
16970 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
16971 + targetPowerValT2[ALL_TARGET_LEGACY_11S] =
16972 + ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
16973 + targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
16974 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
16975 + is2GHz);
16976 + targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
16977 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
16978 + freq, is2GHz);
16979 + targetPowerValT2[ALL_TARGET_HT20_4] =
16980 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
16981 + is2GHz);
16982 + targetPowerValT2[ALL_TARGET_HT20_5] =
16983 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
16984 + is2GHz);
16985 + targetPowerValT2[ALL_TARGET_HT20_6] =
16986 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
16987 + is2GHz);
16988 + targetPowerValT2[ALL_TARGET_HT20_7] =
16989 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
16990 + is2GHz);
16991 + targetPowerValT2[ALL_TARGET_HT20_12] =
16992 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
16993 + is2GHz);
16994 + targetPowerValT2[ALL_TARGET_HT20_13] =
16995 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
16996 + is2GHz);
16997 + targetPowerValT2[ALL_TARGET_HT20_14] =
16998 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
16999 + is2GHz);
17000 + targetPowerValT2[ALL_TARGET_HT20_15] =
17001 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
17002 + is2GHz);
17003 + targetPowerValT2[ALL_TARGET_HT20_20] =
17004 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
17005 + is2GHz);
17006 + targetPowerValT2[ALL_TARGET_HT20_21] =
17007 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
17008 + is2GHz);
17009 + targetPowerValT2[ALL_TARGET_HT20_22] =
17010 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
17011 + is2GHz);
17012 + targetPowerValT2[ALL_TARGET_HT20_23] =
17013 + ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
17014 + is2GHz);
17015 + targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
17016 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
17017 + is2GHz) + ht40PowerIncForPdadc;
17018 + targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
17019 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
17020 + freq,
17021 + is2GHz) + ht40PowerIncForPdadc;
17022 + targetPowerValT2[ALL_TARGET_HT40_4] =
17023 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
17024 + is2GHz) + ht40PowerIncForPdadc;
17025 + targetPowerValT2[ALL_TARGET_HT40_5] =
17026 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
17027 + is2GHz) + ht40PowerIncForPdadc;
17028 + targetPowerValT2[ALL_TARGET_HT40_6] =
17029 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
17030 + is2GHz) + ht40PowerIncForPdadc;
17031 + targetPowerValT2[ALL_TARGET_HT40_7] =
17032 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
17033 + is2GHz) + ht40PowerIncForPdadc;
17034 + targetPowerValT2[ALL_TARGET_HT40_12] =
17035 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
17036 + is2GHz) + ht40PowerIncForPdadc;
17037 + targetPowerValT2[ALL_TARGET_HT40_13] =
17038 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
17039 + is2GHz) + ht40PowerIncForPdadc;
17040 + targetPowerValT2[ALL_TARGET_HT40_14] =
17041 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
17042 + is2GHz) + ht40PowerIncForPdadc;
17043 + targetPowerValT2[ALL_TARGET_HT40_15] =
17044 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
17045 + is2GHz) + ht40PowerIncForPdadc;
17046 + targetPowerValT2[ALL_TARGET_HT40_20] =
17047 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
17048 + is2GHz) + ht40PowerIncForPdadc;
17049 + targetPowerValT2[ALL_TARGET_HT40_21] =
17050 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
17051 + is2GHz) + ht40PowerIncForPdadc;
17052 + targetPowerValT2[ALL_TARGET_HT40_22] =
17053 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
17054 + is2GHz) + ht40PowerIncForPdadc;
17055 + targetPowerValT2[ALL_TARGET_HT40_23] =
17056 + ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
17057 + is2GHz) + ht40PowerIncForPdadc;
17058 +
17059 + while (i < ar9300RateSize) {
17060 + ath_print(common, ATH_DBG_EEPROM,
17061 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
17062 + i++;
17063 +
17064 + ath_print(common, ATH_DBG_EEPROM,
17065 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
17066 + i++;
17067 +
17068 + ath_print(common, ATH_DBG_EEPROM,
17069 + "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
17070 + i++;
17071 +
17072 + ath_print(common, ATH_DBG_EEPROM,
17073 + "TPC[%02d] 0x%08x \n", i, targetPowerValT2[i]);
17074 + i++;
17075 + }
17076 +
17077 + /* Write target power array to registers */
17078 + ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
17079 +}
17080 +
17081 +static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
17082 + int mode,
17083 + int ipier,
17084 + int ichain,
17085 + int *pfrequency,
17086 + int *pcorrection,
17087 + int *ptemperature, int *pvoltage)
17088 +{
17089 + u8 *pCalPier;
17090 + struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
17091 + int is2GHz;
17092 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
17093 + struct ath_common *common = ath9k_hw_common(ah);
17094 +
17095 + if (ichain >= AR9300_MAX_CHAINS) {
17096 + ath_print(common, ATH_DBG_EEPROM,
17097 + "Invalid chain index, must be less than %d\n",
17098 + AR9300_MAX_CHAINS);
17099 + return -1;
17100 + }
17101 +
17102 + if (mode) { /* 5GHz */
17103 + if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
17104 + ath_print(common, ATH_DBG_EEPROM,
17105 + "Invalid 5GHz cal pier index, must be less than %d\n",
17106 + AR9300_NUM_5G_CAL_PIERS);
17107 + return -1;
17108 + }
17109 + pCalPier = &(eep->calFreqPier5G[ipier]);
17110 + pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
17111 + is2GHz = 0;
17112 + } else {
17113 + if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
17114 + ath_print(common, ATH_DBG_EEPROM,
17115 + "Invalid 2GHz cal pier index, must "
17116 + "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
17117 + return -1;
17118 + }
17119 +
17120 + pCalPier = &(eep->calFreqPier2G[ipier]);
17121 + pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
17122 + is2GHz = 1;
17123 + }
17124 +
17125 + *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
17126 + *pcorrection = pCalPierStruct->refPower;
17127 + *ptemperature = pCalPierStruct->tempMeas;
17128 + *pvoltage = pCalPierStruct->voltMeas;
17129 +
17130 + return 0;
17131 +}
17132 +
17133 +static int ar9003_hw_power_control_override(struct ath_hw *ah,
17134 + int frequency,
17135 + int *correction,
17136 + int *voltage, int *temperature)
17137 +{
17138 + int tempSlope = 0;
17139 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
17140 +
17141 + REG_RMW(ah, AR_PHY_TPC_11_B0,
17142 + (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
17143 + AR_PHY_TPC_OLPC_GAIN_DELTA);
17144 + REG_RMW(ah, AR_PHY_TPC_11_B1,
17145 + (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
17146 + AR_PHY_TPC_OLPC_GAIN_DELTA);
17147 + REG_RMW(ah, AR_PHY_TPC_11_B2,
17148 + (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
17149 + AR_PHY_TPC_OLPC_GAIN_DELTA);
17150 +
17151 + /* enable open loop power control on chip */
17152 + REG_RMW(ah, AR_PHY_TPC_6_B0,
17153 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
17154 + AR_PHY_TPC_6_ERROR_EST_MODE);
17155 + REG_RMW(ah, AR_PHY_TPC_6_B1,
17156 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
17157 + AR_PHY_TPC_6_ERROR_EST_MODE);
17158 + REG_RMW(ah, AR_PHY_TPC_6_B2,
17159 + (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
17160 + AR_PHY_TPC_6_ERROR_EST_MODE);
17161 +
17162 + /*
17163 + * enable temperature compensation
17164 + * Need to use register names
17165 + */
17166 + if (frequency < 4000)
17167 + tempSlope = eep->modalHeader2G.tempSlope;
17168 + else
17169 + tempSlope = eep->modalHeader5G.tempSlope;
17170 +
17171 + REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
17172 + REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
17173 + temperature[0]);
17174 +
17175 + return 0;
17176 +}
17177 +
17178 +/* Apply the recorded correction values. */
17179 +static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
17180 +{
17181 + int ichain, ipier, npier;
17182 + int mode;
17183 + int lfrequency[AR9300_MAX_CHAINS],
17184 + lcorrection[AR9300_MAX_CHAINS],
17185 + ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
17186 + int hfrequency[AR9300_MAX_CHAINS],
17187 + hcorrection[AR9300_MAX_CHAINS],
17188 + htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
17189 + int fdiff;
17190 + int correction[AR9300_MAX_CHAINS],
17191 + voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
17192 + int pfrequency, pcorrection, ptemperature, pvoltage;
17193 + struct ath_common *common = ath9k_hw_common(ah);
17194 +
17195 + mode = (frequency >= 4000);
17196 + if (mode)
17197 + npier = AR9300_NUM_5G_CAL_PIERS;
17198 + else
17199 + npier = AR9300_NUM_2G_CAL_PIERS;
17200 +
17201 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
17202 + lfrequency[ichain] = 0;
17203 + hfrequency[ichain] = 100000;
17204 + }
17205 + /* identify best lower and higher frequency calibration measurement */
17206 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
17207 + for (ipier = 0; ipier < npier; ipier++) {
17208 + if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
17209 + &pfrequency, &pcorrection,
17210 + &ptemperature, &pvoltage)) {
17211 + fdiff = frequency - pfrequency;
17212 +
17213 + /*
17214 + * this measurement is higher than
17215 + * our desired frequency
17216 + */
17217 + if (fdiff <= 0) {
17218 + if (hfrequency[ichain] <= 0 ||
17219 + hfrequency[ichain] >= 100000 ||
17220 + fdiff >
17221 + (frequency - hfrequency[ichain])) {
17222 + /* new best higher frequency measurement */
17223 + hfrequency[ichain] = pfrequency;
17224 + hcorrection[ichain] =
17225 + pcorrection;
17226 + htemperature[ichain] =
17227 + ptemperature;
17228 + hvoltage[ichain] = pvoltage;
17229 + }
17230 + }
17231 + if (fdiff >= 0) {
17232 + if (lfrequency[ichain] <= 0
17233 + || fdiff <
17234 + (frequency - lfrequency[ichain])) {
17235 + /* new best lower frequency measurement */
17236 + lfrequency[ichain] = pfrequency;
17237 + lcorrection[ichain] =
17238 + pcorrection;
17239 + ltemperature[ichain] =
17240 + ptemperature;
17241 + lvoltage[ichain] = pvoltage;
17242 + }
17243 + }
17244 + }
17245 + }
17246 + }
17247 +
17248 + /* interpolate */
17249 + for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
17250 + ath_print(common, ATH_DBG_EEPROM,
17251 + "ch=%d f=%d low=%d %d h=%d %d\n",
17252 + ichain, frequency, lfrequency[ichain],
17253 + lcorrection[ichain], hfrequency[ichain],
17254 + hcorrection[ichain]);
17255 + /* they're the same, so just pick one */
17256 + if (hfrequency[ichain] == lfrequency[ichain]) {
17257 + correction[ichain] = lcorrection[ichain];
17258 + voltage[ichain] = lvoltage[ichain];
17259 + temperature[ichain] = ltemperature[ichain];
17260 + }
17261 + /* the low frequency is good */
17262 + else if (frequency - lfrequency[ichain] < 1000) {
17263 + /* so is the high frequency, interpolate */
17264 + if (hfrequency[ichain] - frequency < 1000) {
17265 +
17266 + correction[ichain] = lcorrection[ichain] +
17267 + (((frequency - lfrequency[ichain]) *
17268 + (hcorrection[ichain] -
17269 + lcorrection[ichain])) /
17270 + (hfrequency[ichain] - lfrequency[ichain]));
17271 +
17272 + temperature[ichain] = ltemperature[ichain] +
17273 + (((frequency - lfrequency[ichain]) *
17274 + (htemperature[ichain] -
17275 + ltemperature[ichain])) /
17276 + (hfrequency[ichain] - lfrequency[ichain]));
17277 +
17278 + voltage[ichain] =
17279 + lvoltage[ichain] +
17280 + (((frequency -
17281 + lfrequency[ichain]) * (hvoltage[ichain] -
17282 + lvoltage[ichain]))
17283 + / (hfrequency[ichain] -
17284 + lfrequency[ichain]));
17285 + }
17286 + /* only low is good, use it */
17287 + else {
17288 + correction[ichain] = lcorrection[ichain];
17289 + temperature[ichain] = ltemperature[ichain];
17290 + voltage[ichain] = lvoltage[ichain];
17291 + }
17292 + }
17293 + /* only high is good, use it */
17294 + else if (hfrequency[ichain] - frequency < 1000) {
17295 + correction[ichain] = hcorrection[ichain];
17296 + temperature[ichain] = htemperature[ichain];
17297 + voltage[ichain] = hvoltage[ichain];
17298 + } else { /* nothing is good, presume 0???? */
17299 + correction[ichain] = 0;
17300 + temperature[ichain] = 0;
17301 + voltage[ichain] = 0;
17302 + }
17303 + }
17304 +
17305 + ar9003_hw_power_control_override(ah, frequency, correction, voltage,
17306 + temperature);
17307 +
17308 + ath_print(common, ATH_DBG_EEPROM,
17309 + "for frequency=%d, calibration correction = %d %d %d\n",
17310 + frequency, correction[0], correction[1], correction[2]);
17311 +
17312 + return 0;
17313 +}
17314 +
17315 +static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
17316 + struct ath9k_channel *chan, u16 cfgCtl,
17317 + u8 twiceAntennaReduction,
17318 + u8 twiceMaxRegulatoryPower,
17319 + u8 powerLimit)
17320 +{
17321 + ar9003_hw_set_target_power_eeprom(ah, chan->channel);
17322 + ar9003_hw_calibration_apply(ah, chan->channel);
17323 +}
17324 +
17325 +static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
17326 + u16 i, bool is2GHz)
17327 +{
17328 + return AR_NO_SPUR;
17329 +}
17330 +
17331 +s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
17332 +{
17333 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
17334 +
17335 + return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
17336 +}
17337 +
17338 +s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
17339 +{
17340 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
17341 +
17342 + return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
17343 +}
17344 +
17345 +const struct eeprom_ops eep_ar9300_ops = {
17346 + .check_eeprom = ath9k_hw_ar9300_check_eeprom,
17347 + .get_eeprom = ath9k_hw_ar9300_get_eeprom,
17348 + .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
17349 + .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
17350 + .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
17351 + .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
17352 + .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
17353 + .set_board_values = ath9k_hw_ar9300_set_board_values,
17354 + .set_addac = ath9k_hw_ar9300_set_addac,
17355 + .set_txpower = ath9k_hw_ar9300_set_txpower,
17356 + .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
17357 +};
17358 --- /dev/null
17359 +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
17360 @@ -0,0 +1,323 @@
17361 +#ifndef AR9003_EEPROM_H
17362 +#define AR9003_EEPROM_H
17363 +
17364 +#include <linux/types.h>
17365 +
17366 +#define AR9300_EEP_VER 0xD000
17367 +#define AR9300_EEP_VER_MINOR_MASK 0xFFF
17368 +#define AR9300_EEP_MINOR_VER_1 0x1
17369 +#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
17370 +
17371 +// 16-bit offset location start of calibration struct
17372 +#define AR9300_EEP_START_LOC 256
17373 +#define AR9300_NUM_5G_CAL_PIERS 8
17374 +#define AR9300_NUM_2G_CAL_PIERS 3
17375 +#define AR9300_NUM_5G_20_TARGET_POWERS 8
17376 +#define AR9300_NUM_5G_40_TARGET_POWERS 8
17377 +#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
17378 +#define AR9300_NUM_2G_20_TARGET_POWERS 3
17379 +#define AR9300_NUM_2G_40_TARGET_POWERS 3
17380 +//#define AR9300_NUM_CTLS 21
17381 +#define AR9300_NUM_CTLS_5G 9
17382 +#define AR9300_NUM_CTLS_2G 12
17383 +#define AR9300_CTL_MODE_M 0xF
17384 +#define AR9300_NUM_BAND_EDGES_5G 8
17385 +#define AR9300_NUM_BAND_EDGES_2G 4
17386 +#define AR9300_NUM_PD_GAINS 4
17387 +#define AR9300_PD_GAINS_IN_MASK 4
17388 +#define AR9300_PD_GAIN_ICEPTS 5
17389 +#define AR9300_EEPROM_MODAL_SPURS 5
17390 +#define AR9300_MAX_RATE_POWER 63
17391 +#define AR9300_NUM_PDADC_VALUES 128
17392 +#define AR9300_NUM_RATES 16
17393 +#define AR9300_BCHAN_UNUSED 0xFF
17394 +#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
17395 +#define AR9300_OPFLAGS_11A 0x01
17396 +#define AR9300_OPFLAGS_11G 0x02
17397 +#define AR9300_OPFLAGS_5G_HT40 0x04
17398 +#define AR9300_OPFLAGS_2G_HT40 0x08
17399 +#define AR9300_OPFLAGS_5G_HT20 0x10
17400 +#define AR9300_OPFLAGS_2G_HT20 0x20
17401 +#define AR9300_EEPMISC_BIG_ENDIAN 0x01
17402 +#define AR9300_EEPMISC_WOW 0x02
17403 +#define AR9300_CUSTOMER_DATA_SIZE 20
17404 +
17405 +#define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
17406 +#define FBIN2FREQ(x,y) ((y) ? (2300 + x) : (4800 + 5 * x))
17407 +#define AR9300_MAX_CHAINS 3
17408 +#define AR9300_ANT_16S 25
17409 +#define AR9300_FUTURE_MODAL_SZ 6
17410 +
17411 +#define AR9300_NUM_ANT_CHAIN_FIELDS 7
17412 +#define AR9300_NUM_ANT_COMMON_FIELDS 4
17413 +#define AR9300_SIZE_ANT_CHAIN_FIELD 3
17414 +#define AR9300_SIZE_ANT_COMMON_FIELD 4
17415 +#define AR9300_ANT_CHAIN_MASK 0x7
17416 +#define AR9300_ANT_COMMON_MASK 0xf
17417 +#define AR9300_CHAIN_0_IDX 0
17418 +#define AR9300_CHAIN_1_IDX 1
17419 +#define AR9300_CHAIN_2_IDX 2
17420 +
17421 +#define AR928X_NUM_ANT_CHAIN_FIELDS 6
17422 +#define AR928X_SIZE_ANT_CHAIN_FIELD 2
17423 +#define AR928X_ANT_CHAIN_MASK 0x3
17424 +
17425 +/* Delta from which to start power to pdadc table */
17426 +/* This offset is used in both open loop and closed loop power control
17427 + * schemes. In open loop power control, it is not really needed, but for
17428 + * the "sake of consistency" it was kept. For certain AP designs, this
17429 + * value is overwritten by the value in the flag "pwrTableOffset" just
17430 + * before writing the pdadc vs pwr into the chip registers.
17431 + */
17432 +#define AR9300_PWR_TABLE_OFFSET 0
17433 +
17434 +/* enable flags for voltage and temp compensation */
17435 +#define ENABLE_TEMP_COMPENSATION 0x01
17436 +#define ENABLE_VOLT_COMPENSATION 0x02
17437 +/* byte addressable */
17438 +#define AR9300_EEPROM_SIZE 16*1024
17439 +#define FIXED_CCA_THRESHOLD 15
17440 +
17441 +#define AR9300_BASE_ADDR 0x3ff
17442 +
17443 +enum targetPowerHTRates {
17444 + HT_TARGET_RATE_0_8_16,
17445 + HT_TARGET_RATE_1_3_9_11_17_19,
17446 + HT_TARGET_RATE_4,
17447 + HT_TARGET_RATE_5,
17448 + HT_TARGET_RATE_6,
17449 + HT_TARGET_RATE_7,
17450 + HT_TARGET_RATE_12,
17451 + HT_TARGET_RATE_13,
17452 + HT_TARGET_RATE_14,
17453 + HT_TARGET_RATE_15,
17454 + HT_TARGET_RATE_20,
17455 + HT_TARGET_RATE_21,
17456 + HT_TARGET_RATE_22,
17457 + HT_TARGET_RATE_23
17458 +};
17459 +
17460 +enum targetPowerLegacyRates {
17461 + LEGACY_TARGET_RATE_6_24,
17462 + LEGACY_TARGET_RATE_36,
17463 + LEGACY_TARGET_RATE_48,
17464 + LEGACY_TARGET_RATE_54
17465 +};
17466 +
17467 +enum targetPowerCckRates {
17468 + LEGACY_TARGET_RATE_1L_5L,
17469 + LEGACY_TARGET_RATE_5S,
17470 + LEGACY_TARGET_RATE_11L,
17471 + LEGACY_TARGET_RATE_11S
17472 +};
17473 +
17474 +enum ar9300_Rates {
17475 + ALL_TARGET_LEGACY_6_24,
17476 + ALL_TARGET_LEGACY_36,
17477 + ALL_TARGET_LEGACY_48,
17478 + ALL_TARGET_LEGACY_54,
17479 + ALL_TARGET_LEGACY_1L_5L,
17480 + ALL_TARGET_LEGACY_5S,
17481 + ALL_TARGET_LEGACY_11L,
17482 + ALL_TARGET_LEGACY_11S,
17483 + ALL_TARGET_HT20_0_8_16,
17484 + ALL_TARGET_HT20_1_3_9_11_17_19,
17485 + ALL_TARGET_HT20_4,
17486 + ALL_TARGET_HT20_5,
17487 + ALL_TARGET_HT20_6,
17488 + ALL_TARGET_HT20_7,
17489 + ALL_TARGET_HT20_12,
17490 + ALL_TARGET_HT20_13,
17491 + ALL_TARGET_HT20_14,
17492 + ALL_TARGET_HT20_15,
17493 + ALL_TARGET_HT20_20,
17494 + ALL_TARGET_HT20_21,
17495 + ALL_TARGET_HT20_22,
17496 + ALL_TARGET_HT20_23,
17497 + ALL_TARGET_HT40_0_8_16,
17498 + ALL_TARGET_HT40_1_3_9_11_17_19,
17499 + ALL_TARGET_HT40_4,
17500 + ALL_TARGET_HT40_5,
17501 + ALL_TARGET_HT40_6,
17502 + ALL_TARGET_HT40_7,
17503 + ALL_TARGET_HT40_12,
17504 + ALL_TARGET_HT40_13,
17505 + ALL_TARGET_HT40_14,
17506 + ALL_TARGET_HT40_15,
17507 + ALL_TARGET_HT40_20,
17508 + ALL_TARGET_HT40_21,
17509 + ALL_TARGET_HT40_22,
17510 + ALL_TARGET_HT40_23,
17511 + ar9300RateSize,
17512 +};
17513 +
17514 +
17515 +struct eepFlags {
17516 + u8 opFlags;
17517 + u8 eepMisc;
17518 +} __packed;
17519 +
17520 +enum CompressAlgorithm {
17521 + _CompressNone = 0,
17522 + _CompressLzma,
17523 + _CompressPairs,
17524 + _CompressBlock,
17525 + _Compress4,
17526 + _Compress5,
17527 + _Compress6,
17528 + _Compress7,
17529 +};
17530 +
17531 +struct ar9300_base_eep_hdr {
17532 + u16 regDmn[2];
17533 + /* 4 bits tx and 4 bits rx */
17534 + u8 txrxMask;
17535 + struct eepFlags opCapFlags;
17536 + u8 rfSilent;
17537 + u8 blueToothOptions;
17538 + u8 deviceCap;
17539 + /* takes lower byte in eeprom location */
17540 + u8 deviceType;
17541 + /* offset in dB to be added to beginning
17542 + * of pdadc table in calibration
17543 + */
17544 + int8_t pwrTableOffset;
17545 + u8 params_for_tuning_caps[2];
17546 + /*
17547 + * bit0 - enable tx temp comp
17548 + * bit1 - enable tx volt comp
17549 + * bit2 - enable fastClock - default to 1
17550 + * bit3 - enable doubling - default to 1
17551 + * bit4 - enable internal regulator - default to 1
17552 + */
17553 + u8 featureEnable;
17554 + /* misc flags: bit0 - turn down drivestrength */
17555 + u8 miscConfiguration;
17556 + u8 eepromWriteEnableGpio;
17557 + u8 wlanDisableGpio;
17558 + u8 wlanLedGpio;
17559 + u8 rxBandSelectGpio;
17560 + u8 txrxgain;
17561 + /* SW controlled internal regulator fields */
17562 + u32 swreg;
17563 +} __packed;
17564 +
17565 +struct ar9300_modal_eep_header {
17566 + /* 4 idle, t1, t2, b (4 bits per setting) */
17567 + u32 antCtrlCommon;
17568 + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
17569 + u32 antCtrlCommon2;
17570 + /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
17571 + u16 antCtrlChain[AR9300_MAX_CHAINS];
17572 + /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
17573 + u8 xatten1DB[AR9300_MAX_CHAINS];
17574 + /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
17575 + u8 xatten1Margin[AR9300_MAX_CHAINS];
17576 + int8_t tempSlope;
17577 + int8_t voltSlope;
17578 + /* spur channels in usual fbin coding format */
17579 + u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
17580 + /* 3 Check if the register is per chain */
17581 + int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
17582 + u8 ob[AR9300_MAX_CHAINS];
17583 + u8 db_stage2[AR9300_MAX_CHAINS];
17584 + u8 db_stage3[AR9300_MAX_CHAINS];
17585 + u8 db_stage4[AR9300_MAX_CHAINS];
17586 + u8 xpaBiasLvl;
17587 + u8 txFrameToDataStart;
17588 + u8 txFrameToPaOn;
17589 + u8 txClip;
17590 + int8_t antennaGain;
17591 + u8 switchSettling;
17592 + int8_t adcDesiredSize;
17593 + u8 txEndToXpaOff;
17594 + u8 txEndToRxOn;
17595 + u8 txFrameToXpaOn;
17596 + u8 thresh62;
17597 + u8 futureModal[32];
17598 +} __packed;
17599 +
17600 +struct ar9300_cal_data_per_freq_op_loop {
17601 + int8_t refPower;
17602 + /* pdadc voltage at power measurement */
17603 + u8 voltMeas;
17604 + /* pcdac used for power measurement */
17605 + u8 tempMeas;
17606 + /* range is -60 to -127 create a mapping equation 1db resolution */
17607 + int8_t rxNoisefloorCal;
17608 + /*range is same as noisefloor */
17609 + int8_t rxNoisefloorPower;
17610 + /* temp measured when noisefloor cal was performed */
17611 + u8 rxTempMeas;
17612 +} __packed;
17613 +
17614 +struct cal_tgt_pow_legacy {
17615 + u8 tPow2x[4];
17616 +} __packed;
17617 +
17618 +struct cal_tgt_pow_ht {
17619 + u8 tPow2x[14];
17620 +} __packed;
17621 +
17622 +struct cal_ctl_edge_pwr {
17623 + u8 tPower :6,
17624 + flag :2;
17625 +} __packed;
17626 +
17627 +struct cal_ctl_data_2g {
17628 + struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
17629 +} __packed;
17630 +
17631 +struct cal_ctl_data_5g {
17632 + struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
17633 +} __packed;
17634 +
17635 +struct ar9300_eeprom {
17636 + u8 eepromVersion;
17637 + u8 templateVersion;
17638 + u8 macAddr[6];
17639 + u8 custData[AR9300_CUSTOMER_DATA_SIZE];
17640 +
17641 + struct ar9300_base_eep_hdr baseEepHeader;
17642 +
17643 + struct ar9300_modal_eep_header modalHeader2G;
17644 + u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
17645 + struct ar9300_cal_data_per_freq_op_loop
17646 + calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
17647 + u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
17648 + u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
17649 + u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
17650 + u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
17651 + struct cal_tgt_pow_legacy
17652 + calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
17653 + struct cal_tgt_pow_legacy
17654 + calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
17655 + struct cal_tgt_pow_ht
17656 + calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
17657 + struct cal_tgt_pow_ht
17658 + calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
17659 + u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
17660 + u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
17661 + struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
17662 + struct ar9300_modal_eep_header modalHeader5G;
17663 + u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
17664 + struct ar9300_cal_data_per_freq_op_loop
17665 + calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
17666 + u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
17667 + u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
17668 + u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
17669 + struct cal_tgt_pow_legacy
17670 + calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
17671 + struct cal_tgt_pow_ht
17672 + calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
17673 + struct cal_tgt_pow_ht
17674 + calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
17675 + u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
17676 + u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
17677 + struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
17678 +} __packed;
17679 +
17680 +s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
17681 +s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
17682 +
17683 +#endif
17684 --- /dev/null
17685 +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
17686 @@ -0,0 +1,205 @@
17687 +/*
17688 + * Copyright (c) 2008-2010 Atheros Communications Inc.
17689 + *
17690 + * Permission to use, copy, modify, and/or distribute this software for any
17691 + * purpose with or without fee is hereby granted, provided that the above
17692 + * copyright notice and this permission notice appear in all copies.
17693 + *
17694 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17695 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17696 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17697 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17698 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17699 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17700 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17701 + */
17702 +
17703 +#include "hw.h"
17704 +#include "ar9003_initvals.h"
17705 +
17706 +/* General hardware code for the AR9003 hadware family */
17707 +
17708 +static bool ar9003_hw_macversion_supported(u32 macversion)
17709 +{
17710 + switch (macversion) {
17711 + case AR_SREV_VERSION_9300:
17712 + return true;
17713 + default:
17714 + break;
17715 + }
17716 + return false;
17717 +}
17718 +
17719 +/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
17720 +/*
17721 + * XXX: move TX/RX gain INI to its own init_mode_gain_regs after
17722 + * ensuring it does not affect hardware bring up
17723 + */
17724 +static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
17725 +{
17726 + /* mac */
17727 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
17728 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
17729 + ar9300_2p0_mac_core,
17730 + ARRAY_SIZE(ar9300_2p0_mac_core), 2);
17731 + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
17732 + ar9300_2p0_mac_postamble,
17733 + ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
17734 +
17735 + /* bb */
17736 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
17737 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
17738 + ar9300_2p0_baseband_core,
17739 + ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
17740 + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
17741 + ar9300_2p0_baseband_postamble,
17742 + ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
17743 +
17744 + /* radio */
17745 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
17746 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
17747 + ar9300_2p0_radio_core,
17748 + ARRAY_SIZE(ar9300_2p0_radio_core), 2);
17749 + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
17750 + ar9300_2p0_radio_postamble,
17751 + ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
17752 +
17753 + /* soc */
17754 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
17755 + ar9300_2p0_soc_preamble,
17756 + ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
17757 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
17758 + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
17759 + ar9300_2p0_soc_postamble,
17760 + ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
17761 +
17762 + /* rx/tx gain */
17763 + INIT_INI_ARRAY(&ah->iniModesRxGain,
17764 + ar9300Common_rx_gain_table_2p0,
17765 + ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
17766 + INIT_INI_ARRAY(&ah->iniModesTxGain,
17767 + ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
17768 + ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
17769 + 5);
17770 +
17771 + /* Load PCIE SERDES settings from INI */
17772 +
17773 + /* Awake Setting */
17774 +
17775 + INIT_INI_ARRAY(&ah->iniPcieSerdes,
17776 + ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
17777 + ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
17778 + 2);
17779 +
17780 + /* Sleep Setting */
17781 +
17782 + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
17783 + ar9300PciePhy_clkreq_enable_L1_2p0,
17784 + ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
17785 + 2);
17786 +
17787 + /* Fast clock modal settings */
17788 + INIT_INI_ARRAY(&ah->iniModesAdditional,
17789 + ar9300Modes_fast_clock_2p0,
17790 + ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
17791 + 3);
17792 +}
17793 +
17794 +static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
17795 +{
17796 + switch(ar9003_hw_get_tx_gain_idx(ah)) {
17797 + case 0:
17798 + default:
17799 + INIT_INI_ARRAY(&ah->iniModesTxGain,
17800 + ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
17801 + ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
17802 + 5);
17803 + break;
17804 + case 1:
17805 + INIT_INI_ARRAY(&ah->iniModesTxGain,
17806 + ar9300Modes_high_ob_db_tx_gain_table_2p0,
17807 + ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
17808 + 5);
17809 + break;
17810 + case 2:
17811 + INIT_INI_ARRAY(&ah->iniModesTxGain,
17812 + ar9300Modes_low_ob_db_tx_gain_table_2p0,
17813 + ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
17814 + 5);
17815 + break;
17816 + }
17817 +}
17818 +
17819 +static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
17820 +{
17821 + switch(ar9003_hw_get_rx_gain_idx(ah))
17822 + {
17823 + case 0:
17824 + default:
17825 + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0,
17826 + ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
17827 + 2);
17828 + break;
17829 + case 1:
17830 + INIT_INI_ARRAY(&ah->iniModesRxGain,
17831 + ar9300Common_wo_xlna_rx_gain_table_2p0,
17832 + ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
17833 + 2);
17834 + break;
17835 + }
17836 +}
17837 +
17838 +/* set gain table pointers according to values read from the eeprom */
17839 +static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
17840 +{
17841 + ar9003_tx_gain_table_apply(ah);
17842 + ar9003_rx_gain_table_apply(ah);
17843 +}
17844 +
17845 +/*
17846 + * Helper for ASPM support.
17847 + *
17848 + * Disable PLL when in L0s as well as receiver clock when in L1.
17849 + * This power saving option must be enabled through the SerDes.
17850 + *
17851 + * Programming the SerDes must go through the same 288 bit serial shift
17852 + * register as the other analog registers. Hence the 9 writes.
17853 + */
17854 +static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
17855 + int restore,
17856 + int power_off)
17857 +{
17858 + if (ah->is_pciexpress != true)
17859 + return;
17860 +
17861 + /* Do not touch SerDes registers */
17862 + if (ah->config.pcie_powersave_enable == 2)
17863 + return;
17864 +
17865 + /* Nothing to do on restore for 11N */
17866 + if (!restore) {
17867 + /* set bit 19 to allow forcing of pcie core into L1 state */
17868 + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
17869 +
17870 + /* Several PCIe massages to ensure proper behaviour */
17871 + if (ah->config.pcie_waen)
17872 + REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
17873 + }
17874 +}
17875 +
17876 +/* Sets up the AR9003 hardware familiy callbacks */
17877 +void ar9003_hw_attach_ops(struct ath_hw *ah)
17878 +{
17879 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
17880 + struct ath_hw_ops *ops = ath9k_hw_ops(ah);
17881 +
17882 + priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
17883 + priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
17884 + priv_ops->macversion_supported = ar9003_hw_macversion_supported;
17885 +
17886 + ops->config_pci_powersave = ar9003_hw_configpcipowersave;
17887 +
17888 + ar9003_hw_attach_phy_ops(ah);
17889 + ar9003_hw_attach_calib_ops(ah);
17890 + ar9003_hw_attach_mac_ops(ah);
17891 +}
17892 --- /dev/null
17893 +++ b/drivers/net/wireless/ath/ath9k/ar9003_initvals.h
17894 @@ -0,0 +1,1793 @@
17895 +/*
17896 + * Copyright (c) 2010 Atheros Communications Inc.
17897 + *
17898 + * Permission to use, copy, modify, and/or distribute this software for any
17899 + * purpose with or without fee is hereby granted, provided that the above
17900 + * copyright notice and this permission notice appear in all copies.
17901 + *
17902 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17903 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17904 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17905 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17906 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17907 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17908 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17909 + */
17910 +
17911 +#ifndef INITVALS_9003_H
17912 +#define INITVALS_9003_H
17913 +
17914 +/* AR9003 2.0 */
17915 +
17916 +static const u32 ar9300_2p0_radio_postamble[][5] = {
17917 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
17918 + {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
17919 + {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
17920 + {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
17921 + {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
17922 + {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
17923 + {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
17924 +};
17925 +
17926 +static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
17927 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
17928 + {0x0000a410, 0x000050da, 0x000050da, 0x000050da, 0x000050da},
17929 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
17930 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
17931 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
17932 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
17933 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
17934 + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
17935 + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
17936 + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
17937 + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
17938 + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
17939 + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
17940 + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
17941 + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
17942 + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
17943 + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
17944 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
17945 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
17946 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
17947 + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
17948 + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
17949 + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
17950 + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
17951 + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
17952 + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
17953 + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
17954 + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
17955 + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
17956 + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
17957 + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
17958 + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
17959 + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
17960 + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
17961 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
17962 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
17963 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
17964 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
17965 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
17966 + {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
17967 + {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
17968 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
17969 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
17970 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
17971 + {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
17972 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
17973 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
17974 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
17975 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
17976 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
17977 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
17978 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
17979 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
17980 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
17981 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
17982 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
17983 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
17984 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
17985 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
17986 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
17987 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
17988 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
17989 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
17990 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
17991 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
17992 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
17993 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
17994 + {0x00016048, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
17995 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
17996 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
17997 + {0x00016448, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
17998 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
17999 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
18000 + {0x00016848, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
18001 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18002 +};
18003 +
18004 +static const u32 ar9300Modes_fast_clock_2p0[][3] = {
18005 + /* Addr 5G_HT20 5G_HT40 */
18006 + {0x00001030, 0x00000268, 0x000004d0},
18007 + {0x00001070, 0x0000018c, 0x00000318},
18008 + {0x000010b0, 0x00000fd0, 0x00001fa0},
18009 + {0x00008014, 0x044c044c, 0x08980898},
18010 + {0x0000801c, 0x148ec02b, 0x148ec057},
18011 + {0x00008318, 0x000044c0, 0x00008980},
18012 + {0x00009e00, 0x03721821, 0x03721821},
18013 + {0x0000a230, 0x0000000b, 0x00000016},
18014 + {0x0000a254, 0x00000898, 0x00001130},
18015 +};
18016 +
18017 +static const u32 ar9300_2p0_radio_core[][2] = {
18018 + /* Addr allmodes */
18019 + {0x00016000, 0x36db6db6},
18020 + {0x00016004, 0x6db6db40},
18021 + {0x00016008, 0x73f00000},
18022 + {0x0001600c, 0x00000000},
18023 + {0x00016040, 0x7f80fff8},
18024 + {0x0001604c, 0x76d005b5},
18025 + {0x00016050, 0x556cf031},
18026 + {0x00016054, 0x43449440},
18027 + {0x00016058, 0x0c51c92c},
18028 + {0x0001605c, 0x3db7fffc},
18029 + {0x00016060, 0xfffffffc},
18030 + {0x00016064, 0x000f0278},
18031 + {0x0001606c, 0x6db60000},
18032 + {0x00016080, 0x00000000},
18033 + {0x00016084, 0x0e48048c},
18034 + {0x00016088, 0x54214514},
18035 + {0x0001608c, 0x119f481e},
18036 + {0x00016090, 0x24926490},
18037 + {0x00016098, 0xd2888888},
18038 + {0x000160a0, 0x0a108ffe},
18039 + {0x000160a4, 0x812fc370},
18040 + {0x000160a8, 0x423c8000},
18041 + {0x000160b4, 0x92480080},
18042 + {0x000160c0, 0x00adb6d0},
18043 + {0x000160c4, 0x6db6db60},
18044 + {0x000160c8, 0x6db6db6c},
18045 + {0x000160cc, 0x01e6c000},
18046 + {0x00016100, 0x3fffbe01},
18047 + {0x00016104, 0xfff80000},
18048 + {0x00016108, 0x00080010},
18049 + {0x00016140, 0x10804008},
18050 + {0x00016144, 0x02084080},
18051 + {0x00016148, 0x00000000},
18052 + {0x00016280, 0x058a0001},
18053 + {0x00016284, 0x3d840208},
18054 + {0x00016288, 0x01a20408},
18055 + {0x0001628c, 0x00038c07},
18056 + {0x00016290, 0x40000004},
18057 + {0x00016294, 0x458aa14f},
18058 + {0x00016380, 0x00000000},
18059 + {0x00016384, 0x00000000},
18060 + {0x00016388, 0x00800700},
18061 + {0x0001638c, 0x00800700},
18062 + {0x00016390, 0x00800700},
18063 + {0x00016394, 0x00000000},
18064 + {0x00016398, 0x00000000},
18065 + {0x0001639c, 0x00000000},
18066 + {0x000163a0, 0x00000001},
18067 + {0x000163a4, 0x00000001},
18068 + {0x000163a8, 0x00000000},
18069 + {0x000163ac, 0x00000000},
18070 + {0x000163b0, 0x00000000},
18071 + {0x000163b4, 0x00000000},
18072 + {0x000163b8, 0x00000000},
18073 + {0x000163bc, 0x00000000},
18074 + {0x000163c0, 0x000000a0},
18075 + {0x000163c4, 0x000c0000},
18076 + {0x000163c8, 0x14021402},
18077 + {0x000163cc, 0x00001402},
18078 + {0x000163d0, 0x00000000},
18079 + {0x000163d4, 0x00000000},
18080 + {0x00016400, 0x36db6db6},
18081 + {0x00016404, 0x6db6db40},
18082 + {0x00016408, 0x73f00000},
18083 + {0x0001640c, 0x00000000},
18084 + {0x00016440, 0x7f80fff8},
18085 + {0x0001644c, 0x76d005b5},
18086 + {0x00016450, 0x556cf031},
18087 + {0x00016454, 0x43449440},
18088 + {0x00016458, 0x0c51c92c},
18089 + {0x0001645c, 0x3db7fffc},
18090 + {0x00016460, 0xfffffffc},
18091 + {0x00016464, 0x000f0278},
18092 + {0x0001646c, 0x6db60000},
18093 + {0x00016500, 0x3fffbe01},
18094 + {0x00016504, 0xfff80000},
18095 + {0x00016508, 0x00080010},
18096 + {0x00016540, 0x10804008},
18097 + {0x00016544, 0x02084080},
18098 + {0x00016548, 0x00000000},
18099 + {0x00016780, 0x00000000},
18100 + {0x00016784, 0x00000000},
18101 + {0x00016788, 0x00800700},
18102 + {0x0001678c, 0x00800700},
18103 + {0x00016790, 0x00800700},
18104 + {0x00016794, 0x00000000},
18105 + {0x00016798, 0x00000000},
18106 + {0x0001679c, 0x00000000},
18107 + {0x000167a0, 0x00000001},
18108 + {0x000167a4, 0x00000001},
18109 + {0x000167a8, 0x00000000},
18110 + {0x000167ac, 0x00000000},
18111 + {0x000167b0, 0x00000000},
18112 + {0x000167b4, 0x00000000},
18113 + {0x000167b8, 0x00000000},
18114 + {0x000167bc, 0x00000000},
18115 + {0x000167c0, 0x000000a0},
18116 + {0x000167c4, 0x000c0000},
18117 + {0x000167c8, 0x14021402},
18118 + {0x000167cc, 0x00001402},
18119 + {0x000167d0, 0x00000000},
18120 + {0x000167d4, 0x00000000},
18121 + {0x00016800, 0x36db6db6},
18122 + {0x00016804, 0x6db6db40},
18123 + {0x00016808, 0x73f00000},
18124 + {0x0001680c, 0x00000000},
18125 + {0x00016840, 0x7f80fff8},
18126 + {0x0001684c, 0x76d005b5},
18127 + {0x00016850, 0x556cf031},
18128 + {0x00016854, 0x43449440},
18129 + {0x00016858, 0x0c51c92c},
18130 + {0x0001685c, 0x3db7fffc},
18131 + {0x00016860, 0xfffffffc},
18132 + {0x00016864, 0x000f0278},
18133 + {0x0001686c, 0x6db60000},
18134 + {0x00016900, 0x3fffbe01},
18135 + {0x00016904, 0xfff80000},
18136 + {0x00016908, 0x00080010},
18137 + {0x00016940, 0x10804008},
18138 + {0x00016944, 0x02084080},
18139 + {0x00016948, 0x00000000},
18140 + {0x00016b80, 0x00000000},
18141 + {0x00016b84, 0x00000000},
18142 + {0x00016b88, 0x00800700},
18143 + {0x00016b8c, 0x00800700},
18144 + {0x00016b90, 0x00800700},
18145 + {0x00016b94, 0x00000000},
18146 + {0x00016b98, 0x00000000},
18147 + {0x00016b9c, 0x00000000},
18148 + {0x00016ba0, 0x00000001},
18149 + {0x00016ba4, 0x00000001},
18150 + {0x00016ba8, 0x00000000},
18151 + {0x00016bac, 0x00000000},
18152 + {0x00016bb0, 0x00000000},
18153 + {0x00016bb4, 0x00000000},
18154 + {0x00016bb8, 0x00000000},
18155 + {0x00016bbc, 0x00000000},
18156 + {0x00016bc0, 0x000000a0},
18157 + {0x00016bc4, 0x000c0000},
18158 + {0x00016bc8, 0x14021402},
18159 + {0x00016bcc, 0x00001402},
18160 + {0x00016bd0, 0x00000000},
18161 + {0x00016bd4, 0x00000000},
18162 +};
18163 +
18164 +static const u32 ar9300Common_rx_gain_table_merlin_2p0[][2] = {
18165 + /* Addr allmodes */
18166 + {0x0000a000, 0x02000101},
18167 + {0x0000a004, 0x02000102},
18168 + {0x0000a008, 0x02000103},
18169 + {0x0000a00c, 0x02000104},
18170 + {0x0000a010, 0x02000200},
18171 + {0x0000a014, 0x02000201},
18172 + {0x0000a018, 0x02000202},
18173 + {0x0000a01c, 0x02000203},
18174 + {0x0000a020, 0x02000204},
18175 + {0x0000a024, 0x02000205},
18176 + {0x0000a028, 0x02000208},
18177 + {0x0000a02c, 0x02000302},
18178 + {0x0000a030, 0x02000303},
18179 + {0x0000a034, 0x02000304},
18180 + {0x0000a038, 0x02000400},
18181 + {0x0000a03c, 0x02010300},
18182 + {0x0000a040, 0x02010301},
18183 + {0x0000a044, 0x02010302},
18184 + {0x0000a048, 0x02000500},
18185 + {0x0000a04c, 0x02010400},
18186 + {0x0000a050, 0x02020300},
18187 + {0x0000a054, 0x02020301},
18188 + {0x0000a058, 0x02020302},
18189 + {0x0000a05c, 0x02020303},
18190 + {0x0000a060, 0x02020400},
18191 + {0x0000a064, 0x02030300},
18192 + {0x0000a068, 0x02030301},
18193 + {0x0000a06c, 0x02030302},
18194 + {0x0000a070, 0x02030303},
18195 + {0x0000a074, 0x02030400},
18196 + {0x0000a078, 0x02040300},
18197 + {0x0000a07c, 0x02040301},
18198 + {0x0000a080, 0x02040302},
18199 + {0x0000a084, 0x02040303},
18200 + {0x0000a088, 0x02030500},
18201 + {0x0000a08c, 0x02040400},
18202 + {0x0000a090, 0x02050203},
18203 + {0x0000a094, 0x02050204},
18204 + {0x0000a098, 0x02050205},
18205 + {0x0000a09c, 0x02040500},
18206 + {0x0000a0a0, 0x02050301},
18207 + {0x0000a0a4, 0x02050302},
18208 + {0x0000a0a8, 0x02050303},
18209 + {0x0000a0ac, 0x02050400},
18210 + {0x0000a0b0, 0x02050401},
18211 + {0x0000a0b4, 0x02050402},
18212 + {0x0000a0b8, 0x02050403},
18213 + {0x0000a0bc, 0x02050500},
18214 + {0x0000a0c0, 0x02050501},
18215 + {0x0000a0c4, 0x02050502},
18216 + {0x0000a0c8, 0x02050503},
18217 + {0x0000a0cc, 0x02050504},
18218 + {0x0000a0d0, 0x02050600},
18219 + {0x0000a0d4, 0x02050601},
18220 + {0x0000a0d8, 0x02050602},
18221 + {0x0000a0dc, 0x02050603},
18222 + {0x0000a0e0, 0x02050604},
18223 + {0x0000a0e4, 0x02050700},
18224 + {0x0000a0e8, 0x02050701},
18225 + {0x0000a0ec, 0x02050702},
18226 + {0x0000a0f0, 0x02050703},
18227 + {0x0000a0f4, 0x02050704},
18228 + {0x0000a0f8, 0x02050705},
18229 + {0x0000a0fc, 0x02050708},
18230 + {0x0000a100, 0x02050709},
18231 + {0x0000a104, 0x0205070a},
18232 + {0x0000a108, 0x0205070b},
18233 + {0x0000a10c, 0x0205070c},
18234 + {0x0000a110, 0x0205070d},
18235 + {0x0000a114, 0x02050710},
18236 + {0x0000a118, 0x02050711},
18237 + {0x0000a11c, 0x02050712},
18238 + {0x0000a120, 0x02050713},
18239 + {0x0000a124, 0x02050714},
18240 + {0x0000a128, 0x02050715},
18241 + {0x0000a12c, 0x02050730},
18242 + {0x0000a130, 0x02050731},
18243 + {0x0000a134, 0x02050732},
18244 + {0x0000a138, 0x02050733},
18245 + {0x0000a13c, 0x02050734},
18246 + {0x0000a140, 0x02050735},
18247 + {0x0000a144, 0x02050750},
18248 + {0x0000a148, 0x02050751},
18249 + {0x0000a14c, 0x02050752},
18250 + {0x0000a150, 0x02050753},
18251 + {0x0000a154, 0x02050754},
18252 + {0x0000a158, 0x02050755},
18253 + {0x0000a15c, 0x02050770},
18254 + {0x0000a160, 0x02050771},
18255 + {0x0000a164, 0x02050772},
18256 + {0x0000a168, 0x02050773},
18257 + {0x0000a16c, 0x02050774},
18258 + {0x0000a170, 0x02050775},
18259 + {0x0000a174, 0x00000776},
18260 + {0x0000a178, 0x00000776},
18261 + {0x0000a17c, 0x00000776},
18262 + {0x0000a180, 0x00000776},
18263 + {0x0000a184, 0x00000776},
18264 + {0x0000a188, 0x00000776},
18265 + {0x0000a18c, 0x00000776},
18266 + {0x0000a190, 0x00000776},
18267 + {0x0000a194, 0x00000776},
18268 + {0x0000a198, 0x00000776},
18269 + {0x0000a19c, 0x00000776},
18270 + {0x0000a1a0, 0x00000776},
18271 + {0x0000a1a4, 0x00000776},
18272 + {0x0000a1a8, 0x00000776},
18273 + {0x0000a1ac, 0x00000776},
18274 + {0x0000a1b0, 0x00000776},
18275 + {0x0000a1b4, 0x00000776},
18276 + {0x0000a1b8, 0x00000776},
18277 + {0x0000a1bc, 0x00000776},
18278 + {0x0000a1c0, 0x00000776},
18279 + {0x0000a1c4, 0x00000776},
18280 + {0x0000a1c8, 0x00000776},
18281 + {0x0000a1cc, 0x00000776},
18282 + {0x0000a1d0, 0x00000776},
18283 + {0x0000a1d4, 0x00000776},
18284 + {0x0000a1d8, 0x00000776},
18285 + {0x0000a1dc, 0x00000776},
18286 + {0x0000a1e0, 0x00000776},
18287 + {0x0000a1e4, 0x00000776},
18288 + {0x0000a1e8, 0x00000776},
18289 + {0x0000a1ec, 0x00000776},
18290 + {0x0000a1f0, 0x00000776},
18291 + {0x0000a1f4, 0x00000776},
18292 + {0x0000a1f8, 0x00000776},
18293 + {0x0000a1fc, 0x00000776},
18294 + {0x0000b000, 0x02000101},
18295 + {0x0000b004, 0x02000102},
18296 + {0x0000b008, 0x02000103},
18297 + {0x0000b00c, 0x02000104},
18298 + {0x0000b010, 0x02000200},
18299 + {0x0000b014, 0x02000201},
18300 + {0x0000b018, 0x02000202},
18301 + {0x0000b01c, 0x02000203},
18302 + {0x0000b020, 0x02000204},
18303 + {0x0000b024, 0x02000205},
18304 + {0x0000b028, 0x02000208},
18305 + {0x0000b02c, 0x02000302},
18306 + {0x0000b030, 0x02000303},
18307 + {0x0000b034, 0x02000304},
18308 + {0x0000b038, 0x02000400},
18309 + {0x0000b03c, 0x02010300},
18310 + {0x0000b040, 0x02010301},
18311 + {0x0000b044, 0x02010302},
18312 + {0x0000b048, 0x02000500},
18313 + {0x0000b04c, 0x02010400},
18314 + {0x0000b050, 0x02020300},
18315 + {0x0000b054, 0x02020301},
18316 + {0x0000b058, 0x02020302},
18317 + {0x0000b05c, 0x02020303},
18318 + {0x0000b060, 0x02020400},
18319 + {0x0000b064, 0x02030300},
18320 + {0x0000b068, 0x02030301},
18321 + {0x0000b06c, 0x02030302},
18322 + {0x0000b070, 0x02030303},
18323 + {0x0000b074, 0x02030400},
18324 + {0x0000b078, 0x02040300},
18325 + {0x0000b07c, 0x02040301},
18326 + {0x0000b080, 0x02040302},
18327 + {0x0000b084, 0x02040303},
18328 + {0x0000b088, 0x02030500},
18329 + {0x0000b08c, 0x02040400},
18330 + {0x0000b090, 0x02050203},
18331 + {0x0000b094, 0x02050204},
18332 + {0x0000b098, 0x02050205},
18333 + {0x0000b09c, 0x02040500},
18334 + {0x0000b0a0, 0x02050301},
18335 + {0x0000b0a4, 0x02050302},
18336 + {0x0000b0a8, 0x02050303},
18337 + {0x0000b0ac, 0x02050400},
18338 + {0x0000b0b0, 0x02050401},
18339 + {0x0000b0b4, 0x02050402},
18340 + {0x0000b0b8, 0x02050403},
18341 + {0x0000b0bc, 0x02050500},
18342 + {0x0000b0c0, 0x02050501},
18343 + {0x0000b0c4, 0x02050502},
18344 + {0x0000b0c8, 0x02050503},
18345 + {0x0000b0cc, 0x02050504},
18346 + {0x0000b0d0, 0x02050600},
18347 + {0x0000b0d4, 0x02050601},
18348 + {0x0000b0d8, 0x02050602},
18349 + {0x0000b0dc, 0x02050603},
18350 + {0x0000b0e0, 0x02050604},
18351 + {0x0000b0e4, 0x02050700},
18352 + {0x0000b0e8, 0x02050701},
18353 + {0x0000b0ec, 0x02050702},
18354 + {0x0000b0f0, 0x02050703},
18355 + {0x0000b0f4, 0x02050704},
18356 + {0x0000b0f8, 0x02050705},
18357 + {0x0000b0fc, 0x02050708},
18358 + {0x0000b100, 0x02050709},
18359 + {0x0000b104, 0x0205070a},
18360 + {0x0000b108, 0x0205070b},
18361 + {0x0000b10c, 0x0205070c},
18362 + {0x0000b110, 0x0205070d},
18363 + {0x0000b114, 0x02050710},
18364 + {0x0000b118, 0x02050711},
18365 + {0x0000b11c, 0x02050712},
18366 + {0x0000b120, 0x02050713},
18367 + {0x0000b124, 0x02050714},
18368 + {0x0000b128, 0x02050715},
18369 + {0x0000b12c, 0x02050730},
18370 + {0x0000b130, 0x02050731},
18371 + {0x0000b134, 0x02050732},
18372 + {0x0000b138, 0x02050733},
18373 + {0x0000b13c, 0x02050734},
18374 + {0x0000b140, 0x02050735},
18375 + {0x0000b144, 0x02050750},
18376 + {0x0000b148, 0x02050751},
18377 + {0x0000b14c, 0x02050752},
18378 + {0x0000b150, 0x02050753},
18379 + {0x0000b154, 0x02050754},
18380 + {0x0000b158, 0x02050755},
18381 + {0x0000b15c, 0x02050770},
18382 + {0x0000b160, 0x02050771},
18383 + {0x0000b164, 0x02050772},
18384 + {0x0000b168, 0x02050773},
18385 + {0x0000b16c, 0x02050774},
18386 + {0x0000b170, 0x02050775},
18387 + {0x0000b174, 0x00000776},
18388 + {0x0000b178, 0x00000776},
18389 + {0x0000b17c, 0x00000776},
18390 + {0x0000b180, 0x00000776},
18391 + {0x0000b184, 0x00000776},
18392 + {0x0000b188, 0x00000776},
18393 + {0x0000b18c, 0x00000776},
18394 + {0x0000b190, 0x00000776},
18395 + {0x0000b194, 0x00000776},
18396 + {0x0000b198, 0x00000776},
18397 + {0x0000b19c, 0x00000776},
18398 + {0x0000b1a0, 0x00000776},
18399 + {0x0000b1a4, 0x00000776},
18400 + {0x0000b1a8, 0x00000776},
18401 + {0x0000b1ac, 0x00000776},
18402 + {0x0000b1b0, 0x00000776},
18403 + {0x0000b1b4, 0x00000776},
18404 + {0x0000b1b8, 0x00000776},
18405 + {0x0000b1bc, 0x00000776},
18406 + {0x0000b1c0, 0x00000776},
18407 + {0x0000b1c4, 0x00000776},
18408 + {0x0000b1c8, 0x00000776},
18409 + {0x0000b1cc, 0x00000776},
18410 + {0x0000b1d0, 0x00000776},
18411 + {0x0000b1d4, 0x00000776},
18412 + {0x0000b1d8, 0x00000776},
18413 + {0x0000b1dc, 0x00000776},
18414 + {0x0000b1e0, 0x00000776},
18415 + {0x0000b1e4, 0x00000776},
18416 + {0x0000b1e8, 0x00000776},
18417 + {0x0000b1ec, 0x00000776},
18418 + {0x0000b1f0, 0x00000776},
18419 + {0x0000b1f4, 0x00000776},
18420 + {0x0000b1f8, 0x00000776},
18421 + {0x0000b1fc, 0x00000776},
18422 +};
18423 +
18424 +static const u32 ar9300_2p0_mac_postamble[][5] = {
18425 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18426 + {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
18427 + {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
18428 + {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
18429 + {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
18430 + {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
18431 + {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
18432 + {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
18433 + {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
18434 +};
18435 +
18436 +static const u32 ar9300_2p0_soc_postamble[][5] = {
18437 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18438 + {0x00007010, 0x00000023, 0x00000023, 0x00000022, 0x00000022},
18439 +};
18440 +
18441 +static const u32 ar9200_merlin_2p0_radio_core[][2] = {
18442 + /* Addr common */
18443 + {0x00007800, 0x00040000},
18444 + {0x00007804, 0xdb005012},
18445 + {0x00007808, 0x04924914},
18446 + {0x0000780c, 0x21084210},
18447 + {0x00007810, 0x6d801300},
18448 + {0x00007814, 0x0019beff},
18449 + {0x00007818, 0x07e41000},
18450 + {0x0000781c, 0x00392000},
18451 + {0x00007820, 0x92592480},
18452 + {0x00007824, 0x00040000},
18453 + {0x00007828, 0xdb005012},
18454 + {0x0000782c, 0x04924914},
18455 + {0x00007830, 0x21084210},
18456 + {0x00007834, 0x6d801300},
18457 + {0x00007838, 0x0019beff},
18458 + {0x0000783c, 0x07e40000},
18459 + {0x00007840, 0x00392000},
18460 + {0x00007844, 0x92592480},
18461 + {0x00007848, 0x00100000},
18462 + {0x0000784c, 0x773f0567},
18463 + {0x00007850, 0x54214514},
18464 + {0x00007854, 0x12035828},
18465 + {0x00007858, 0x92592692},
18466 + {0x0000785c, 0x00000000},
18467 + {0x00007860, 0x56400000},
18468 + {0x00007864, 0x0a8e370e},
18469 + {0x00007868, 0xc0102850},
18470 + {0x0000786c, 0x812d4000},
18471 + {0x00007870, 0x807ec400},
18472 + {0x00007874, 0x001b6db0},
18473 + {0x00007878, 0x00376b63},
18474 + {0x0000787c, 0x06db6db6},
18475 + {0x00007880, 0x006d8000},
18476 + {0x00007884, 0xffeffffe},
18477 + {0x00007888, 0xffeffffe},
18478 + {0x0000788c, 0x00010000},
18479 + {0x00007890, 0x02060aeb},
18480 + {0x00007894, 0x5a108000},
18481 +};
18482 +
18483 +static const u32 ar9300_2p0_baseband_postamble[][5] = {
18484 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18485 + {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
18486 + {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
18487 + {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
18488 + {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
18489 + {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
18490 + {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
18491 + {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044},
18492 + {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
18493 + {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
18494 + {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
18495 + {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
18496 + {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
18497 + {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
18498 + {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
18499 + {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
18500 + {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
18501 + {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
18502 + {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
18503 + {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
18504 + {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
18505 + {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
18506 + {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
18507 + {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
18508 + {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
18509 + {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
18510 + {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
18511 + {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
18512 + {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
18513 + {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
18514 + {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
18515 + {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
18516 + {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
18517 + {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
18518 + {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
18519 + {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
18520 + {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
18521 + {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
18522 + {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
18523 + {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
18524 + {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
18525 + {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
18526 + {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
18527 + {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
18528 + {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
18529 + {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
18530 + {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
18531 + {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
18532 + {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
18533 + {0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
18534 +};
18535 +
18536 +static const u32 ar9300_2p0_baseband_core[][2] = {
18537 + /* Addr allmodes */
18538 + {0x00009800, 0xafe68e30},
18539 + {0x00009804, 0xfd14e000},
18540 + {0x00009808, 0x9c0a9f6b},
18541 + {0x0000980c, 0x04900000},
18542 + {0x00009814, 0x9280c00a},
18543 + {0x00009818, 0x00000000},
18544 + {0x0000981c, 0x00020028},
18545 + {0x00009834, 0x5f3ca3de},
18546 + {0x00009838, 0x0108ecff},
18547 + {0x0000983c, 0x14750600},
18548 + {0x00009880, 0x201fff00},
18549 + {0x00009884, 0x00001042},
18550 + {0x000098a4, 0x00200400},
18551 + {0x000098b0, 0x52440bbe},
18552 + {0x000098d0, 0x004b6a8e},
18553 + {0x000098d4, 0x00000820},
18554 + {0x000098dc, 0x00000000},
18555 + {0x000098f0, 0x00000000},
18556 + {0x000098f4, 0x00000000},
18557 + {0x00009c04, 0xff55ff55},
18558 + {0x00009c08, 0x0320ff55},
18559 + {0x00009c0c, 0x00000000},
18560 + {0x00009c10, 0x00000000},
18561 + {0x00009c14, 0x00046384},
18562 + {0x00009c18, 0x05b6b440},
18563 + {0x00009c1c, 0x00b6b440},
18564 + {0x00009d00, 0xc080a333},
18565 + {0x00009d04, 0x40206c10},
18566 + {0x00009d08, 0x009c4060},
18567 + {0x00009d0c, 0x9883800a},
18568 + {0x00009d10, 0x01834061},
18569 + {0x00009d14, 0x00c0040b},
18570 + {0x00009d18, 0x00000000},
18571 + {0x00009e08, 0x0038233c},
18572 + {0x00009e24, 0x990bb515},
18573 + {0x00009e28, 0x0c6f0000},
18574 + {0x00009e30, 0x06336f77},
18575 + {0x00009e34, 0x6af6532f},
18576 + {0x00009e38, 0x0cc80c00},
18577 + {0x00009e3c, 0xcf946222},
18578 + {0x00009e40, 0x0d261820},
18579 + {0x00009e4c, 0x00001004},
18580 + {0x00009e50, 0x00ff03f1},
18581 + {0x00009e54, 0x00000000},
18582 + {0x00009fc0, 0x803e4788},
18583 + {0x00009fc4, 0x0001efb5},
18584 + {0x00009fcc, 0x40000014},
18585 + {0x00009fd0, 0x01193b93},
18586 + {0x0000a20c, 0x00000000},
18587 + {0x0000a220, 0x00000000},
18588 + {0x0000a224, 0x00000000},
18589 + {0x0000a228, 0x10002310},
18590 + {0x0000a22c, 0x01036a1e},
18591 + {0x0000a234, 0x10000fff},
18592 + {0x0000a23c, 0x00000000},
18593 + {0x0000a244, 0x0c000000},
18594 + {0x0000a2a0, 0x00000001},
18595 + {0x0000a2c0, 0x00000001},
18596 + {0x0000a2c8, 0x00000000},
18597 + {0x0000a2cc, 0x18c43433},
18598 + {0x0000a2d4, 0x00000000},
18599 + {0x0000a2dc, 0x00000000},
18600 + {0x0000a2e0, 0x00000000},
18601 + {0x0000a2e4, 0x00000000},
18602 + {0x0000a2e8, 0x00000000},
18603 + {0x0000a2ec, 0x00000000},
18604 + {0x0000a2f0, 0x00000000},
18605 + {0x0000a2f4, 0x00000000},
18606 + {0x0000a2f8, 0x00000000},
18607 + {0x0000a344, 0x00000000},
18608 + {0x0000a34c, 0x00000000},
18609 + {0x0000a350, 0x0000a000},
18610 + {0x0000a364, 0x00000000},
18611 + {0x0000a370, 0x00000000},
18612 + {0x0000a390, 0x00000001},
18613 + {0x0000a394, 0x00000444},
18614 + {0x0000a398, 0x001f0e0f},
18615 + {0x0000a39c, 0x0075393f},
18616 + {0x0000a3a0, 0xb79f6427},
18617 + {0x0000a3a4, 0x00000000},
18618 + {0x0000a3a8, 0xaaaaaaaa},
18619 + {0x0000a3ac, 0x3c466478},
18620 + {0x0000a3c0, 0x20202020},
18621 + {0x0000a3c4, 0x22222220},
18622 + {0x0000a3c8, 0x20200020},
18623 + {0x0000a3cc, 0x20202020},
18624 + {0x0000a3d0, 0x20202020},
18625 + {0x0000a3d4, 0x20202020},
18626 + {0x0000a3d8, 0x20202020},
18627 + {0x0000a3dc, 0x20202020},
18628 + {0x0000a3e0, 0x20202020},
18629 + {0x0000a3e4, 0x20202020},
18630 + {0x0000a3e8, 0x20202020},
18631 + {0x0000a3ec, 0x20202020},
18632 + {0x0000a3f0, 0x00000000},
18633 + {0x0000a3f4, 0x00000246},
18634 + {0x0000a3f8, 0x0cdbd380},
18635 + {0x0000a3fc, 0x000f0f01},
18636 + {0x0000a400, 0x8fa91f01},
18637 + {0x0000a404, 0x00000000},
18638 + {0x0000a408, 0x0e79e5c6},
18639 + {0x0000a40c, 0x00820820},
18640 + {0x0000a414, 0x1ce739ce},
18641 + {0x0000a418, 0x7d001dce},
18642 + {0x0000a41c, 0x1ce739ce},
18643 + {0x0000a420, 0x000001ce},
18644 + {0x0000a424, 0x1ce739ce},
18645 + {0x0000a428, 0x000001ce},
18646 + {0x0000a42c, 0x1ce739ce},
18647 + {0x0000a430, 0x1ce739ce},
18648 + {0x0000a434, 0x00000000},
18649 + {0x0000a438, 0x00001801},
18650 + {0x0000a43c, 0x00000000},
18651 + {0x0000a440, 0x00000000},
18652 + {0x0000a444, 0x00000000},
18653 + {0x0000a448, 0x07000080},
18654 + {0x0000a44c, 0x00000001},
18655 + {0x0000a450, 0x00010000},
18656 + {0x0000a458, 0x00000000},
18657 + {0x0000a600, 0x00000000},
18658 + {0x0000a604, 0x00000000},
18659 + {0x0000a608, 0x00000000},
18660 + {0x0000a60c, 0x00000000},
18661 + {0x0000a610, 0x00000000},
18662 + {0x0000a614, 0x00000000},
18663 + {0x0000a618, 0x00000000},
18664 + {0x0000a61c, 0x00000000},
18665 + {0x0000a620, 0x00000000},
18666 + {0x0000a624, 0x00000000},
18667 + {0x0000a628, 0x00000000},
18668 + {0x0000a62c, 0x00000000},
18669 + {0x0000a630, 0x00000000},
18670 + {0x0000a634, 0x00000000},
18671 + {0x0000a638, 0x00000000},
18672 + {0x0000a63c, 0x00000000},
18673 + {0x0000a640, 0x00000000},
18674 + {0x0000a644, 0x3ffd9d74},
18675 + {0x0000a648, 0x0048060a},
18676 + {0x0000a64c, 0x00000637},
18677 + {0x0000a670, 0x03020100},
18678 + {0x0000a674, 0x09080504},
18679 + {0x0000a678, 0x0d0c0b0a},
18680 + {0x0000a67c, 0x13121110},
18681 + {0x0000a680, 0x31301514},
18682 + {0x0000a684, 0x35343332},
18683 + {0x0000a688, 0x00000036},
18684 + {0x0000a690, 0x00000838},
18685 + {0x0000a7c0, 0x00000000},
18686 + {0x0000a7c4, 0xfffffffc},
18687 + {0x0000a7c8, 0x00000000},
18688 + {0x0000a7cc, 0x00000000},
18689 + {0x0000a7d0, 0x00000000},
18690 + {0x0000a7d4, 0x00000004},
18691 + {0x0000a7dc, 0x00000001},
18692 + {0x0000a8d0, 0x004b6a8e},
18693 + {0x0000a8d4, 0x00000820},
18694 + {0x0000a8dc, 0x00000000},
18695 + {0x0000a8f0, 0x00000000},
18696 + {0x0000a8f4, 0x00000000},
18697 + {0x0000b2d0, 0x00000080},
18698 + {0x0000b2d4, 0x00000000},
18699 + {0x0000b2dc, 0x00000000},
18700 + {0x0000b2e0, 0x00000000},
18701 + {0x0000b2e4, 0x00000000},
18702 + {0x0000b2e8, 0x00000000},
18703 + {0x0000b2ec, 0x00000000},
18704 + {0x0000b2f0, 0x00000000},
18705 + {0x0000b2f4, 0x00000000},
18706 + {0x0000b2f8, 0x00000000},
18707 + {0x0000b408, 0x0e79e5c0},
18708 + {0x0000b40c, 0x00820820},
18709 + {0x0000b420, 0x00000000},
18710 + {0x0000b8d0, 0x004b6a8e},
18711 + {0x0000b8d4, 0x00000820},
18712 + {0x0000b8dc, 0x00000000},
18713 + {0x0000b8f0, 0x00000000},
18714 + {0x0000b8f4, 0x00000000},
18715 + {0x0000c2d0, 0x00000080},
18716 + {0x0000c2d4, 0x00000000},
18717 + {0x0000c2dc, 0x00000000},
18718 + {0x0000c2e0, 0x00000000},
18719 + {0x0000c2e4, 0x00000000},
18720 + {0x0000c2e8, 0x00000000},
18721 + {0x0000c2ec, 0x00000000},
18722 + {0x0000c2f0, 0x00000000},
18723 + {0x0000c2f4, 0x00000000},
18724 + {0x0000c2f8, 0x00000000},
18725 + {0x0000c408, 0x0e79e5c0},
18726 + {0x0000c40c, 0x00820820},
18727 + {0x0000c420, 0x00000000},
18728 +};
18729 +
18730 +static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
18731 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18732 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050da, 0x000050da},
18733 + {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
18734 + {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
18735 + {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
18736 + {0x0000a50c, 0x10022223, 0x10022223, 0x0b000200, 0x0b000200},
18737 + {0x0000a510, 0x17022620, 0x17022620, 0x0f000202, 0x0f000202},
18738 + {0x0000a514, 0x1b022622, 0x1b022622, 0x11000400, 0x11000400},
18739 + {0x0000a518, 0x1f022822, 0x1f022822, 0x15000402, 0x15000402},
18740 + {0x0000a51c, 0x24022842, 0x24022842, 0x19000404, 0x19000404},
18741 + {0x0000a520, 0x28042840, 0x28042840, 0x1b000603, 0x1b000603},
18742 + {0x0000a524, 0x2c042842, 0x2c042842, 0x1f000a02, 0x1f000a02},
18743 + {0x0000a528, 0x30042844, 0x30042844, 0x23000a04, 0x23000a04},
18744 + {0x0000a52c, 0x34042846, 0x34042846, 0x26000a20, 0x26000a20},
18745 + {0x0000a530, 0x39042869, 0x39042869, 0x2a000e20, 0x2a000e20},
18746 + {0x0000a534, 0x3d062869, 0x3d062869, 0x2e000e22, 0x2e000e22},
18747 + {0x0000a538, 0x44062c69, 0x44062c69, 0x31000e24, 0x31000e24},
18748 + {0x0000a53c, 0x48063069, 0x48063069, 0x34001640, 0x34001640},
18749 + {0x0000a540, 0x4c0a3065, 0x4c0a3065, 0x38001660, 0x38001660},
18750 + {0x0000a544, 0x500a3069, 0x500a3069, 0x3b001861, 0x3b001861},
18751 + {0x0000a548, 0x530a3469, 0x530a3469, 0x3e001a81, 0x3e001a81},
18752 + {0x0000a54c, 0x590a7464, 0x590a7464, 0x42001a83, 0x42001a83},
18753 + {0x0000a550, 0x5e0a7865, 0x5e0a7865, 0x44001c84, 0x44001c84},
18754 + {0x0000a554, 0x630a7e66, 0x630a7e66, 0x48001ce3, 0x48001ce3},
18755 + {0x0000a558, 0x680a7e89, 0x680a7e89, 0x4c001ce5, 0x4c001ce5},
18756 + {0x0000a55c, 0x6e0a7e8c, 0x6e0a7e8c, 0x50001ce9, 0x50001ce9},
18757 + {0x0000a560, 0x730e7e8c, 0x730e7e8c, 0x54001ceb, 0x54001ceb},
18758 + {0x0000a564, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18759 + {0x0000a568, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18760 + {0x0000a56c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18761 + {0x0000a570, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18762 + {0x0000a574, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18763 + {0x0000a578, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18764 + {0x0000a57c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18765 + {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
18766 + {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
18767 + {0x0000a588, 0x0b822220, 0x0b822220, 0x08800004, 0x08800004},
18768 + {0x0000a58c, 0x10822223, 0x10822223, 0x0b800200, 0x0b800200},
18769 + {0x0000a590, 0x17822620, 0x17822620, 0x0f800202, 0x0f800202},
18770 + {0x0000a594, 0x1b822622, 0x1b822622, 0x11800400, 0x11800400},
18771 + {0x0000a598, 0x1f822822, 0x1f822822, 0x15800402, 0x15800402},
18772 + {0x0000a59c, 0x24822842, 0x24822842, 0x19800404, 0x19800404},
18773 + {0x0000a5a0, 0x28842840, 0x28842840, 0x1b800603, 0x1b800603},
18774 + {0x0000a5a4, 0x2c842842, 0x2c842842, 0x1f800a02, 0x1f800a02},
18775 + {0x0000a5a8, 0x30842844, 0x30842844, 0x23800a04, 0x23800a04},
18776 + {0x0000a5ac, 0x34842846, 0x34842846, 0x26800a20, 0x26800a20},
18777 + {0x0000a5b0, 0x39842869, 0x39842869, 0x2a800e20, 0x2a800e20},
18778 + {0x0000a5b4, 0x3d862869, 0x3d862869, 0x2e800e22, 0x2e800e22},
18779 + {0x0000a5b8, 0x44862c69, 0x44862c69, 0x31800e24, 0x31800e24},
18780 + {0x0000a5bc, 0x48863069, 0x48863069, 0x34801640, 0x34801640},
18781 + {0x0000a5c0, 0x4c8a3065, 0x4c8a3065, 0x38801660, 0x38801660},
18782 + {0x0000a5c4, 0x508a3069, 0x508a3069, 0x3b801861, 0x3b801861},
18783 + {0x0000a5c8, 0x538a3469, 0x538a3469, 0x3e801a81, 0x3e801a81},
18784 + {0x0000a5cc, 0x598a7464, 0x598a7464, 0x42801a83, 0x42801a83},
18785 + {0x0000a5d0, 0x5e8a7865, 0x5e8a7865, 0x44801c84, 0x44801c84},
18786 + {0x0000a5d4, 0x638a7e66, 0x638a7e66, 0x48801ce3, 0x48801ce3},
18787 + {0x0000a5d8, 0x688a7e89, 0x688a7e89, 0x4c801ce5, 0x4c801ce5},
18788 + {0x0000a5dc, 0x6e8a7e8c, 0x6e8a7e8c, 0x50801ce9, 0x50801ce9},
18789 + {0x0000a5e0, 0x738e7e8c, 0x738e7e8c, 0x54801ceb, 0x54801ceb},
18790 + {0x0000a5e4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18791 + {0x0000a5e8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18792 + {0x0000a5ec, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18793 + {0x0000a5f0, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18794 + {0x0000a5f4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18795 + {0x0000a5f8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18796 + {0x0000a5fc, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18797 + {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
18798 + {0x00016048, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
18799 + {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
18800 + {0x00016444, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
18801 + {0x00016448, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
18802 + {0x00016468, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
18803 + {0x00016844, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
18804 + {0x00016848, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
18805 + {0x00016868, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
18806 +};
18807 +
18808 +static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
18809 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
18810 + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050da, 0x000050da},
18811 + {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
18812 + {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
18813 + {0x0000a508, 0x0b022220, 0x0b022220, 0x08000004, 0x08000004},
18814 + {0x0000a50c, 0x10022223, 0x10022223, 0x0b000200, 0x0b000200},
18815 + {0x0000a510, 0x17022620, 0x17022620, 0x0f000202, 0x0f000202},
18816 + {0x0000a514, 0x1b022622, 0x1b022622, 0x11000400, 0x11000400},
18817 + {0x0000a518, 0x1f022822, 0x1f022822, 0x15000402, 0x15000402},
18818 + {0x0000a51c, 0x24022842, 0x24022842, 0x19000404, 0x19000404},
18819 + {0x0000a520, 0x28042840, 0x28042840, 0x1b000603, 0x1b000603},
18820 + {0x0000a524, 0x2c042842, 0x2c042842, 0x1f000a02, 0x1f000a02},
18821 + {0x0000a528, 0x30042844, 0x30042844, 0x23000a04, 0x23000a04},
18822 + {0x0000a52c, 0x34042846, 0x34042846, 0x26000a20, 0x26000a20},
18823 + {0x0000a530, 0x39042869, 0x39042869, 0x2a000e20, 0x2a000e20},
18824 + {0x0000a534, 0x3d062869, 0x3d062869, 0x2e000e22, 0x2e000e22},
18825 + {0x0000a538, 0x44062c69, 0x44062c69, 0x31000e24, 0x31000e24},
18826 + {0x0000a53c, 0x48063069, 0x48063069, 0x34001640, 0x34001640},
18827 + {0x0000a540, 0x4c0a3065, 0x4c0a3065, 0x38001660, 0x38001660},
18828 + {0x0000a544, 0x500a3069, 0x500a3069, 0x3b001861, 0x3b001861},
18829 + {0x0000a548, 0x530a3469, 0x530a3469, 0x3e001a81, 0x3e001a81},
18830 + {0x0000a54c, 0x590a7464, 0x590a7464, 0x42001a83, 0x42001a83},
18831 + {0x0000a550, 0x5e0a7865, 0x5e0a7865, 0x44001c84, 0x44001c84},
18832 + {0x0000a554, 0x630a7e66, 0x630a7e66, 0x48001ce3, 0x48001ce3},
18833 + {0x0000a558, 0x680a7e89, 0x680a7e89, 0x4c001ce5, 0x4c001ce5},
18834 + {0x0000a55c, 0x6e0a7e8c, 0x6e0a7e8c, 0x50001ce9, 0x50001ce9},
18835 + {0x0000a560, 0x730e7e8c, 0x730e7e8c, 0x54001ceb, 0x54001ceb},
18836 + {0x0000a564, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18837 + {0x0000a568, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18838 + {0x0000a56c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18839 + {0x0000a570, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18840 + {0x0000a574, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18841 + {0x0000a578, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18842 + {0x0000a57c, 0x730e7e8c, 0x730e7e8c, 0x56001eec, 0x56001eec},
18843 + {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
18844 + {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
18845 + {0x0000a588, 0x0b822220, 0x0b822220, 0x08800004, 0x08800004},
18846 + {0x0000a58c, 0x10822223, 0x10822223, 0x0b800200, 0x0b800200},
18847 + {0x0000a590, 0x17822620, 0x17822620, 0x0f800202, 0x0f800202},
18848 + {0x0000a594, 0x1b822622, 0x1b822622, 0x11800400, 0x11800400},
18849 + {0x0000a598, 0x1f822822, 0x1f822822, 0x15800402, 0x15800402},
18850 + {0x0000a59c, 0x24822842, 0x24822842, 0x19800404, 0x19800404},
18851 + {0x0000a5a0, 0x28842840, 0x28842840, 0x1b800603, 0x1b800603},
18852 + {0x0000a5a4, 0x2c842842, 0x2c842842, 0x1f800a02, 0x1f800a02},
18853 + {0x0000a5a8, 0x30842844, 0x30842844, 0x23800a04, 0x23800a04},
18854 + {0x0000a5ac, 0x34842846, 0x34842846, 0x26800a20, 0x26800a20},
18855 + {0x0000a5b0, 0x39842869, 0x39842869, 0x2a800e20, 0x2a800e20},
18856 + {0x0000a5b4, 0x3d862869, 0x3d862869, 0x2e800e22, 0x2e800e22},
18857 + {0x0000a5b8, 0x44862c69, 0x44862c69, 0x31800e24, 0x31800e24},
18858 + {0x0000a5bc, 0x48863069, 0x48863069, 0x34801640, 0x34801640},
18859 + {0x0000a5c0, 0x4c8a3065, 0x4c8a3065, 0x38801660, 0x38801660},
18860 + {0x0000a5c4, 0x508a3069, 0x508a3069, 0x3b801861, 0x3b801861},
18861 + {0x0000a5c8, 0x538a3469, 0x538a3469, 0x3e801a81, 0x3e801a81},
18862 + {0x0000a5cc, 0x598a7464, 0x598a7464, 0x42801a83, 0x42801a83},
18863 + {0x0000a5d0, 0x5e8a7865, 0x5e8a7865, 0x44801c84, 0x44801c84},
18864 + {0x0000a5d4, 0x638a7e66, 0x638a7e66, 0x48801ce3, 0x48801ce3},
18865 + {0x0000a5d8, 0x688a7e89, 0x688a7e89, 0x4c801ce5, 0x4c801ce5},
18866 + {0x0000a5dc, 0x6e8a7e8c, 0x6e8a7e8c, 0x50801ce9, 0x50801ce9},
18867 + {0x0000a5e0, 0x738e7e8c, 0x738e7e8c, 0x54801ceb, 0x54801ceb},
18868 + {0x0000a5e4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18869 + {0x0000a5e8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18870 + {0x0000a5ec, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18871 + {0x0000a5f0, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18872 + {0x0000a5f4, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18873 + {0x0000a5f8, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18874 + {0x0000a5fc, 0x738e7e8c, 0x738e7e8c, 0x56801eec, 0x56801eec},
18875 + {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
18876 + {0x00016048, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
18877 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18878 + {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
18879 + {0x00016448, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
18880 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18881 + {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
18882 + {0x00016848, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
18883 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
18884 +};
18885 +
18886 +static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
18887 + /* Addr allmodes */
18888 + {0x0000a000, 0x00010000},
18889 + {0x0000a004, 0x00030002},
18890 + {0x0000a008, 0x00050004},
18891 + {0x0000a00c, 0x00810080},
18892 + {0x0000a010, 0x01800082},
18893 + {0x0000a014, 0x01820181},
18894 + {0x0000a018, 0x01840183},
18895 + {0x0000a01c, 0x01880185},
18896 + {0x0000a020, 0x018a0189},
18897 + {0x0000a024, 0x02850284},
18898 + {0x0000a028, 0x02890288},
18899 + {0x0000a02c, 0x028b028a},
18900 + {0x0000a030, 0x028d028c},
18901 + {0x0000a034, 0x02910290},
18902 + {0x0000a038, 0x02930292},
18903 + {0x0000a03c, 0x03910390},
18904 + {0x0000a040, 0x03930392},
18905 + {0x0000a044, 0x03950394},
18906 + {0x0000a048, 0x00000396},
18907 + {0x0000a04c, 0x00000000},
18908 + {0x0000a050, 0x00000000},
18909 + {0x0000a054, 0x00000000},
18910 + {0x0000a058, 0x00000000},
18911 + {0x0000a05c, 0x00000000},
18912 + {0x0000a060, 0x00000000},
18913 + {0x0000a064, 0x00000000},
18914 + {0x0000a068, 0x00000000},
18915 + {0x0000a06c, 0x00000000},
18916 + {0x0000a070, 0x00000000},
18917 + {0x0000a074, 0x00000000},
18918 + {0x0000a078, 0x00000000},
18919 + {0x0000a07c, 0x00000000},
18920 + {0x0000a080, 0x28282828},
18921 + {0x0000a084, 0x21212128},
18922 + {0x0000a088, 0x21212121},
18923 + {0x0000a08c, 0x1c1c1c21},
18924 + {0x0000a090, 0x1c1c1c1c},
18925 + {0x0000a094, 0x17171c1c},
18926 + {0x0000a098, 0x02020212},
18927 + {0x0000a09c, 0x02020202},
18928 + {0x0000a0a0, 0x00000000},
18929 + {0x0000a0a4, 0x00000000},
18930 + {0x0000a0a8, 0x00000000},
18931 + {0x0000a0ac, 0x00000000},
18932 + {0x0000a0b0, 0x00000000},
18933 + {0x0000a0b4, 0x00000000},
18934 + {0x0000a0b8, 0x00000000},
18935 + {0x0000a0bc, 0x00000000},
18936 + {0x0000a0c0, 0x001f0000},
18937 + {0x0000a0c4, 0x011f0100},
18938 + {0x0000a0c8, 0x011d011e},
18939 + {0x0000a0cc, 0x011b011c},
18940 + {0x0000a0d0, 0x02030204},
18941 + {0x0000a0d4, 0x02010202},
18942 + {0x0000a0d8, 0x021f0200},
18943 + {0x0000a0dc, 0x021d021e},
18944 + {0x0000a0e0, 0x03010302},
18945 + {0x0000a0e4, 0x031f0300},
18946 + {0x0000a0e8, 0x0402031e},
18947 + {0x0000a0ec, 0x04000401},
18948 + {0x0000a0f0, 0x041e041f},
18949 + {0x0000a0f4, 0x05010502},
18950 + {0x0000a0f8, 0x051f0500},
18951 + {0x0000a0fc, 0x0602051e},
18952 + {0x0000a100, 0x06000601},
18953 + {0x0000a104, 0x061e061f},
18954 + {0x0000a108, 0x0703061d},
18955 + {0x0000a10c, 0x07010702},
18956 + {0x0000a110, 0x00000700},
18957 + {0x0000a114, 0x00000000},
18958 + {0x0000a118, 0x00000000},
18959 + {0x0000a11c, 0x00000000},
18960 + {0x0000a120, 0x00000000},
18961 + {0x0000a124, 0x00000000},
18962 + {0x0000a128, 0x00000000},
18963 + {0x0000a12c, 0x00000000},
18964 + {0x0000a130, 0x00000000},
18965 + {0x0000a134, 0x00000000},
18966 + {0x0000a138, 0x00000000},
18967 + {0x0000a13c, 0x00000000},
18968 + {0x0000a140, 0x001f0000},
18969 + {0x0000a144, 0x011f0100},
18970 + {0x0000a148, 0x011d011e},
18971 + {0x0000a14c, 0x011b011c},
18972 + {0x0000a150, 0x02030204},
18973 + {0x0000a154, 0x02010202},
18974 + {0x0000a158, 0x021f0200},
18975 + {0x0000a15c, 0x021d021e},
18976 + {0x0000a160, 0x03010302},
18977 + {0x0000a164, 0x031f0300},
18978 + {0x0000a168, 0x0402031e},
18979 + {0x0000a16c, 0x04000401},
18980 + {0x0000a170, 0x041e041f},
18981 + {0x0000a174, 0x05010502},
18982 + {0x0000a178, 0x051f0500},
18983 + {0x0000a17c, 0x0602051e},
18984 + {0x0000a180, 0x06000601},
18985 + {0x0000a184, 0x061e061f},
18986 + {0x0000a188, 0x0703061d},
18987 + {0x0000a18c, 0x07010702},
18988 + {0x0000a190, 0x00000700},
18989 + {0x0000a194, 0x00000000},
18990 + {0x0000a198, 0x00000000},
18991 + {0x0000a19c, 0x00000000},
18992 + {0x0000a1a0, 0x00000000},
18993 + {0x0000a1a4, 0x00000000},
18994 + {0x0000a1a8, 0x00000000},
18995 + {0x0000a1ac, 0x00000000},
18996 + {0x0000a1b0, 0x00000000},
18997 + {0x0000a1b4, 0x00000000},
18998 + {0x0000a1b8, 0x00000000},
18999 + {0x0000a1bc, 0x00000000},
19000 + {0x0000a1c0, 0x00000000},
19001 + {0x0000a1c4, 0x00000000},
19002 + {0x0000a1c8, 0x00000000},
19003 + {0x0000a1cc, 0x00000000},
19004 + {0x0000a1d0, 0x00000000},
19005 + {0x0000a1d4, 0x00000000},
19006 + {0x0000a1d8, 0x00000000},
19007 + {0x0000a1dc, 0x00000000},
19008 + {0x0000a1e0, 0x00000000},
19009 + {0x0000a1e4, 0x00000000},
19010 + {0x0000a1e8, 0x00000000},
19011 + {0x0000a1ec, 0x00000000},
19012 + {0x0000a1f0, 0x00000396},
19013 + {0x0000a1f4, 0x00000396},
19014 + {0x0000a1f8, 0x00000396},
19015 + {0x0000a1fc, 0x00000196},
19016 + {0x0000b000, 0x00010000},
19017 + {0x0000b004, 0x00030002},
19018 + {0x0000b008, 0x00050004},
19019 + {0x0000b00c, 0x00810080},
19020 + {0x0000b010, 0x00830082},
19021 + {0x0000b014, 0x01810180},
19022 + {0x0000b018, 0x01830182},
19023 + {0x0000b01c, 0x01850184},
19024 + {0x0000b020, 0x02810280},
19025 + {0x0000b024, 0x02830282},
19026 + {0x0000b028, 0x02850284},
19027 + {0x0000b02c, 0x02890288},
19028 + {0x0000b030, 0x028b028a},
19029 + {0x0000b034, 0x0388028c},
19030 + {0x0000b038, 0x038a0389},
19031 + {0x0000b03c, 0x038c038b},
19032 + {0x0000b040, 0x0390038d},
19033 + {0x0000b044, 0x03920391},
19034 + {0x0000b048, 0x03940393},
19035 + {0x0000b04c, 0x03960395},
19036 + {0x0000b050, 0x00000000},
19037 + {0x0000b054, 0x00000000},
19038 + {0x0000b058, 0x00000000},
19039 + {0x0000b05c, 0x00000000},
19040 + {0x0000b060, 0x00000000},
19041 + {0x0000b064, 0x00000000},
19042 + {0x0000b068, 0x00000000},
19043 + {0x0000b06c, 0x00000000},
19044 + {0x0000b070, 0x00000000},
19045 + {0x0000b074, 0x00000000},
19046 + {0x0000b078, 0x00000000},
19047 + {0x0000b07c, 0x00000000},
19048 + {0x0000b080, 0x32323232},
19049 + {0x0000b084, 0x2f2f3232},
19050 + {0x0000b088, 0x23282a2d},
19051 + {0x0000b08c, 0x1c1e2123},
19052 + {0x0000b090, 0x14171919},
19053 + {0x0000b094, 0x0e0e1214},
19054 + {0x0000b098, 0x03050707},
19055 + {0x0000b09c, 0x00030303},
19056 + {0x0000b0a0, 0x00000000},
19057 + {0x0000b0a4, 0x00000000},
19058 + {0x0000b0a8, 0x00000000},
19059 + {0x0000b0ac, 0x00000000},
19060 + {0x0000b0b0, 0x00000000},
19061 + {0x0000b0b4, 0x00000000},
19062 + {0x0000b0b8, 0x00000000},
19063 + {0x0000b0bc, 0x00000000},
19064 + {0x0000b0c0, 0x003f0020},
19065 + {0x0000b0c4, 0x00400041},
19066 + {0x0000b0c8, 0x0140005f},
19067 + {0x0000b0cc, 0x0160015f},
19068 + {0x0000b0d0, 0x017e017f},
19069 + {0x0000b0d4, 0x02410242},
19070 + {0x0000b0d8, 0x025f0240},
19071 + {0x0000b0dc, 0x027f0260},
19072 + {0x0000b0e0, 0x0341027e},
19073 + {0x0000b0e4, 0x035f0340},
19074 + {0x0000b0e8, 0x037f0360},
19075 + {0x0000b0ec, 0x04400441},
19076 + {0x0000b0f0, 0x0460045f},
19077 + {0x0000b0f4, 0x0541047f},
19078 + {0x0000b0f8, 0x055f0540},
19079 + {0x0000b0fc, 0x057f0560},
19080 + {0x0000b100, 0x06400641},
19081 + {0x0000b104, 0x0660065f},
19082 + {0x0000b108, 0x067e067f},
19083 + {0x0000b10c, 0x07410742},
19084 + {0x0000b110, 0x075f0740},
19085 + {0x0000b114, 0x077f0760},
19086 + {0x0000b118, 0x07800781},
19087 + {0x0000b11c, 0x07a0079f},
19088 + {0x0000b120, 0x07c107bf},
19089 + {0x0000b124, 0x000007c0},
19090 + {0x0000b128, 0x00000000},
19091 + {0x0000b12c, 0x00000000},
19092 + {0x0000b130, 0x00000000},
19093 + {0x0000b134, 0x00000000},
19094 + {0x0000b138, 0x00000000},
19095 + {0x0000b13c, 0x00000000},
19096 + {0x0000b140, 0x003f0020},
19097 + {0x0000b144, 0x00400041},
19098 + {0x0000b148, 0x0140005f},
19099 + {0x0000b14c, 0x0160015f},
19100 + {0x0000b150, 0x017e017f},
19101 + {0x0000b154, 0x02410242},
19102 + {0x0000b158, 0x025f0240},
19103 + {0x0000b15c, 0x027f0260},
19104 + {0x0000b160, 0x0341027e},
19105 + {0x0000b164, 0x035f0340},
19106 + {0x0000b168, 0x037f0360},
19107 + {0x0000b16c, 0x04400441},
19108 + {0x0000b170, 0x0460045f},
19109 + {0x0000b174, 0x0541047f},
19110 + {0x0000b178, 0x055f0540},
19111 + {0x0000b17c, 0x057f0560},
19112 + {0x0000b180, 0x06400641},
19113 + {0x0000b184, 0x0660065f},
19114 + {0x0000b188, 0x067e067f},
19115 + {0x0000b18c, 0x07410742},
19116 + {0x0000b190, 0x075f0740},
19117 + {0x0000b194, 0x077f0760},
19118 + {0x0000b198, 0x07800781},
19119 + {0x0000b19c, 0x07a0079f},
19120 + {0x0000b1a0, 0x07c107bf},
19121 + {0x0000b1a4, 0x000007c0},
19122 + {0x0000b1a8, 0x00000000},
19123 + {0x0000b1ac, 0x00000000},
19124 + {0x0000b1b0, 0x00000000},
19125 + {0x0000b1b4, 0x00000000},
19126 + {0x0000b1b8, 0x00000000},
19127 + {0x0000b1bc, 0x00000000},
19128 + {0x0000b1c0, 0x00000000},
19129 + {0x0000b1c4, 0x00000000},
19130 + {0x0000b1c8, 0x00000000},
19131 + {0x0000b1cc, 0x00000000},
19132 + {0x0000b1d0, 0x00000000},
19133 + {0x0000b1d4, 0x00000000},
19134 + {0x0000b1d8, 0x00000000},
19135 + {0x0000b1dc, 0x00000000},
19136 + {0x0000b1e0, 0x00000000},
19137 + {0x0000b1e4, 0x00000000},
19138 + {0x0000b1e8, 0x00000000},
19139 + {0x0000b1ec, 0x00000000},
19140 + {0x0000b1f0, 0x00000396},
19141 + {0x0000b1f4, 0x00000396},
19142 + {0x0000b1f8, 0x00000396},
19143 + {0x0000b1fc, 0x00000196},
19144 +};
19145 +
19146 +static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
19147 + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
19148 + {0x0000a410, 0x000050da, 0x000050da, 0x000050da, 0x000050da},
19149 + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
19150 + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
19151 + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
19152 + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
19153 + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
19154 + {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
19155 + {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
19156 + {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
19157 + {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
19158 + {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
19159 + {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
19160 + {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
19161 + {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
19162 + {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
19163 + {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
19164 + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
19165 + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
19166 + {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
19167 + {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
19168 + {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
19169 + {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
19170 + {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
19171 + {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
19172 + {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
19173 + {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
19174 + {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19175 + {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19176 + {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19177 + {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19178 + {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19179 + {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19180 + {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
19181 + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
19182 + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
19183 + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
19184 + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
19185 + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
19186 + {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
19187 + {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
19188 + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
19189 + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
19190 + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
19191 + {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
19192 + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
19193 + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
19194 + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
19195 + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
19196 + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
19197 + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
19198 + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
19199 + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
19200 + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
19201 + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
19202 + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
19203 + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
19204 + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
19205 + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
19206 + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19207 + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19208 + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19209 + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19210 + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19211 + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19212 + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
19213 + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
19214 + {0x00016048, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
19215 + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
19216 + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
19217 + {0x00016448, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
19218 + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
19219 + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
19220 + {0x00016848, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
19221 + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
19222 +};
19223 +
19224 +static const u32 ar9300_2p0_mac_core[][2] = {
19225 + /* Addr allmodes */
19226 + {0x00000008, 0x00000000},
19227 + {0x00000030, 0x00020085},
19228 + {0x00000034, 0x00000005},
19229 + {0x00000040, 0x00000000},
19230 + {0x00000044, 0x00000000},
19231 + {0x00000048, 0x00000008},
19232 + {0x0000004c, 0x00000010},
19233 + {0x00000050, 0x00000000},
19234 + {0x00001040, 0x002ffc0f},
19235 + {0x00001044, 0x002ffc0f},
19236 + {0x00001048, 0x002ffc0f},
19237 + {0x0000104c, 0x002ffc0f},
19238 + {0x00001050, 0x002ffc0f},
19239 + {0x00001054, 0x002ffc0f},
19240 + {0x00001058, 0x002ffc0f},
19241 + {0x0000105c, 0x002ffc0f},
19242 + {0x00001060, 0x002ffc0f},
19243 + {0x00001064, 0x002ffc0f},
19244 + {0x000010f0, 0x00000100},
19245 + {0x00001270, 0x00000000},
19246 + {0x000012b0, 0x00000000},
19247 + {0x000012f0, 0x00000000},
19248 + {0x0000143c, 0x00000000},
19249 + {0x0000147c, 0x00000000},
19250 + {0x00008000, 0x00000000},
19251 + {0x00008004, 0x00000000},
19252 + {0x00008008, 0x00000000},
19253 + {0x0000800c, 0x00000000},
19254 + {0x00008018, 0x00000000},
19255 + {0x00008020, 0x00000000},
19256 + {0x00008038, 0x00000000},
19257 + {0x0000803c, 0x00000000},
19258 + {0x00008040, 0x00000000},
19259 + {0x00008044, 0x00000000},
19260 + {0x00008048, 0x00000000},
19261 + {0x0000804c, 0xffffffff},
19262 + {0x00008054, 0x00000000},
19263 + {0x00008058, 0x00000000},
19264 + {0x0000805c, 0x000fc78f},
19265 + {0x00008060, 0x0000000f},
19266 + {0x00008064, 0x00000000},
19267 + {0x00008070, 0x00000310},
19268 + {0x00008074, 0x00000020},
19269 + {0x00008078, 0x00000000},
19270 + {0x0000809c, 0x0000000f},
19271 + {0x000080a0, 0x00000000},
19272 + {0x000080a4, 0x02ff0000},
19273 + {0x000080a8, 0x0e070605},
19274 + {0x000080ac, 0x0000000d},
19275 + {0x000080b0, 0x00000000},
19276 + {0x000080b4, 0x00000000},
19277 + {0x000080b8, 0x00000000},
19278 + {0x000080bc, 0x00000000},
19279 + {0x000080c0, 0x2a800000},
19280 + {0x000080c4, 0x06900168},
19281 + {0x000080c8, 0x13881c20},
19282 + {0x000080cc, 0x01f40000},
19283 + {0x000080d0, 0x00252500},
19284 + {0x000080d4, 0x00a00000},
19285 + {0x000080d8, 0x00400000},
19286 + {0x000080dc, 0x00000000},
19287 + {0x000080e0, 0xffffffff},
19288 + {0x000080e4, 0x0000ffff},
19289 + {0x000080e8, 0x3f3f3f3f},
19290 + {0x000080ec, 0x00000000},
19291 + {0x000080f0, 0x00000000},
19292 + {0x000080f4, 0x00000000},
19293 + {0x000080fc, 0x00020000},
19294 + {0x00008100, 0x00000000},
19295 + {0x00008108, 0x00000052},
19296 + {0x0000810c, 0x00000000},
19297 + {0x00008110, 0x00000000},
19298 + {0x00008114, 0x000007ff},
19299 + {0x00008118, 0x000000aa},
19300 + {0x0000811c, 0x00003210},
19301 + {0x00008124, 0x00000000},
19302 + {0x00008128, 0x00000000},
19303 + {0x0000812c, 0x00000000},
19304 + {0x00008130, 0x00000000},
19305 + {0x00008134, 0x00000000},
19306 + {0x00008138, 0x00000000},
19307 + {0x0000813c, 0x0000ffff},
19308 + {0x00008144, 0xffffffff},
19309 + {0x00008168, 0x00000000},
19310 + {0x0000816c, 0x00000000},
19311 + {0x00008170, 0x18486200},
19312 + {0x00008174, 0x33332210},
19313 + {0x00008178, 0x00000000},
19314 + {0x0000817c, 0x00020000},
19315 + {0x000081c0, 0x00000000},
19316 + {0x000081c4, 0x33332210},
19317 + {0x000081c8, 0x00000000},
19318 + {0x000081cc, 0x00000000},
19319 + {0x000081d4, 0x00000000},
19320 + {0x000081ec, 0x00000000},
19321 + {0x000081f0, 0x00000000},
19322 + {0x000081f4, 0x00000000},
19323 + {0x000081f8, 0x00000000},
19324 + {0x000081fc, 0x00000000},
19325 + {0x00008240, 0x00100000},
19326 + {0x00008244, 0x0010f424},
19327 + {0x00008248, 0x00000800},
19328 + {0x0000824c, 0x0001e848},
19329 + {0x00008250, 0x00000000},
19330 + {0x00008254, 0x00000000},
19331 + {0x00008258, 0x00000000},
19332 + {0x0000825c, 0x40000000},
19333 + {0x00008260, 0x00080922},
19334 + {0x00008264, 0x98a00010},
19335 + {0x00008268, 0xffffffff},
19336 + {0x0000826c, 0x0000ffff},
19337 + {0x00008270, 0x00000000},
19338 + {0x00008274, 0x40000000},
19339 + {0x00008278, 0x003e4180},
19340 + {0x0000827c, 0x00000004},
19341 + {0x00008284, 0x0000002c},
19342 + {0x00008288, 0x0000002c},
19343 + {0x0000828c, 0x000000ff},
19344 + {0x00008294, 0x00000000},
19345 + {0x00008298, 0x00000000},
19346 + {0x0000829c, 0x00000000},
19347 + {0x00008300, 0x00000140},
19348 + {0x00008314, 0x00000000},
19349 + {0x0000831c, 0x0000010d},
19350 + {0x00008328, 0x00000000},
19351 + {0x0000832c, 0x00000007},
19352 + {0x00008330, 0x00000302},
19353 + {0x00008334, 0x00000700},
19354 + {0x00008338, 0x00ff0000},
19355 + {0x0000833c, 0x02400000},
19356 + {0x00008340, 0x000107ff},
19357 + {0x00008344, 0xaa48105b},
19358 + {0x00008348, 0x008f0000},
19359 + {0x0000835c, 0x00000000},
19360 + {0x00008360, 0xffffffff},
19361 + {0x00008364, 0xffffffff},
19362 + {0x00008368, 0x00000000},
19363 + {0x00008370, 0x00000000},
19364 + {0x00008374, 0x000000ff},
19365 + {0x00008378, 0x00000000},
19366 + {0x0000837c, 0x00000000},
19367 + {0x00008380, 0xffffffff},
19368 + {0x00008384, 0xffffffff},
19369 + {0x00008390, 0xffffffff},
19370 + {0x00008394, 0xffffffff},
19371 + {0x00008398, 0x00000000},
19372 + {0x0000839c, 0x00000000},
19373 + {0x000083a0, 0x00000000},
19374 + {0x000083a4, 0x0000fa14},
19375 + {0x000083a8, 0x000f0c00},
19376 + {0x000083ac, 0x33332210},
19377 + {0x000083b0, 0x33332210},
19378 + {0x000083b4, 0x33332210},
19379 + {0x000083b8, 0x33332210},
19380 + {0x000083bc, 0x00000000},
19381 + {0x000083c0, 0x00000000},
19382 + {0x000083c4, 0x00000000},
19383 + {0x000083c8, 0x00000000},
19384 + {0x000083cc, 0x00000200},
19385 + {0x000083d0, 0x000301ff},
19386 +};
19387 +
19388 +static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
19389 + /* Addr allmodes */
19390 + {0x0000a000, 0x00010000},
19391 + {0x0000a004, 0x00030002},
19392 + {0x0000a008, 0x00050004},
19393 + {0x0000a00c, 0x00810080},
19394 + {0x0000a010, 0x01800082},
19395 + {0x0000a014, 0x01820181},
19396 + {0x0000a018, 0x01840183},
19397 + {0x0000a01c, 0x01880185},
19398 + {0x0000a020, 0x018a0189},
19399 + {0x0000a024, 0x02850284},
19400 + {0x0000a028, 0x02890288},
19401 + {0x0000a02c, 0x03850384},
19402 + {0x0000a030, 0x03890388},
19403 + {0x0000a034, 0x038b038a},
19404 + {0x0000a038, 0x038d038c},
19405 + {0x0000a03c, 0x03910390},
19406 + {0x0000a040, 0x03930392},
19407 + {0x0000a044, 0x03950394},
19408 + {0x0000a048, 0x00000396},
19409 + {0x0000a04c, 0x00000000},
19410 + {0x0000a050, 0x00000000},
19411 + {0x0000a054, 0x00000000},
19412 + {0x0000a058, 0x00000000},
19413 + {0x0000a05c, 0x00000000},
19414 + {0x0000a060, 0x00000000},
19415 + {0x0000a064, 0x00000000},
19416 + {0x0000a068, 0x00000000},
19417 + {0x0000a06c, 0x00000000},
19418 + {0x0000a070, 0x00000000},
19419 + {0x0000a074, 0x00000000},
19420 + {0x0000a078, 0x00000000},
19421 + {0x0000a07c, 0x00000000},
19422 + {0x0000a080, 0x28282828},
19423 + {0x0000a084, 0x28282828},
19424 + {0x0000a088, 0x28282828},
19425 + {0x0000a08c, 0x28282828},
19426 + {0x0000a090, 0x28282828},
19427 + {0x0000a094, 0x21212128},
19428 + {0x0000a098, 0x171c1c1c},
19429 + {0x0000a09c, 0x02020212},
19430 + {0x0000a0a0, 0x00000202},
19431 + {0x0000a0a4, 0x00000000},
19432 + {0x0000a0a8, 0x00000000},
19433 + {0x0000a0ac, 0x00000000},
19434 + {0x0000a0b0, 0x00000000},
19435 + {0x0000a0b4, 0x00000000},
19436 + {0x0000a0b8, 0x00000000},
19437 + {0x0000a0bc, 0x00000000},
19438 + {0x0000a0c0, 0x001f0000},
19439 + {0x0000a0c4, 0x011f0100},
19440 + {0x0000a0c8, 0x011d011e},
19441 + {0x0000a0cc, 0x011b011c},
19442 + {0x0000a0d0, 0x02030204},
19443 + {0x0000a0d4, 0x02010202},
19444 + {0x0000a0d8, 0x021f0200},
19445 + {0x0000a0dc, 0x021d021e},
19446 + {0x0000a0e0, 0x03010302},
19447 + {0x0000a0e4, 0x031f0300},
19448 + {0x0000a0e8, 0x0402031e},
19449 + {0x0000a0ec, 0x04000401},
19450 + {0x0000a0f0, 0x041e041f},
19451 + {0x0000a0f4, 0x05010502},
19452 + {0x0000a0f8, 0x051f0500},
19453 + {0x0000a0fc, 0x0602051e},
19454 + {0x0000a100, 0x06000601},
19455 + {0x0000a104, 0x061e061f},
19456 + {0x0000a108, 0x0703061d},
19457 + {0x0000a10c, 0x07010702},
19458 + {0x0000a110, 0x00000700},
19459 + {0x0000a114, 0x00000000},
19460 + {0x0000a118, 0x00000000},
19461 + {0x0000a11c, 0x00000000},
19462 + {0x0000a120, 0x00000000},
19463 + {0x0000a124, 0x00000000},
19464 + {0x0000a128, 0x00000000},
19465 + {0x0000a12c, 0x00000000},
19466 + {0x0000a130, 0x00000000},
19467 + {0x0000a134, 0x00000000},
19468 + {0x0000a138, 0x00000000},
19469 + {0x0000a13c, 0x00000000},
19470 + {0x0000a140, 0x001f0000},
19471 + {0x0000a144, 0x011f0100},
19472 + {0x0000a148, 0x011d011e},
19473 + {0x0000a14c, 0x011b011c},
19474 + {0x0000a150, 0x02030204},
19475 + {0x0000a154, 0x02010202},
19476 + {0x0000a158, 0x021f0200},
19477 + {0x0000a15c, 0x021d021e},
19478 + {0x0000a160, 0x03010302},
19479 + {0x0000a164, 0x031f0300},
19480 + {0x0000a168, 0x0402031e},
19481 + {0x0000a16c, 0x04000401},
19482 + {0x0000a170, 0x041e041f},
19483 + {0x0000a174, 0x05010502},
19484 + {0x0000a178, 0x051f0500},
19485 + {0x0000a17c, 0x0602051e},
19486 + {0x0000a180, 0x06000601},
19487 + {0x0000a184, 0x061e061f},
19488 + {0x0000a188, 0x0703061d},
19489 + {0x0000a18c, 0x07010702},
19490 + {0x0000a190, 0x00000700},
19491 + {0x0000a194, 0x00000000},
19492 + {0x0000a198, 0x00000000},
19493 + {0x0000a19c, 0x00000000},
19494 + {0x0000a1a0, 0x00000000},
19495 + {0x0000a1a4, 0x00000000},
19496 + {0x0000a1a8, 0x00000000},
19497 + {0x0000a1ac, 0x00000000},
19498 + {0x0000a1b0, 0x00000000},
19499 + {0x0000a1b4, 0x00000000},
19500 + {0x0000a1b8, 0x00000000},
19501 + {0x0000a1bc, 0x00000000},
19502 + {0x0000a1c0, 0x00000000},
19503 + {0x0000a1c4, 0x00000000},
19504 + {0x0000a1c8, 0x00000000},
19505 + {0x0000a1cc, 0x00000000},
19506 + {0x0000a1d0, 0x00000000},
19507 + {0x0000a1d4, 0x00000000},
19508 + {0x0000a1d8, 0x00000000},
19509 + {0x0000a1dc, 0x00000000},
19510 + {0x0000a1e0, 0x00000000},
19511 + {0x0000a1e4, 0x00000000},
19512 + {0x0000a1e8, 0x00000000},
19513 + {0x0000a1ec, 0x00000000},
19514 + {0x0000a1f0, 0x00000396},
19515 + {0x0000a1f4, 0x00000396},
19516 + {0x0000a1f8, 0x00000396},
19517 + {0x0000a1fc, 0x00000296},
19518 + {0x0000b000, 0x00010000},
19519 + {0x0000b004, 0x00030002},
19520 + {0x0000b008, 0x00050004},
19521 + {0x0000b00c, 0x00810080},
19522 + {0x0000b010, 0x00830082},
19523 + {0x0000b014, 0x01810180},
19524 + {0x0000b018, 0x01830182},
19525 + {0x0000b01c, 0x01850184},
19526 + {0x0000b020, 0x02810280},
19527 + {0x0000b024, 0x02830282},
19528 + {0x0000b028, 0x02850284},
19529 + {0x0000b02c, 0x02890288},
19530 + {0x0000b030, 0x028b028a},
19531 + {0x0000b034, 0x0388028c},
19532 + {0x0000b038, 0x038a0389},
19533 + {0x0000b03c, 0x038c038b},
19534 + {0x0000b040, 0x0390038d},
19535 + {0x0000b044, 0x03920391},
19536 + {0x0000b048, 0x03940393},
19537 + {0x0000b04c, 0x03960395},
19538 + {0x0000b050, 0x00000000},
19539 + {0x0000b054, 0x00000000},
19540 + {0x0000b058, 0x00000000},
19541 + {0x0000b05c, 0x00000000},
19542 + {0x0000b060, 0x00000000},
19543 + {0x0000b064, 0x00000000},
19544 + {0x0000b068, 0x00000000},
19545 + {0x0000b06c, 0x00000000},
19546 + {0x0000b070, 0x00000000},
19547 + {0x0000b074, 0x00000000},
19548 + {0x0000b078, 0x00000000},
19549 + {0x0000b07c, 0x00000000},
19550 + {0x0000b080, 0x32323232},
19551 + {0x0000b084, 0x2f2f3232},
19552 + {0x0000b088, 0x23282a2d},
19553 + {0x0000b08c, 0x1c1e2123},
19554 + {0x0000b090, 0x14171919},
19555 + {0x0000b094, 0x0e0e1214},
19556 + {0x0000b098, 0x03050707},
19557 + {0x0000b09c, 0x00030303},
19558 + {0x0000b0a0, 0x00000000},
19559 + {0x0000b0a4, 0x00000000},
19560 + {0x0000b0a8, 0x00000000},
19561 + {0x0000b0ac, 0x00000000},
19562 + {0x0000b0b0, 0x00000000},
19563 + {0x0000b0b4, 0x00000000},
19564 + {0x0000b0b8, 0x00000000},
19565 + {0x0000b0bc, 0x00000000},
19566 + {0x0000b0c0, 0x003f0020},
19567 + {0x0000b0c4, 0x00400041},
19568 + {0x0000b0c8, 0x0140005f},
19569 + {0x0000b0cc, 0x0160015f},
19570 + {0x0000b0d0, 0x017e017f},
19571 + {0x0000b0d4, 0x02410242},
19572 + {0x0000b0d8, 0x025f0240},
19573 + {0x0000b0dc, 0x027f0260},
19574 + {0x0000b0e0, 0x0341027e},
19575 + {0x0000b0e4, 0x035f0340},
19576 + {0x0000b0e8, 0x037f0360},
19577 + {0x0000b0ec, 0x04400441},
19578 + {0x0000b0f0, 0x0460045f},
19579 + {0x0000b0f4, 0x0541047f},
19580 + {0x0000b0f8, 0x055f0540},
19581 + {0x0000b0fc, 0x057f0560},
19582 + {0x0000b100, 0x06400641},
19583 + {0x0000b104, 0x0660065f},
19584 + {0x0000b108, 0x067e067f},
19585 + {0x0000b10c, 0x07410742},
19586 + {0x0000b110, 0x075f0740},
19587 + {0x0000b114, 0x077f0760},
19588 + {0x0000b118, 0x07800781},
19589 + {0x0000b11c, 0x07a0079f},
19590 + {0x0000b120, 0x07c107bf},
19591 + {0x0000b124, 0x000007c0},
19592 + {0x0000b128, 0x00000000},
19593 + {0x0000b12c, 0x00000000},
19594 + {0x0000b130, 0x00000000},
19595 + {0x0000b134, 0x00000000},
19596 + {0x0000b138, 0x00000000},
19597 + {0x0000b13c, 0x00000000},
19598 + {0x0000b140, 0x003f0020},
19599 + {0x0000b144, 0x00400041},
19600 + {0x0000b148, 0x0140005f},
19601 + {0x0000b14c, 0x0160015f},
19602 + {0x0000b150, 0x017e017f},
19603 + {0x0000b154, 0x02410242},
19604 + {0x0000b158, 0x025f0240},
19605 + {0x0000b15c, 0x027f0260},
19606 + {0x0000b160, 0x0341027e},
19607 + {0x0000b164, 0x035f0340},
19608 + {0x0000b168, 0x037f0360},
19609 + {0x0000b16c, 0x04400441},
19610 + {0x0000b170, 0x0460045f},
19611 + {0x0000b174, 0x0541047f},
19612 + {0x0000b178, 0x055f0540},
19613 + {0x0000b17c, 0x057f0560},
19614 + {0x0000b180, 0x06400641},
19615 + {0x0000b184, 0x0660065f},
19616 + {0x0000b188, 0x067e067f},
19617 + {0x0000b18c, 0x07410742},
19618 + {0x0000b190, 0x075f0740},
19619 + {0x0000b194, 0x077f0760},
19620 + {0x0000b198, 0x07800781},
19621 + {0x0000b19c, 0x07a0079f},
19622 + {0x0000b1a0, 0x07c107bf},
19623 + {0x0000b1a4, 0x000007c0},
19624 + {0x0000b1a8, 0x00000000},
19625 + {0x0000b1ac, 0x00000000},
19626 + {0x0000b1b0, 0x00000000},
19627 + {0x0000b1b4, 0x00000000},
19628 + {0x0000b1b8, 0x00000000},
19629 + {0x0000b1bc, 0x00000000},
19630 + {0x0000b1c0, 0x00000000},
19631 + {0x0000b1c4, 0x00000000},
19632 + {0x0000b1c8, 0x00000000},
19633 + {0x0000b1cc, 0x00000000},
19634 + {0x0000b1d0, 0x00000000},
19635 + {0x0000b1d4, 0x00000000},
19636 + {0x0000b1d8, 0x00000000},
19637 + {0x0000b1dc, 0x00000000},
19638 + {0x0000b1e0, 0x00000000},
19639 + {0x0000b1e4, 0x00000000},
19640 + {0x0000b1e8, 0x00000000},
19641 + {0x0000b1ec, 0x00000000},
19642 + {0x0000b1f0, 0x00000396},
19643 + {0x0000b1f4, 0x00000396},
19644 + {0x0000b1f8, 0x00000396},
19645 + {0x0000b1fc, 0x00000196},
19646 +};
19647 +
19648 +static const u32 ar9300_2p0_soc_preamble[][2] = {
19649 + /* Addr allmodes */
19650 + {0x000040a4, 0x00a0c1c9},
19651 + {0x00007008, 0x00000000},
19652 + {0x00007020, 0x00000000},
19653 + {0x00007034, 0x00000002},
19654 + {0x00007038, 0x000004c2},
19655 +};
19656 +
19657 +/*
19658 + * PCIE-PHY programming array, to be used prior to entering
19659 + * full sleep (holding RTC in reset, PLL is ON in L1 mode)
19660 + */
19661 +static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0[][2] = {
19662 + {0x00004040, 0x08212e5e},
19663 + {0x00004040, 0x0008003b},
19664 + {0x00004044, 0x00000000},
19665 +};
19666 +
19667 +/*
19668 + * PCIE-PHY programming array, to be used when not in
19669 + * full sleep (holding RTC in reset)
19670 + */
19671 +static const u32 ar9300PciePhy_clkreq_enable_L1_2p0[][2] = {
19672 + {0x00004040, 0x08253e5e},
19673 + {0x00004040, 0x0008003b},
19674 + {0x00004044, 0x00000000},
19675 +};
19676 +
19677 +/*
19678 + * PCIE-PHY programming array, to be used prior to entering
19679 + * full sleep (holding RTC in reset)
19680 + */
19681 +static const u32 ar9300PciePhy_clkreq_disable_L1_2p0[][2] = {
19682 + {0x00004040, 0x08213e5e},
19683 + {0x00004040, 0x0008003b},
19684 + {0x00004044, 0x00000000},
19685 +};
19686 +
19687 +#endif /* INITVALS_9003_H */
19688 --- /dev/null
19689 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
19690 @@ -0,0 +1,620 @@
19691 +/*
19692 + * Copyright (c) 2010 Atheros Communications Inc.
19693 + *
19694 + * Permission to use, copy, modify, and/or distribute this software for any
19695 + * purpose with or without fee is hereby granted, provided that the above
19696 + * copyright notice and this permission notice appear in all copies.
19697 + *
19698 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
19699 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
19700 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
19701 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19702 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19703 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19704 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19705 + */
19706 +#include "hw.h"
19707 +
19708 +static void ar9003_hw_rx_enable(struct ath_hw *hw)
19709 +{
19710 + REG_WRITE(hw, AR_CR, 0);
19711 +}
19712 +
19713 +static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
19714 +{
19715 + int checksum;
19716 +
19717 + checksum = ads->info + ads->link
19718 + + ads->data0 + ads->ctl3
19719 + + ads->data1 + ads->ctl5
19720 + + ads->data2 + ads->ctl7
19721 + + ads->data3 + ads->ctl9;
19722 +
19723 + return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
19724 +}
19725 +
19726 +static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
19727 +{
19728 + struct ar9003_txc *ads = ds;
19729 +
19730 + ads->link = ds_link;
19731 + ads->ctl10 &= ~AR_TxPtrChkSum;
19732 + ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
19733 +}
19734 +
19735 +static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
19736 +{
19737 + struct ar9003_txc *ads = ds;
19738 +
19739 + *ds_link = &ads->link;
19740 +}
19741 +
19742 +static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
19743 +{
19744 + u32 isr = 0;
19745 + u32 mask2 = 0;
19746 + struct ath9k_hw_capabilities *pCap = &ah->caps;
19747 + u32 sync_cause = 0;
19748 + struct ath_common *common = ath9k_hw_common(ah);
19749 +
19750 + if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
19751 + if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
19752 + == AR_RTC_STATUS_ON)
19753 + isr = REG_READ(ah, AR_ISR);
19754 + }
19755 +
19756 + sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
19757 +
19758 + *masked = 0;
19759 +
19760 + if (!isr && !sync_cause)
19761 + return false;
19762 +
19763 + if (isr) {
19764 + if (isr & AR_ISR_BCNMISC) {
19765 + u32 isr2;
19766 + isr2 = REG_READ(ah, AR_ISR_S2);
19767 +
19768 + mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
19769 + MAP_ISR_S2_TIM);
19770 + mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
19771 + MAP_ISR_S2_DTIM);
19772 + mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
19773 + MAP_ISR_S2_DTIMSYNC);
19774 + mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
19775 + MAP_ISR_S2_CABEND);
19776 + mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
19777 + MAP_ISR_S2_GTT);
19778 + mask2 |= ((isr2 & AR_ISR_S2_CST) <<
19779 + MAP_ISR_S2_CST);
19780 + mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
19781 + MAP_ISR_S2_TSFOOR);
19782 +
19783 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
19784 + REG_WRITE(ah, AR_ISR_S2, isr2);
19785 + isr &= ~AR_ISR_BCNMISC;
19786 + }
19787 + }
19788 +
19789 + if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
19790 + isr = REG_READ(ah, AR_ISR_RAC);
19791 +
19792 + if (isr == 0xffffffff) {
19793 + *masked = 0;
19794 + return false;
19795 + }
19796 +
19797 + *masked = isr & ATH9K_INT_COMMON;
19798 +
19799 + if (ah->config.rx_intr_mitigation)
19800 + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
19801 + *masked |= ATH9K_INT_RXLP;
19802 +
19803 + if (ah->config.tx_intr_mitigation)
19804 + if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
19805 + *masked |= ATH9K_INT_TX;
19806 +
19807 + if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
19808 + *masked |= ATH9K_INT_RXLP;
19809 +
19810 + if (isr & AR_ISR_HP_RXOK)
19811 + *masked |= ATH9K_INT_RXHP;
19812 +
19813 + if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
19814 + *masked |= ATH9K_INT_TX;
19815 +
19816 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
19817 + u32 s0, s1;
19818 + s0 = REG_READ(ah, AR_ISR_S0);
19819 + REG_WRITE(ah, AR_ISR_S0, s0);
19820 + s1 = REG_READ(ah, AR_ISR_S1);
19821 + REG_WRITE(ah, AR_ISR_S1, s1);
19822 +
19823 + isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
19824 + AR_ISR_TXEOL);
19825 + }
19826 + }
19827 +
19828 + if (isr & AR_ISR_GENTMR) {
19829 + u32 s5;
19830 +
19831 + if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
19832 + s5 = REG_READ(ah, AR_ISR_S5_S);
19833 + else
19834 + s5 = REG_READ(ah, AR_ISR_S5);
19835 +
19836 + ah->intr_gen_timer_trigger =
19837 + MS(s5, AR_ISR_S5_GENTIMER_TRIG);
19838 +
19839 + ah->intr_gen_timer_thresh =
19840 + MS(s5, AR_ISR_S5_GENTIMER_THRESH);
19841 +
19842 + if (ah->intr_gen_timer_trigger)
19843 + *masked |= ATH9K_INT_GENTIMER;
19844 +
19845 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
19846 + REG_WRITE(ah, AR_ISR_S5, s5);
19847 + isr &= ~AR_ISR_GENTMR;
19848 + }
19849 +
19850 + }
19851 +
19852 + *masked |= mask2;
19853 +
19854 + if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
19855 + REG_WRITE(ah, AR_ISR, isr);
19856 +
19857 + (void) REG_READ(ah, AR_ISR);
19858 + }
19859 + }
19860 +
19861 + if (sync_cause) {
19862 + if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
19863 + REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
19864 + REG_WRITE(ah, AR_RC, 0);
19865 + *masked |= ATH9K_INT_FATAL;
19866 + }
19867 +
19868 + if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
19869 + ath_print(common, ATH_DBG_INTERRUPT,
19870 + "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
19871 +
19872 + REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
19873 + (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
19874 +
19875 + }
19876 + return true;
19877 +}
19878 +
19879 +static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
19880 + bool is_firstseg, bool is_lastseg,
19881 + const void *ds0, dma_addr_t buf_addr,
19882 + unsigned int qcu)
19883 +{
19884 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
19885 + unsigned int descid = 0;
19886 +
19887 + ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
19888 + (1 << AR_TxRxDesc_S) |
19889 + (1 << AR_CtrlStat_S) |
19890 + (qcu << AR_TxQcuNum_S) | 0x17;
19891 +
19892 + ads->data0 = buf_addr;
19893 + ads->data1 = 0;
19894 + ads->data2 = 0;
19895 + ads->data3 = 0;
19896 +
19897 + ads->ctl3 = (seglen << AR_BufLen_S);
19898 + ads->ctl3 &= AR_BufLen;
19899 +
19900 + /* Fill in pointer checksum and descriptor id */
19901 + ads->ctl10 = ar9003_calc_ptr_chksum(ads);
19902 + ads->ctl10 |= (descid << AR_TxDescId_S);
19903 +
19904 + if (is_firstseg) {
19905 + ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
19906 + } else if (is_lastseg) {
19907 + ads->ctl11 = 0;
19908 + ads->ctl12 = 0;
19909 + ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
19910 + ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
19911 + } else {
19912 + /* XXX Intermediate descriptor in a multi-descriptor frame.*/
19913 + ads->ctl11 = 0;
19914 + ads->ctl12 = AR_TxMore;
19915 + ads->ctl13 = 0;
19916 + ads->ctl14 = 0;
19917 + }
19918 +}
19919 +
19920 +static void ar9003_hw_clear_txdesc(struct ath_hw *ah, void *ds)
19921 +{
19922 + struct ar9003_txs *ads = (struct ar9003_txs *) ds;
19923 + ads->status1 = ads->status2 = 0;
19924 + ads->status3 = ads->status4 = 0;
19925 + ads->status5 = ads->status6 = 0;
19926 + ads->status7 = ads->status8 = 0;
19927 +}
19928 +
19929 +static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
19930 + struct ath_tx_status *ts)
19931 +{
19932 + struct ar9003_txs *ads;
19933 +
19934 + ads = &ah->ts_ring[ah->ts_tail];
19935 +
19936 + if ((ads->status8 & AR_TxDone) == 0)
19937 + return -EINPROGRESS;
19938 +
19939 + ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
19940 +
19941 + if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
19942 + (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
19943 + ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
19944 + "Tx Descriptor error %x\n", ads->ds_info);
19945 + memset(ads, 0, sizeof(*ads));
19946 + return -EIO;
19947 + }
19948 +
19949 + ts->qid = MS(ads->ds_info, AR_TxQcuNum);
19950 + ts->desc_id = MS(ads->status1, AR_TxDescId);
19951 + ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
19952 + ts->ts_tstamp = ads->status4;
19953 + ts->ts_status = 0;
19954 + ts->ts_flags = 0;
19955 +
19956 + if (ads->status3 & AR_ExcessiveRetries)
19957 + ts->ts_status |= ATH9K_TXERR_XRETRY;
19958 + if (ads->status3 & AR_Filtered)
19959 + ts->ts_status |= ATH9K_TXERR_FILT;
19960 + if (ads->status3 & AR_FIFOUnderrun) {
19961 + ts->ts_status |= ATH9K_TXERR_FIFO;
19962 + ath9k_hw_updatetxtriglevel(ah, true);
19963 + }
19964 + if (ads->status8 & AR_TxOpExceeded)
19965 + ts->ts_status |= ATH9K_TXERR_XTXOP;
19966 + if (ads->status3 & AR_TxTimerExpired)
19967 + ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
19968 +
19969 + if (ads->status3 & AR_DescCfgErr)
19970 + ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
19971 + if (ads->status3 & AR_TxDataUnderrun) {
19972 + ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
19973 + ath9k_hw_updatetxtriglevel(ah, true);
19974 + }
19975 + if (ads->status3 & AR_TxDelimUnderrun) {
19976 + ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
19977 + ath9k_hw_updatetxtriglevel(ah, true);
19978 + }
19979 + if (ads->status2 & AR_TxBaStatus) {
19980 + ts->ts_flags |= ATH9K_TX_BA;
19981 + ts->ba_low = ads->status5;
19982 + ts->ba_high = ads->status6;
19983 + }
19984 +
19985 + ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
19986 +
19987 + ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
19988 + ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
19989 + ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
19990 + ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
19991 + ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
19992 + ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
19993 + ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
19994 + ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
19995 + ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
19996 + ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
19997 + ts->ts_antenna = 0;
19998 +
19999 + ts->tid = MS(ads->status8, AR_TxTid);
20000 +
20001 + memset(ads, 0, sizeof(*ads));
20002 +
20003 + return 0;
20004 +}
20005 +
20006 +static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
20007 + u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
20008 + u32 keyIx, enum ath9k_key_type keyType, u32 flags)
20009 +{
20010 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20011 +
20012 + txpower += ah->txpower_indexoffset;
20013 + if (txpower > 63)
20014 + txpower = 63;
20015 +
20016 + ads->ctl11 = (pktlen & AR_FrameLen)
20017 + | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
20018 + | SM(txpower, AR_XmitPower)
20019 + | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
20020 + | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
20021 + | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
20022 + | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
20023 +
20024 + ads->ctl12 =
20025 + (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
20026 + | SM(type, AR_FrameType)
20027 + | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
20028 + | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
20029 + | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
20030 +
20031 + ads->ctl17 = SM(keyType, AR_EncrType) |
20032 + (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
20033 + ads->ctl18 = 0;
20034 + ads->ctl19 = AR_Not_Sounding;
20035 +
20036 + ads->ctl20 = 0;
20037 + ads->ctl21 = 0;
20038 + ads->ctl22 = 0;
20039 +}
20040 +
20041 +static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
20042 + void *lastds,
20043 + u32 durUpdateEn, u32 rtsctsRate,
20044 + u32 rtsctsDuration,
20045 + struct ath9k_11n_rate_series series[],
20046 + u32 nseries, u32 flags)
20047 +{
20048 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20049 + struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
20050 + u_int32_t ctl11;
20051 +
20052 + if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
20053 + ctl11 = ads->ctl11;
20054 +
20055 + if (flags & ATH9K_TXDESC_RTSENA) {
20056 + ctl11 &= ~AR_CTSEnable;
20057 + ctl11 |= AR_RTSEnable;
20058 + } else {
20059 + ctl11 &= ~AR_RTSEnable;
20060 + ctl11 |= AR_CTSEnable;
20061 + }
20062 +
20063 + ads->ctl11 = ctl11;
20064 + } else {
20065 + ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
20066 + }
20067 +
20068 + ads->ctl13 = set11nTries(series, 0)
20069 + | set11nTries(series, 1)
20070 + | set11nTries(series, 2)
20071 + | set11nTries(series, 3)
20072 + | (durUpdateEn ? AR_DurUpdateEna : 0)
20073 + | SM(0, AR_BurstDur);
20074 +
20075 + ads->ctl14 = set11nRate(series, 0)
20076 + | set11nRate(series, 1)
20077 + | set11nRate(series, 2)
20078 + | set11nRate(series, 3);
20079 +
20080 + ads->ctl15 = set11nPktDurRTSCTS(series, 0)
20081 + | set11nPktDurRTSCTS(series, 1);
20082 +
20083 + ads->ctl16 = set11nPktDurRTSCTS(series, 2)
20084 + | set11nPktDurRTSCTS(series, 3);
20085 +
20086 + ads->ctl18 = set11nRateFlags(series, 0)
20087 + | set11nRateFlags(series, 1)
20088 + | set11nRateFlags(series, 2)
20089 + | set11nRateFlags(series, 3)
20090 + | SM(rtsctsRate, AR_RTSCTSRate);
20091 + ads->ctl19 = AR_Not_Sounding;
20092 +
20093 + last_ads->ctl13 = ads->ctl13;
20094 + last_ads->ctl14 = ads->ctl14;
20095 +}
20096 +
20097 +static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
20098 + u32 aggrLen)
20099 +{
20100 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20101 +
20102 + ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
20103 +
20104 + ads->ctl17 &= ~AR_AggrLen;
20105 + ads->ctl17 |= SM(aggrLen, AR_AggrLen);
20106 +}
20107 +
20108 +static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
20109 + u32 numDelims)
20110 +{
20111 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20112 + unsigned int ctl17;
20113 +
20114 + ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
20115 +
20116 + /*
20117 + * We use a stack variable to manipulate ctl6 to reduce uncached
20118 + * read modify, modfiy, write.
20119 + */
20120 + ctl17 = ads->ctl17;
20121 + ctl17 &= ~AR_PadDelim;
20122 + ctl17 |= SM(numDelims, AR_PadDelim);
20123 + ads->ctl17 = ctl17;
20124 +}
20125 +
20126 +static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
20127 +{
20128 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20129 +
20130 + ads->ctl12 |= AR_IsAggr;
20131 + ads->ctl12 &= ~AR_MoreAggr;
20132 + ads->ctl17 &= ~AR_PadDelim;
20133 +}
20134 +
20135 +static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
20136 +{
20137 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20138 +
20139 + ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
20140 +}
20141 +
20142 +static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
20143 + u32 burstDuration)
20144 +{
20145 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20146 +
20147 + ads->ctl13 &= ~AR_BurstDur;
20148 + ads->ctl13 |= SM(burstDuration, AR_BurstDur);
20149 +
20150 +}
20151 +
20152 +static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
20153 + u32 vmf)
20154 +{
20155 + struct ar9003_txc *ads = (struct ar9003_txc *) ds;
20156 +
20157 + if (vmf)
20158 + ads->ctl11 |= AR_VirtMoreFrag;
20159 + else
20160 + ads->ctl11 &= ~AR_VirtMoreFrag;
20161 +}
20162 +
20163 +void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
20164 +{
20165 + struct ath_hw_ops *ops = ath9k_hw_ops(hw);
20166 +
20167 + ops->rx_enable = ar9003_hw_rx_enable;
20168 + ops->set_desc_link = ar9003_hw_set_desc_link;
20169 + ops->get_desc_link = ar9003_hw_get_desc_link;
20170 + ops->get_isr = ar9003_hw_get_isr;
20171 + ops->fill_txdesc = ar9003_hw_fill_txdesc;
20172 + ops->clear_txdesc = ar9003_hw_clear_txdesc;
20173 + ops->proc_txdesc = ar9003_hw_proc_txdesc;
20174 + ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
20175 + ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
20176 + ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
20177 + ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
20178 + ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
20179 + ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
20180 + ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
20181 + ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
20182 +}
20183 +
20184 +void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
20185 +{
20186 + REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
20187 +}
20188 +EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
20189 +
20190 +void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
20191 + enum ath9k_rx_qtype qtype)
20192 +{
20193 + if (qtype == ATH9K_RX_QUEUE_HP)
20194 + REG_WRITE(ah, AR_HP_RXDP, rxdp);
20195 + else
20196 + REG_WRITE(ah, AR_LP_RXDP, rxdp);
20197 +}
20198 +EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
20199 +
20200 +int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
20201 + void *buf_addr)
20202 +{
20203 + struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
20204 + unsigned int phyerr;
20205 +
20206 + /* TODO: byte swap on big endian for ar9300_10 */
20207 +
20208 + if ((rxsp->status11 & AR_RxDone) == 0)
20209 + return -EINPROGRESS;
20210 +
20211 + if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
20212 + return -EINVAL;
20213 +
20214 + if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
20215 + return -EINPROGRESS;
20216 +
20217 + if (!rxs)
20218 + return 0;
20219 +
20220 + rxs->rs_status = 0;
20221 + rxs->rs_flags = 0;
20222 +
20223 + rxs->rs_datalen = rxsp->status2 & AR_DataLen;
20224 + rxs->rs_tstamp = rxsp->status3;
20225 +
20226 + /* XXX: Keycache */
20227 + rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
20228 + rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
20229 + rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
20230 + rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
20231 + rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
20232 + rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
20233 + rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
20234 +
20235 + if (rxsp->status11 & AR_RxKeyIdxValid)
20236 + rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
20237 + else
20238 + rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
20239 +
20240 + rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
20241 + rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
20242 +
20243 + rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
20244 + rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
20245 + rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
20246 + rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
20247 + rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
20248 +
20249 + rxs->evm0 = rxsp->status6;
20250 + rxs->evm1 = rxsp->status7;
20251 + rxs->evm2 = rxsp->status8;
20252 + rxs->evm3 = rxsp->status9;
20253 + rxs->evm4 = (rxsp->status10 & 0xffff);
20254 +
20255 + if (rxsp->status11 & AR_PreDelimCRCErr)
20256 + rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
20257 +
20258 + if (rxsp->status11 & AR_PostDelimCRCErr)
20259 + rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
20260 +
20261 + if (rxsp->status11 & AR_DecryptBusyErr)
20262 + rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
20263 +
20264 + if ((rxsp->status11 & AR_RxFrameOK) == 0) {
20265 + if (rxsp->status11 & AR_CRCErr) {
20266 + rxs->rs_status |= ATH9K_RXERR_CRC;
20267 + } else if (rxsp->status11 & AR_PHYErr) {
20268 + rxs->rs_status |= ATH9K_RXERR_PHY;
20269 + phyerr = MS(rxsp->status11, AR_PHYErrCode);
20270 + rxs->rs_phyerr = phyerr;
20271 + } else if (rxsp->status11 & AR_DecryptCRCErr) {
20272 + rxs->rs_status |= ATH9K_RXERR_DECRYPT;
20273 + } else if (rxsp->status11 & AR_MichaelErr) {
20274 + rxs->rs_status |= ATH9K_RXERR_MIC;
20275 + }
20276 + }
20277 +
20278 + return 0;
20279 +}
20280 +EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
20281 +
20282 +void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
20283 +{
20284 + ah->ts_tail = 0;
20285 +
20286 + memset((void *) ah->ts_ring, 0,
20287 + ah->ts_size * sizeof(struct ar9003_txs));
20288 +
20289 + ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
20290 + "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
20291 + ah->ts_paddr_start, ah->ts_paddr_end,
20292 + ah->ts_ring, ah->ts_size);
20293 +
20294 + REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
20295 + REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
20296 +}
20297 +
20298 +void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
20299 + u32 ts_paddr_start,
20300 + u8 size)
20301 +{
20302 +
20303 + ah->ts_paddr_start = ts_paddr_start;
20304 + ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
20305 + ah->ts_size = size;
20306 + ah->ts_ring = (struct ar9003_txs *) ts_start;
20307 +
20308 + ath9k_hw_reset_txstatus_ring(ah);
20309 +}
20310 +EXPORT_SYMBOL(ath9k_hw_setup_statusring);
20311 --- /dev/null
20312 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
20313 @@ -0,0 +1,124 @@
20314 +/*
20315 + * Copyright (c) 2010 Atheros Communications Inc.
20316 + *
20317 + * Permission to use, copy, modify, and/or distribute this software for any
20318 + * purpose with or without fee is hereby granted, provided that the above
20319 + * copyright notice and this permission notice appear in all copies.
20320 + *
20321 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
20322 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
20323 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
20324 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20325 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20326 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20327 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20328 + */
20329 +
20330 +#ifndef AR9003_MAC_H
20331 +#define AR9003_MAC_H
20332 +
20333 +#define AR_DescId 0xffff0000
20334 +#define AR_DescId_S 16
20335 +#define AR_CtrlStat 0x00004000
20336 +#define AR_CtrlStat_S 14
20337 +#define AR_TxRxDesc 0x00008000
20338 +#define AR_TxRxDesc_S 15
20339 +#define AR_TxQcuNum 0x00000f00
20340 +#define AR_TxQcuNum_S 8
20341 +#define AR_BufLen_S 16
20342 +
20343 +#define AR_TxDescId 0xffff0000
20344 +#define AR_TxDescId_S 16
20345 +#define AR_TxPtrChkSum 0x0000ffff
20346 +
20347 +#define AR_TxTid 0xf0000000
20348 +#define AR_TxTid_S 28
20349 +
20350 +#define AR_LowRxChain 0x00004000
20351 +
20352 +#define AR_Not_Sounding 0x20000000
20353 +
20354 +#define MAP_ISR_S2_CST 6
20355 +#define MAP_ISR_S2_GTT 6
20356 +#define MAP_ISR_S2_TIM 3
20357 +#define MAP_ISR_S2_CABEND 0
20358 +#define MAP_ISR_S2_DTIMSYNC 7
20359 +#define MAP_ISR_S2_DTIM 7
20360 +#define MAP_ISR_S2_TSFOOR 4
20361 +
20362 +#define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
20363 +
20364 +enum ath9k_rx_qtype {
20365 + ATH9K_RX_QUEUE_HP,
20366 + ATH9K_RX_QUEUE_LP,
20367 + ATH9K_RX_QUEUE_MAX,
20368 +};
20369 +
20370 +struct ar9003_rxs {
20371 + u32 ds_info;
20372 + u32 status1;
20373 + u32 status2;
20374 + u32 status3;
20375 + u32 status4;
20376 + u32 status5;
20377 + u32 status6;
20378 + u32 status7;
20379 + u32 status8;
20380 + u32 status9;
20381 + u32 status10;
20382 + u32 status11;
20383 +} __packed;
20384 +
20385 +/* Transmit Control Descriptor */
20386 +struct ar9003_txc {
20387 + u32 info; /* descriptor information */
20388 + u32 link; /* link pointer */
20389 + u32 data0; /* data pointer to 1st buffer */
20390 + u32 ctl3; /* DMA control 3 */
20391 + u32 data1; /* data pointer to 2nd buffer */
20392 + u32 ctl5; /* DMA control 5 */
20393 + u32 data2; /* data pointer to 3rd buffer */
20394 + u32 ctl7; /* DMA control 7 */
20395 + u32 data3; /* data pointer to 4th buffer */
20396 + u32 ctl9; /* DMA control 9 */
20397 + u32 ctl10; /* DMA control 10 */
20398 + u32 ctl11; /* DMA control 11 */
20399 + u32 ctl12; /* DMA control 12 */
20400 + u32 ctl13; /* DMA control 13 */
20401 + u32 ctl14; /* DMA control 14 */
20402 + u32 ctl15; /* DMA control 15 */
20403 + u32 ctl16; /* DMA control 16 */
20404 + u32 ctl17; /* DMA control 17 */
20405 + u32 ctl18; /* DMA control 18 */
20406 + u32 ctl19; /* DMA control 19 */
20407 + u32 ctl20; /* DMA control 20 */
20408 + u32 ctl21; /* DMA control 21 */
20409 + u32 ctl22; /* DMA control 22 */
20410 + u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
20411 +} __packed;
20412 +
20413 +struct ar9003_txs {
20414 + u32 ds_info;
20415 + u32 status1;
20416 + u32 status2;
20417 + u32 status3;
20418 + u32 status4;
20419 + u32 status5;
20420 + u32 status6;
20421 + u32 status7;
20422 + u32 status8;
20423 +} __packed;
20424 +
20425 +void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
20426 +void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
20427 +void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
20428 + enum ath9k_rx_qtype qtype);
20429 +
20430 +int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
20431 + struct ath_rx_status *rxs,
20432 + void *buf_addr);
20433 +void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
20434 +void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
20435 + u32 ts_paddr_start,
20436 + u8 size);
20437 +#endif
20438 --- /dev/null
20439 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
20440 @@ -0,0 +1,1138 @@
20441 +/*
20442 + * Copyright (c) 2010 Atheros Communications Inc.
20443 + *
20444 + * Permission to use, copy, modify, and/or distribute this software for any
20445 + * purpose with or without fee is hereby granted, provided that the above
20446 + * copyright notice and this permission notice appear in all copies.
20447 + *
20448 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
20449 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
20450 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
20451 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20452 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20453 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20454 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20455 + */
20456 +
20457 +#include "hw.h"
20458 +#include "ar9003_phy.h"
20459 +
20460 +/**
20461 + * ar9003_hw_set_channel - set channel on single-chip device
20462 + * @ah: atheros hardware structure
20463 + * @chan:
20464 + *
20465 + * This is the function to change channel on single-chip devices, that is
20466 + * all devices after ar9280.
20467 + *
20468 + * This function takes the channel value in MHz and sets
20469 + * hardware channel value. Assumes writes have been enabled to analog bus.
20470 + *
20471 + * Actual Expression,
20472 + *
20473 + * For 2GHz channel,
20474 + * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
20475 + * (freq_ref = 40MHz)
20476 + *
20477 + * For 5GHz channel,
20478 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
20479 + * (freq_ref = 40MHz/(24>>amodeRefSel))
20480 + *
20481 + * For 5GHz channels which are 5MHz spaced,
20482 + * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
20483 + * (freq_ref = 40MHz)
20484 + */
20485 +static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
20486 +{
20487 + u16 bMode, fracMode = 0, aModeRefSel = 0;
20488 + u32 freq, channelSel = 0, reg32 = 0;
20489 + struct chan_centers centers;
20490 + int loadSynthChannel;
20491 +
20492 + ath9k_hw_get_channel_centers(ah, chan, &centers);
20493 + freq = centers.synth_center;
20494 +
20495 + if (freq < 4800) { /* 2 GHz, fractional mode */
20496 + channelSel = CHANSEL_2G(freq);
20497 + /* Set to 2G mode */
20498 + bMode = 1;
20499 + } else {
20500 + channelSel = CHANSEL_5G(freq);
20501 + /* Doubler is ON, so, divide channelSel by 2. */
20502 + channelSel >>= 1;
20503 + /* Set to 5G mode */
20504 + bMode = 0;
20505 + }
20506 +
20507 + /* Enable fractional mode for all channels */
20508 + fracMode = 1;
20509 + aModeRefSel = 0;
20510 + loadSynthChannel = 0;
20511 +
20512 + reg32 = (bMode << 29);
20513 + REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
20514 +
20515 + /* Enable Long shift Select for Synthesizer */
20516 + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
20517 + AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
20518 +
20519 + /* Program Synth. setting */
20520 + reg32 = (channelSel << 2 ) | (fracMode << 30) |
20521 + (aModeRefSel << 28) | (loadSynthChannel << 31);
20522 + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
20523 +
20524 + /* Toggle Load Synth channel bit */
20525 + loadSynthChannel = 1;
20526 + reg32 = (channelSel << 2 ) | (fracMode << 30) |
20527 + (aModeRefSel << 28) | (loadSynthChannel << 31);
20528 + REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
20529 +
20530 + ah->curchan = chan;
20531 + ah->curchan_rad_index = -1;
20532 +
20533 + return 0;
20534 +}
20535 +
20536 +/**
20537 + * ar9003_hw_spur_mitigate - convert baseband spur frequency
20538 + * @ah: atheros hardware structure
20539 + * @chan:
20540 + *
20541 + * For single-chip solutions. Converts to baseband spur frequency given the
20542 + * input channel frequency and compute register settings below.
20543 + *
20544 + * Spur mitigation for MRC CCK
20545 + */
20546 +static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
20547 + struct ath9k_channel *chan)
20548 +{
20549 + u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
20550 + int cur_bb_spur, negative = 0, cck_spur_freq;
20551 + int i;
20552 +
20553 + /*
20554 + * Need to verify range +/- 10 MHz in control channel, otherwise spur
20555 + * is out-of-band and can be ignored.
20556 + */
20557 +
20558 + for (i = 0; i < 4; i++) {
20559 + negative = 0;
20560 + cur_bb_spur = spur_freq[i] - chan->channel;
20561 +
20562 + if(cur_bb_spur < 0) {
20563 + negative = 1;
20564 + cur_bb_spur = -cur_bb_spur;
20565 + }
20566 + if (cur_bb_spur < 10) {
20567 + cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
20568 +
20569 + if (negative == 1)
20570 + cck_spur_freq = -cck_spur_freq;
20571 +
20572 + cck_spur_freq = cck_spur_freq & 0xfffff;
20573 +
20574 + REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
20575 + AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
20576 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20577 + AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
20578 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20579 + AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
20580 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20581 + AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x1);
20582 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20583 + AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, cck_spur_freq);
20584 +
20585 + return;
20586 + }
20587 + }
20588 +
20589 + REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
20590 + AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
20591 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20592 + AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
20593 + REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
20594 + AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
20595 +}
20596 +
20597 +/* Clean all spur register fields */
20598 +static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
20599 +{
20600 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20601 + AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
20602 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20603 + AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
20604 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20605 + AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
20606 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
20607 + AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
20608 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20609 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
20610 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20611 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
20612 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20613 + AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
20614 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20615 + AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
20616 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20617 + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
20618 +
20619 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20620 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
20621 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20622 + AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
20623 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20624 + AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
20625 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
20626 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
20627 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
20628 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
20629 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
20630 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
20631 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
20632 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
20633 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
20634 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
20635 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
20636 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
20637 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20638 + AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
20639 +}
20640 +
20641 +static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
20642 + int freq_offset,
20643 + int spur_freq_sd,
20644 + int spur_delta_phase,
20645 + int spur_subchannel_sd)
20646 +{
20647 + int mask_index = 0;
20648 +
20649 + /* OFDM Spur mitigation */
20650 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20651 + AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
20652 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20653 + AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
20654 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20655 + AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
20656 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
20657 + AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
20658 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20659 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
20660 + REG_RMW_FIELD(ah, AR_PHY_TIMING11,
20661 + AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
20662 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20663 + AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
20664 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20665 + AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
20666 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20667 + AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
20668 +
20669 + if (REG_READ_FIELD(ah, AR_PHY_MODE,
20670 + AR_PHY_MODE_DYNAMIC) == 0x1)
20671 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20672 + AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
20673 +
20674 + mask_index = (freq_offset << 4) / 5;
20675 + if (mask_index < 0)
20676 + mask_index = mask_index - 1;
20677 +
20678 + mask_index = mask_index & 0x7f;
20679 +
20680 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20681 + AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
20682 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20683 + AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
20684 + REG_RMW_FIELD(ah, AR_PHY_TIMING4,
20685 + AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
20686 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
20687 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
20688 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
20689 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
20690 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
20691 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
20692 + REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
20693 + AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
20694 + REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
20695 + AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
20696 + REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
20697 + AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
20698 + REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
20699 + AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
20700 +}
20701 +
20702 +static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
20703 + struct ath9k_channel *chan,
20704 + int freq_offset)
20705 +{
20706 + int spur_freq_sd = 0;
20707 + int spur_subchannel_sd = 0;
20708 + int spur_delta_phase = 0;
20709 +
20710 + if (IS_CHAN_HT40(chan)) {
20711 + if (freq_offset < 0) {
20712 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
20713 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
20714 + spur_subchannel_sd = 1;
20715 + else
20716 + spur_subchannel_sd = 0;
20717 +
20718 + spur_freq_sd = ((freq_offset + 10) << 9) / 11;
20719 +
20720 + } else {
20721 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
20722 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
20723 + spur_subchannel_sd = 0;
20724 + else
20725 + spur_subchannel_sd = 1;
20726 +
20727 + spur_freq_sd = ((freq_offset - 10) << 9) / 11;
20728 +
20729 + }
20730 +
20731 + spur_delta_phase = (freq_offset << 17) / 5;
20732 +
20733 + } else {
20734 + spur_subchannel_sd = 0;
20735 + spur_freq_sd = (freq_offset << 9) /11;
20736 + spur_delta_phase = (freq_offset << 18) / 5;
20737 + }
20738 +
20739 + spur_freq_sd = spur_freq_sd & 0x3ff;
20740 + spur_delta_phase = spur_delta_phase & 0xfffff;
20741 +
20742 + ar9003_hw_spur_ofdm(ah,
20743 + freq_offset,
20744 + spur_freq_sd,
20745 + spur_delta_phase,
20746 + spur_subchannel_sd);
20747 +}
20748 +
20749 +/* Spur mitigation for OFDM */
20750 +static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
20751 + struct ath9k_channel *chan)
20752 +{
20753 + int synth_freq;
20754 + int range = 10;
20755 + int freq_offset = 0;
20756 + int mode;
20757 + u8* spurChansPtr;
20758 + unsigned int i;
20759 + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
20760 +
20761 + if (IS_CHAN_5GHZ(chan)) {
20762 + spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
20763 + mode = 0;
20764 + }
20765 + else {
20766 + spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
20767 + mode = 1;
20768 + }
20769 +
20770 + if (spurChansPtr[0] == 0)
20771 + return; /* No spur in the mode */
20772 +
20773 + if (IS_CHAN_HT40(chan)) {
20774 + range = 19;
20775 + if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
20776 + AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
20777 + synth_freq = chan->channel - 10;
20778 + else
20779 + synth_freq = chan->channel + 10;
20780 + } else {
20781 + range = 10;
20782 + synth_freq = chan->channel;
20783 + }
20784 +
20785 + ar9003_hw_spur_ofdm_clear(ah);
20786 +
20787 + for (i = 0; spurChansPtr[i] && i < 5; i++) {
20788 + freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
20789 + if (abs(freq_offset) < range) {
20790 + ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
20791 + break;
20792 + }
20793 + }
20794 +}
20795 +
20796 +static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
20797 + struct ath9k_channel *chan)
20798 +{
20799 + ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
20800 + ar9003_hw_spur_mitigate_ofdm(ah, chan);
20801 +}
20802 +
20803 +static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
20804 + struct ath9k_channel *chan)
20805 +{
20806 + u32 pll;
20807 +
20808 + pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
20809 +
20810 + if (chan && IS_CHAN_HALF_RATE(chan))
20811 + pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
20812 + else if (chan && IS_CHAN_QUARTER_RATE(chan))
20813 + pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
20814 +
20815 + if (chan && IS_CHAN_5GHZ(chan)) {
20816 + pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
20817 +
20818 + /*
20819 + * When doing fast clock, set PLL to 0x142c
20820 + */
20821 + if (IS_CHAN_A_5MHZ_SPACED(chan))
20822 + pll = 0x142c;
20823 + } else
20824 + pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
20825 +
20826 + return pll;
20827 +}
20828 +
20829 +static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
20830 + struct ath9k_channel *chan)
20831 +{
20832 + u32 phymode;
20833 + u32 enableDacFifo = 0;
20834 +
20835 + enableDacFifo =
20836 + (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
20837 +
20838 + /* Enable 11n HT, 20 MHz */
20839 + phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
20840 + AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
20841 +
20842 + /* Configure baseband for dynamic 20/40 operation */
20843 + if (IS_CHAN_HT40(chan)) {
20844 + phymode |= AR_PHY_GC_DYN2040_EN;
20845 + /* Configure control (primary) channel at +-10MHz */
20846 + if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
20847 + (chan->chanmode == CHANNEL_G_HT40PLUS))
20848 + phymode |= AR_PHY_GC_DYN2040_PRI_CH;
20849 +
20850 + }
20851 +
20852 + /* make sure we preserve INI settings */
20853 + phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
20854 + /* turn off Green Field detection for STA for now */
20855 + phymode &= ~AR_PHY_GC_GF_DETECT_EN;
20856 +
20857 + REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
20858 +
20859 + /* Configure MAC for 20/40 operation */
20860 + ath9k_hw_set11nmac2040(ah);
20861 +
20862 + /* global transmit timeout (25 TUs default)*/
20863 + REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
20864 + /* carrier sense timeout */
20865 + REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
20866 +}
20867 +
20868 +static void ar9003_hw_init_bb(struct ath_hw *ah,
20869 + struct ath9k_channel *chan)
20870 +{
20871 + u32 synthDelay;
20872 +
20873 + /*
20874 + * Wait for the frequency synth to settle (synth goes on
20875 + * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
20876 + * Value is in 100ns increments.
20877 + */
20878 + synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
20879 + if (IS_CHAN_B(chan))
20880 + synthDelay = (4 * synthDelay) / 22;
20881 + else
20882 + synthDelay /= 10;
20883 +
20884 + /* Activate the PHY (includes baseband activate + synthesizer on) */
20885 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
20886 +
20887 + /*
20888 + * There is an issue if the AP starts the calibration before
20889 + * the base band timeout completes. This could result in the
20890 + * rx_clear false triggering. As a workaround we add delay an
20891 + * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
20892 + * does not happen.
20893 + */
20894 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
20895 +}
20896 +
20897 +void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
20898 +{
20899 + switch (rx) {
20900 + case 0x5:
20901 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
20902 + AR_PHY_SWAP_ALT_CHAIN);
20903 + case 0x3:
20904 + case 0x1:
20905 + case 0x2:
20906 + case 0x7:
20907 + REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
20908 + REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
20909 + break;
20910 + default:
20911 + break;
20912 + }
20913 +
20914 + REG_WRITE(ah, AR_SELFGEN_MASK, tx);
20915 + if (tx == 0x5) {
20916 + REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
20917 + AR_PHY_SWAP_ALT_CHAIN);
20918 + }
20919 +}
20920 +
20921 +/*
20922 + * Override INI values with chip specific configuration.
20923 + */
20924 +static void ar9003_hw_override_ini(struct ath_hw *ah)
20925 +{
20926 + u32 val;
20927 +
20928 + /*
20929 + * Set the RX_ABORT and RX_DIS and clear it only after
20930 + * RXE is set for MAC. This prevents frames with
20931 + * corrupted descriptor status.
20932 + */
20933 + REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
20934 +
20935 + /*
20936 + * For AR9280 and above, there is a new feature that allows
20937 + * Multicast search based on both MAC Address and Key ID. By default,
20938 + * this feature is enabled. But since the driver is not using this
20939 + * feature, we switch it off; otherwise multicast search based on
20940 + * MAC addr only will fail.
20941 + */
20942 + val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
20943 + REG_WRITE(ah, AR_PCU_MISC_MODE2, val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
20944 +}
20945 +
20946 +static void ar9003_hw_prog_ini(struct ath_hw *ah,
20947 + struct ar5416IniArray *iniArr,
20948 + int column)
20949 +{
20950 + unsigned int i, regWrites = 0;
20951 +
20952 + /* New INI format: Array may be undefined (pre, core, post arrays) */
20953 + if (!iniArr->ia_array)
20954 + return;
20955 +
20956 + /*
20957 + * New INI format: Pre, core, and post arrays for a given subsystem
20958 + * may be modal (> 2 columns) or non-modal (2 columns). Determine if
20959 + * the array is non-modal and force the column to 1.
20960 + */
20961 + if (column >= iniArr->ia_columns)
20962 + column = 1;
20963 +
20964 + for (i = 0; i < iniArr->ia_rows; i++) {
20965 + u32 reg = INI_RA(iniArr, i, 0);
20966 + u32 val = INI_RA(iniArr, i, column);
20967 +
20968 + REG_WRITE(ah, reg, val);
20969 +
20970 + /*
20971 + * Determine if this is a shift register value, and insert the
20972 + * configured delay if so.
20973 + */
20974 + if (reg >= 0x16000 && reg < 0x17000
20975 + && ah->config.analog_shiftreg)
20976 + udelay(100);
20977 +
20978 + DO_DELAY(regWrites);
20979 + }
20980 +}
20981 +
20982 +static int ar9003_hw_process_ini(struct ath_hw *ah,
20983 + struct ath9k_channel *chan)
20984 +{
20985 + struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
20986 + unsigned int regWrites = 0, i;
20987 + struct ieee80211_channel *channel = chan->chan;
20988 + u32 modesIndex, freqIndex;
20989 +
20990 + switch (chan->chanmode) {
20991 + case CHANNEL_A:
20992 + case CHANNEL_A_HT20:
20993 + modesIndex = 1;
20994 + freqIndex = 1;
20995 + break;
20996 + case CHANNEL_A_HT40PLUS:
20997 + case CHANNEL_A_HT40MINUS:
20998 + modesIndex = 2;
20999 + freqIndex = 1;
21000 + break;
21001 + case CHANNEL_G:
21002 + case CHANNEL_G_HT20:
21003 + case CHANNEL_B:
21004 + modesIndex = 4;
21005 + freqIndex = 2;
21006 + break;
21007 + case CHANNEL_G_HT40PLUS:
21008 + case CHANNEL_G_HT40MINUS:
21009 + modesIndex = 3;
21010 + freqIndex = 2;
21011 + break;
21012 +
21013 + default:
21014 + return -EINVAL;
21015 + }
21016 +
21017 + for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
21018 + ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
21019 + ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
21020 + ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
21021 + ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
21022 + }
21023 +
21024 + REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
21025 + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
21026 +
21027 + /*
21028 + * For 5GHz channels requiring Fast Clock, apply
21029 + * different modal values.
21030 + */
21031 + if (IS_CHAN_A_5MHZ_SPACED(chan))
21032 + REG_WRITE_ARRAY(&ah->iniModesAdditional,
21033 + modesIndex, regWrites);
21034 +
21035 + ar9003_hw_override_ini(ah);
21036 + ar9003_hw_set_channel_regs(ah, chan);
21037 + ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
21038 +
21039 + /* Set TX power */
21040 + ah->eep_ops->set_txpower(ah, chan,
21041 + ath9k_regd_get_ctl(regulatory, chan),
21042 + channel->max_antenna_gain * 2,
21043 + channel->max_power * 2,
21044 + min((u32) MAX_RATE_POWER,
21045 + (u32) regulatory->power_limit));
21046 +
21047 + return 0;
21048 +}
21049 +
21050 +static void ar9003_hw_set_rfmode(struct ath_hw *ah,
21051 + struct ath9k_channel *chan)
21052 +{
21053 + u32 rfMode = 0;
21054 +
21055 + if (chan == NULL)
21056 + return;
21057 +
21058 + rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
21059 + ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
21060 +
21061 + if (IS_CHAN_A_5MHZ_SPACED(chan))
21062 + rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
21063 +
21064 + REG_WRITE(ah, AR_PHY_MODE, rfMode);
21065 +}
21066 +
21067 +static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
21068 +{
21069 + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
21070 +}
21071 +
21072 +static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
21073 + struct ath9k_channel *chan)
21074 +{
21075 + u32 coef_scaled, ds_coef_exp, ds_coef_man;
21076 + u32 clockMhzScaled = 0x64000000;
21077 + struct chan_centers centers;
21078 +
21079 + /*
21080 + * half and quarter rate can divide the scaled clock by 2 or 4
21081 + * scale for selected channel bandwidth
21082 + */
21083 + if (IS_CHAN_HALF_RATE(chan))
21084 + clockMhzScaled = clockMhzScaled >> 1;
21085 + else if (IS_CHAN_QUARTER_RATE(chan))
21086 + clockMhzScaled = clockMhzScaled >> 2;
21087 +
21088 + /*
21089 + * ALGO -> coef = 1e8/fcarrier*fclock/40;
21090 + * scaled coef to provide precision for this floating calculation
21091 + */
21092 + ath9k_hw_get_channel_centers(ah, chan, &centers);
21093 + coef_scaled = clockMhzScaled / centers.synth_center;
21094 +
21095 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
21096 + &ds_coef_exp);
21097 +
21098 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
21099 + AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
21100 + REG_RMW_FIELD(ah, AR_PHY_TIMING3,
21101 + AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
21102 +
21103 + /*
21104 + * For Short GI,
21105 + * scaled coeff is 9/10 that of normal coeff
21106 + */
21107 + coef_scaled = (9 * coef_scaled) / 10;
21108 +
21109 + ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
21110 + &ds_coef_exp);
21111 +
21112 + /* for short gi */
21113 + REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
21114 + AR_PHY_SGI_DSC_MAN, ds_coef_man);
21115 + REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
21116 + AR_PHY_SGI_DSC_EXP, ds_coef_exp);
21117 +}
21118 +
21119 +static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
21120 +{
21121 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
21122 + return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
21123 + AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
21124 +}
21125 +
21126 +/*
21127 + * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
21128 + * Read the phy active delay register. Value is in 100ns increments.
21129 + */
21130 +static void ar9003_hw_rfbus_done(struct ath_hw *ah)
21131 +{
21132 + u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
21133 + if (IS_CHAN_B(ah->curchan))
21134 + synthDelay = (4 * synthDelay) / 22;
21135 + else
21136 + synthDelay /= 10;
21137 +
21138 + udelay(synthDelay + BASE_ACTIVATE_DELAY);
21139 +
21140 + REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
21141 +}
21142 +
21143 +/*
21144 + * Set the interrupt and GPIO values so the ISR can disable RF
21145 + * on a switch signal. Assumes GPIO port and interrupt polarity
21146 + * are set prior to call.
21147 + */
21148 +static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
21149 +{
21150 + /* Connect rfsilent_bb_l to baseband */
21151 + REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
21152 + AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
21153 + /* Set input mux for rfsilent_bb_l to GPIO #0 */
21154 + REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
21155 + AR_GPIO_INPUT_MUX2_RFSILENT);
21156 +
21157 + /*
21158 + * Configure the desired GPIO port for input and
21159 + * enable baseband rf silence.
21160 + */
21161 + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
21162 + REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
21163 +}
21164 +
21165 +static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
21166 +{
21167 + u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
21168 + if (value)
21169 + v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
21170 + else
21171 + v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
21172 + REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
21173 +}
21174 +
21175 +static bool ar9003_hw_ani_control(struct ath_hw *ah,
21176 + enum ath9k_ani_cmd cmd, int param)
21177 +{
21178 + struct ar5416AniState *aniState = ah->curani;
21179 + struct ath_common *common = ath9k_hw_common(ah);
21180 +
21181 + switch (cmd & ah->ani_function) {
21182 + case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
21183 + u32 level = param;
21184 +
21185 + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
21186 + ath_print(common, ATH_DBG_ANI,
21187 + "level out of range (%u > %u)\n",
21188 + level,
21189 + (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
21190 + return false;
21191 + }
21192 +
21193 + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
21194 + AR_PHY_DESIRED_SZ_TOT_DES,
21195 + ah->totalSizeDesired[level]);
21196 + REG_RMW_FIELD(ah, AR_PHY_AGC,
21197 + AR_PHY_AGC_COARSE_LOW,
21198 + ah->coarse_low[level]);
21199 + REG_RMW_FIELD(ah, AR_PHY_AGC,
21200 + AR_PHY_AGC_COARSE_HIGH,
21201 + ah->coarse_high[level]);
21202 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
21203 + AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
21204 +
21205 + if (level > aniState->noiseImmunityLevel)
21206 + ah->stats.ast_ani_niup++;
21207 + else if (level < aniState->noiseImmunityLevel)
21208 + ah->stats.ast_ani_nidown++;
21209 + aniState->noiseImmunityLevel = level;
21210 + break;
21211 + }
21212 + case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
21213 + const int m1ThreshLow[] = { 127, 50 };
21214 + const int m2ThreshLow[] = { 127, 40 };
21215 + const int m1Thresh[] = { 127, 0x4d };
21216 + const int m2Thresh[] = { 127, 0x40 };
21217 + const int m2CountThr[] = { 31, 16 };
21218 + const int m2CountThrLow[] = { 63, 48 };
21219 + u32 on = param ? 1 : 0;
21220 +
21221 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
21222 + AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
21223 + m1ThreshLow[on]);
21224 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
21225 + AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
21226 + m2ThreshLow[on]);
21227 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
21228 + AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
21229 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
21230 + AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
21231 + REG_RMW_FIELD(ah, AR_PHY_SFCORR,
21232 + AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
21233 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
21234 + AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
21235 +
21236 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
21237 + AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
21238 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
21239 + AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
21240 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
21241 + AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
21242 + REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
21243 + AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
21244 +
21245 + if (on)
21246 + REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
21247 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
21248 + else
21249 + REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
21250 + AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
21251 +
21252 + if (!on != aniState->ofdmWeakSigDetectOff) {
21253 + if (on)
21254 + ah->stats.ast_ani_ofdmon++;
21255 + else
21256 + ah->stats.ast_ani_ofdmoff++;
21257 + aniState->ofdmWeakSigDetectOff = !on;
21258 + }
21259 + break;
21260 + }
21261 + case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
21262 + const int weakSigThrCck[] = { 8, 6 };
21263 + u32 high = param ? 1 : 0;
21264 +
21265 + REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
21266 + AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
21267 + weakSigThrCck[high]);
21268 + if (high != aniState->cckWeakSigThreshold) {
21269 + if (high)
21270 + ah->stats.ast_ani_cckhigh++;
21271 + else
21272 + ah->stats.ast_ani_ccklow++;
21273 + aniState->cckWeakSigThreshold = high;
21274 + }
21275 + break;
21276 + }
21277 + case ATH9K_ANI_FIRSTEP_LEVEL:{
21278 + const int firstep[] = { 0, 4, 8 };
21279 + u32 level = param;
21280 +
21281 + if (level >= ARRAY_SIZE(firstep)) {
21282 + ath_print(common, ATH_DBG_ANI,
21283 + "level out of range (%u > %u)\n",
21284 + level,
21285 + (unsigned) ARRAY_SIZE(firstep));
21286 + return false;
21287 + }
21288 + REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
21289 + AR_PHY_FIND_SIG_FIRSTEP,
21290 + firstep[level]);
21291 + if (level > aniState->firstepLevel)
21292 + ah->stats.ast_ani_stepup++;
21293 + else if (level < aniState->firstepLevel)
21294 + ah->stats.ast_ani_stepdown++;
21295 + aniState->firstepLevel = level;
21296 + break;
21297 + }
21298 + case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
21299 + const int cycpwrThr1[] =
21300 + { 2, 4, 6, 8, 10, 12, 14, 16 };
21301 + u32 level = param;
21302 +
21303 + if (level >= ARRAY_SIZE(cycpwrThr1)) {
21304 + ath_print(common, ATH_DBG_ANI,
21305 + "level out of range (%u > %u)\n",
21306 + level,
21307 + (unsigned) ARRAY_SIZE(cycpwrThr1));
21308 + return false;
21309 + }
21310 + REG_RMW_FIELD(ah, AR_PHY_TIMING5,
21311 + AR_PHY_TIMING5_CYCPWR_THR1,
21312 + cycpwrThr1[level]);
21313 + if (level > aniState->spurImmunityLevel)
21314 + ah->stats.ast_ani_spurup++;
21315 + else if (level < aniState->spurImmunityLevel)
21316 + ah->stats.ast_ani_spurdown++;
21317 + aniState->spurImmunityLevel = level;
21318 + break;
21319 + }
21320 + case ATH9K_ANI_PRESENT:
21321 + break;
21322 + default:
21323 + ath_print(common, ATH_DBG_ANI,
21324 + "invalid cmd %u\n", cmd);
21325 + return false;
21326 + }
21327 +
21328 + ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
21329 + ath_print(common, ATH_DBG_ANI,
21330 + "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
21331 + "ofdmWeakSigDetectOff=%d\n",
21332 + aniState->noiseImmunityLevel,
21333 + aniState->spurImmunityLevel,
21334 + !aniState->ofdmWeakSigDetectOff);
21335 + ath_print(common, ATH_DBG_ANI,
21336 + "cckWeakSigThreshold=%d, "
21337 + "firstepLevel=%d, listenTime=%d\n",
21338 + aniState->cckWeakSigThreshold,
21339 + aniState->firstepLevel,
21340 + aniState->listenTime);
21341 + ath_print(common, ATH_DBG_ANI,
21342 + "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
21343 + aniState->cycleCount,
21344 + aniState->ofdmPhyErrCount,
21345 + aniState->cckPhyErrCount);
21346 +
21347 + return true;
21348 +}
21349 +
21350 +static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
21351 +{
21352 + struct ath_common *common = ath9k_hw_common(ah);
21353 +
21354 + if (*nf > ah->nf_2g_max) {
21355 + ath_print(common, ATH_DBG_CALIBRATE,
21356 + "2 GHz NF (%d) > MAX (%d), "
21357 + "correcting to MAX",
21358 + *nf, ah->nf_2g_max);
21359 + *nf = ah->nf_2g_max;
21360 + } else if (*nf < ah->nf_2g_min) {
21361 + ath_print(common, ATH_DBG_CALIBRATE,
21362 + "2 GHz NF (%d) < MIN (%d), "
21363 + "correcting to MIN",
21364 + *nf, ah->nf_2g_min);
21365 + *nf = ah->nf_2g_min;
21366 + }
21367 +}
21368 +
21369 +static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
21370 +{
21371 + struct ath_common *common = ath9k_hw_common(ah);
21372 +
21373 + if (*nf > ah->nf_5g_max) {
21374 + ath_print(common, ATH_DBG_CALIBRATE,
21375 + "5 GHz NF (%d) > MAX (%d), "
21376 + "correcting to MAX",
21377 + *nf, ah->nf_5g_max);
21378 + *nf = ah->nf_5g_max;
21379 + } else if (*nf < ah->nf_5g_min) {
21380 + ath_print(common, ATH_DBG_CALIBRATE,
21381 + "5 GHz NF (%d) < MIN (%d), "
21382 + "correcting to MIN",
21383 + *nf, ah->nf_5g_min);
21384 + *nf = ah->nf_5g_min;
21385 + }
21386 +}
21387 +
21388 +static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
21389 +{
21390 + if (IS_CHAN_2GHZ(ah->curchan))
21391 + ar9003_hw_nf_sanitize_2g(ah, nf);
21392 + else
21393 + ar9003_hw_nf_sanitize_5g(ah, nf);
21394 +}
21395 +
21396 +static void ar9003_hw_do_getnf(struct ath_hw *ah,
21397 + int16_t nfarray[NUM_NF_READINGS])
21398 +{
21399 + struct ath_common *common = ath9k_hw_common(ah);
21400 + int16_t nf;
21401 +
21402 + nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
21403 + if (nf & 0x100)
21404 + nf = 0 - ((nf ^ 0x1ff) + 1);
21405 + ar9003_hw_nf_sanitize(ah, &nf);
21406 + ath_print(common, ATH_DBG_CALIBRATE,
21407 + "NF calibrated [ctl] [chain 0] is %d\n", nf);
21408 + nfarray[0] = nf;
21409 +
21410 + nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
21411 + if (nf & 0x100)
21412 + nf = 0 - ((nf ^ 0x1ff) + 1);
21413 + ar9003_hw_nf_sanitize(ah, &nf);
21414 + ath_print(common, ATH_DBG_CALIBRATE,
21415 + "NF calibrated [ctl] [chain 1] is %d\n", nf);
21416 + nfarray[1] = nf;
21417 +
21418 + nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
21419 + if (nf & 0x100)
21420 + nf = 0 - ((nf ^ 0x1ff) + 1);
21421 + ar9003_hw_nf_sanitize(ah, &nf);
21422 + ath_print(common, ATH_DBG_CALIBRATE,
21423 + "NF calibrated [ctl] [chain 2] is %d\n", nf);
21424 + nfarray[2] = nf;
21425 +
21426 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
21427 + if (nf & 0x100)
21428 + nf = 0 - ((nf ^ 0x1ff) + 1);
21429 + ar9003_hw_nf_sanitize(ah, &nf);
21430 + ath_print(common, ATH_DBG_CALIBRATE,
21431 + "NF calibrated [ext] [chain 0] is %d\n", nf);
21432 + nfarray[3] = nf;
21433 +
21434 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
21435 + if (nf & 0x100)
21436 + nf = 0 - ((nf ^ 0x1ff) + 1);
21437 + ar9003_hw_nf_sanitize(ah, &nf);
21438 + ath_print(common, ATH_DBG_CALIBRATE,
21439 + "NF calibrated [ext] [chain 1] is %d\n", nf);
21440 + nfarray[4] = nf;
21441 +
21442 + nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
21443 + if (nf & 0x100)
21444 + nf = 0 - ((nf ^ 0x1ff) + 1);
21445 + ar9003_hw_nf_sanitize(ah, &nf);
21446 + ath_print(common, ATH_DBG_CALIBRATE,
21447 + "NF calibrated [ext] [chain 2] is %d\n", nf);
21448 + nfarray[5] = nf;
21449 +}
21450 +
21451 +void ar9003_hw_set_nf_limits(struct ath_hw *ah)
21452 +{
21453 + ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
21454 + ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
21455 + ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
21456 + ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
21457 +}
21458 +
21459 +/*
21460 + * Find out which of the RX chains are enabled
21461 + */
21462 +static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
21463 +{
21464 + u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
21465 + /*
21466 + * The bits [2:0] indicate the rx chain mask and are to be
21467 + * interpreted as follows:
21468 + * 00x => Only chain 0 is enabled
21469 + * 01x => Chain 1 and 0 enabled
21470 + * 1xx => Chain 2,1 and 0 enabled
21471 + */
21472 + return (chain & 0x7);
21473 +}
21474 +
21475 +static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
21476 +{
21477 + struct ath9k_nfcal_hist *h;
21478 + unsigned i, j;
21479 + int32_t val;
21480 + const u32 ar9300_cca_regs[6] = {
21481 + AR_PHY_CCA_0,
21482 + AR_PHY_CCA_1,
21483 + AR_PHY_CCA_2,
21484 + AR_PHY_EXT_CCA,
21485 + AR_PHY_EXT_CCA_1,
21486 + AR_PHY_EXT_CCA_2,
21487 + };
21488 + u8 chainmask, rx_chain_status;
21489 + struct ath_common *common = ath9k_hw_common(ah);
21490 +
21491 + rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
21492 +
21493 + chainmask = 0x3F;
21494 + h = ah->nfCalHist;
21495 +
21496 + for (i = 0; i < NUM_NF_READINGS; i++) {
21497 + if (chainmask & (1 << i)) {
21498 + val = REG_READ(ah, ar9300_cca_regs[i]);
21499 + val &= 0xFFFFFE00;
21500 + val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
21501 + REG_WRITE(ah, ar9300_cca_regs[i], val);
21502 + }
21503 + }
21504 +
21505 + /*
21506 + * Load software filtered NF value into baseband internal minCCApwr
21507 + * variable.
21508 + */
21509 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
21510 + AR_PHY_AGC_CONTROL_ENABLE_NF);
21511 + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
21512 + AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
21513 + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
21514 +
21515 + /*
21516 + * Wait for load to complete, should be fast, a few 10s of us.
21517 + * The max delay was changed from an original 250us to 10000us
21518 + * since 250us often results in NF load timeout and causes deaf
21519 + * condition during stress testing 12/12/2009
21520 + */
21521 + for (j = 0; j < 1000; j++) {
21522 + if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
21523 + AR_PHY_AGC_CONTROL_NF) == 0)
21524 + break;
21525 + udelay(10);
21526 + }
21527 +
21528 + /*
21529 + * We timed out waiting for the noisefloor to load, probably due to an
21530 + * in-progress rx. Simply return here and allow the load plenty of time
21531 + * to complete before the next calibration interval. We need to avoid
21532 + * trying to load -50 (which happens below) while the previous load is
21533 + * still in progress as this can cause rx deafness. Instead by returning
21534 + * here, the baseband nf cal will just be capped by our present
21535 + * noisefloor until the next calibration timer.
21536 + */
21537 + if (j == 1000) {
21538 + ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
21539 + "to load: AR_PHY_AGC_CONTROL=0x%x\n",
21540 + REG_READ(ah, AR_PHY_AGC_CONTROL));
21541 + }
21542 +
21543 + /*
21544 + * Restore maxCCAPower register parameter again so that we're not capped
21545 + * by the median we just loaded. This will be initial (and max) value
21546 + * of next noise floor calibration the baseband does.
21547 + */
21548 + for (i = 0; i < NUM_NF_READINGS; i++) {
21549 + if (chainmask & (1 << i)) {
21550 + val = REG_READ(ah, ar9300_cca_regs[i]);
21551 + val &= 0xFFFFFE00;
21552 + val |= (((u32) (-50) << 1) & 0x1ff);
21553 + REG_WRITE(ah, ar9300_cca_regs[i], val);
21554 + }
21555 + }
21556 +}
21557 +
21558 +void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
21559 +{
21560 + struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
21561 +
21562 + priv_ops->rf_set_freq = ar9003_hw_set_channel;
21563 + priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
21564 + priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
21565 + priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
21566 + priv_ops->init_bb = ar9003_hw_init_bb;
21567 + priv_ops->process_ini = ar9003_hw_process_ini;
21568 + priv_ops->set_rfmode = ar9003_hw_set_rfmode;
21569 + priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
21570 + priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
21571 + priv_ops->rfbus_req = ar9003_hw_rfbus_req;
21572 + priv_ops->rfbus_done = ar9003_hw_rfbus_done;
21573 + priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
21574 + priv_ops->set_diversity = ar9003_hw_set_diversity;
21575 + priv_ops->ani_control = ar9003_hw_ani_control;
21576 + priv_ops->do_getnf = ar9003_hw_do_getnf;
21577 + priv_ops->loadnf = ar9003_hw_loadnf;
21578 +}
21579 --- /dev/null
21580 +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
21581 @@ -0,0 +1,847 @@
21582 +/*
21583 + * Copyright (c) 2002-2010 Atheros Communications, Inc.
21584 + *
21585 + * Permission to use, copy, modify, and/or distribute this software for any
21586 + * purpose with or without fee is hereby granted, provided that the above
21587 + * copyright notice and this permission notice appear in all copies.
21588 + *
21589 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
21590 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
21591 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
21592 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
21593 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
21594 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21595 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21596 + */
21597 +
21598 +#ifndef AR9003_PHY_H
21599 +#define AR9003_PHY_H
21600 +
21601 +/*
21602 + * Channel Register Map
21603 + */
21604 +#define AR_CHAN_BASE 0x9800
21605 +
21606 +#define AR_PHY_TIMING1 AR_CHAN_BASE + 0x0
21607 +#define AR_PHY_TIMING2 AR_CHAN_BASE + 0x4
21608 +#define AR_PHY_TIMING3 AR_CHAN_BASE + 0x8
21609 +#define AR_PHY_TIMING4 AR_CHAN_BASE + 0xc
21610 +#define AR_PHY_TIMING5 AR_CHAN_BASE + 0x10
21611 +#define AR_PHY_TIMING6 AR_CHAN_BASE + 0x14
21612 +#define AR_PHY_TIMING11 AR_CHAN_BASE + 0x18
21613 +#define AR_PHY_SPUR_REG AR_CHAN_BASE + 0x1c
21614 +#define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_BASE + 0xdc
21615 +#define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_BASE + 0xb0
21616 +
21617 +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
21618 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
21619 +
21620 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
21621 +#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
21622 +
21623 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
21624 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
21625 +
21626 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
21627 +#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
21628 +
21629 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
21630 +#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
21631 +
21632 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
21633 +#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
21634 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
21635 +#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
21636 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
21637 +#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
21638 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
21639 +#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
21640 +
21641 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
21642 +#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
21643 +
21644 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
21645 +#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
21646 +
21647 +#define AR_PHY_FIND_SIG_LOW AR_CHAN_BASE + 0x20
21648 +
21649 +#define AR_PHY_SFCORR AR_CHAN_BASE + 0x24
21650 +#define AR_PHY_SFCORR_LOW AR_CHAN_BASE + 0x28
21651 +#define AR_PHY_SFCORR_EXT AR_CHAN_BASE + 0x2c
21652 +
21653 +#define AR_PHY_EXT_CCA AR_CHAN_BASE + 0x30
21654 +#define AR_PHY_RADAR_0 AR_CHAN_BASE + 0x34
21655 +#define AR_PHY_RADAR_1 AR_CHAN_BASE + 0x38
21656 +#define AR_PHY_RADAR_EXT AR_CHAN_BASE + 0x3c
21657 +#define AR_PHY_MULTICHAIN_CTRL AR_CHAN_BASE + 0x80
21658 +#define AR_PHY_PERCHAIN_CSD AR_CHAN_BASE + 0x84
21659 +
21660 +#define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_BASE + 0xd0
21661 +#define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_BASE + 0xd4
21662 +#define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_BASE + 0xc0
21663 +#define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_BASE + 0xc4
21664 +#define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_BASE + 0xc8
21665 +#define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_BASE + 0xcc
21666 +
21667 +/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
21668 +#define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
21669 +#define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
21670 +#define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
21671 +#define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
21672 +#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
21673 +#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
21674 +
21675 +#define AR_PHY_TX_CRC AR_CHAN_BASE + 0xa0
21676 +#define AR_PHY_TST_DAC_CONST AR_CHAN_BASE + 0xa4
21677 +#define AR_PHY_SPUR_REPORT_0 AR_CHAN_BASE + 0xa8
21678 +#define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_BASE + 0x300
21679 +
21680 +/*
21681 + * Channel Field Definitions
21682 + */
21683 +#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
21684 +#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
21685 +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
21686 +#define AR_PHY_TIMING3_DSC_MAN_S 17
21687 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
21688 +#define AR_PHY_TIMING3_DSC_EXP_S 13
21689 +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
21690 +#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
21691 +#define AR_PHY_TIMING4_DO_CAL 0x10000
21692 +
21693 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
21694 +#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
21695 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
21696 +#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
21697 +
21698 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
21699 +#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
21700 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
21701 +#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
21702 +
21703 +#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
21704 +#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
21705 +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
21706 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
21707 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
21708 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
21709 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
21710 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
21711 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
21712 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
21713 +#define AR_PHY_SFCORR_M2COUNT_THR_S 0
21714 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
21715 +#define AR_PHY_SFCORR_M1_THRESH_S 17
21716 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
21717 +#define AR_PHY_SFCORR_M2_THRESH_S 24
21718 +#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
21719 +#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
21720 +#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
21721 +#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
21722 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
21723 +#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
21724 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
21725 +#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
21726 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
21727 +#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
21728 +#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
21729 +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
21730 +#define AR_PHY_EXT_CCA_THRESH62_S 16
21731 +#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
21732 +#define AR_PHY_EXT_MINCCA_PWR_S 16
21733 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
21734 +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
21735 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
21736 +#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
21737 +#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
21738 +#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
21739 +#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
21740 +#define AR_PHY_TIMING5_RSSI_THR1A_S 16
21741 +#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
21742 +#define AR_PHY_RADAR_0_ENA 0x00000001
21743 +#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
21744 +#define AR_PHY_RADAR_0_INBAND 0x0000003e
21745 +#define AR_PHY_RADAR_0_INBAND_S 1
21746 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
21747 +#define AR_PHY_RADAR_0_PRSSI_S 6
21748 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
21749 +#define AR_PHY_RADAR_0_HEIGHT_S 12
21750 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
21751 +#define AR_PHY_RADAR_0_RRSSI_S 18
21752 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
21753 +#define AR_PHY_RADAR_0_FIRPWR_S 24
21754 +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
21755 +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
21756 +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
21757 +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
21758 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
21759 +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
21760 +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
21761 +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
21762 +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
21763 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
21764 +#define AR_PHY_RADAR_1_MAXLEN_S 0
21765 +#define AR_PHY_RADAR_EXT_ENA 0x00004000
21766 +#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
21767 +#define AR_PHY_RADAR_DC_PWR_THRESH_S 15
21768 +#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
21769 +#define AR_PHY_RADAR_LB_DC_CAP_S 23
21770 +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
21771 +#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
21772 +#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
21773 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
21774 +#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
21775 +#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
21776 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
21777 +#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
21778 +#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
21779 +#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
21780 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
21781 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
21782 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
21783 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
21784 +#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
21785 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
21786 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
21787 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
21788 +#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
21789 +
21790 +/*
21791 + * MRC Register Map
21792 + */
21793 +#define AR_MRC_BASE 0x9c00
21794 +
21795 +#define AR_PHY_TIMING_3A AR_MRC_BASE + 0x0
21796 +#define AR_PHY_LDPC_CNTL1 AR_MRC_BASE + 0x4
21797 +#define AR_PHY_LDPC_CNTL2 AR_MRC_BASE + 0x8
21798 +#define AR_PHY_PILOT_SPUR_MASK AR_MRC_BASE + 0xc
21799 +#define AR_PHY_CHAN_SPUR_MASK AR_MRC_BASE + 0x10
21800 +#define AR_PHY_SGI_DELTA AR_MRC_BASE + 0x14
21801 +#define AR_PHY_ML_CNTL_1 AR_MRC_BASE + 0x18
21802 +#define AR_PHY_ML_CNTL_2 AR_MRC_BASE + 0x1c
21803 +#define AR_PHY_TST_ADC AR_MRC_BASE + 0x20
21804 +
21805 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
21806 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
21807 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
21808 +#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
21809 +
21810 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
21811 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
21812 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
21813 +#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
21814 +
21815 +/*
21816 + * MRC Feild Definitions
21817 + */
21818 +#define AR_PHY_SGI_DSC_MAN 0x0007FFF0
21819 +#define AR_PHY_SGI_DSC_MAN_S 4
21820 +#define AR_PHY_SGI_DSC_EXP 0x0000000F
21821 +#define AR_PHY_SGI_DSC_EXP_S 0
21822 +/*
21823 + * BBB Register Map
21824 + */
21825 +#define AR_BBB_BASE 0x9d00
21826 +
21827 +/*
21828 + * AGC Register Map
21829 + */
21830 +#define AR_AGC_BASE 0x9e00
21831 +
21832 +#define AR_PHY_SETTLING AR_AGC_BASE + 0x0
21833 +#define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_BASE + 0x4
21834 +#define AR_PHY_GAINS_MINOFF0 AR_AGC_BASE + 0x8
21835 +#define AR_PHY_DESIRED_SZ AR_AGC_BASE + 0xc
21836 +#define AR_PHY_FIND_SIG AR_AGC_BASE + 0x10
21837 +#define AR_PHY_AGC AR_AGC_BASE + 0x14
21838 +#define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_BASE + 0x18
21839 +#define AR_PHY_CCA_0 AR_AGC_BASE + 0x1c
21840 +#define AR_PHY_EXT_CCA0 AR_AGC_BASE + 0x20
21841 +#define AR_PHY_RESTART AR_AGC_BASE + 0x24
21842 +#define AR_PHY_MC_GAIN_CTRL AR_AGC_BASE + 0x28
21843 +#define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_BASE + 0x2c
21844 +#define AR_PHY_EXT_CHN_WIN AR_AGC_BASE + 0x30
21845 +#define AR_PHY_20_40_DET_THR AR_AGC_BASE + 0x34
21846 +#define AR_PHY_RIFS_SRCH AR_AGC_BASE + 0x38
21847 +#define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_BASE + 0x3c
21848 +#define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_BASE + 0x40
21849 +#define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_BASE + 0x44
21850 +#define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_BASE + 0x48
21851 +#define AR_PHY_RSSI_0 AR_AGC_BASE + 0x180
21852 +#define AR_PHY_SPUR_CCK_REP0 AR_AGC_BASE + 0x184
21853 +#define AR_PHY_CCK_DETECT AR_AGC_BASE + 0x1c0
21854 +#define AR_PHY_DAG_CTRLCCK AR_AGC_BASE + 0x1c4
21855 +#define AR_PHY_IQCORR_CTRL_CCK AR_AGC_BASE + 0x1c8
21856 +
21857 +#define AR_PHY_CCK_SPUR_MIT AR_AGC_BASE + 0x1cc
21858 +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
21859 +#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
21860 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
21861 +#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
21862 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
21863 +#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
21864 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
21865 +#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
21866 +
21867 +#define AR_PHY_RX_OCGAIN AR_AGC_BASE + 0x200
21868 +
21869 +#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
21870 +#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
21871 +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
21872 +#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
21873 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
21874 +#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
21875 +
21876 +/*
21877 + * AGC Field Definitions
21878 + */
21879 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
21880 +#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
21881 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
21882 +#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
21883 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
21884 +#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
21885 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
21886 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
21887 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
21888 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
21889 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
21890 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
21891 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
21892 +#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
21893 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
21894 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
21895 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
21896 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
21897 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
21898 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
21899 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
21900 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
21901 +#define AR_PHY_SETTLING_SWITCH 0x00003F80
21902 +#define AR_PHY_SETTLING_SWITCH_S 7
21903 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
21904 +#define AR_PHY_DESIRED_SZ_ADC_S 0
21905 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
21906 +#define AR_PHY_DESIRED_SZ_PGA_S 8
21907 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
21908 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
21909 +#define AR_PHY_MINCCA_PWR 0x1FF00000
21910 +#define AR_PHY_MINCCA_PWR_S 20
21911 +#define AR_PHY_CCA_THRESH62 0x0007F000
21912 +#define AR_PHY_CCA_THRESH62_S 12
21913 +#define AR9280_PHY_MINCCA_PWR 0x1FF00000
21914 +#define AR9280_PHY_MINCCA_PWR_S 20
21915 +#define AR9280_PHY_CCA_THRESH62 0x000FF000
21916 +#define AR9280_PHY_CCA_THRESH62_S 12
21917 +#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
21918 +#define AR_PHY_EXT_CCA0_THRESH62_S 0
21919 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
21920 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
21921 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
21922 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
21923 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
21924 +
21925 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
21926 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
21927 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
21928 +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
21929 +
21930 +#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
21931 +#define AR_PHY_AGC_COARSE_LOW 0x00007F80
21932 +#define AR_PHY_AGC_COARSE_LOW_S 7
21933 +#define AR_PHY_AGC_COARSE_HIGH 0x003F8000
21934 +#define AR_PHY_AGC_COARSE_HIGH_S 15
21935 +#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
21936 +#define AR_PHY_AGC_COARSE_PWR_CONST_S 0
21937 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
21938 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12
21939 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
21940 +#define AR_PHY_FIND_SIG_FIRPWR_S 18
21941 +#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
21942 +#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
21943 +#define AR_PHY_FIND_SIG_RELPWR_S 6
21944 +#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
21945 +#define AR_PHY_FIND_SIG_RELSTEP 0x1f
21946 +#define AR_PHY_FIND_SIG_RELSTEP_S 0
21947 +#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
21948 +#define AR_PHY_RESTART_DIV_GC 0x001C0000
21949 +#define AR_PHY_RESTART_DIV_GC_S 18
21950 +#define AR_PHY_RESTART_ENA 0x01
21951 +#define AR_PHY_DC_RESTART_DIS 0x40000000
21952 +
21953 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
21954 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
21955 +#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
21956 +#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
21957 +
21958 +#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
21959 +#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
21960 +
21961 +/*
21962 + * SM Register Map
21963 + */
21964 +#define AR_SM_BASE 0xa200
21965 +
21966 +#define AR_PHY_D2_CHIP_ID AR_SM_BASE + 0x0
21967 +#define AR_PHY_GEN_CTRL AR_SM_BASE + 0x4
21968 +#define AR_PHY_MODE AR_SM_BASE + 0x8
21969 +#define AR_PHY_ACTIVE AR_SM_BASE + 0xc
21970 +#define AR_PHY_SPUR_MASK_A AR_SM_BASE + 0x20
21971 +#define AR_PHY_SPUR_MASK_B AR_SM_BASE + 0x24
21972 +#define AR_PHY_SPECTRAL_SCAN AR_SM_BASE + 0x28
21973 +#define AR_PHY_RADAR_BW_FILTER AR_SM_BASE + 0x2c
21974 +#define AR_PHY_SEARCH_START_DELAY AR_SM_BASE + 0x30
21975 +#define AR_PHY_MAX_RX_LEN AR_SM_BASE + 0x34
21976 +#define AR_PHY_FRAME_CTL AR_SM_BASE + 0x38
21977 +#define AR_PHY_RFBUS_REQ AR_SM_BASE + 0x3c
21978 +#define AR_PHY_RFBUS_GRANT AR_SM_BASE + 0x40
21979 +#define AR_PHY_RIFS AR_SM_BASE + 0x44
21980 +#define AR_PHY_RX_CLR_DELAY AR_SM_BASE + 0x50
21981 +#define AR_PHY_RX_DELAY AR_SM_BASE + 0x54
21982 +
21983 +#define AR_PHY_XPA_TIMING_CTL AR_SM_BASE + 0x64
21984 +#define AR_PHY_MISC_PA_CTL AR_SM_BASE + 0x80
21985 +#define AR_PHY_SWITCH_CHAIN_0 AR_SM_BASE + 0x84
21986 +#define AR_PHY_SWITCH_COM AR_SM_BASE + 0x88
21987 +#define AR_PHY_SWITCH_COM_2 AR_SM_BASE + 0x8c
21988 +#define AR_PHY_RX_CHAINMASK AR_SM_BASE + 0xa0
21989 +#define AR_PHY_CAL_CHAINMASK AR_SM_BASE + 0xc0
21990 +#define AR_PHY_CALMODE AR_SM_BASE + 0xc8
21991 +#define AR_PHY_FCAL_1 AR_SM_BASE + 0xcc
21992 +#define AR_PHY_FCAL_2_0 AR_SM_BASE + 0xd0
21993 +#define AR_PHY_DFT_TONE_CTL_0 AR_SM_BASE + 0xd4
21994 +#define AR_PHY_CL_CAL_CTL AR_SM_BASE + 0xd8
21995 +#define AR_PHY_CL_TAB_0 AR_SM_BASE + 0x100
21996 +#define AR_PHY_SYNTH_CONTROL AR_SM_BASE + 0x140
21997 +#define AR_PHY_ADDAC_CLK_SEL AR_SM_BASE + 0x144
21998 +#define AR_PHY_PLL_CTL AR_SM_BASE + 0x148
21999 +#define AR_PHY_ANALOG_SWAP AR_SM_BASE + 0x14c
22000 +#define AR_PHY_ADDAC_PARA_CTL AR_SM_BASE + 0x150
22001 +#define AR_PHY_XPA_CFG AR_SM_BASE + 0x158
22002 +
22003 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
22004 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
22005 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
22006 +#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
22007 +
22008 +#define AR_PHY_TEST AR_SM_BASE + 0x160
22009 +
22010 +#define AR_PHY_TEST_BBB_OBS_SEL 0x780000
22011 +#define AR_PHY_TEST_BBB_OBS_SEL_S 19
22012 +
22013 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
22014 +#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
22015 +
22016 +#define AR_PHY_TEST_CHAIN_SEL 0xC0000000
22017 +#define AR_PHY_TEST_CHAIN_SEL_S 30
22018 +
22019 +#define AR_PHY_TEST_CTL_STATUS AR_SM_BASE + 0x164
22020 +#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
22021 +#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
22022 +#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
22023 +#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
22024 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
22025 +#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
22026 +#define AR_PHY_TEST_CTL_TSTADC_EN 0x100
22027 +#define AR_PHY_TEST_CTL_TSTADC_EN_S 8
22028 +#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
22029 +#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
22030 +
22031 +
22032 +#define AR_PHY_TSTDAC AR_SM_BASE + 0x168
22033 +
22034 +#define AR_PHY_CHAN_STATUS AR_SM_BASE + 0x16c
22035 +#define AR_PHY_CHAN_INFO_MEMORY AR_SM_BASE + 0x170
22036 +#define AR_PHY_CHNINFO_NOISEPWR AR_SM_BASE + 0x174
22037 +#define AR_PHY_CHNINFO_GAINDIFF AR_SM_BASE + 0x178
22038 +#define AR_PHY_CHNINFO_FINETIM AR_SM_BASE + 0x17c
22039 +#define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_BASE + 0x180
22040 +#define AR_PHY_SCRAMBLER_SEED AR_SM_BASE + 0x190
22041 +#define AR_PHY_CCK_TX_CTRL AR_SM_BASE + 0x194
22042 +
22043 +#define AR_PHY_HEAVYCLIP_CTL AR_SM_BASE + 0x1a4
22044 +#define AR_PHY_HEAVYCLIP_20 AR_SM_BASE + 0x1a8
22045 +#define AR_PHY_HEAVYCLIP_40 AR_SM_BASE + 0x1ac
22046 +#define AR_PHY_ILLEGAL_TXRATE AR_SM_BASE + 0x1b0
22047 +
22048 +#define AR_PHY_PWRTX_MAX AR_SM_BASE + 0x1f0
22049 +#define AR_PHY_POWER_TX_SUB AR_SM_BASE + 0x1f4
22050 +
22051 +#define AR_PHY_TPC_4_B0 AR_SM_BASE + 0x204
22052 +#define AR_PHY_TPC_5_B0 AR_SM_BASE + 0x208
22053 +#define AR_PHY_TPC_6_B0 AR_SM_BASE + 0x20c
22054 +#define AR_PHY_TPC_11_B0 AR_SM_BASE + 0x220
22055 +#define AR_PHY_TPC_18 AR_SM_BASE + 0x23c
22056 +#define AR_PHY_TPC_19 AR_SM_BASE + 0x240
22057 +
22058 +#define AR_PHY_TX_FORCED_GAIN AR_SM_BASE + 0x258
22059 +
22060 +#define AR_PHY_PDADC_TAB_0 AR_SM_BASE + 0x280
22061 +
22062 +#define AR_PHY_TX_IQCAL_CONTROL_1 AR_SM_BASE + 0x448
22063 +#define AR_PHY_TX_IQCAL_START AR_SM_BASE + 0x440
22064 +#define AR_PHY_TX_IQCAL_STATUS_B0 AR_SM_BASE + 0x48c
22065 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_BASE + 0x450
22066 +
22067 +#define AR_PHY_PANIC_WD_STATUS AR_SM_BASE + 0x5c0
22068 +#define AR_PHY_PANIC_WD_CTL_1 AR_SM_BASE + 0x5c4
22069 +#define AR_PHY_PANIC_WD_CTL_2 AR_SM_BASE + 0x5c8
22070 +#define AR_PHY_BT_CTL AR_SM_BASE + 0x5cc
22071 +#define AR_PHY_ONLY_WARMRESET AR_SM_BASE + 0x5d0
22072 +#define AR_PHY_ONLY_CTL AR_SM_BASE + 0x5d4
22073 +#define AR_PHY_ECO_CTRL AR_SM_BASE + 0x5dc
22074 +#define AR_PHY_BB_THERM_ADC_1 AR_SM_BASE + 0x248
22075 +
22076 +#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
22077 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
22078 +#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
22079 +#define AR_PHY_65NM_CH0_SYNTH7 0x16098
22080 +#define AR_PHY_65NM_CH0_BIAS1 0x160c0
22081 +#define AR_PHY_65NM_CH0_BIAS2 0x160c4
22082 +#define AR_PHY_65NM_CH0_BIAS4 0x160cc
22083 +#define AR_PHY_65NM_CH0_RXTX4 0x1610c
22084 +#define AR_PHY_65NM_CH0_THERM 0x16290
22085 +
22086 +#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
22087 +#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
22088 +#define AR_PHY_65NM_CH0_THERM_START 0x20000000
22089 +#define AR_PHY_65NM_CH0_THERM_START_S 29
22090 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
22091 +#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
22092 +
22093 +#define AR_PHY_65NM_CH0_RXTX1 0x16100
22094 +#define AR_PHY_65NM_CH0_RXTX2 0x16104
22095 +#define AR_PHY_65NM_CH1_RXTX1 0x16500
22096 +#define AR_PHY_65NM_CH1_RXTX2 0x16504
22097 +#define AR_PHY_65NM_CH2_RXTX1 0x16900
22098 +#define AR_PHY_65NM_CH2_RXTX2 0x16904
22099 +
22100 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
22101 +#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
22102 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
22103 +#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
22104 +#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
22105 +#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
22106 +#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
22107 +#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
22108 +#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
22109 +#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
22110 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
22111 +#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
22112 +#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
22113 +#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
22114 +
22115 +/*
22116 + * SM Field Definitions
22117 + */
22118 +#define AR_PHY_CL_CAL_ENABLE 0x00000002
22119 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
22120 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
22121 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
22122 +
22123 +#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
22124 +
22125 +#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
22126 +#define AR_PHY_FCAL20_CAP_STATUS_0_S 20
22127 +
22128 +#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
22129 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
22130 +#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
22131 +#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
22132 +#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
22133 +#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
22134 +#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
22135 +#define AR_PHY_GC_DYN2040_PRI_CH_S 4
22136 +#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
22137 +#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
22138 +#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
22139 +#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
22140 +#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
22141 +#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
22142 +#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
22143 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
22144 +
22145 +#define AR_PHY_CALMODE_IQ 0x00000000
22146 +#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
22147 +#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
22148 +#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
22149 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
22150 +#define AR_PHY_MODE_OFDM 0x00000000
22151 +#define AR_PHY_MODE_CCK 0x00000001
22152 +#define AR_PHY_MODE_DYNAMIC 0x00000004
22153 +#define AR_PHY_MODE_DYNAMIC_S 2
22154 +#define AR_PHY_MODE_HALF 0x00000020
22155 +#define AR_PHY_MODE_QUARTER 0x00000040
22156 +#define AR_PHY_MAC_CLK_MODE 0x00000080
22157 +#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
22158 +#define AR_PHY_MODE_SVD_HALF 0x00000200
22159 +#define AR_PHY_ACTIVE_EN 0x00000001
22160 +#define AR_PHY_ACTIVE_DIS 0x00000000
22161 +#define AR_PHY_FORCE_XPA_CFG 0x000000001
22162 +#define AR_PHY_FORCE_XPA_CFG_S 0
22163 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
22164 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
22165 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
22166 +#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
22167 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
22168 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
22169 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
22170 +#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
22171 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
22172 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
22173 +#define AR_PHY_TX_END_DATA_START 0x000000FF
22174 +#define AR_PHY_TX_END_DATA_START_S 0
22175 +#define AR_PHY_TX_END_PA_ON 0x0000FF00
22176 +#define AR_PHY_TX_END_PA_ON_S 8
22177 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
22178 +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
22179 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
22180 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
22181 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
22182 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
22183 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
22184 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
22185 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
22186 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
22187 +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
22188 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
22189 +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
22190 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
22191 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
22192 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
22193 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
22194 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
22195 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
22196 +#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
22197 +#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
22198 +#define AR_PHY_TXGAIN_FORCE 0x00000001
22199 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
22200 +#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
22201 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
22202 +#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
22203 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
22204 +#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
22205 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
22206 +#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
22207 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
22208 +#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
22209 +
22210 +#define AR_PHY_POWER_TX_RATE1 0x9934
22211 +#define AR_PHY_POWER_TX_RATE2 0x9938
22212 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c
22213 +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
22214 +#define PHY_AGC_CLR 0x10000000
22215 +#define RFSILENT_BB 0x00002000
22216 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
22217 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
22218 +#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
22219 +#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
22220 +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
22221 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
22222 +#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
22223 +#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
22224 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
22225 +#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
22226 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
22227 +#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
22228 +#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
22229 +#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
22230 +#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
22231 +#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
22232 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
22233 +#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
22234 +#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
22235 +#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
22236 +#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
22237 +#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
22238 +#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
22239 +
22240 +#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
22241 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
22242 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
22243 +
22244 +#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff
22245 +#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
22246 +#define AR_PHY_TPC_19_ALPHA_THERM 0xff
22247 +#define AR_PHY_TPC_19_ALPHA_THERM_S 0
22248 +
22249 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
22250 +#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
22251 +
22252 +#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
22253 +#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
22254 +
22255 +/*
22256 + * Channel 1 Register Map
22257 + */
22258 +#define AR_CHAN1_BASE 0xa800
22259 +
22260 +#define AR_PHY_EXT_CCA_1 AR_CHAN1_BASE + 0x30
22261 +#define AR_PHY_TX_PHASE_RAMP_1 AR_CHAN1_BASE + 0xd0
22262 +#define AR_PHY_ADC_GAIN_DC_CORR_1 AR_CHAN1_BASE + 0xd4
22263 +
22264 +#define AR_PHY_SPUR_REPORT_1 AR_CHAN1_BASE + 0xa8
22265 +#define AR_PHY_CHAN_INFO_TAB_1 AR_CHAN1_BASE + 0x300
22266 +#define AR_PHY_RX_IQCAL_CORR_B1 AR_CHAN1_BASE + 0xdc
22267 +
22268 +/*
22269 + * Channel 1 Field Definitions
22270 + */
22271 +#define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
22272 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
22273 +
22274 +/*
22275 + * AGC 1 Register Map
22276 + */
22277 +#define AR_AGC1_BASE 0xae00
22278 +
22279 +#define AR_PHY_FORCEMAX_GAINS_1 AR_AGC1_BASE + 0x4
22280 +#define AR_PHY_EXT_ATTEN_CTL_1 AR_AGC1_BASE + 0x18
22281 +#define AR_PHY_CCA_1 AR_AGC1_BASE + 0x1c
22282 +#define AR_PHY_CCA_CTRL_1 AR_AGC1_BASE + 0x20
22283 +#define AR_PHY_RSSI_1 AR_AGC1_BASE + 0x180
22284 +#define AR_PHY_SPUR_CCK_REP_1 AR_AGC1_BASE + 0x184
22285 +#define AR_PHY_RX_OCGAIN_2 AR_AGC1_BASE + 0x200
22286 +
22287 +/*
22288 + * AGC 1 Field Definitions
22289 + */
22290 +#define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
22291 +#define AR_PHY_CH1_MINCCA_PWR_S 20
22292 +
22293 +/*
22294 + * SM 1 Register Map
22295 + */
22296 +#define AR_SM1_BASE 0xb200
22297 +
22298 +#define AR_PHY_SWITCH_CHAIN_1 AR_SM1_BASE + 0x84
22299 +#define AR_PHY_FCAL_2_1 AR_SM1_BASE + 0xd0
22300 +#define AR_PHY_DFT_TONE_CTL_1 AR_SM1_BASE + 0xd4
22301 +#define AR_PHY_CL_TAB_1 AR_SM1_BASE + 0x100
22302 +#define AR_PHY_CHAN_INFO_GAIN_1 AR_SM1_BASE + 0x180
22303 +#define AR_PHY_TPC_4_B1 AR_SM1_BASE + 0x204
22304 +#define AR_PHY_TPC_5_B1 AR_SM1_BASE + 0x208
22305 +#define AR_PHY_TPC_6_B1 AR_SM1_BASE + 0x20c
22306 +#define AR_PHY_TPC_11_B1 AR_SM1_BASE + 0x220
22307 +#define AR_PHY_PDADC_TAB_1 AR_SM1_BASE + 0x240
22308 +#define AR_PHY_TX_IQCAL_STATUS_B1 AR_SM1_BASE + 0x48c
22309 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 AR_SM1_BASE + 0x450
22310 +
22311 +/*
22312 + * Channel 2 Register Map
22313 + */
22314 +#define AR_CHAN2_BASE 0xb800
22315 +
22316 +#define AR_PHY_EXT_CCA_2 AR_CHAN2_BASE + 0x30
22317 +#define AR_PHY_TX_PHASE_RAMP_2 AR_CHAN2_BASE + 0xd0
22318 +#define AR_PHY_ADC_GAIN_DC_CORR_2 AR_CHAN2_BASE + 0xd4
22319 +
22320 +#define AR_PHY_SPUR_REPORT_2 AR_CHAN2_BASE + 0xa8
22321 +#define AR_PHY_CHAN_INFO_TAB_2 AR_CHAN2_BASE + 0x300
22322 +#define AR_PHY_RX_IQCAL_CORR_B2 AR_CHAN2_BASE + 0xdc
22323 +
22324 +/*
22325 + * Channel 2 Field Definitions
22326 + */
22327 +#define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
22328 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
22329 +/*
22330 + * AGC 2 Register Map
22331 + */
22332 +#define AR_AGC2_BASE 0xbe00
22333 +
22334 +#define AR_PHY_FORCEMAX_GAINS_2 AR_AGC2_BASE + 0x4
22335 +#define AR_PHY_EXT_ATTEN_CTL_2 AR_AGC2_BASE + 0x18
22336 +#define AR_PHY_CCA_2 AR_AGC2_BASE + 0x1c
22337 +#define AR_PHY_CCA_CTRL_2 AR_AGC2_BASE + 0x20
22338 +#define AR_PHY_RSSI_2 AR_AGC2_BASE + 0x180
22339 +
22340 +/*
22341 + * AGC 2 Field Definitions
22342 + */
22343 +#define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
22344 +#define AR_PHY_CH2_MINCCA_PWR_S 20
22345 +
22346 +/*
22347 + * SM 2 Register Map
22348 + */
22349 +#define AR_SM2_BASE 0xc200
22350 +
22351 +#define AR_PHY_SWITCH_CHAIN_2 AR_SM2_BASE + 0x84
22352 +#define AR_PHY_FCAL_2_2 AR_SM2_BASE + 0xd0
22353 +#define AR_PHY_DFT_TONE_CTL_2 AR_SM2_BASE + 0xd4
22354 +#define AR_PHY_CL_TAB_2 AR_SM2_BASE + 0x100
22355 +#define AR_PHY_CHAN_INFO_GAIN_2 AR_SM2_BASE + 0x180
22356 +#define AR_PHY_TPC_4_B2 AR_SM2_BASE + 0x204
22357 +#define AR_PHY_TPC_5_B2 AR_SM2_BASE + 0x208
22358 +#define AR_PHY_TPC_6_B2 AR_SM2_BASE + 0x20c
22359 +#define AR_PHY_TPC_11_B2 AR_SM2_BASE + 0x220
22360 +#define AR_PHY_PDADC_TAB_2 AR_SM2_BASE + 0x240
22361 +#define AR_PHY_TX_IQCAL_STATUS_B2 AR_SM2_BASE + 0x48c
22362 +#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 AR_SM2_BASE + 0x450
22363 +
22364 +#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
22365 +
22366 +/*
22367 + * AGC 3 Register Map
22368 + */
22369 +#define AR_AGC3_BASE 0xce00
22370 +
22371 +#define AR_PHY_RSSI_3 AR_AGC3_BASE + 0x180
22372 +
22373 +/*
22374 + * Misc helper defines
22375 + */
22376 +#define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
22377 +
22378 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22379 +#define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22380 +#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22381 +#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22382 +
22383 +#define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22384 +#define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22385 +#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22386 +
22387 +#define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22388 +#define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22389 +#define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22390 +#define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
22391 +#define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22392 +#define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22393 +#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22394 +#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
22395 +
22396 +#define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001
22397 +#define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002
22398 +#define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000
22399 +#define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC
22400 +
22401 +#define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002
22402 +#define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004
22403 +#define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9
22404 +
22405 +#define AR_PHY_BB_WD_STATUS 0x00000007
22406 +#define AR_PHY_BB_WD_STATUS_S 0
22407 +#define AR_PHY_BB_WD_DET_HANG 0x00000008
22408 +#define AR_PHY_BB_WD_DET_HANG_S 3
22409 +#define AR_PHY_BB_WD_RADAR_SM 0x000000F0
22410 +#define AR_PHY_BB_WD_RADAR_SM_S 4
22411 +#define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00
22412 +#define AR_PHY_BB_WD_RX_OFDM_SM_S 8
22413 +#define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000
22414 +#define AR_PHY_BB_WD_RX_CCK_SM_S 12
22415 +#define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000
22416 +#define AR_PHY_BB_WD_TX_OFDM_SM_S 16
22417 +#define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000
22418 +#define AR_PHY_BB_WD_TX_CCK_SM_S 20
22419 +#define AR_PHY_BB_WD_AGC_SM 0x0F000000
22420 +#define AR_PHY_BB_WD_AGC_SM_S 24
22421 +#define AR_PHY_BB_WD_SRCH_SM 0xF0000000
22422 +#define AR_PHY_BB_WD_SRCH_SM_S 28
22423 +
22424 +#define AR_PHY_BB_WD_STATUS_CLR 0x00000008
22425 +
22426 +void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
22427 +
22428 +#endif /* AR9003_PHY_H */
22429 --- a/drivers/net/wireless/ath/ath9k/ath9k.h
22430 +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
22431 @@ -114,8 +114,10 @@ enum buffer_type {
22432 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
22433 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
22434
22435 +#define ATH_TXSTATUS_RING_SIZE 64
22436 +
22437 struct ath_descdma {
22438 - struct ath_desc *dd_desc;
22439 + void *dd_desc;
22440 dma_addr_t dd_desc_paddr;
22441 u32 dd_desc_len;
22442 struct ath_buf *dd_bufptr;
22443 @@ -123,7 +125,7 @@ struct ath_descdma {
22444
22445 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
22446 struct list_head *head, const char *name,
22447 - int nbuf, int ndesc);
22448 + int nbuf, int ndesc, bool is_tx);
22449 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
22450 struct list_head *head);
22451
22452 @@ -188,6 +190,7 @@ enum ATH_AGGR_STATUS {
22453 ATH_AGGR_LIMITED,
22454 };
22455
22456 +#define ATH_TXFIFO_DEPTH 8
22457 struct ath_txq {
22458 u32 axq_qnum;
22459 u32 *axq_link;
22460 @@ -197,6 +200,10 @@ struct ath_txq {
22461 bool stopped;
22462 bool axq_tx_inprogress;
22463 struct list_head axq_acq;
22464 + struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
22465 + struct list_head txq_fifo_pending;
22466 + u8 txq_headidx;
22467 + u8 txq_tailidx;
22468 };
22469
22470 #define AGGR_CLEANUP BIT(1)
22471 @@ -223,6 +230,12 @@ struct ath_tx {
22472 struct ath_descdma txdma;
22473 };
22474
22475 +struct ath_rx_edma {
22476 + struct sk_buff_head rx_fifo;
22477 + struct sk_buff_head rx_buffers;
22478 + u32 rx_fifo_hwsize;
22479 +};
22480 +
22481 struct ath_rx {
22482 u8 defant;
22483 u8 rxotherant;
22484 @@ -232,6 +245,8 @@ struct ath_rx {
22485 spinlock_t rxbuflock;
22486 struct list_head rxbuf;
22487 struct ath_descdma rxdma;
22488 + struct ath_buf *rx_bufptr;
22489 + struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
22490 };
22491
22492 int ath_startrecv(struct ath_softc *sc);
22493 @@ -240,7 +255,7 @@ void ath_flushrecv(struct ath_softc *sc)
22494 u32 ath_calcrxfilter(struct ath_softc *sc);
22495 int ath_rx_init(struct ath_softc *sc, int nbufs);
22496 void ath_rx_cleanup(struct ath_softc *sc);
22497 -int ath_rx_tasklet(struct ath_softc *sc, int flush);
22498 +int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
22499 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
22500 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
22501 int ath_tx_setup(struct ath_softc *sc, int haltype);
22502 @@ -258,6 +273,7 @@ int ath_txq_update(struct ath_softc *sc,
22503 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
22504 struct ath_tx_control *txctl);
22505 void ath_tx_tasklet(struct ath_softc *sc);
22506 +void ath_tx_edma_tasklet(struct ath_softc *sc);
22507 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
22508 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
22509 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
22510 @@ -507,6 +523,8 @@ struct ath_softc {
22511 struct ath_beacon_config cur_beacon_conf;
22512 struct delayed_work tx_complete_work;
22513 struct ath_btcoex btcoex;
22514 +
22515 + struct ath_descdma txsdma;
22516 };
22517
22518 struct ath_wiphy {
22519 --- a/drivers/net/wireless/ath/ath9k/beacon.c
22520 +++ b/drivers/net/wireless/ath/ath9k/beacon.c
22521 @@ -93,8 +93,6 @@ static void ath_beacon_setup(struct ath_
22522 antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
22523 }
22524
22525 - ds->ds_data = bf->bf_buf_addr;
22526 -
22527 sband = &sc->sbands[common->hw->conf.channel->band];
22528 rate = sband->bitrates[rateidx].hw_value;
22529 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
22530 @@ -109,7 +107,8 @@ static void ath_beacon_setup(struct ath_
22531
22532 /* NB: beacon's BufLen must be a multiple of 4 bytes */
22533 ath9k_hw_filltxdesc(ah, ds, roundup(skb->len, 4),
22534 - true, true, ds);
22535 + true, true, ds, bf->bf_buf_addr,
22536 + sc->beacon.beaconq);
22537
22538 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
22539 series[0].Tries = 1;
22540 --- a/drivers/net/wireless/ath/ath9k/calib.c
22541 +++ b/drivers/net/wireless/ath/ath9k/calib.c
22542 @@ -15,10 +15,12 @@
22543 */
22544
22545 #include "hw.h"
22546 +#include "hw-ops.h"
22547 +
22548 +/* Common calibration code */
22549
22550 /* We can tune this as we go by monitoring really low values */
22551 #define ATH9K_NF_TOO_LOW -60
22552 -#define AR9285_CLCAL_REDO_THRESH 1
22553
22554 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
22555 * is incorrect and we should use the static NF value. Later we can try to
22556 @@ -87,98 +89,9 @@ static void ath9k_hw_update_nfcal_hist_b
22557 return;
22558 }
22559
22560 -static void ath9k_hw_do_getnf(struct ath_hw *ah,
22561 - int16_t nfarray[NUM_NF_READINGS])
22562 -{
22563 - struct ath_common *common = ath9k_hw_common(ah);
22564 - int16_t nf;
22565 -
22566 - if (AR_SREV_9280_10_OR_LATER(ah))
22567 - nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
22568 - else
22569 - nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
22570 -
22571 - if (nf & 0x100)
22572 - nf = 0 - ((nf ^ 0x1ff) + 1);
22573 - ath_print(common, ATH_DBG_CALIBRATE,
22574 - "NF calibrated [ctl] [chain 0] is %d\n", nf);
22575 -
22576 - if (AR_SREV_9271(ah) && (nf >= -114))
22577 - nf = -116;
22578 -
22579 - nfarray[0] = nf;
22580 -
22581 - if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
22582 - if (AR_SREV_9280_10_OR_LATER(ah))
22583 - nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
22584 - AR9280_PHY_CH1_MINCCA_PWR);
22585 - else
22586 - nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
22587 - AR_PHY_CH1_MINCCA_PWR);
22588 -
22589 - if (nf & 0x100)
22590 - nf = 0 - ((nf ^ 0x1ff) + 1);
22591 - ath_print(common, ATH_DBG_CALIBRATE,
22592 - "NF calibrated [ctl] [chain 1] is %d\n", nf);
22593 - nfarray[1] = nf;
22594 -
22595 - if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
22596 - nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
22597 - AR_PHY_CH2_MINCCA_PWR);
22598 - if (nf & 0x100)
22599 - nf = 0 - ((nf ^ 0x1ff) + 1);
22600 - ath_print(common, ATH_DBG_CALIBRATE,
22601 - "NF calibrated [ctl] [chain 2] is %d\n", nf);
22602 - nfarray[2] = nf;
22603 - }
22604 - }
22605 -
22606 - if (AR_SREV_9280_10_OR_LATER(ah))
22607 - nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
22608 - AR9280_PHY_EXT_MINCCA_PWR);
22609 - else
22610 - nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
22611 - AR_PHY_EXT_MINCCA_PWR);
22612 -
22613 - if (nf & 0x100)
22614 - nf = 0 - ((nf ^ 0x1ff) + 1);
22615 - ath_print(common, ATH_DBG_CALIBRATE,
22616 - "NF calibrated [ext] [chain 0] is %d\n", nf);
22617 -
22618 - if (AR_SREV_9271(ah) && (nf >= -114))
22619 - nf = -116;
22620 -
22621 - nfarray[3] = nf;
22622 -
22623 - if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
22624 - if (AR_SREV_9280_10_OR_LATER(ah))
22625 - nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
22626 - AR9280_PHY_CH1_EXT_MINCCA_PWR);
22627 - else
22628 - nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
22629 - AR_PHY_CH1_EXT_MINCCA_PWR);
22630 -
22631 - if (nf & 0x100)
22632 - nf = 0 - ((nf ^ 0x1ff) + 1);
22633 - ath_print(common, ATH_DBG_CALIBRATE,
22634 - "NF calibrated [ext] [chain 1] is %d\n", nf);
22635 - nfarray[4] = nf;
22636 -
22637 - if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
22638 - nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
22639 - AR_PHY_CH2_EXT_MINCCA_PWR);
22640 - if (nf & 0x100)
22641 - nf = 0 - ((nf ^ 0x1ff) + 1);
22642 - ath_print(common, ATH_DBG_CALIBRATE,
22643 - "NF calibrated [ext] [chain 2] is %d\n", nf);
22644 - nfarray[5] = nf;
22645 - }
22646 - }
22647 -}
22648 -
22649 -static bool getNoiseFloorThresh(struct ath_hw *ah,
22650 - enum ieee80211_band band,
22651 - int16_t *nft)
22652 +static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
22653 + enum ieee80211_band band,
22654 + int16_t *nft)
22655 {
22656 switch (band) {
22657 case IEEE80211_BAND_5GHZ:
22658 @@ -195,44 +108,8 @@ static bool getNoiseFloorThresh(struct a
22659 return true;
22660 }
22661
22662 -static void ath9k_hw_setup_calibration(struct ath_hw *ah,
22663 - struct ath9k_cal_list *currCal)
22664 -{
22665 - struct ath_common *common = ath9k_hw_common(ah);
22666 -
22667 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
22668 - AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
22669 - currCal->calData->calCountMax);
22670 -
22671 - switch (currCal->calData->calType) {
22672 - case IQ_MISMATCH_CAL:
22673 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
22674 - ath_print(common, ATH_DBG_CALIBRATE,
22675 - "starting IQ Mismatch Calibration\n");
22676 - break;
22677 - case ADC_GAIN_CAL:
22678 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
22679 - ath_print(common, ATH_DBG_CALIBRATE,
22680 - "starting ADC Gain Calibration\n");
22681 - break;
22682 - case ADC_DC_CAL:
22683 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
22684 - ath_print(common, ATH_DBG_CALIBRATE,
22685 - "starting ADC DC Calibration\n");
22686 - break;
22687 - case ADC_DC_INIT_CAL:
22688 - REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
22689 - ath_print(common, ATH_DBG_CALIBRATE,
22690 - "starting Init ADC DC Calibration\n");
22691 - break;
22692 - }
22693 -
22694 - REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
22695 - AR_PHY_TIMING_CTRL4_DO_CAL);
22696 -}
22697 -
22698 -static void ath9k_hw_reset_calibration(struct ath_hw *ah,
22699 - struct ath9k_cal_list *currCal)
22700 +void ath9k_hw_reset_calibration(struct ath_hw *ah,
22701 + struct ath9k_cal_list *currCal)
22702 {
22703 int i;
22704
22705 @@ -250,324 +127,6 @@ static void ath9k_hw_reset_calibration(s
22706 ah->cal_samples = 0;
22707 }
22708
22709 -static bool ath9k_hw_per_calibration(struct ath_hw *ah,
22710 - struct ath9k_channel *ichan,
22711 - u8 rxchainmask,
22712 - struct ath9k_cal_list *currCal)
22713 -{
22714 - bool iscaldone = false;
22715 -
22716 - if (currCal->calState == CAL_RUNNING) {
22717 - if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
22718 - AR_PHY_TIMING_CTRL4_DO_CAL)) {
22719 -
22720 - currCal->calData->calCollect(ah);
22721 - ah->cal_samples++;
22722 -
22723 - if (ah->cal_samples >= currCal->calData->calNumSamples) {
22724 - int i, numChains = 0;
22725 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
22726 - if (rxchainmask & (1 << i))
22727 - numChains++;
22728 - }
22729 -
22730 - currCal->calData->calPostProc(ah, numChains);
22731 - ichan->CalValid |= currCal->calData->calType;
22732 - currCal->calState = CAL_DONE;
22733 - iscaldone = true;
22734 - } else {
22735 - ath9k_hw_setup_calibration(ah, currCal);
22736 - }
22737 - }
22738 - } else if (!(ichan->CalValid & currCal->calData->calType)) {
22739 - ath9k_hw_reset_calibration(ah, currCal);
22740 - }
22741 -
22742 - return iscaldone;
22743 -}
22744 -
22745 -/* Assumes you are talking about the currently configured channel */
22746 -static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
22747 - enum ath9k_cal_types calType)
22748 -{
22749 - struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
22750 -
22751 - switch (calType & ah->supp_cals) {
22752 - case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
22753 - return true;
22754 - case ADC_GAIN_CAL:
22755 - case ADC_DC_CAL:
22756 - if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
22757 - conf_is_ht20(conf)))
22758 - return true;
22759 - break;
22760 - }
22761 - return false;
22762 -}
22763 -
22764 -static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
22765 -{
22766 - int i;
22767 -
22768 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
22769 - ah->totalPowerMeasI[i] +=
22770 - REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
22771 - ah->totalPowerMeasQ[i] +=
22772 - REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
22773 - ah->totalIqCorrMeas[i] +=
22774 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
22775 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
22776 - "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
22777 - ah->cal_samples, i, ah->totalPowerMeasI[i],
22778 - ah->totalPowerMeasQ[i],
22779 - ah->totalIqCorrMeas[i]);
22780 - }
22781 -}
22782 -
22783 -static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
22784 -{
22785 - int i;
22786 -
22787 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
22788 - ah->totalAdcIOddPhase[i] +=
22789 - REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
22790 - ah->totalAdcIEvenPhase[i] +=
22791 - REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
22792 - ah->totalAdcQOddPhase[i] +=
22793 - REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
22794 - ah->totalAdcQEvenPhase[i] +=
22795 - REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
22796 -
22797 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
22798 - "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
22799 - "oddq=0x%08x; evenq=0x%08x;\n",
22800 - ah->cal_samples, i,
22801 - ah->totalAdcIOddPhase[i],
22802 - ah->totalAdcIEvenPhase[i],
22803 - ah->totalAdcQOddPhase[i],
22804 - ah->totalAdcQEvenPhase[i]);
22805 - }
22806 -}
22807 -
22808 -static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
22809 -{
22810 - int i;
22811 -
22812 - for (i = 0; i < AR5416_MAX_CHAINS; i++) {
22813 - ah->totalAdcDcOffsetIOddPhase[i] +=
22814 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
22815 - ah->totalAdcDcOffsetIEvenPhase[i] +=
22816 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
22817 - ah->totalAdcDcOffsetQOddPhase[i] +=
22818 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
22819 - ah->totalAdcDcOffsetQEvenPhase[i] +=
22820 - (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
22821 -
22822 - ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
22823 - "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
22824 - "oddq=0x%08x; evenq=0x%08x;\n",
22825 - ah->cal_samples, i,
22826 - ah->totalAdcDcOffsetIOddPhase[i],
22827 - ah->totalAdcDcOffsetIEvenPhase[i],
22828 - ah->totalAdcDcOffsetQOddPhase[i],
22829 - ah->totalAdcDcOffsetQEvenPhase[i]);
22830 - }
22831 -}
22832 -
22833 -static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
22834 -{
22835 - struct ath_common *common = ath9k_hw_common(ah);
22836 - u32 powerMeasQ, powerMeasI, iqCorrMeas;
22837 - u32 qCoffDenom, iCoffDenom;
22838 - int32_t qCoff, iCoff;
22839 - int iqCorrNeg, i;
22840 -
22841 - for (i = 0; i < numChains; i++) {
22842 - powerMeasI = ah->totalPowerMeasI[i];
22843 - powerMeasQ = ah->totalPowerMeasQ[i];
22844 - iqCorrMeas = ah->totalIqCorrMeas[i];
22845 -
22846 - ath_print(common, ATH_DBG_CALIBRATE,
22847 - "Starting IQ Cal and Correction for Chain %d\n",
22848 - i);
22849 -
22850 - ath_print(common, ATH_DBG_CALIBRATE,
22851 - "Orignal: Chn %diq_corr_meas = 0x%08x\n",
22852 - i, ah->totalIqCorrMeas[i]);
22853 -
22854 - iqCorrNeg = 0;
22855 -
22856 - if (iqCorrMeas > 0x80000000) {
22857 - iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
22858 - iqCorrNeg = 1;
22859 - }
22860 -
22861 - ath_print(common, ATH_DBG_CALIBRATE,
22862 - "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
22863 - ath_print(common, ATH_DBG_CALIBRATE,
22864 - "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
22865 - ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
22866 - iqCorrNeg);
22867 -
22868 - iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
22869 - qCoffDenom = powerMeasQ / 64;
22870 -
22871 - if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
22872 - (qCoffDenom != 0)) {
22873 - iCoff = iqCorrMeas / iCoffDenom;
22874 - qCoff = powerMeasI / qCoffDenom - 64;
22875 - ath_print(common, ATH_DBG_CALIBRATE,
22876 - "Chn %d iCoff = 0x%08x\n", i, iCoff);
22877 - ath_print(common, ATH_DBG_CALIBRATE,
22878 - "Chn %d qCoff = 0x%08x\n", i, qCoff);
22879 -
22880 - iCoff = iCoff & 0x3f;
22881 - ath_print(common, ATH_DBG_CALIBRATE,
22882 - "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
22883 - if (iqCorrNeg == 0x0)
22884 - iCoff = 0x40 - iCoff;
22885 -
22886 - if (qCoff > 15)
22887 - qCoff = 15;
22888 - else if (qCoff <= -16)
22889 - qCoff = 16;
22890 -
22891 - ath_print(common, ATH_DBG_CALIBRATE,
22892 - "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
22893 - i, iCoff, qCoff);
22894 -
22895 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
22896 - AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
22897 - iCoff);
22898 - REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
22899 - AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
22900 - qCoff);
22901 - ath_print(common, ATH_DBG_CALIBRATE,
22902 - "IQ Cal and Correction done for Chain %d\n",
22903 - i);
22904 - }
22905 - }
22906 -
22907 - REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
22908 - AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
22909 -}
22910 -
22911 -static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
22912 -{
22913 - struct ath_common *common = ath9k_hw_common(ah);
22914 - u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
22915 - u32 qGainMismatch, iGainMismatch, val, i;
22916 -
22917 - for (i = 0; i < numChains; i++) {
22918 - iOddMeasOffset = ah->totalAdcIOddPhase[i];
22919 - iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
22920 - qOddMeasOffset = ah->totalAdcQOddPhase[i];
22921 - qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
22922 -
22923 - ath_print(common, ATH_DBG_CALIBRATE,
22924 - "Starting ADC Gain Cal for Chain %d\n", i);
22925 -
22926 - ath_print(common, ATH_DBG_CALIBRATE,
22927 - "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
22928 - iOddMeasOffset);
22929 - ath_print(common, ATH_DBG_CALIBRATE,
22930 - "Chn %d pwr_meas_even_i = 0x%08x\n", i,
22931 - iEvenMeasOffset);
22932 - ath_print(common, ATH_DBG_CALIBRATE,
22933 - "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
22934 - qOddMeasOffset);
22935 - ath_print(common, ATH_DBG_CALIBRATE,
22936 - "Chn %d pwr_meas_even_q = 0x%08x\n", i,
22937 - qEvenMeasOffset);
22938 -
22939 - if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
22940 - iGainMismatch =
22941 - ((iEvenMeasOffset * 32) /
22942 - iOddMeasOffset) & 0x3f;
22943 - qGainMismatch =
22944 - ((qOddMeasOffset * 32) /
22945 - qEvenMeasOffset) & 0x3f;
22946 -
22947 - ath_print(common, ATH_DBG_CALIBRATE,
22948 - "Chn %d gain_mismatch_i = 0x%08x\n", i,
22949 - iGainMismatch);
22950 - ath_print(common, ATH_DBG_CALIBRATE,
22951 - "Chn %d gain_mismatch_q = 0x%08x\n", i,
22952 - qGainMismatch);
22953 -
22954 - val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
22955 - val &= 0xfffff000;
22956 - val |= (qGainMismatch) | (iGainMismatch << 6);
22957 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
22958 -
22959 - ath_print(common, ATH_DBG_CALIBRATE,
22960 - "ADC Gain Cal done for Chain %d\n", i);
22961 - }
22962 - }
22963 -
22964 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
22965 - REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
22966 - AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
22967 -}
22968 -
22969 -static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
22970 -{
22971 - struct ath_common *common = ath9k_hw_common(ah);
22972 - u32 iOddMeasOffset, iEvenMeasOffset, val, i;
22973 - int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
22974 - const struct ath9k_percal_data *calData =
22975 - ah->cal_list_curr->calData;
22976 - u32 numSamples =
22977 - (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
22978 -
22979 - for (i = 0; i < numChains; i++) {
22980 - iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
22981 - iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
22982 - qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
22983 - qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
22984 -
22985 - ath_print(common, ATH_DBG_CALIBRATE,
22986 - "Starting ADC DC Offset Cal for Chain %d\n", i);
22987 -
22988 - ath_print(common, ATH_DBG_CALIBRATE,
22989 - "Chn %d pwr_meas_odd_i = %d\n", i,
22990 - iOddMeasOffset);
22991 - ath_print(common, ATH_DBG_CALIBRATE,
22992 - "Chn %d pwr_meas_even_i = %d\n", i,
22993 - iEvenMeasOffset);
22994 - ath_print(common, ATH_DBG_CALIBRATE,
22995 - "Chn %d pwr_meas_odd_q = %d\n", i,
22996 - qOddMeasOffset);
22997 - ath_print(common, ATH_DBG_CALIBRATE,
22998 - "Chn %d pwr_meas_even_q = %d\n", i,
22999 - qEvenMeasOffset);
23000 -
23001 - iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
23002 - numSamples) & 0x1ff;
23003 - qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
23004 - numSamples) & 0x1ff;
23005 -
23006 - ath_print(common, ATH_DBG_CALIBRATE,
23007 - "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
23008 - iDcMismatch);
23009 - ath_print(common, ATH_DBG_CALIBRATE,
23010 - "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
23011 - qDcMismatch);
23012 -
23013 - val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
23014 - val &= 0xc0000fff;
23015 - val |= (qDcMismatch << 12) | (iDcMismatch << 21);
23016 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
23017 -
23018 - ath_print(common, ATH_DBG_CALIBRATE,
23019 - "ADC DC Offset Cal done for Chain %d\n", i);
23020 - }
23021 -
23022 - REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
23023 - REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
23024 - AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
23025 -}
23026 -
23027 /* This is done for the currently configured channel */
23028 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
23029 {
23030 @@ -614,72 +173,6 @@ void ath9k_hw_start_nfcal(struct ath_hw
23031 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
23032 }
23033
23034 -void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
23035 -{
23036 - struct ath9k_nfcal_hist *h;
23037 - int i, j;
23038 - int32_t val;
23039 - const u32 ar5416_cca_regs[6] = {
23040 - AR_PHY_CCA,
23041 - AR_PHY_CH1_CCA,
23042 - AR_PHY_CH2_CCA,
23043 - AR_PHY_EXT_CCA,
23044 - AR_PHY_CH1_EXT_CCA,
23045 - AR_PHY_CH2_EXT_CCA
23046 - };
23047 - u8 chainmask, rx_chain_status;
23048 -
23049 - rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
23050 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
23051 - chainmask = 0x9;
23052 - else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
23053 - if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
23054 - chainmask = 0x1B;
23055 - else
23056 - chainmask = 0x09;
23057 - } else {
23058 - if (rx_chain_status & 0x4)
23059 - chainmask = 0x3F;
23060 - else if (rx_chain_status & 0x2)
23061 - chainmask = 0x1B;
23062 - else
23063 - chainmask = 0x09;
23064 - }
23065 -
23066 - h = ah->nfCalHist;
23067 -
23068 - for (i = 0; i < NUM_NF_READINGS; i++) {
23069 - if (chainmask & (1 << i)) {
23070 - val = REG_READ(ah, ar5416_cca_regs[i]);
23071 - val &= 0xFFFFFE00;
23072 - val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
23073 - REG_WRITE(ah, ar5416_cca_regs[i], val);
23074 - }
23075 - }
23076 -
23077 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
23078 - AR_PHY_AGC_CONTROL_ENABLE_NF);
23079 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
23080 - AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
23081 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
23082 -
23083 - for (j = 0; j < 5; j++) {
23084 - if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
23085 - AR_PHY_AGC_CONTROL_NF) == 0)
23086 - break;
23087 - udelay(50);
23088 - }
23089 -
23090 - for (i = 0; i < NUM_NF_READINGS; i++) {
23091 - if (chainmask & (1 << i)) {
23092 - val = REG_READ(ah, ar5416_cca_regs[i]);
23093 - val &= 0xFFFFFE00;
23094 - val |= (((u32) (-50) << 1) & 0x1ff);
23095 - REG_WRITE(ah, ar5416_cca_regs[i], val);
23096 - }
23097 - }
23098 -}
23099 -
23100 int16_t ath9k_hw_getnf(struct ath_hw *ah,
23101 struct ath9k_channel *chan)
23102 {
23103 @@ -699,7 +192,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah
23104 } else {
23105 ath9k_hw_do_getnf(ah, nfarray);
23106 nf = nfarray[0];
23107 - if (getNoiseFloorThresh(ah, c->band, &nfThresh)
23108 + if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
23109 && nf > nfThresh) {
23110 ath_print(common, ATH_DBG_CALIBRATE,
23111 "noise floor failed detected; "
23112 @@ -757,567 +250,3 @@ s16 ath9k_hw_getchan_noise(struct ath_hw
23113 return nf;
23114 }
23115 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
23116 -
23117 -static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
23118 -{
23119 - u32 rddata;
23120 - int32_t delta, currPDADC, slope;
23121 -
23122 - rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
23123 - currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
23124 -
23125 - if (ah->initPDADC == 0 || currPDADC == 0) {
23126 - /*
23127 - * Zero value indicates that no frames have been transmitted yet,
23128 - * can't do temperature compensation until frames are transmitted.
23129 - */
23130 - return;
23131 - } else {
23132 - slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
23133 -
23134 - if (slope == 0) { /* to avoid divide by zero case */
23135 - delta = 0;
23136 - } else {
23137 - delta = ((currPDADC - ah->initPDADC)*4) / slope;
23138 - }
23139 - REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
23140 - AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
23141 - REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
23142 - AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
23143 - }
23144 -}
23145 -
23146 -static void ath9k_olc_temp_compensation(struct ath_hw *ah)
23147 -{
23148 - u32 rddata, i;
23149 - int delta, currPDADC, regval;
23150 -
23151 - if (OLC_FOR_AR9287_10_LATER) {
23152 - ath9k_olc_temp_compensation_9287(ah);
23153 - } else {
23154 - rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
23155 - currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
23156 -
23157 - if (ah->initPDADC == 0 || currPDADC == 0) {
23158 - return;
23159 - } else {
23160 - if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
23161 - delta = (currPDADC - ah->initPDADC + 4) / 8;
23162 - else
23163 - delta = (currPDADC - ah->initPDADC + 5) / 10;
23164 -
23165 - if (delta != ah->PDADCdelta) {
23166 - ah->PDADCdelta = delta;
23167 - for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
23168 - regval = ah->originalGain[i] - delta;
23169 - if (regval < 0)
23170 - regval = 0;
23171 -
23172 - REG_RMW_FIELD(ah,
23173 - AR_PHY_TX_GAIN_TBL1 + i * 4,
23174 - AR_PHY_TX_GAIN, regval);
23175 - }
23176 - }
23177 - }
23178 - }
23179 -}
23180 -
23181 -static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
23182 -{
23183 - u32 regVal;
23184 - unsigned int i;
23185 - u32 regList [][2] = {
23186 - { 0x786c, 0 },
23187 - { 0x7854, 0 },
23188 - { 0x7820, 0 },
23189 - { 0x7824, 0 },
23190 - { 0x7868, 0 },
23191 - { 0x783c, 0 },
23192 - { 0x7838, 0 } ,
23193 - { 0x7828, 0 } ,
23194 - };
23195 -
23196 - for (i = 0; i < ARRAY_SIZE(regList); i++)
23197 - regList[i][1] = REG_READ(ah, regList[i][0]);
23198 -
23199 - regVal = REG_READ(ah, 0x7834);
23200 - regVal &= (~(0x1));
23201 - REG_WRITE(ah, 0x7834, regVal);
23202 - regVal = REG_READ(ah, 0x9808);
23203 - regVal |= (0x1 << 27);
23204 - REG_WRITE(ah, 0x9808, regVal);
23205 -
23206 - /* 786c,b23,1, pwddac=1 */
23207 - REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
23208 - /* 7854, b5,1, pdrxtxbb=1 */
23209 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
23210 - /* 7854, b7,1, pdv2i=1 */
23211 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
23212 - /* 7854, b8,1, pddacinterface=1 */
23213 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
23214 - /* 7824,b12,0, offcal=0 */
23215 - REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
23216 - /* 7838, b1,0, pwddb=0 */
23217 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
23218 - /* 7820,b11,0, enpacal=0 */
23219 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
23220 - /* 7820,b25,1, pdpadrv1=0 */
23221 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
23222 - /* 7820,b24,0, pdpadrv2=0 */
23223 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
23224 - /* 7820,b23,0, pdpaout=0 */
23225 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
23226 - /* 783c,b14-16,7, padrvgn2tab_0=7 */
23227 - REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
23228 - /*
23229 - * 7838,b29-31,0, padrvgn1tab_0=0
23230 - * does not matter since we turn it off
23231 - */
23232 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
23233 -
23234 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
23235 -
23236 - /* Set:
23237 - * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
23238 - * txon=1,paon=1,oscon=1,synthon_force=1
23239 - */
23240 - REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
23241 - udelay(30);
23242 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
23243 -
23244 - /* find off_6_1; */
23245 - for (i = 6; i > 0; i--) {
23246 - regVal = REG_READ(ah, 0x7834);
23247 - regVal |= (1 << (20 + i));
23248 - REG_WRITE(ah, 0x7834, regVal);
23249 - udelay(1);
23250 - //regVal = REG_READ(ah, 0x7834);
23251 - regVal &= (~(0x1 << (20 + i)));
23252 - regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
23253 - << (20 + i));
23254 - REG_WRITE(ah, 0x7834, regVal);
23255 - }
23256 -
23257 - regVal = (regVal >>20) & 0x7f;
23258 -
23259 - /* Update PA cal info */
23260 - if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
23261 - if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
23262 - ah->pacal_info.max_skipcount =
23263 - 2 * ah->pacal_info.max_skipcount;
23264 - ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
23265 - } else {
23266 - ah->pacal_info.max_skipcount = 1;
23267 - ah->pacal_info.skipcount = 0;
23268 - ah->pacal_info.prev_offset = regVal;
23269 - }
23270 -
23271 - regVal = REG_READ(ah, 0x7834);
23272 - regVal |= 0x1;
23273 - REG_WRITE(ah, 0x7834, regVal);
23274 - regVal = REG_READ(ah, 0x9808);
23275 - regVal &= (~(0x1 << 27));
23276 - REG_WRITE(ah, 0x9808, regVal);
23277 -
23278 - for (i = 0; i < ARRAY_SIZE(regList); i++)
23279 - REG_WRITE(ah, regList[i][0], regList[i][1]);
23280 -}
23281 -
23282 -static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
23283 -{
23284 - struct ath_common *common = ath9k_hw_common(ah);
23285 - u32 regVal;
23286 - int i, offset, offs_6_1, offs_0;
23287 - u32 ccomp_org, reg_field;
23288 - u32 regList[][2] = {
23289 - { 0x786c, 0 },
23290 - { 0x7854, 0 },
23291 - { 0x7820, 0 },
23292 - { 0x7824, 0 },
23293 - { 0x7868, 0 },
23294 - { 0x783c, 0 },
23295 - { 0x7838, 0 },
23296 - };
23297 -
23298 - ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
23299 -
23300 - /* PA CAL is not needed for high power solution */
23301 - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
23302 - AR5416_EEP_TXGAIN_HIGH_POWER)
23303 - return;
23304 -
23305 - if (AR_SREV_9285_11(ah)) {
23306 - REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
23307 - udelay(10);
23308 - }
23309 -
23310 - for (i = 0; i < ARRAY_SIZE(regList); i++)
23311 - regList[i][1] = REG_READ(ah, regList[i][0]);
23312 -
23313 - regVal = REG_READ(ah, 0x7834);
23314 - regVal &= (~(0x1));
23315 - REG_WRITE(ah, 0x7834, regVal);
23316 - regVal = REG_READ(ah, 0x9808);
23317 - regVal |= (0x1 << 27);
23318 - REG_WRITE(ah, 0x9808, regVal);
23319 -
23320 - REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
23321 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
23322 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
23323 - REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
23324 - REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
23325 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
23326 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
23327 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
23328 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
23329 - REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
23330 - REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
23331 - REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
23332 - ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
23333 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
23334 -
23335 - REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
23336 - udelay(30);
23337 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
23338 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
23339 -
23340 - for (i = 6; i > 0; i--) {
23341 - regVal = REG_READ(ah, 0x7834);
23342 - regVal |= (1 << (19 + i));
23343 - REG_WRITE(ah, 0x7834, regVal);
23344 - udelay(1);
23345 - regVal = REG_READ(ah, 0x7834);
23346 - regVal &= (~(0x1 << (19 + i)));
23347 - reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
23348 - regVal |= (reg_field << (19 + i));
23349 - REG_WRITE(ah, 0x7834, regVal);
23350 - }
23351 -
23352 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
23353 - udelay(1);
23354 - reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
23355 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
23356 - offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
23357 - offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
23358 -
23359 - offset = (offs_6_1<<1) | offs_0;
23360 - offset = offset - 0;
23361 - offs_6_1 = offset>>1;
23362 - offs_0 = offset & 1;
23363 -
23364 - if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
23365 - if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
23366 - ah->pacal_info.max_skipcount =
23367 - 2 * ah->pacal_info.max_skipcount;
23368 - ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
23369 - } else {
23370 - ah->pacal_info.max_skipcount = 1;
23371 - ah->pacal_info.skipcount = 0;
23372 - ah->pacal_info.prev_offset = offset;
23373 - }
23374 -
23375 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
23376 - REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
23377 -
23378 - regVal = REG_READ(ah, 0x7834);
23379 - regVal |= 0x1;
23380 - REG_WRITE(ah, 0x7834, regVal);
23381 - regVal = REG_READ(ah, 0x9808);
23382 - regVal &= (~(0x1 << 27));
23383 - REG_WRITE(ah, 0x9808, regVal);
23384 -
23385 - for (i = 0; i < ARRAY_SIZE(regList); i++)
23386 - REG_WRITE(ah, regList[i][0], regList[i][1]);
23387 -
23388 - REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
23389 -
23390 - if (AR_SREV_9285_11(ah))
23391 - REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
23392 -
23393 -}
23394 -
23395 -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
23396 - u8 rxchainmask, bool longcal)
23397 -{
23398 - bool iscaldone = true;
23399 - struct ath9k_cal_list *currCal = ah->cal_list_curr;
23400 -
23401 - if (currCal &&
23402 - (currCal->calState == CAL_RUNNING ||
23403 - currCal->calState == CAL_WAITING)) {
23404 - iscaldone = ath9k_hw_per_calibration(ah, chan,
23405 - rxchainmask, currCal);
23406 - if (iscaldone) {
23407 - ah->cal_list_curr = currCal = currCal->calNext;
23408 -
23409 - if (currCal->calState == CAL_WAITING) {
23410 - iscaldone = false;
23411 - ath9k_hw_reset_calibration(ah, currCal);
23412 - }
23413 - }
23414 - }
23415 -
23416 - /* Do NF cal only at longer intervals */
23417 - if (longcal) {
23418 - /* Do periodic PAOffset Cal */
23419 - if (AR_SREV_9271(ah)) {
23420 - if (!ah->pacal_info.skipcount)
23421 - ath9k_hw_9271_pa_cal(ah, false);
23422 - else
23423 - ah->pacal_info.skipcount--;
23424 - } else if (AR_SREV_9285_11_OR_LATER(ah)) {
23425 - if (!ah->pacal_info.skipcount)
23426 - ath9k_hw_9285_pa_cal(ah, false);
23427 - else
23428 - ah->pacal_info.skipcount--;
23429 - }
23430 -
23431 - if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
23432 - ath9k_olc_temp_compensation(ah);
23433 -
23434 - /* Get the value from the previous NF cal and update history buffer */
23435 - ath9k_hw_getnf(ah, chan);
23436 -
23437 - /*
23438 - * Load the NF from history buffer of the current channel.
23439 - * NF is slow time-variant, so it is OK to use a historical value.
23440 - */
23441 - ath9k_hw_loadnf(ah, ah->curchan);
23442 -
23443 - ath9k_hw_start_nfcal(ah);
23444 - }
23445 -
23446 - return iscaldone;
23447 -}
23448 -EXPORT_SYMBOL(ath9k_hw_calibrate);
23449 -
23450 -/* Carrier leakage Calibration fix */
23451 -static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
23452 -{
23453 - struct ath_common *common = ath9k_hw_common(ah);
23454 -
23455 - REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
23456 - if (IS_CHAN_HT20(chan)) {
23457 - REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
23458 - REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
23459 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
23460 - AR_PHY_AGC_CONTROL_FLTR_CAL);
23461 - REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
23462 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
23463 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
23464 - AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
23465 - ath_print(common, ATH_DBG_CALIBRATE, "offset "
23466 - "calibration failed to complete in "
23467 - "1ms; noisy ??\n");
23468 - return false;
23469 - }
23470 - REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
23471 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
23472 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
23473 - }
23474 - REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
23475 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
23476 - REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
23477 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
23478 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
23479 - 0, AH_WAIT_TIMEOUT)) {
23480 - ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
23481 - "failed to complete in 1ms; noisy ??\n");
23482 - return false;
23483 - }
23484 -
23485 - REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
23486 - REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
23487 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
23488 -
23489 - return true;
23490 -}
23491 -
23492 -static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
23493 -{
23494 - int i;
23495 - u_int32_t txgain_max;
23496 - u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
23497 - u_int32_t reg_clc_I0, reg_clc_Q0;
23498 - u_int32_t i0_num = 0;
23499 - u_int32_t q0_num = 0;
23500 - u_int32_t total_num = 0;
23501 - u_int32_t reg_rf2g5_org;
23502 - bool retv = true;
23503 -
23504 - if (!(ar9285_cl_cal(ah, chan)))
23505 - return false;
23506 -
23507 - txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
23508 - AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
23509 -
23510 - for (i = 0; i < (txgain_max+1); i++) {
23511 - clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
23512 - AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
23513 - if (!(gain_mask & (1 << clc_gain))) {
23514 - gain_mask |= (1 << clc_gain);
23515 - clc_num++;
23516 - }
23517 - }
23518 -
23519 - for (i = 0; i < clc_num; i++) {
23520 - reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
23521 - & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
23522 - reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
23523 - & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
23524 - if (reg_clc_I0 == 0)
23525 - i0_num++;
23526 -
23527 - if (reg_clc_Q0 == 0)
23528 - q0_num++;
23529 - }
23530 - total_num = i0_num + q0_num;
23531 - if (total_num > AR9285_CLCAL_REDO_THRESH) {
23532 - reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
23533 - if (AR_SREV_9285E_20(ah)) {
23534 - REG_WRITE(ah, AR9285_RF2G5,
23535 - (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
23536 - AR9285_RF2G5_IC50TX_XE_SET);
23537 - } else {
23538 - REG_WRITE(ah, AR9285_RF2G5,
23539 - (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
23540 - AR9285_RF2G5_IC50TX_SET);
23541 - }
23542 - retv = ar9285_cl_cal(ah, chan);
23543 - REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
23544 - }
23545 - return retv;
23546 -}
23547 -
23548 -bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
23549 -{
23550 - struct ath_common *common = ath9k_hw_common(ah);
23551 -
23552 - if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
23553 - if (!ar9285_clc(ah, chan))
23554 - return false;
23555 - } else {
23556 - if (AR_SREV_9280_10_OR_LATER(ah)) {
23557 - if (!AR_SREV_9287_10_OR_LATER(ah))
23558 - REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
23559 - AR_PHY_ADC_CTL_OFF_PWDADC);
23560 - REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
23561 - AR_PHY_AGC_CONTROL_FLTR_CAL);
23562 - }
23563 -
23564 - /* Calibrate the AGC */
23565 - REG_WRITE(ah, AR_PHY_AGC_CONTROL,
23566 - REG_READ(ah, AR_PHY_AGC_CONTROL) |
23567 - AR_PHY_AGC_CONTROL_CAL);
23568 -
23569 - /* Poll for offset calibration complete */
23570 - if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
23571 - 0, AH_WAIT_TIMEOUT)) {
23572 - ath_print(common, ATH_DBG_CALIBRATE,
23573 - "offset calibration failed to "
23574 - "complete in 1ms; noisy environment?\n");
23575 - return false;
23576 - }
23577 -
23578 - if (AR_SREV_9280_10_OR_LATER(ah)) {
23579 - if (!AR_SREV_9287_10_OR_LATER(ah))
23580 - REG_SET_BIT(ah, AR_PHY_ADC_CTL,
23581 - AR_PHY_ADC_CTL_OFF_PWDADC);
23582 - REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
23583 - AR_PHY_AGC_CONTROL_FLTR_CAL);
23584 - }
23585 - }
23586 -
23587 - /* Do PA Calibration */
23588 - if (AR_SREV_9271(ah))
23589 - ath9k_hw_9271_pa_cal(ah, true);
23590 - else if (AR_SREV_9285_11_OR_LATER(ah))
23591 - ath9k_hw_9285_pa_cal(ah, true);
23592 -
23593 - /* Do NF Calibration after DC offset and other calibrations */
23594 - REG_WRITE(ah, AR_PHY_AGC_CONTROL,
23595 - REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
23596 -
23597 - ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
23598 -
23599 - /* Enable IQ, ADC Gain and ADC DC offset CALs */
23600 - if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
23601 - if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
23602 - INIT_CAL(&ah->adcgain_caldata);
23603 - INSERT_CAL(ah, &ah->adcgain_caldata);
23604 - ath_print(common, ATH_DBG_CALIBRATE,
23605 - "enabling ADC Gain Calibration.\n");
23606 - }
23607 - if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
23608 - INIT_CAL(&ah->adcdc_caldata);
23609 - INSERT_CAL(ah, &ah->adcdc_caldata);
23610 - ath_print(common, ATH_DBG_CALIBRATE,
23611 - "enabling ADC DC Calibration.\n");
23612 - }
23613 - if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
23614 - INIT_CAL(&ah->iq_caldata);
23615 - INSERT_CAL(ah, &ah->iq_caldata);
23616 - ath_print(common, ATH_DBG_CALIBRATE,
23617 - "enabling IQ Calibration.\n");
23618 - }
23619 -
23620 - ah->cal_list_curr = ah->cal_list;
23621 -
23622 - if (ah->cal_list_curr)
23623 - ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
23624 - }
23625 -
23626 - chan->CalValid = 0;
23627 -
23628 - return true;
23629 -}
23630 -
23631 -const struct ath9k_percal_data iq_cal_multi_sample = {
23632 - IQ_MISMATCH_CAL,
23633 - MAX_CAL_SAMPLES,
23634 - PER_MIN_LOG_COUNT,
23635 - ath9k_hw_iqcal_collect,
23636 - ath9k_hw_iqcalibrate
23637 -};
23638 -const struct ath9k_percal_data iq_cal_single_sample = {
23639 - IQ_MISMATCH_CAL,
23640 - MIN_CAL_SAMPLES,
23641 - PER_MAX_LOG_COUNT,
23642 - ath9k_hw_iqcal_collect,
23643 - ath9k_hw_iqcalibrate
23644 -};
23645 -const struct ath9k_percal_data adc_gain_cal_multi_sample = {
23646 - ADC_GAIN_CAL,
23647 - MAX_CAL_SAMPLES,
23648 - PER_MIN_LOG_COUNT,
23649 - ath9k_hw_adc_gaincal_collect,
23650 - ath9k_hw_adc_gaincal_calibrate
23651 -};
23652 -const struct ath9k_percal_data adc_gain_cal_single_sample = {
23653 - ADC_GAIN_CAL,
23654 - MIN_CAL_SAMPLES,
23655 - PER_MAX_LOG_COUNT,
23656 - ath9k_hw_adc_gaincal_collect,
23657 - ath9k_hw_adc_gaincal_calibrate
23658 -};
23659 -const struct ath9k_percal_data adc_dc_cal_multi_sample = {
23660 - ADC_DC_CAL,
23661 - MAX_CAL_SAMPLES,
23662 - PER_MIN_LOG_COUNT,
23663 - ath9k_hw_adc_dccal_collect,
23664 - ath9k_hw_adc_dccal_calibrate
23665 -};
23666 -const struct ath9k_percal_data adc_dc_cal_single_sample = {
23667 - ADC_DC_CAL,
23668 - MIN_CAL_SAMPLES,
23669 - PER_MAX_LOG_COUNT,
23670 - ath9k_hw_adc_dccal_collect,
23671 - ath9k_hw_adc_dccal_calibrate
23672 -};
23673 -const struct ath9k_percal_data adc_init_dc_cal = {
23674 - ADC_DC_INIT_CAL,
23675 - MIN_CAL_SAMPLES,
23676 - INIT_LOG_COUNT,
23677 - ath9k_hw_adc_dccal_collect,
23678 - ath9k_hw_adc_dccal_calibrate
23679 -};
23680 --- a/drivers/net/wireless/ath/ath9k/calib.h
23681 +++ b/drivers/net/wireless/ath/ath9k/calib.h
23682 @@ -19,14 +19,6 @@
23683
23684 #include "hw.h"
23685
23686 -extern const struct ath9k_percal_data iq_cal_multi_sample;
23687 -extern const struct ath9k_percal_data iq_cal_single_sample;
23688 -extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
23689 -extern const struct ath9k_percal_data adc_gain_cal_single_sample;
23690 -extern const struct ath9k_percal_data adc_dc_cal_multi_sample;
23691 -extern const struct ath9k_percal_data adc_dc_cal_single_sample;
23692 -extern const struct ath9k_percal_data adc_init_dc_cal;
23693 -
23694 #define AR_PHY_CCA_MAX_AR5416_GOOD_VALUE -85
23695 #define AR_PHY_CCA_MAX_AR9280_GOOD_VALUE -112
23696 #define AR_PHY_CCA_MAX_AR9285_GOOD_VALUE -118
23697 @@ -76,7 +68,8 @@ enum ath9k_cal_types {
23698 ADC_DC_INIT_CAL = 0x1,
23699 ADC_GAIN_CAL = 0x2,
23700 ADC_DC_CAL = 0x4,
23701 - IQ_MISMATCH_CAL = 0x8
23702 + IQ_MISMATCH_CAL = 0x8,
23703 + TEMP_COMP_CAL = 0x10,
23704 };
23705
23706 enum ath9k_cal_state {
23707 @@ -122,14 +115,12 @@ struct ath9k_pacal_info{
23708
23709 bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
23710 void ath9k_hw_start_nfcal(struct ath_hw *ah);
23711 -void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
23712 int16_t ath9k_hw_getnf(struct ath_hw *ah,
23713 struct ath9k_channel *chan);
23714 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
23715 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
23716 -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
23717 - u8 rxchainmask, bool longcal);
23718 -bool ath9k_hw_init_cal(struct ath_hw *ah,
23719 - struct ath9k_channel *chan);
23720 +void ath9k_hw_reset_calibration(struct ath_hw *ah,
23721 + struct ath9k_cal_list *currCal);
23722 +
23723
23724 #endif /* CALIB_H */
23725 --- a/drivers/net/wireless/ath/ath9k/common.h
23726 +++ b/drivers/net/wireless/ath/ath9k/common.h
23727 @@ -20,6 +20,7 @@
23728 #include "../debug.h"
23729
23730 #include "hw.h"
23731 +#include "hw-ops.h"
23732
23733 /* Common header for Atheros 802.11n base driver cores */
23734
23735 @@ -76,11 +77,12 @@ struct ath_buf {
23736 an aggregate) */
23737 struct ath_buf *bf_next; /* next subframe in the aggregate */
23738 struct sk_buff *bf_mpdu; /* enclosing frame structure */
23739 - struct ath_desc *bf_desc; /* virtual addr of desc */
23740 + void *bf_desc; /* virtual addr of desc */
23741 dma_addr_t bf_daddr; /* physical addr of desc */
23742 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
23743 bool bf_stale;
23744 bool bf_isnullfunc;
23745 + bool bf_tx_aborted;
23746 u16 bf_flags;
23747 struct ath_buf_state bf_state;
23748 dma_addr_t bf_dmacontext;
23749 --- a/drivers/net/wireless/ath/ath9k/debug.c
23750 +++ b/drivers/net/wireless/ath/ath9k/debug.c
23751 @@ -179,8 +179,15 @@ void ath_debug_stat_interrupt(struct ath
23752 {
23753 if (status)
23754 sc->debug.stats.istats.total++;
23755 - if (status & ATH9K_INT_RX)
23756 - sc->debug.stats.istats.rxok++;
23757 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
23758 + if (status & ATH9K_INT_RXLP)
23759 + sc->debug.stats.istats.rxlp++;
23760 + if (status & ATH9K_INT_RXHP)
23761 + sc->debug.stats.istats.rxhp++;
23762 + } else {
23763 + if (status & ATH9K_INT_RX)
23764 + sc->debug.stats.istats.rxok++;
23765 + }
23766 if (status & ATH9K_INT_RXEOL)
23767 sc->debug.stats.istats.rxeol++;
23768 if (status & ATH9K_INT_RXORN)
23769 @@ -222,8 +229,15 @@ static ssize_t read_file_interrupt(struc
23770 char buf[512];
23771 unsigned int len = 0;
23772
23773 - len += snprintf(buf + len, sizeof(buf) - len,
23774 - "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
23775 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
23776 + len += snprintf(buf + len, sizeof(buf) - len,
23777 + "%8s: %10u\n", "RXLP", sc->debug.stats.istats.rxlp);
23778 + len += snprintf(buf + len, sizeof(buf) - len,
23779 + "%8s: %10u\n", "RXHP", sc->debug.stats.istats.rxhp);
23780 + } else {
23781 + len += snprintf(buf + len, sizeof(buf) - len,
23782 + "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
23783 + }
23784 len += snprintf(buf + len, sizeof(buf) - len,
23785 "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol);
23786 len += snprintf(buf + len, sizeof(buf) - len,
23787 --- a/drivers/net/wireless/ath/ath9k/debug.h
23788 +++ b/drivers/net/wireless/ath/ath9k/debug.h
23789 @@ -35,6 +35,8 @@ struct ath_buf;
23790 * struct ath_interrupt_stats - Contains statistics about interrupts
23791 * @total: Total no. of interrupts generated so far
23792 * @rxok: RX with no errors
23793 + * @rxlp: RX with low priority RX
23794 + * @rxhp: RX with high priority, uapsd only
23795 * @rxeol: RX with no more RXDESC available
23796 * @rxorn: RX FIFO overrun
23797 * @txok: TX completed at the requested rate
23798 @@ -55,6 +57,8 @@ struct ath_buf;
23799 struct ath_interrupt_stats {
23800 u32 total;
23801 u32 rxok;
23802 + u32 rxlp;
23803 + u32 rxhp;
23804 u32 rxeol;
23805 u32 rxorn;
23806 u32 txok;
23807 --- a/drivers/net/wireless/ath/ath9k/eeprom.c
23808 +++ b/drivers/net/wireless/ath/ath9k/eeprom.c
23809 @@ -256,14 +256,13 @@ int ath9k_hw_eeprom_init(struct ath_hw *
23810 {
23811 int status;
23812
23813 - if (AR_SREV_9287(ah)) {
23814 - ah->eep_map = EEP_MAP_AR9287;
23815 - ah->eep_ops = &eep_AR9287_ops;
23816 + if (AR_SREV_9300_20_OR_LATER(ah))
23817 + ah->eep_ops = &eep_ar9300_ops;
23818 + else if (AR_SREV_9287(ah)) {
23819 + ah->eep_ops = &eep_ar9287_ops;
23820 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
23821 - ah->eep_map = EEP_MAP_4KBITS;
23822 ah->eep_ops = &eep_4k_ops;
23823 } else {
23824 - ah->eep_map = EEP_MAP_DEFAULT;
23825 ah->eep_ops = &eep_def_ops;
23826 }
23827
23828 --- a/drivers/net/wireless/ath/ath9k/eeprom.h
23829 +++ b/drivers/net/wireless/ath/ath9k/eeprom.h
23830 @@ -19,6 +19,7 @@
23831
23832 #include "../ath.h"
23833 #include <net/cfg80211.h>
23834 +#include "ar9003_eeprom.h"
23835
23836 #define AH_USE_EEPROM 0x1
23837
23838 @@ -93,7 +94,6 @@
23839 */
23840 #define AR9285_RDEXT_DEFAULT 0x1F
23841
23842 -#define AR_EEPROM_MAC(i) (0x1d+(i))
23843 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
23844 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
23845 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
23846 @@ -155,6 +155,7 @@
23847 #define AR5416_BCHAN_UNUSED 0xFF
23848 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
23849 #define AR5416_MAX_CHAINS 3
23850 +#define AR9300_MAX_CHAINS 3
23851 #define AR5416_PWR_TABLE_OFFSET_DB -5
23852
23853 /* Rx gain type values */
23854 @@ -249,16 +250,20 @@ enum eeprom_param {
23855 EEP_MINOR_REV,
23856 EEP_TX_MASK,
23857 EEP_RX_MASK,
23858 + EEP_FSTCLK_5G,
23859 EEP_RXGAIN_TYPE,
23860 - EEP_TXGAIN_TYPE,
23861 EEP_OL_PWRCTRL,
23862 + EEP_TXGAIN_TYPE,
23863 EEP_RC_CHAIN_MASK,
23864 EEP_DAC_HPWR_5G,
23865 EEP_FRAC_N_5G,
23866 EEP_DEV_TYPE,
23867 EEP_TEMPSENSE_SLOPE,
23868 EEP_TEMPSENSE_SLOPE_PAL_ON,
23869 - EEP_PWR_TABLE_OFFSET
23870 + EEP_PWR_TABLE_OFFSET,
23871 + EEP_DRIVE_STRENGTH,
23872 + EEP_INTERNAL_REGULATOR,
23873 + EEP_SWREG
23874 };
23875
23876 enum ar5416_rates {
23877 @@ -656,13 +661,6 @@ struct ath9k_country_entry {
23878 u8 iso[3];
23879 };
23880
23881 -enum ath9k_eep_map {
23882 - EEP_MAP_DEFAULT = 0x0,
23883 - EEP_MAP_4KBITS,
23884 - EEP_MAP_AR9287,
23885 - EEP_MAP_MAX
23886 -};
23887 -
23888 struct eeprom_ops {
23889 int (*check_eeprom)(struct ath_hw *hw);
23890 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
23891 @@ -713,6 +711,8 @@ int ath9k_hw_eeprom_init(struct ath_hw *
23892
23893 extern const struct eeprom_ops eep_def_ops;
23894 extern const struct eeprom_ops eep_4k_ops;
23895 -extern const struct eeprom_ops eep_AR9287_ops;
23896 +extern const struct eeprom_ops eep_ar9287_ops;
23897 +extern const struct eeprom_ops eep_ar9287_ops;
23898 +extern const struct eeprom_ops eep_ar9300_ops;
23899
23900 #endif /* EEPROM_H */
23901 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
23902 +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
23903 @@ -15,6 +15,7 @@
23904 */
23905
23906 #include "hw.h"
23907 +#include "ar9002_phy.h"
23908
23909 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
23910 {
23911 @@ -182,11 +183,11 @@ static u32 ath9k_hw_4k_get_eeprom(struct
23912 switch (param) {
23913 case EEP_NFTHRESH_2:
23914 return pModal->noiseFloorThreshCh[0];
23915 - case AR_EEPROM_MAC(0):
23916 + case EEP_MAC_LSW:
23917 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
23918 - case AR_EEPROM_MAC(1):
23919 + case EEP_MAC_MID:
23920 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
23921 - case AR_EEPROM_MAC(2):
23922 + case EEP_MAC_MSW:
23923 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
23924 case EEP_REG_0:
23925 return pBase->regDmn[0];
23926 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
23927 +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
23928 @@ -15,6 +15,7 @@
23929 */
23930
23931 #include "hw.h"
23932 +#include "ar9002_phy.h"
23933
23934 static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
23935 {
23936 @@ -172,11 +173,11 @@ static u32 ath9k_hw_AR9287_get_eeprom(st
23937 switch (param) {
23938 case EEP_NFTHRESH_2:
23939 return pModal->noiseFloorThreshCh[0];
23940 - case AR_EEPROM_MAC(0):
23941 + case EEP_MAC_LSW:
23942 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
23943 - case AR_EEPROM_MAC(1):
23944 + case EEP_MAC_MID:
23945 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
23946 - case AR_EEPROM_MAC(2):
23947 + case EEP_MAC_MSW:
23948 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
23949 case EEP_REG_0:
23950 return pBase->regDmn[0];
23951 @@ -1169,7 +1170,7 @@ static u16 ath9k_hw_AR9287_get_spur_chan
23952 #undef EEP_MAP9287_SPURCHAN
23953 }
23954
23955 -const struct eeprom_ops eep_AR9287_ops = {
23956 +const struct eeprom_ops eep_ar9287_ops = {
23957 .check_eeprom = ath9k_hw_AR9287_check_eeprom,
23958 .get_eeprom = ath9k_hw_AR9287_get_eeprom,
23959 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom,
23960 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
23961 +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
23962 @@ -15,6 +15,7 @@
23963 */
23964
23965 #include "hw.h"
23966 +#include "ar9002_phy.h"
23967
23968 static void ath9k_get_txgain_index(struct ath_hw *ah,
23969 struct ath9k_channel *chan,
23970 @@ -222,6 +223,12 @@ static int ath9k_hw_def_check_eeprom(str
23971 return -EINVAL;
23972 }
23973
23974 + /* Enable fixup for AR_AN_TOP2 if necessary */
23975 + if (AR_SREV_9280_10_OR_LATER(ah) &&
23976 + (eep->baseEepHeader.version & 0xff) > 0x0a &&
23977 + eep->baseEepHeader.pwdclkind == 0)
23978 + ah->need_an_top2_fixup = 1;
23979 +
23980 return 0;
23981 }
23982
23983 @@ -237,11 +244,11 @@ static u32 ath9k_hw_def_get_eeprom(struc
23984 return pModal[0].noiseFloorThreshCh[0];
23985 case EEP_NFTHRESH_2:
23986 return pModal[1].noiseFloorThreshCh[0];
23987 - case AR_EEPROM_MAC(0):
23988 + case EEP_MAC_LSW:
23989 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
23990 - case AR_EEPROM_MAC(1):
23991 + case EEP_MAC_MID:
23992 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
23993 - case AR_EEPROM_MAC(2):
23994 + case EEP_MAC_MSW:
23995 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
23996 case EEP_REG_0:
23997 return pBase->regDmn[0];
23998 --- /dev/null
23999 +++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
24000 @@ -0,0 +1,284 @@
24001 +/*
24002 + * Copyright (c) 2010 Atheros Communications Inc.
24003 + *
24004 + * Permission to use, copy, modify, and/or distribute this software for any
24005 + * purpose with or without fee is hereby granted, provided that the above
24006 + * copyright notice and this permission notice appear in all copies.
24007 + *
24008 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
24009 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
24010 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
24011 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
24012 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
24013 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
24014 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24015 + */
24016 +
24017 +#ifndef ATH9K_HW_OPS_H
24018 +#define ATH9K_HW_OPS_H
24019 +
24020 +#include "hw.h"
24021 +
24022 +/* Hardware core and driver accessible callbacks */
24023 +
24024 +static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
24025 + int restore,
24026 + int power_off)
24027 +{
24028 + ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
24029 +}
24030 +
24031 +static inline void ath9k_hw_rxena(struct ath_hw *ah)
24032 +{
24033 + ath9k_hw_ops(ah)->rx_enable(ah);
24034 +}
24035 +
24036 +static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
24037 + u32 link)
24038 +{
24039 + ath9k_hw_ops(ah)->set_desc_link(ds, link);
24040 +}
24041 +
24042 +static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
24043 + u32 **link)
24044 +{
24045 + ath9k_hw_ops(ah)->get_desc_link(ds, link);
24046 +}
24047 +static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
24048 + struct ath9k_channel *chan,
24049 + u8 rxchainmask,
24050 + bool longcal)
24051 +{
24052 + return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
24053 +}
24054 +
24055 +static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
24056 +{
24057 + return ath9k_hw_ops(ah)->get_isr(ah, masked);
24058 +}
24059 +
24060 +static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
24061 + bool is_firstseg, bool is_lastseg,
24062 + const void *ds0, dma_addr_t buf_addr,
24063 + unsigned int qcu)
24064 +{
24065 + ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
24066 + ds0, buf_addr, qcu);
24067 +}
24068 +
24069 +static inline void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
24070 +{
24071 + ath9k_hw_ops(ah)->clear_txdesc(ah, ds);
24072 +}
24073 +
24074 +static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
24075 + struct ath_tx_status *ts)
24076 +{
24077 + return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
24078 +}
24079 +
24080 +static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
24081 + u32 pktLen, enum ath9k_pkt_type type,
24082 + u32 txPower, u32 keyIx,
24083 + enum ath9k_key_type keyType,
24084 + u32 flags)
24085 +{
24086 + ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
24087 + keyType, flags);
24088 +}
24089 +
24090 +static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
24091 + void *lastds,
24092 + u32 durUpdateEn, u32 rtsctsRate,
24093 + u32 rtsctsDuration,
24094 + struct ath9k_11n_rate_series series[],
24095 + u32 nseries, u32 flags)
24096 +{
24097 + ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
24098 + rtsctsRate, rtsctsDuration, series,
24099 + nseries, flags);
24100 +}
24101 +
24102 +static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
24103 + u32 aggrLen)
24104 +{
24105 + ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
24106 +}
24107 +
24108 +static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
24109 + u32 numDelims)
24110 +{
24111 + ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
24112 +}
24113 +
24114 +static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
24115 +{
24116 + ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
24117 +}
24118 +
24119 +static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
24120 +{
24121 + ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
24122 +}
24123 +
24124 +static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
24125 + u32 burstDuration)
24126 +{
24127 + ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
24128 +}
24129 +
24130 +static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
24131 + u32 vmf)
24132 +{
24133 + ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
24134 +}
24135 +
24136 +/* Private hardware call ops */
24137 +
24138 +/* PHY ops */
24139 +
24140 +static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
24141 + struct ath9k_channel *chan)
24142 +{
24143 + return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
24144 +}
24145 +
24146 +static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
24147 + struct ath9k_channel *chan)
24148 +{
24149 + ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
24150 +}
24151 +
24152 +static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
24153 +{
24154 + if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
24155 + return 0;
24156 +
24157 + return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
24158 +}
24159 +
24160 +static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
24161 +{
24162 + if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
24163 + return;
24164 +
24165 + ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
24166 +}
24167 +
24168 +static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
24169 + struct ath9k_channel *chan,
24170 + u16 modesIndex)
24171 +{
24172 + if (!ath9k_hw_private_ops(ah)->set_rf_regs)
24173 + return true;
24174 +
24175 + return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
24176 +}
24177 +
24178 +static inline void ath9k_hw_init_bb(struct ath_hw *ah,
24179 + struct ath9k_channel *chan)
24180 +{
24181 + return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
24182 +}
24183 +
24184 +static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
24185 + struct ath9k_channel *chan)
24186 +{
24187 + return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
24188 +}
24189 +
24190 +static inline int ath9k_hw_process_ini(struct ath_hw *ah,
24191 + struct ath9k_channel *chan)
24192 +{
24193 + return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
24194 +}
24195 +
24196 +static inline void ath9k_olc_init(struct ath_hw *ah)
24197 +{
24198 + if (!ath9k_hw_private_ops(ah)->olc_init)
24199 + return;
24200 +
24201 + return ath9k_hw_private_ops(ah)->olc_init(ah);
24202 +}
24203 +
24204 +static inline void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
24205 +{
24206 + return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
24207 +}
24208 +
24209 +static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
24210 +{
24211 + return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
24212 +}
24213 +
24214 +static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
24215 + struct ath9k_channel *chan)
24216 +{
24217 + return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
24218 +}
24219 +
24220 +static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah)
24221 +{
24222 + return ath9k_hw_private_ops(ah)->rfbus_req(ah);
24223 +}
24224 +
24225 +static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
24226 +{
24227 + return ath9k_hw_private_ops(ah)->rfbus_done(ah);
24228 +}
24229 +
24230 +static inline void ath9k_enable_rfkill(struct ath_hw *ah)
24231 +{
24232 + return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
24233 +}
24234 +
24235 +static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
24236 +{
24237 + if (!ath9k_hw_private_ops(ah)->restore_chainmask)
24238 + return;
24239 +
24240 + return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
24241 +}
24242 +
24243 +static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
24244 +{
24245 + return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
24246 +}
24247 +
24248 +static inline bool ath9k_hw_ani_control(struct ath_hw *ah,
24249 + enum ath9k_ani_cmd cmd, int param)
24250 +{
24251 + return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
24252 +}
24253 +
24254 +static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
24255 + int16_t nfarray[NUM_NF_READINGS])
24256 +{
24257 + ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
24258 +}
24259 +
24260 +static inline void ath9k_hw_loadnf(struct ath_hw *ah,
24261 + struct ath9k_channel *chan)
24262 +{
24263 + ath9k_hw_private_ops(ah)->loadnf(ah, chan);
24264 +}
24265 +
24266 +static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
24267 + struct ath9k_channel *chan)
24268 +{
24269 + return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
24270 +}
24271 +
24272 +static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
24273 + struct ath9k_cal_list *currCal)
24274 +{
24275 + ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
24276 +}
24277 +
24278 +static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
24279 + enum ath9k_cal_types calType)
24280 +{
24281 + return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
24282 +}
24283 +
24284 +#endif /* ATH9K_HW_OPS_H */
24285 --- a/drivers/net/wireless/ath/ath9k/hw.c
24286 +++ b/drivers/net/wireless/ath/ath9k/hw.c
24287 @@ -1,5 +1,5 @@
24288 /*
24289 - * Copyright (c) 2008-2009 Atheros Communications Inc.
24290 + * Copyright (c) 2008-2010 Atheros Communications Inc.
24291 *
24292 * Permission to use, copy, modify, and/or distribute this software for any
24293 * purpose with or without fee is hereby granted, provided that the above
24294 @@ -14,19 +14,17 @@
24295 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24296 */
24297
24298 -#include <linux/io.h>
24299 #include <asm/unaligned.h>
24300
24301 #include "hw.h"
24302 +#include "hw-ops.h"
24303 #include "rc.h"
24304 -#include "initvals.h"
24305
24306 #define ATH9K_CLOCK_RATE_CCK 22
24307 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
24308 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
24309
24310 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
24311 -static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
24312
24313 MODULE_AUTHOR("Atheros Communications");
24314 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24315 @@ -45,6 +43,37 @@ static void __exit ath9k_exit(void)
24316 }
24317 module_exit(ath9k_exit);
24318
24319 +/* Private hardware callbacks */
24320 +
24321 +static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
24322 +{
24323 + ath9k_hw_private_ops(ah)->init_cal_settings(ah);
24324 +}
24325 +
24326 +static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
24327 +{
24328 + ath9k_hw_private_ops(ah)->init_mode_regs(ah);
24329 +}
24330 +
24331 +static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
24332 +{
24333 + return ath9k_hw_private_ops(ah)->macversion_supported(ah->hw_version.macVersion);
24334 +}
24335 +
24336 +static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
24337 + struct ath9k_channel *chan)
24338 +{
24339 + return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
24340 +}
24341 +
24342 +static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
24343 +{
24344 + if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
24345 + return;
24346 +
24347 + ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
24348 +}
24349 +
24350 /********************/
24351 /* Helper Functions */
24352 /********************/
24353 @@ -232,21 +261,6 @@ static void ath9k_hw_read_revisions(stru
24354 }
24355 }
24356
24357 -static int ath9k_hw_get_radiorev(struct ath_hw *ah)
24358 -{
24359 - u32 val;
24360 - int i;
24361 -
24362 - REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
24363 -
24364 - for (i = 0; i < 8; i++)
24365 - REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
24366 - val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
24367 - val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
24368 -
24369 - return ath9k_hw_reverse_bits(val, 8);
24370 -}
24371 -
24372 /************************************/
24373 /* HW Attach, Detach, Init Routines */
24374 /************************************/
24375 @@ -269,18 +283,25 @@ static void ath9k_hw_disablepcie(struct
24376 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
24377 }
24378
24379 +/* This should work for all families including legacy */
24380 static bool ath9k_hw_chip_test(struct ath_hw *ah)
24381 {
24382 struct ath_common *common = ath9k_hw_common(ah);
24383 - u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
24384 + u32 regAddr[2] = { AR_STA_ID0 };
24385 u32 regHold[2];
24386 u32 patternData[4] = { 0x55555555,
24387 0xaaaaaaaa,
24388 0x66666666,
24389 0x99999999 };
24390 - int i, j;
24391 + int i, j, loop_max;
24392 +
24393 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
24394 + loop_max = 2;
24395 + regAddr[1] = AR_PHY_BASE + (8 << 2);
24396 + } else
24397 + loop_max = 1;
24398
24399 - for (i = 0; i < 2; i++) {
24400 + for (i = 0; i < loop_max; i++) {
24401 u32 addr = regAddr[i];
24402 u32 wrData, rdData;
24403
24404 @@ -368,7 +389,6 @@ static void ath9k_hw_init_config(struct
24405 if (num_possible_cpus() > 1)
24406 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
24407 }
24408 -EXPORT_SYMBOL(ath9k_hw_init);
24409
24410 static void ath9k_hw_init_defaults(struct ath_hw *ah)
24411 {
24412 @@ -396,44 +416,17 @@ static void ath9k_hw_init_defaults(struc
24413 ah->power_mode = ATH9K_PM_UNDEFINED;
24414 }
24415
24416 -static int ath9k_hw_rf_claim(struct ath_hw *ah)
24417 -{
24418 - u32 val;
24419 -
24420 - REG_WRITE(ah, AR_PHY(0), 0x00000007);
24421 -
24422 - val = ath9k_hw_get_radiorev(ah);
24423 - switch (val & AR_RADIO_SREV_MAJOR) {
24424 - case 0:
24425 - val = AR_RAD5133_SREV_MAJOR;
24426 - break;
24427 - case AR_RAD5133_SREV_MAJOR:
24428 - case AR_RAD5122_SREV_MAJOR:
24429 - case AR_RAD2133_SREV_MAJOR:
24430 - case AR_RAD2122_SREV_MAJOR:
24431 - break;
24432 - default:
24433 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
24434 - "Radio Chip Rev 0x%02X not supported\n",
24435 - val & AR_RADIO_SREV_MAJOR);
24436 - return -EOPNOTSUPP;
24437 - }
24438 -
24439 - ah->hw_version.analog5GhzRev = val;
24440 -
24441 - return 0;
24442 -}
24443 -
24444 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
24445 {
24446 struct ath_common *common = ath9k_hw_common(ah);
24447 u32 sum;
24448 int i;
24449 u16 eeval;
24450 + u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
24451
24452 sum = 0;
24453 for (i = 0; i < 3; i++) {
24454 - eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
24455 + eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
24456 sum += eeval;
24457 common->macaddr[2 * i] = eeval >> 8;
24458 common->macaddr[2 * i + 1] = eeval & 0xff;
24459 @@ -444,54 +437,6 @@ static int ath9k_hw_init_macaddr(struct
24460 return 0;
24461 }
24462
24463 -static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
24464 -{
24465 - u32 rxgain_type;
24466 -
24467 - if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
24468 - rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
24469 -
24470 - if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
24471 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24472 - ar9280Modes_backoff_13db_rxgain_9280_2,
24473 - ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
24474 - else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
24475 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24476 - ar9280Modes_backoff_23db_rxgain_9280_2,
24477 - ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
24478 - else
24479 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24480 - ar9280Modes_original_rxgain_9280_2,
24481 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
24482 - } else {
24483 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24484 - ar9280Modes_original_rxgain_9280_2,
24485 - ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
24486 - }
24487 -}
24488 -
24489 -static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
24490 -{
24491 - u32 txgain_type;
24492 -
24493 - if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
24494 - txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
24495 -
24496 - if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
24497 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24498 - ar9280Modes_high_power_tx_gain_9280_2,
24499 - ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
24500 - else
24501 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24502 - ar9280Modes_original_tx_gain_9280_2,
24503 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
24504 - } else {
24505 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24506 - ar9280Modes_original_tx_gain_9280_2,
24507 - ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
24508 - }
24509 -}
24510 -
24511 static int ath9k_hw_post_init(struct ath_hw *ah)
24512 {
24513 int ecode;
24514 @@ -501,9 +446,11 @@ static int ath9k_hw_post_init(struct ath
24515 return -ENODEV;
24516 }
24517
24518 - ecode = ath9k_hw_rf_claim(ah);
24519 - if (ecode != 0)
24520 - return ecode;
24521 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
24522 + ecode = ar9002_hw_rf_claim(ah);
24523 + if (ecode != 0)
24524 + return ecode;
24525 + }
24526
24527 ecode = ath9k_hw_eeprom_init(ah);
24528 if (ecode != 0)
24529 @@ -514,14 +461,12 @@ static int ath9k_hw_post_init(struct ath
24530 ah->eep_ops->get_eeprom_ver(ah),
24531 ah->eep_ops->get_eeprom_rev(ah));
24532
24533 - if (!AR_SREV_9280_10_OR_LATER(ah)) {
24534 - ecode = ath9k_hw_rf_alloc_ext_banks(ah);
24535 - if (ecode) {
24536 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
24537 - "Failed allocating banks for "
24538 - "external radio\n");
24539 - return ecode;
24540 - }
24541 + ecode = ath9k_hw_rf_alloc_ext_banks(ah);
24542 + if (ecode) {
24543 + ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
24544 + "Failed allocating banks for "
24545 + "external radio\n");
24546 + return ecode;
24547 }
24548
24549 if (!AR_SREV_9100(ah)) {
24550 @@ -532,351 +477,31 @@ static int ath9k_hw_post_init(struct ath
24551 return 0;
24552 }
24553
24554 -static bool ath9k_hw_devid_supported(u16 devid)
24555 +static void ath9k_hw_attach_ops(struct ath_hw *ah)
24556 {
24557 - switch (devid) {
24558 - case AR5416_DEVID_PCI:
24559 - case AR5416_DEVID_PCIE:
24560 - case AR5416_AR9100_DEVID:
24561 - case AR9160_DEVID_PCI:
24562 - case AR9280_DEVID_PCI:
24563 - case AR9280_DEVID_PCIE:
24564 - case AR9285_DEVID_PCIE:
24565 - case AR5416_DEVID_AR9287_PCI:
24566 - case AR5416_DEVID_AR9287_PCIE:
24567 - case AR2427_DEVID_PCIE:
24568 - return true;
24569 - default:
24570 - break;
24571 - }
24572 - return false;
24573 -}
24574 -
24575 -static bool ath9k_hw_macversion_supported(u32 macversion)
24576 -{
24577 - switch (macversion) {
24578 - case AR_SREV_VERSION_5416_PCI:
24579 - case AR_SREV_VERSION_5416_PCIE:
24580 - case AR_SREV_VERSION_9160:
24581 - case AR_SREV_VERSION_9100:
24582 - case AR_SREV_VERSION_9280:
24583 - case AR_SREV_VERSION_9285:
24584 - case AR_SREV_VERSION_9287:
24585 - case AR_SREV_VERSION_9271:
24586 - return true;
24587 - default:
24588 - break;
24589 - }
24590 - return false;
24591 -}
24592 -
24593 -static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
24594 -{
24595 - if (AR_SREV_9160_10_OR_LATER(ah)) {
24596 - if (AR_SREV_9280_10_OR_LATER(ah)) {
24597 - ah->iq_caldata.calData = &iq_cal_single_sample;
24598 - ah->adcgain_caldata.calData =
24599 - &adc_gain_cal_single_sample;
24600 - ah->adcdc_caldata.calData =
24601 - &adc_dc_cal_single_sample;
24602 - ah->adcdc_calinitdata.calData =
24603 - &adc_init_dc_cal;
24604 - } else {
24605 - ah->iq_caldata.calData = &iq_cal_multi_sample;
24606 - ah->adcgain_caldata.calData =
24607 - &adc_gain_cal_multi_sample;
24608 - ah->adcdc_caldata.calData =
24609 - &adc_dc_cal_multi_sample;
24610 - ah->adcdc_calinitdata.calData =
24611 - &adc_init_dc_cal;
24612 - }
24613 - ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
24614 - }
24615 -}
24616 -
24617 -static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
24618 -{
24619 - if (AR_SREV_9271(ah)) {
24620 - INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
24621 - ARRAY_SIZE(ar9271Modes_9271), 6);
24622 - INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
24623 - ARRAY_SIZE(ar9271Common_9271), 2);
24624 - INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
24625 - ar9271Common_normal_cck_fir_coeff_9271,
24626 - ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
24627 - INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
24628 - ar9271Common_japan_2484_cck_fir_coeff_9271,
24629 - ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
24630 - INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
24631 - ar9271Modes_9271_1_0_only,
24632 - ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
24633 - INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
24634 - ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
24635 - INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
24636 - ar9271Modes_high_power_tx_gain_9271,
24637 - ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
24638 - INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
24639 - ar9271Modes_normal_power_tx_gain_9271,
24640 - ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
24641 - return;
24642 - }
24643 -
24644 - if (AR_SREV_9287_11_OR_LATER(ah)) {
24645 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
24646 - ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
24647 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
24648 - ARRAY_SIZE(ar9287Common_9287_1_1), 2);
24649 - if (ah->config.pcie_clock_req)
24650 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24651 - ar9287PciePhy_clkreq_off_L1_9287_1_1,
24652 - ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
24653 - else
24654 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24655 - ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
24656 - ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
24657 - 2);
24658 - } else if (AR_SREV_9287_10_OR_LATER(ah)) {
24659 - INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
24660 - ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
24661 - INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
24662 - ARRAY_SIZE(ar9287Common_9287_1_0), 2);
24663 -
24664 - if (ah->config.pcie_clock_req)
24665 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24666 - ar9287PciePhy_clkreq_off_L1_9287_1_0,
24667 - ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
24668 - else
24669 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24670 - ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
24671 - ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
24672 - 2);
24673 - } else if (AR_SREV_9285_12_OR_LATER(ah)) {
24674 -
24675 -
24676 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
24677 - ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
24678 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
24679 - ARRAY_SIZE(ar9285Common_9285_1_2), 2);
24680 -
24681 - if (ah->config.pcie_clock_req) {
24682 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24683 - ar9285PciePhy_clkreq_off_L1_9285_1_2,
24684 - ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
24685 - } else {
24686 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24687 - ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
24688 - ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
24689 - 2);
24690 - }
24691 - } else if (AR_SREV_9285_10_OR_LATER(ah)) {
24692 - INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
24693 - ARRAY_SIZE(ar9285Modes_9285), 6);
24694 - INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
24695 - ARRAY_SIZE(ar9285Common_9285), 2);
24696 -
24697 - if (ah->config.pcie_clock_req) {
24698 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24699 - ar9285PciePhy_clkreq_off_L1_9285,
24700 - ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
24701 - } else {
24702 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24703 - ar9285PciePhy_clkreq_always_on_L1_9285,
24704 - ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
24705 - }
24706 - } else if (AR_SREV_9280_20_OR_LATER(ah)) {
24707 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
24708 - ARRAY_SIZE(ar9280Modes_9280_2), 6);
24709 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
24710 - ARRAY_SIZE(ar9280Common_9280_2), 2);
24711 -
24712 - if (ah->config.pcie_clock_req) {
24713 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24714 - ar9280PciePhy_clkreq_off_L1_9280,
24715 - ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
24716 - } else {
24717 - INIT_INI_ARRAY(&ah->iniPcieSerdes,
24718 - ar9280PciePhy_clkreq_always_on_L1_9280,
24719 - ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
24720 - }
24721 - INIT_INI_ARRAY(&ah->iniModesAdditional,
24722 - ar9280Modes_fast_clock_9280_2,
24723 - ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
24724 - } else if (AR_SREV_9280_10_OR_LATER(ah)) {
24725 - INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
24726 - ARRAY_SIZE(ar9280Modes_9280), 6);
24727 - INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
24728 - ARRAY_SIZE(ar9280Common_9280), 2);
24729 - } else if (AR_SREV_9160_10_OR_LATER(ah)) {
24730 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
24731 - ARRAY_SIZE(ar5416Modes_9160), 6);
24732 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
24733 - ARRAY_SIZE(ar5416Common_9160), 2);
24734 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
24735 - ARRAY_SIZE(ar5416Bank0_9160), 2);
24736 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
24737 - ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
24738 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
24739 - ARRAY_SIZE(ar5416Bank1_9160), 2);
24740 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
24741 - ARRAY_SIZE(ar5416Bank2_9160), 2);
24742 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
24743 - ARRAY_SIZE(ar5416Bank3_9160), 3);
24744 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
24745 - ARRAY_SIZE(ar5416Bank6_9160), 3);
24746 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
24747 - ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
24748 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
24749 - ARRAY_SIZE(ar5416Bank7_9160), 2);
24750 - if (AR_SREV_9160_11(ah)) {
24751 - INIT_INI_ARRAY(&ah->iniAddac,
24752 - ar5416Addac_91601_1,
24753 - ARRAY_SIZE(ar5416Addac_91601_1), 2);
24754 - } else {
24755 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
24756 - ARRAY_SIZE(ar5416Addac_9160), 2);
24757 - }
24758 - } else if (AR_SREV_9100_OR_LATER(ah)) {
24759 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
24760 - ARRAY_SIZE(ar5416Modes_9100), 6);
24761 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
24762 - ARRAY_SIZE(ar5416Common_9100), 2);
24763 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
24764 - ARRAY_SIZE(ar5416Bank0_9100), 2);
24765 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
24766 - ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
24767 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
24768 - ARRAY_SIZE(ar5416Bank1_9100), 2);
24769 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
24770 - ARRAY_SIZE(ar5416Bank2_9100), 2);
24771 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
24772 - ARRAY_SIZE(ar5416Bank3_9100), 3);
24773 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
24774 - ARRAY_SIZE(ar5416Bank6_9100), 3);
24775 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
24776 - ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
24777 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
24778 - ARRAY_SIZE(ar5416Bank7_9100), 2);
24779 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
24780 - ARRAY_SIZE(ar5416Addac_9100), 2);
24781 - } else {
24782 - INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
24783 - ARRAY_SIZE(ar5416Modes), 6);
24784 - INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
24785 - ARRAY_SIZE(ar5416Common), 2);
24786 - INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
24787 - ARRAY_SIZE(ar5416Bank0), 2);
24788 - INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
24789 - ARRAY_SIZE(ar5416BB_RfGain), 3);
24790 - INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
24791 - ARRAY_SIZE(ar5416Bank1), 2);
24792 - INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
24793 - ARRAY_SIZE(ar5416Bank2), 2);
24794 - INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
24795 - ARRAY_SIZE(ar5416Bank3), 3);
24796 - INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
24797 - ARRAY_SIZE(ar5416Bank6), 3);
24798 - INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
24799 - ARRAY_SIZE(ar5416Bank6TPC), 3);
24800 - INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
24801 - ARRAY_SIZE(ar5416Bank7), 2);
24802 - INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
24803 - ARRAY_SIZE(ar5416Addac), 2);
24804 - }
24805 -}
24806 -
24807 -static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
24808 -{
24809 - if (AR_SREV_9287_11_OR_LATER(ah))
24810 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24811 - ar9287Modes_rx_gain_9287_1_1,
24812 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
24813 - else if (AR_SREV_9287_10(ah))
24814 - INIT_INI_ARRAY(&ah->iniModesRxGain,
24815 - ar9287Modes_rx_gain_9287_1_0,
24816 - ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
24817 - else if (AR_SREV_9280_20(ah))
24818 - ath9k_hw_init_rxgain_ini(ah);
24819 -
24820 - if (AR_SREV_9287_11_OR_LATER(ah)) {
24821 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24822 - ar9287Modes_tx_gain_9287_1_1,
24823 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
24824 - } else if (AR_SREV_9287_10(ah)) {
24825 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24826 - ar9287Modes_tx_gain_9287_1_0,
24827 - ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
24828 - } else if (AR_SREV_9280_20(ah)) {
24829 - ath9k_hw_init_txgain_ini(ah);
24830 - } else if (AR_SREV_9285_12_OR_LATER(ah)) {
24831 - u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
24832 -
24833 - /* txgain table */
24834 - if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
24835 - if (AR_SREV_9285E_20(ah)) {
24836 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24837 - ar9285Modes_XE2_0_high_power,
24838 - ARRAY_SIZE(
24839 - ar9285Modes_XE2_0_high_power), 6);
24840 - } else {
24841 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24842 - ar9285Modes_high_power_tx_gain_9285_1_2,
24843 - ARRAY_SIZE(
24844 - ar9285Modes_high_power_tx_gain_9285_1_2), 6);
24845 - }
24846 - } else {
24847 - if (AR_SREV_9285E_20(ah)) {
24848 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24849 - ar9285Modes_XE2_0_normal_power,
24850 - ARRAY_SIZE(
24851 - ar9285Modes_XE2_0_normal_power), 6);
24852 - } else {
24853 - INIT_INI_ARRAY(&ah->iniModesTxGain,
24854 - ar9285Modes_original_tx_gain_9285_1_2,
24855 - ARRAY_SIZE(
24856 - ar9285Modes_original_tx_gain_9285_1_2), 6);
24857 - }
24858 - }
24859 - }
24860 -}
24861 -
24862 -static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
24863 -{
24864 - struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
24865 - struct ath_common *common = ath9k_hw_common(ah);
24866 -
24867 - ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
24868 - (ah->eep_map != EEP_MAP_4KBITS) &&
24869 - ((pBase->version & 0xff) > 0x0a) &&
24870 - (pBase->pwdclkind == 0);
24871 -
24872 - if (ah->need_an_top2_fixup)
24873 - ath_print(common, ATH_DBG_EEPROM,
24874 - "needs fixup for AR_AN_TOP2 register\n");
24875 + if (AR_SREV_9300_20_OR_LATER(ah))
24876 + ar9003_hw_attach_ops(ah);
24877 + else
24878 + ar9002_hw_attach_ops(ah);
24879 }
24880
24881 -int ath9k_hw_init(struct ath_hw *ah)
24882 +/* Called for all hardware families */
24883 +static int __ath9k_hw_init(struct ath_hw *ah)
24884 {
24885 struct ath_common *common = ath9k_hw_common(ah);
24886 int r = 0;
24887
24888 - if (common->bus_ops->ath_bus_type != ATH_USB) {
24889 - if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
24890 - ath_print(common, ATH_DBG_FATAL,
24891 - "Unsupported device ID: 0x%0x\n",
24892 - ah->hw_version.devid);
24893 - return -EOPNOTSUPP;
24894 - }
24895 - }
24896 -
24897 - ath9k_hw_init_defaults(ah);
24898 - ath9k_hw_init_config(ah);
24899 -
24900 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
24901 ath_print(common, ATH_DBG_FATAL,
24902 "Couldn't reset chip\n");
24903 return -EIO;
24904 }
24905
24906 + ath9k_hw_init_defaults(ah);
24907 + ath9k_hw_init_config(ah);
24908 +
24909 + ath9k_hw_attach_ops(ah);
24910 +
24911 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
24912 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
24913 return -EIO;
24914 @@ -901,7 +526,7 @@ int ath9k_hw_init(struct ath_hw *ah)
24915 else
24916 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
24917
24918 - if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
24919 + if (!ath9k_hw_macversion_supported(ah)) {
24920 ath_print(common, ATH_DBG_FATAL,
24921 "Mac Chip Rev 0x%02x.%x is not supported by "
24922 "this driver\n", ah->hw_version.macVersion,
24923 @@ -909,28 +534,15 @@ int ath9k_hw_init(struct ath_hw *ah)
24924 return -EOPNOTSUPP;
24925 }
24926
24927 - if (AR_SREV_9100(ah)) {
24928 - ah->iq_caldata.calData = &iq_cal_multi_sample;
24929 - ah->supp_cals = IQ_MISMATCH_CAL;
24930 - ah->is_pciexpress = false;
24931 - }
24932 -
24933 - if (AR_SREV_9271(ah))
24934 + if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
24935 ah->is_pciexpress = false;
24936
24937 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
24938 -
24939 ath9k_hw_init_cal_settings(ah);
24940
24941 ah->ani_function = ATH9K_ANI_ALL;
24942 - if (AR_SREV_9280_10_OR_LATER(ah)) {
24943 + if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
24944 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
24945 - ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
24946 - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
24947 - } else {
24948 - ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
24949 - ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
24950 - }
24951
24952 ath9k_hw_init_mode_regs(ah);
24953
24954 @@ -939,15 +551,8 @@ int ath9k_hw_init(struct ath_hw *ah)
24955 else
24956 ath9k_hw_disablepcie(ah);
24957
24958 - /* Support for Japan ch.14 (2484) spread */
24959 - if (AR_SREV_9287_11_OR_LATER(ah)) {
24960 - INIT_INI_ARRAY(&ah->iniCckfirNormal,
24961 - ar9287Common_normal_cck_fir_coeff_92871_1,
24962 - ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
24963 - INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
24964 - ar9287Common_japan_2484_cck_fir_coeff_92871_1,
24965 - ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
24966 - }
24967 + if (!AR_SREV_9300_20_OR_LATER(ah))
24968 + ar9002_hw_cck_chan14_spread(ah);
24969
24970 r = ath9k_hw_post_init(ah);
24971 if (r)
24972 @@ -958,8 +563,6 @@ int ath9k_hw_init(struct ath_hw *ah)
24973 if (r)
24974 return r;
24975
24976 - ath9k_hw_init_eeprom_fix(ah);
24977 -
24978 r = ath9k_hw_init_macaddr(ah);
24979 if (r) {
24980 ath_print(common, ATH_DBG_FATAL,
24981 @@ -972,6 +575,9 @@ int ath9k_hw_init(struct ath_hw *ah)
24982 else
24983 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
24984
24985 + if (AR_SREV_9300_20_OR_LATER(ah))
24986 + ar9003_hw_set_nf_limits(ah);
24987 +
24988 ath9k_init_nfcal_hist_buffer(ah);
24989
24990 common->state = ATH_HW_INITIALIZED;
24991 @@ -979,21 +585,45 @@ int ath9k_hw_init(struct ath_hw *ah)
24992 return 0;
24993 }
24994
24995 -static void ath9k_hw_init_bb(struct ath_hw *ah,
24996 - struct ath9k_channel *chan)
24997 +int ath9k_hw_init(struct ath_hw *ah)
24998 {
24999 - u32 synthDelay;
25000 + int ret;
25001 + struct ath_common *common = ath9k_hw_common(ah);
25002
25003 - synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
25004 - if (IS_CHAN_B(chan))
25005 - synthDelay = (4 * synthDelay) / 22;
25006 - else
25007 - synthDelay /= 10;
25008 + /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
25009 + switch (ah->hw_version.devid) {
25010 + case AR5416_DEVID_PCI:
25011 + case AR5416_DEVID_PCIE:
25012 + case AR5416_AR9100_DEVID:
25013 + case AR9160_DEVID_PCI:
25014 + case AR9280_DEVID_PCI:
25015 + case AR9280_DEVID_PCIE:
25016 + case AR9285_DEVID_PCIE:
25017 + case AR9287_DEVID_PCI:
25018 + case AR9287_DEVID_PCIE:
25019 + case AR2427_DEVID_PCIE:
25020 + case AR9300_DEVID_PCIE:
25021 + break;
25022 + default:
25023 + if (common->bus_ops->ath_bus_type == ATH_USB)
25024 + break;
25025 + ath_print(common, ATH_DBG_FATAL,
25026 + "Hardware device ID 0x%04x not supported\n",
25027 + ah->hw_version.devid);
25028 + return -EOPNOTSUPP;
25029 + }
25030
25031 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
25032 + ret = __ath9k_hw_init(ah);
25033 + if (ret) {
25034 + ath_print(common, ATH_DBG_FATAL,
25035 + "Unable to initialize hardware; "
25036 + "initialization status: %d\n", ret);
25037 + return ret;
25038 + }
25039
25040 - udelay(synthDelay + BASE_ACTIVATE_DELAY);
25041 + return 0;
25042 }
25043 +EXPORT_SYMBOL(ath9k_hw_init);
25044
25045 static void ath9k_hw_init_qos(struct ath_hw *ah)
25046 {
25047 @@ -1015,64 +645,8 @@ static void ath9k_hw_init_qos(struct ath
25048 static void ath9k_hw_init_pll(struct ath_hw *ah,
25049 struct ath9k_channel *chan)
25050 {
25051 - u32 pll;
25052 -
25053 - if (AR_SREV_9100(ah)) {
25054 - if (chan && IS_CHAN_5GHZ(chan))
25055 - pll = 0x1450;
25056 - else
25057 - pll = 0x1458;
25058 - } else {
25059 - if (AR_SREV_9280_10_OR_LATER(ah)) {
25060 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
25061 -
25062 - if (chan && IS_CHAN_HALF_RATE(chan))
25063 - pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
25064 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
25065 - pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
25066 -
25067 - if (chan && IS_CHAN_5GHZ(chan)) {
25068 - pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
25069 -
25070 -
25071 - if (AR_SREV_9280_20(ah)) {
25072 - if (((chan->channel % 20) == 0)
25073 - || ((chan->channel % 10) == 0))
25074 - pll = 0x2850;
25075 - else
25076 - pll = 0x142c;
25077 - }
25078 - } else {
25079 - pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
25080 - }
25081 -
25082 - } else if (AR_SREV_9160_10_OR_LATER(ah)) {
25083 -
25084 - pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
25085 -
25086 - if (chan && IS_CHAN_HALF_RATE(chan))
25087 - pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
25088 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
25089 - pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
25090 -
25091 - if (chan && IS_CHAN_5GHZ(chan))
25092 - pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
25093 - else
25094 - pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
25095 - } else {
25096 - pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
25097 + u32 pll = ath9k_hw_compute_pll_control(ah, chan);
25098
25099 - if (chan && IS_CHAN_HALF_RATE(chan))
25100 - pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
25101 - else if (chan && IS_CHAN_QUARTER_RATE(chan))
25102 - pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
25103 -
25104 - if (chan && IS_CHAN_5GHZ(chan))
25105 - pll |= SM(0xa, AR_RTC_PLL_DIV);
25106 - else
25107 - pll |= SM(0xb, AR_RTC_PLL_DIV);
25108 - }
25109 - }
25110 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
25111
25112 /* Switch the core clock for ar9271 to 117Mhz */
25113 @@ -1086,43 +660,6 @@ static void ath9k_hw_init_pll(struct ath
25114 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
25115 }
25116
25117 -static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
25118 -{
25119 - int rx_chainmask, tx_chainmask;
25120 -
25121 - rx_chainmask = ah->rxchainmask;
25122 - tx_chainmask = ah->txchainmask;
25123 -
25124 - switch (rx_chainmask) {
25125 - case 0x5:
25126 - REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
25127 - AR_PHY_SWAP_ALT_CHAIN);
25128 - case 0x3:
25129 - if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
25130 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
25131 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
25132 - break;
25133 - }
25134 - case 0x1:
25135 - case 0x2:
25136 - case 0x7:
25137 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
25138 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
25139 - break;
25140 - default:
25141 - break;
25142 - }
25143 -
25144 - REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
25145 - if (tx_chainmask == 0x5) {
25146 - REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
25147 - AR_PHY_SWAP_ALT_CHAIN);
25148 - }
25149 - if (AR_SREV_9100(ah))
25150 - REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
25151 - REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
25152 -}
25153 -
25154 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
25155 enum nl80211_iftype opmode)
25156 {
25157 @@ -1132,12 +669,24 @@ static void ath9k_hw_init_interrupt_mask
25158 AR_IMR_RXORN |
25159 AR_IMR_BCNMISC;
25160
25161 - if (ah->config.rx_intr_mitigation)
25162 - imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
25163 - else
25164 - imr_reg |= AR_IMR_RXOK;
25165 + if (AR_SREV_9300_20_OR_LATER(ah)) {
25166 + imr_reg |= AR_IMR_RXOK_HP;
25167 + if (ah->config.rx_intr_mitigation)
25168 + imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
25169 + else
25170 + imr_reg |= AR_IMR_RXOK_LP;
25171 +
25172 + } else {
25173 + if (ah->config.rx_intr_mitigation)
25174 + imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
25175 + else
25176 + imr_reg |= AR_IMR_RXOK;
25177 + }
25178
25179 - imr_reg |= AR_IMR_TXOK;
25180 + if (ah->config.tx_intr_mitigation)
25181 + imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
25182 + else
25183 + imr_reg |= AR_IMR_TXOK;
25184
25185 if (opmode == NL80211_IFTYPE_AP)
25186 imr_reg |= AR_IMR_MIB;
25187 @@ -1151,6 +700,13 @@ static void ath9k_hw_init_interrupt_mask
25188 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
25189 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
25190 }
25191 +
25192 + if (AR_SREV_9300_20_OR_LATER(ah)) {
25193 + REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
25194 + REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
25195 + REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
25196 + REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
25197 + }
25198 }
25199
25200 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
25201 @@ -1214,310 +770,72 @@ void ath9k_hw_init_global_settings(struc
25202 /*
25203 * Workaround for early ACK timeouts, add an offset to match the
25204 * initval's 64us ack timeout value.
25205 - * This was initially only meant to work around an issue with delayed
25206 - * BA frames in some implementations, but it has been found to fix ACK
25207 - * timeout issues in other cases as well.
25208 - */
25209 - if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
25210 - acktimeout += 64 - sifstime - ah->slottime;
25211 -
25212 - ath9k_hw_setslottime(ah, slottime);
25213 - ath9k_hw_set_ack_timeout(ah, acktimeout);
25214 - ath9k_hw_set_cts_timeout(ah, acktimeout);
25215 - if (ah->globaltxtimeout != (u32) -1)
25216 - ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
25217 -}
25218 -EXPORT_SYMBOL(ath9k_hw_init_global_settings);
25219 -
25220 -void ath9k_hw_deinit(struct ath_hw *ah)
25221 -{
25222 - struct ath_common *common = ath9k_hw_common(ah);
25223 -
25224 - if (common->state < ATH_HW_INITIALIZED)
25225 - goto free_hw;
25226 -
25227 - if (!AR_SREV_9100(ah))
25228 - ath9k_hw_ani_disable(ah);
25229 -
25230 - ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
25231 -
25232 -free_hw:
25233 - if (!AR_SREV_9280_10_OR_LATER(ah))
25234 - ath9k_hw_rf_free_ext_banks(ah);
25235 -}
25236 -EXPORT_SYMBOL(ath9k_hw_deinit);
25237 -
25238 -/*******/
25239 -/* INI */
25240 -/*******/
25241 -
25242 -static void ath9k_hw_override_ini(struct ath_hw *ah,
25243 - struct ath9k_channel *chan)
25244 -{
25245 - u32 val;
25246 -
25247 - /*
25248 - * Set the RX_ABORT and RX_DIS and clear if off only after
25249 - * RXE is set for MAC. This prevents frames with corrupted
25250 - * descriptor status.
25251 - */
25252 - REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
25253 -
25254 - if (AR_SREV_9280_10_OR_LATER(ah)) {
25255 - val = REG_READ(ah, AR_PCU_MISC_MODE2);
25256 -
25257 - if (!AR_SREV_9271(ah))
25258 - val &= ~AR_PCU_MISC_MODE2_HWWAR1;
25259 -
25260 - if (AR_SREV_9287_10_OR_LATER(ah))
25261 - val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
25262 -
25263 - REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
25264 - }
25265 -
25266 - if (!AR_SREV_5416_20_OR_LATER(ah) ||
25267 - AR_SREV_9280_10_OR_LATER(ah))
25268 - return;
25269 - /*
25270 - * Disable BB clock gating
25271 - * Necessary to avoid issues on AR5416 2.0
25272 - */
25273 - REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
25274 -
25275 - /*
25276 - * Disable RIFS search on some chips to avoid baseband
25277 - * hang issues.
25278 - */
25279 - if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
25280 - val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
25281 - val &= ~AR_PHY_RIFS_INIT_DELAY;
25282 - REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
25283 - }
25284 -}
25285 -
25286 -static void ath9k_olc_init(struct ath_hw *ah)
25287 -{
25288 - u32 i;
25289 -
25290 - if (OLC_FOR_AR9287_10_LATER) {
25291 - REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
25292 - AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
25293 - ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
25294 - AR9287_AN_TXPC0_TXPCMODE,
25295 - AR9287_AN_TXPC0_TXPCMODE_S,
25296 - AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
25297 - udelay(100);
25298 - } else {
25299 - for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
25300 - ah->originalGain[i] =
25301 - MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
25302 - AR_PHY_TX_GAIN);
25303 - ah->PDADCdelta = 0;
25304 - }
25305 -}
25306 -
25307 -static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
25308 - struct ath9k_channel *chan)
25309 -{
25310 - u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
25311 -
25312 - if (IS_CHAN_B(chan))
25313 - ctl |= CTL_11B;
25314 - else if (IS_CHAN_G(chan))
25315 - ctl |= CTL_11G;
25316 - else
25317 - ctl |= CTL_11A;
25318 -
25319 - return ctl;
25320 -}
25321 -
25322 -static int ath9k_hw_process_ini(struct ath_hw *ah,
25323 - struct ath9k_channel *chan)
25324 -{
25325 - struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
25326 - int i, regWrites = 0;
25327 - struct ieee80211_channel *channel = chan->chan;
25328 - u32 modesIndex, freqIndex;
25329 -
25330 - switch (chan->chanmode) {
25331 - case CHANNEL_A:
25332 - case CHANNEL_A_HT20:
25333 - modesIndex = 1;
25334 - freqIndex = 1;
25335 - break;
25336 - case CHANNEL_A_HT40PLUS:
25337 - case CHANNEL_A_HT40MINUS:
25338 - modesIndex = 2;
25339 - freqIndex = 1;
25340 - break;
25341 - case CHANNEL_G:
25342 - case CHANNEL_G_HT20:
25343 - case CHANNEL_B:
25344 - modesIndex = 4;
25345 - freqIndex = 2;
25346 - break;
25347 - case CHANNEL_G_HT40PLUS:
25348 - case CHANNEL_G_HT40MINUS:
25349 - modesIndex = 3;
25350 - freqIndex = 2;
25351 - break;
25352 -
25353 - default:
25354 - return -EINVAL;
25355 - }
25356 -
25357 - /* Set correct baseband to analog shift setting to access analog chips */
25358 - REG_WRITE(ah, AR_PHY(0), 0x00000007);
25359 -
25360 - /* Write ADDAC shifts */
25361 - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
25362 - ah->eep_ops->set_addac(ah, chan);
25363 -
25364 - if (AR_SREV_5416_22_OR_LATER(ah)) {
25365 - REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
25366 - } else {
25367 - struct ar5416IniArray temp;
25368 - u32 addacSize =
25369 - sizeof(u32) * ah->iniAddac.ia_rows *
25370 - ah->iniAddac.ia_columns;
25371 -
25372 - /* For AR5416 2.0/2.1 */
25373 - memcpy(ah->addac5416_21,
25374 - ah->iniAddac.ia_array, addacSize);
25375 -
25376 - /* override CLKDRV value at [row, column] = [31, 1] */
25377 - (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
25378 -
25379 - temp.ia_array = ah->addac5416_21;
25380 - temp.ia_columns = ah->iniAddac.ia_columns;
25381 - temp.ia_rows = ah->iniAddac.ia_rows;
25382 - REG_WRITE_ARRAY(&temp, 1, regWrites);
25383 - }
25384 -
25385 - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
25386 -
25387 - for (i = 0; i < ah->iniModes.ia_rows; i++) {
25388 - u32 reg = INI_RA(&ah->iniModes, i, 0);
25389 - u32 val = INI_RA(&ah->iniModes, i, modesIndex);
25390 -
25391 - if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
25392 - val &= ~AR_AN_TOP2_PWDCLKIND;
25393 -
25394 - REG_WRITE(ah, reg, val);
25395 -
25396 - if (reg >= 0x7800 && reg < 0x78a0
25397 - && ah->config.analog_shiftreg) {
25398 - udelay(100);
25399 - }
25400 -
25401 - DO_DELAY(regWrites);
25402 - }
25403 -
25404 - if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
25405 - REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
25406 -
25407 - if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
25408 - AR_SREV_9287_10_OR_LATER(ah))
25409 - REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
25410 -
25411 - if (AR_SREV_9271_10(ah))
25412 - REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
25413 - modesIndex, regWrites);
25414 -
25415 - /* Write common array parameters */
25416 - for (i = 0; i < ah->iniCommon.ia_rows; i++) {
25417 - u32 reg = INI_RA(&ah->iniCommon, i, 0);
25418 - u32 val = INI_RA(&ah->iniCommon, i, 1);
25419 -
25420 - REG_WRITE(ah, reg, val);
25421 -
25422 - if (reg >= 0x7800 && reg < 0x78a0
25423 - && ah->config.analog_shiftreg) {
25424 - udelay(100);
25425 - }
25426 -
25427 - DO_DELAY(regWrites);
25428 - }
25429 -
25430 - if (AR_SREV_9271(ah)) {
25431 - if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
25432 - REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
25433 - modesIndex, regWrites);
25434 - else
25435 - REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
25436 - modesIndex, regWrites);
25437 - }
25438 -
25439 - ath9k_hw_write_regs(ah, freqIndex, regWrites);
25440 + * This was initially only meant to work around an issue with delayed
25441 + * BA frames in some implementations, but it has been found to fix ACK
25442 + * timeout issues in other cases as well.
25443 + */
25444 + if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
25445 + acktimeout += 64 - sifstime - ah->slottime;
25446
25447 - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
25448 - REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
25449 - regWrites);
25450 - }
25451 + ath9k_hw_setslottime(ah, slottime);
25452 + ath9k_hw_set_ack_timeout(ah, acktimeout);
25453 + ath9k_hw_set_cts_timeout(ah, acktimeout);
25454 + if (ah->globaltxtimeout != (u32) -1)
25455 + ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
25456 +}
25457 +EXPORT_SYMBOL(ath9k_hw_init_global_settings);
25458
25459 - ath9k_hw_override_ini(ah, chan);
25460 - ath9k_hw_set_regs(ah, chan);
25461 - ath9k_hw_init_chain_masks(ah);
25462 +void ath9k_hw_deinit(struct ath_hw *ah)
25463 +{
25464 + struct ath_common *common = ath9k_hw_common(ah);
25465
25466 - if (OLC_FOR_AR9280_20_LATER)
25467 - ath9k_olc_init(ah);
25468 + if (common->state < ATH_HW_INITIALIZED)
25469 + goto free_hw;
25470
25471 - /* Set TX power */
25472 - ah->eep_ops->set_txpower(ah, chan,
25473 - ath9k_regd_get_ctl(regulatory, chan),
25474 - channel->max_antenna_gain * 2,
25475 - channel->max_power * 2,
25476 - min((u32) MAX_RATE_POWER,
25477 - (u32) regulatory->power_limit));
25478 + if (!AR_SREV_9100(ah))
25479 + ath9k_hw_ani_disable(ah);
25480
25481 - /* Write analog registers */
25482 - if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
25483 - ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
25484 - "ar5416SetRfRegs failed\n");
25485 - return -EIO;
25486 - }
25487 + ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
25488
25489 - return 0;
25490 +free_hw:
25491 + ath9k_hw_rf_free_ext_banks(ah);
25492 }
25493 +EXPORT_SYMBOL(ath9k_hw_deinit);
25494
25495 -/****************************************/
25496 -/* Reset and Channel Switching Routines */
25497 -/****************************************/
25498 +/*******/
25499 +/* INI */
25500 +/*******/
25501
25502 -static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
25503 +u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
25504 {
25505 - u32 rfMode = 0;
25506 -
25507 - if (chan == NULL)
25508 - return;
25509 -
25510 - rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
25511 - ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
25512 -
25513 - if (!AR_SREV_9280_10_OR_LATER(ah))
25514 - rfMode |= (IS_CHAN_5GHZ(chan)) ?
25515 - AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
25516 + u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
25517
25518 - if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
25519 - rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
25520 + if (IS_CHAN_B(chan))
25521 + ctl |= CTL_11B;
25522 + else if (IS_CHAN_G(chan))
25523 + ctl |= CTL_11G;
25524 + else
25525 + ctl |= CTL_11A;
25526
25527 - REG_WRITE(ah, AR_PHY_MODE, rfMode);
25528 + return ctl;
25529 }
25530
25531 -static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
25532 -{
25533 - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
25534 -}
25535 +/****************************************/
25536 +/* Reset and Channel Switching Routines */
25537 +/****************************************/
25538
25539 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
25540 {
25541 + struct ath_common *common = ath9k_hw_common(ah);
25542 u32 regval;
25543
25544 /*
25545 * set AHB_MODE not to do cacheline prefetches
25546 */
25547 - regval = REG_READ(ah, AR_AHB_MODE);
25548 - REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
25549 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
25550 + regval = REG_READ(ah, AR_AHB_MODE);
25551 + REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
25552 + }
25553
25554 /*
25555 * let mac dma reads be in 128 byte chunks
25556 @@ -1530,7 +848,8 @@ static inline void ath9k_hw_set_dma(stru
25557 * The initial value depends on whether aggregation is enabled, and is
25558 * adjusted whenever underruns are detected.
25559 */
25560 - REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
25561 + if (!AR_SREV_9300_20_OR_LATER(ah))
25562 + REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
25563
25564 /*
25565 * let mac dma writes be in 128 byte chunks
25566 @@ -1543,6 +862,14 @@ static inline void ath9k_hw_set_dma(stru
25567 */
25568 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
25569
25570 + if (AR_SREV_9300_20_OR_LATER(ah)) {
25571 + REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
25572 + REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
25573 +
25574 + ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
25575 + ah->caps.rx_status_len);
25576 + }
25577 +
25578 /*
25579 * reduce the number of usable entries in PCU TXBUF to avoid
25580 * wrap around issues.
25581 @@ -1558,6 +885,9 @@ static inline void ath9k_hw_set_dma(stru
25582 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
25583 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
25584 }
25585 +
25586 + if (AR_SREV_9300_20_OR_LATER(ah))
25587 + ath9k_hw_reset_txstatus_ring(ah);
25588 }
25589
25590 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
25591 @@ -1585,10 +915,8 @@ static void ath9k_hw_set_operating_mode(
25592 }
25593 }
25594
25595 -static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
25596 - u32 coef_scaled,
25597 - u32 *coef_mantissa,
25598 - u32 *coef_exponent)
25599 +void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
25600 + u32 *coef_mantissa, u32 *coef_exponent)
25601 {
25602 u32 coef_exp, coef_man;
25603
25604 @@ -1604,40 +932,6 @@ static inline void ath9k_hw_get_delta_sl
25605 *coef_exponent = coef_exp - 16;
25606 }
25607
25608 -static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
25609 - struct ath9k_channel *chan)
25610 -{
25611 - u32 coef_scaled, ds_coef_exp, ds_coef_man;
25612 - u32 clockMhzScaled = 0x64000000;
25613 - struct chan_centers centers;
25614 -
25615 - if (IS_CHAN_HALF_RATE(chan))
25616 - clockMhzScaled = clockMhzScaled >> 1;
25617 - else if (IS_CHAN_QUARTER_RATE(chan))
25618 - clockMhzScaled = clockMhzScaled >> 2;
25619 -
25620 - ath9k_hw_get_channel_centers(ah, chan, &centers);
25621 - coef_scaled = clockMhzScaled / centers.synth_center;
25622 -
25623 - ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
25624 - &ds_coef_exp);
25625 -
25626 - REG_RMW_FIELD(ah, AR_PHY_TIMING3,
25627 - AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
25628 - REG_RMW_FIELD(ah, AR_PHY_TIMING3,
25629 - AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
25630 -
25631 - coef_scaled = (9 * coef_scaled) / 10;
25632 -
25633 - ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
25634 - &ds_coef_exp);
25635 -
25636 - REG_RMW_FIELD(ah, AR_PHY_HALFGI,
25637 - AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
25638 - REG_RMW_FIELD(ah, AR_PHY_HALFGI,
25639 - AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
25640 -}
25641 -
25642 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
25643 {
25644 u32 rst_flags;
25645 @@ -1662,11 +956,16 @@ static bool ath9k_hw_set_reset(struct at
25646 if (tmpReg &
25647 (AR_INTR_SYNC_LOCAL_TIMEOUT |
25648 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
25649 + u32 val;
25650 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
25651 - REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
25652 - } else {
25653 +
25654 + val = AR_RC_HOSTIF;
25655 + if (!AR_SREV_9300_20_OR_LATER(ah))
25656 + val |= AR_RC_AHB;
25657 + REG_WRITE(ah, AR_RC, val);
25658 +
25659 + } else if (!AR_SREV_9300_20_OR_LATER(ah))
25660 REG_WRITE(ah, AR_RC, AR_RC_AHB);
25661 - }
25662
25663 rst_flags = AR_RTC_RC_MAC_WARM;
25664 if (type == ATH9K_RESET_COLD)
25665 @@ -1697,13 +996,15 @@ static bool ath9k_hw_set_reset_power_on(
25666 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
25667 AR_RTC_FORCE_WAKE_ON_INT);
25668
25669 - if (!AR_SREV_9100(ah))
25670 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
25671 REG_WRITE(ah, AR_RC, AR_RC_AHB);
25672
25673 REG_WRITE(ah, AR_RTC_RESET, 0);
25674 - udelay(2);
25675
25676 - if (!AR_SREV_9100(ah))
25677 + if (!AR_SREV_9300_20_OR_LATER(ah))
25678 + udelay(2);
25679 +
25680 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
25681 REG_WRITE(ah, AR_RC, 0);
25682
25683 REG_WRITE(ah, AR_RTC_RESET, 1);
25684 @@ -1739,34 +1040,6 @@ static bool ath9k_hw_set_reset_reg(struc
25685 }
25686 }
25687
25688 -static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
25689 -{
25690 - u32 phymode;
25691 - u32 enableDacFifo = 0;
25692 -
25693 - if (AR_SREV_9285_10_OR_LATER(ah))
25694 - enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
25695 - AR_PHY_FC_ENABLE_DAC_FIFO);
25696 -
25697 - phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
25698 - | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
25699 -
25700 - if (IS_CHAN_HT40(chan)) {
25701 - phymode |= AR_PHY_FC_DYN2040_EN;
25702 -
25703 - if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
25704 - (chan->chanmode == CHANNEL_G_HT40PLUS))
25705 - phymode |= AR_PHY_FC_DYN2040_PRI_CH;
25706 -
25707 - }
25708 - REG_WRITE(ah, AR_PHY_TURBO, phymode);
25709 -
25710 - ath9k_hw_set11nmac2040(ah);
25711 -
25712 - REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
25713 - REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
25714 -}
25715 -
25716 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
25717 struct ath9k_channel *chan)
25718 {
25719 @@ -1792,7 +1065,7 @@ static bool ath9k_hw_channel_change(stru
25720 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
25721 struct ath_common *common = ath9k_hw_common(ah);
25722 struct ieee80211_channel *channel = chan->chan;
25723 - u32 synthDelay, qnum;
25724 + u32 qnum;
25725 int r;
25726
25727 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
25728 @@ -1804,17 +1077,15 @@ static bool ath9k_hw_channel_change(stru
25729 }
25730 }
25731
25732 - REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
25733 - if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
25734 - AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
25735 + if (!ath9k_hw_rfbus_req(ah)) {
25736 ath_print(common, ATH_DBG_FATAL,
25737 "Could not kill baseband RX\n");
25738 return false;
25739 }
25740
25741 - ath9k_hw_set_regs(ah, chan);
25742 + ath9k_hw_set_channel_regs(ah, chan);
25743
25744 - r = ah->ath9k_hw_rf_set_freq(ah, chan);
25745 + r = ath9k_hw_rf_set_freq(ah, chan);
25746 if (r) {
25747 ath_print(common, ATH_DBG_FATAL,
25748 "Failed to set channel\n");
25749 @@ -1828,20 +1099,12 @@ static bool ath9k_hw_channel_change(stru
25750 min((u32) MAX_RATE_POWER,
25751 (u32) regulatory->power_limit));
25752
25753 - synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
25754 - if (IS_CHAN_B(chan))
25755 - synthDelay = (4 * synthDelay) / 22;
25756 - else
25757 - synthDelay /= 10;
25758 -
25759 - udelay(synthDelay + BASE_ACTIVATE_DELAY);
25760 -
25761 - REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
25762 + ath9k_hw_rfbus_done(ah);
25763
25764 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
25765 ath9k_hw_set_delta_slope(ah, chan);
25766
25767 - ah->ath9k_hw_spur_mitigate_freq(ah, chan);
25768 + ath9k_hw_spur_mitigate_freq(ah, chan);
25769
25770 if (!chan->oneTimeCalsDone)
25771 chan->oneTimeCalsDone = true;
25772 @@ -1849,18 +1112,6 @@ static bool ath9k_hw_channel_change(stru
25773 return true;
25774 }
25775
25776 -static void ath9k_enable_rfkill(struct ath_hw *ah)
25777 -{
25778 - REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
25779 - AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
25780 -
25781 - REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
25782 - AR_GPIO_INPUT_MUX2_RFSILENT);
25783 -
25784 - ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
25785 - REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
25786 -}
25787 -
25788 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
25789 bool bChannelChange)
25790 {
25791 @@ -1870,11 +1121,18 @@ int ath9k_hw_reset(struct ath_hw *ah, st
25792 u32 saveDefAntenna;
25793 u32 macStaId1;
25794 u64 tsf = 0;
25795 - int i, rx_chainmask, r;
25796 + int i, r;
25797
25798 ah->txchainmask = common->tx_chainmask;
25799 ah->rxchainmask = common->rx_chainmask;
25800
25801 + if (!ah->chip_fullsleep) {
25802 + ath9k_hw_abortpcurecv(ah);
25803 + if (!ath9k_hw_stopdmarecv(ah))
25804 + ath_print(common, ATH_DBG_XMIT,
25805 + "Failed to stop receive dma\n");
25806 + }
25807 +
25808 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
25809 return -EIO;
25810
25811 @@ -1939,19 +1197,14 @@ int ath9k_hw_reset(struct ath_hw *ah, st
25812 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
25813 ath9k_hw_settsf64(ah, tsf);
25814
25815 + if (AR_SREV_9300_20_OR_LATER(ah))
25816 + ar9003_hw_attach_mac_ops(ah);
25817 + else
25818 + ar9002_hw_attach_mac_ops(ah);
25819 +
25820 if (AR_SREV_9280_10_OR_LATER(ah))
25821 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
25822
25823 - if (AR_SREV_9287_12_OR_LATER(ah)) {
25824 - /* Enable ASYNC FIFO */
25825 - REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
25826 - AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
25827 - REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
25828 - REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
25829 - AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
25830 - REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
25831 - AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
25832 - }
25833 r = ath9k_hw_process_ini(ah, chan);
25834 if (r)
25835 return r;
25836 @@ -1976,7 +1229,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
25837 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
25838 ath9k_hw_set_delta_slope(ah, chan);
25839
25840 - ah->ath9k_hw_spur_mitigate_freq(ah, chan);
25841 + ath9k_hw_spur_mitigate_freq(ah, chan);
25842 ah->eep_ops->set_board_values(ah, chan);
25843
25844 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
25845 @@ -1998,7 +1251,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
25846
25847 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
25848
25849 - r = ah->ath9k_hw_rf_set_freq(ah, chan);
25850 + r = ath9k_hw_rf_set_freq(ah, chan);
25851 if (r)
25852 return r;
25853
25854 @@ -2017,25 +1270,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
25855
25856 ath9k_hw_init_global_settings(ah);
25857
25858 - if (AR_SREV_9287_12_OR_LATER(ah)) {
25859 - REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
25860 - AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
25861 - REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
25862 - AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
25863 - REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
25864 - AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
25865 -
25866 - REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
25867 - REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
25868 -
25869 - REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
25870 - AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
25871 - REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
25872 - AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
25873 - }
25874 - if (AR_SREV_9287_12_OR_LATER(ah)) {
25875 - REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
25876 - AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
25877 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
25878 + ar9002_hw_enable_async_fifo(ah);
25879 + ar9002_hw_enable_wep_aggregation(ah);
25880 }
25881
25882 REG_WRITE(ah, AR_STA_ID1,
25883 @@ -2050,17 +1287,17 @@ int ath9k_hw_reset(struct ath_hw *ah, st
25884 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
25885 }
25886
25887 + if (ah->config.tx_intr_mitigation) {
25888 + REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
25889 + REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
25890 + }
25891 +
25892 ath9k_hw_init_bb(ah, chan);
25893
25894 if (!ath9k_hw_init_cal(ah, chan))
25895 return -EIO;
25896
25897 - rx_chainmask = ah->rxchainmask;
25898 - if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
25899 - REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
25900 - REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
25901 - }
25902 -
25903 + ath9k_hw_restore_chainmask(ah);
25904 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
25905
25906 /*
25907 @@ -2092,6 +1329,11 @@ int ath9k_hw_reset(struct ath_hw *ah, st
25908 if (ah->btcoex_hw.enabled)
25909 ath9k_hw_btcoex_enable(ah);
25910
25911 + if (AR_SREV_9300_20_OR_LATER(ah)) {
25912 + ath9k_hw_loadnf(ah, curchan);
25913 + ath9k_hw_start_nfcal(ah);
25914 + }
25915 +
25916 return 0;
25917 }
25918 EXPORT_SYMBOL(ath9k_hw_reset);
25919 @@ -2378,21 +1620,32 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid);
25920 /* Power Management (Chipset) */
25921 /******************************/
25922
25923 +/*
25924 + * Notify Power Mgt is disabled in self-generated frames.
25925 + * If requested, force chip to sleep.
25926 + */
25927 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
25928 {
25929 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
25930 if (setChip) {
25931 + /* Clear the RTC force wake bit to allow the mac to go to sleep */
25932 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
25933 AR_RTC_FORCE_WAKE_EN);
25934 - if (!AR_SREV_9100(ah))
25935 + if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
25936 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
25937
25938 + /* Shutdown chip. Active low */
25939 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
25940 REG_CLR_BIT(ah, (AR_RTC_RESET),
25941 AR_RTC_RESET_EN);
25942 }
25943 }
25944
25945 +/*
25946 + * Notify Power Management is enabled in self-generating
25947 + * frames. If request, set power mode of chip to
25948 + * auto/normal. Duration in units of 128us (1/8 TU).
25949 + */
25950 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
25951 {
25952 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
25953 @@ -2400,9 +1653,14 @@ static void ath9k_set_power_network_slee
25954 struct ath9k_hw_capabilities *pCap = &ah->caps;
25955
25956 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
25957 + /* Set WakeOnInterrupt bit; clear ForceWake bit */
25958 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
25959 AR_RTC_FORCE_WAKE_ON_INT);
25960 } else {
25961 + /*
25962 + * Clear the RTC force wake bit to allow the
25963 + * mac to go to sleep.
25964 + */
25965 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
25966 AR_RTC_FORCE_WAKE_EN);
25967 }
25968 @@ -2421,7 +1679,8 @@ static bool ath9k_hw_set_power_awake(str
25969 ATH9K_RESET_POWER_ON) != true) {
25970 return false;
25971 }
25972 - ath9k_hw_init_pll(ah, NULL);
25973 + if (!AR_SREV_9300_20_OR_LATER(ah))
25974 + ath9k_hw_init_pll(ah, NULL);
25975 }
25976 if (AR_SREV_9100(ah))
25977 REG_SET_BIT(ah, AR_RTC_RESET,
25978 @@ -2491,420 +1750,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah
25979 }
25980 EXPORT_SYMBOL(ath9k_hw_setpower);
25981
25982 -/*
25983 - * Helper for ASPM support.
25984 - *
25985 - * Disable PLL when in L0s as well as receiver clock when in L1.
25986 - * This power saving option must be enabled through the SerDes.
25987 - *
25988 - * Programming the SerDes must go through the same 288 bit serial shift
25989 - * register as the other analog registers. Hence the 9 writes.
25990 - */
25991 -void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
25992 -{
25993 - u8 i;
25994 - u32 val;
25995 -
25996 - if (ah->is_pciexpress != true)
25997 - return;
25998 -
25999 - /* Do not touch SerDes registers */
26000 - if (ah->config.pcie_powersave_enable == 2)
26001 - return;
26002 -
26003 - /* Nothing to do on restore for 11N */
26004 - if (!restore) {
26005 - if (AR_SREV_9280_20_OR_LATER(ah)) {
26006 - /*
26007 - * AR9280 2.0 or later chips use SerDes values from the
26008 - * initvals.h initialized depending on chipset during
26009 - * ath9k_hw_init()
26010 - */
26011 - for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
26012 - REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
26013 - INI_RA(&ah->iniPcieSerdes, i, 1));
26014 - }
26015 - } else if (AR_SREV_9280(ah) &&
26016 - (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
26017 - REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
26018 - REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
26019 -
26020 - /* RX shut off when elecidle is asserted */
26021 - REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
26022 - REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
26023 - REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
26024 -
26025 - /* Shut off CLKREQ active in L1 */
26026 - if (ah->config.pcie_clock_req)
26027 - REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
26028 - else
26029 - REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
26030 -
26031 - REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
26032 - REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
26033 - REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
26034 -
26035 - /* Load the new settings */
26036 - REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
26037 -
26038 - } else {
26039 - REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
26040 - REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
26041 -
26042 - /* RX shut off when elecidle is asserted */
26043 - REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
26044 - REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
26045 - REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
26046 -
26047 - /*
26048 - * Ignore ah->ah_config.pcie_clock_req setting for
26049 - * pre-AR9280 11n
26050 - */
26051 - REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
26052 -
26053 - REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
26054 - REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
26055 - REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
26056 -
26057 - /* Load the new settings */
26058 - REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
26059 - }
26060 -
26061 - udelay(1000);
26062 -
26063 - /* set bit 19 to allow forcing of pcie core into L1 state */
26064 - REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
26065 -
26066 - /* Several PCIe massages to ensure proper behaviour */
26067 - if (ah->config.pcie_waen) {
26068 - val = ah->config.pcie_waen;
26069 - if (!power_off)
26070 - val &= (~AR_WA_D3_L1_DISABLE);
26071 - } else {
26072 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
26073 - AR_SREV_9287(ah)) {
26074 - val = AR9285_WA_DEFAULT;
26075 - if (!power_off)
26076 - val &= (~AR_WA_D3_L1_DISABLE);
26077 - } else if (AR_SREV_9280(ah)) {
26078 - /*
26079 - * On AR9280 chips bit 22 of 0x4004 needs to be
26080 - * set otherwise card may disappear.
26081 - */
26082 - val = AR9280_WA_DEFAULT;
26083 - if (!power_off)
26084 - val &= (~AR_WA_D3_L1_DISABLE);
26085 - } else
26086 - val = AR_WA_DEFAULT;
26087 - }
26088 -
26089 - REG_WRITE(ah, AR_WA, val);
26090 - }
26091 -
26092 - if (power_off) {
26093 - /*
26094 - * Set PCIe workaround bits
26095 - * bit 14 in WA register (disable L1) should only
26096 - * be set when device enters D3 and be cleared
26097 - * when device comes back to D0.
26098 - */
26099 - if (ah->config.pcie_waen) {
26100 - if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
26101 - REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
26102 - } else {
26103 - if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
26104 - AR_SREV_9287(ah)) &&
26105 - (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
26106 - (AR_SREV_9280(ah) &&
26107 - (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
26108 - REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
26109 - }
26110 - }
26111 - }
26112 -}
26113 -EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
26114 -
26115 -/**********************/
26116 -/* Interrupt Handling */
26117 -/**********************/
26118 -
26119 -bool ath9k_hw_intrpend(struct ath_hw *ah)
26120 -{
26121 - u32 host_isr;
26122 -
26123 - if (AR_SREV_9100(ah))
26124 - return true;
26125 -
26126 - host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
26127 - if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
26128 - return true;
26129 -
26130 - host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
26131 - if ((host_isr & AR_INTR_SYNC_DEFAULT)
26132 - && (host_isr != AR_INTR_SPURIOUS))
26133 - return true;
26134 -
26135 - return false;
26136 -}
26137 -EXPORT_SYMBOL(ath9k_hw_intrpend);
26138 -
26139 -bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
26140 -{
26141 - u32 isr = 0;
26142 - u32 mask2 = 0;
26143 - struct ath9k_hw_capabilities *pCap = &ah->caps;
26144 - u32 sync_cause = 0;
26145 - bool fatal_int = false;
26146 - struct ath_common *common = ath9k_hw_common(ah);
26147 -
26148 - if (!AR_SREV_9100(ah)) {
26149 - if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
26150 - if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
26151 - == AR_RTC_STATUS_ON) {
26152 - isr = REG_READ(ah, AR_ISR);
26153 - }
26154 - }
26155 -
26156 - sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
26157 - AR_INTR_SYNC_DEFAULT;
26158 -
26159 - *masked = 0;
26160 -
26161 - if (!isr && !sync_cause)
26162 - return false;
26163 - } else {
26164 - *masked = 0;
26165 - isr = REG_READ(ah, AR_ISR);
26166 - }
26167 -
26168 - if (isr) {
26169 - if (isr & AR_ISR_BCNMISC) {
26170 - u32 isr2;
26171 - isr2 = REG_READ(ah, AR_ISR_S2);
26172 - if (isr2 & AR_ISR_S2_TIM)
26173 - mask2 |= ATH9K_INT_TIM;
26174 - if (isr2 & AR_ISR_S2_DTIM)
26175 - mask2 |= ATH9K_INT_DTIM;
26176 - if (isr2 & AR_ISR_S2_DTIMSYNC)
26177 - mask2 |= ATH9K_INT_DTIMSYNC;
26178 - if (isr2 & (AR_ISR_S2_CABEND))
26179 - mask2 |= ATH9K_INT_CABEND;
26180 - if (isr2 & AR_ISR_S2_GTT)
26181 - mask2 |= ATH9K_INT_GTT;
26182 - if (isr2 & AR_ISR_S2_CST)
26183 - mask2 |= ATH9K_INT_CST;
26184 - if (isr2 & AR_ISR_S2_TSFOOR)
26185 - mask2 |= ATH9K_INT_TSFOOR;
26186 - }
26187 -
26188 - isr = REG_READ(ah, AR_ISR_RAC);
26189 - if (isr == 0xffffffff) {
26190 - *masked = 0;
26191 - return false;
26192 - }
26193 -
26194 - *masked = isr & ATH9K_INT_COMMON;
26195 -
26196 - if (ah->config.rx_intr_mitigation) {
26197 - if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
26198 - *masked |= ATH9K_INT_RX;
26199 - }
26200 -
26201 - if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
26202 - *masked |= ATH9K_INT_RX;
26203 - if (isr &
26204 - (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
26205 - AR_ISR_TXEOL)) {
26206 - u32 s0_s, s1_s;
26207 -
26208 - *masked |= ATH9K_INT_TX;
26209 -
26210 - s0_s = REG_READ(ah, AR_ISR_S0_S);
26211 - ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
26212 - ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
26213 -
26214 - s1_s = REG_READ(ah, AR_ISR_S1_S);
26215 - ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
26216 - ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
26217 - }
26218 -
26219 - if (isr & AR_ISR_RXORN) {
26220 - ath_print(common, ATH_DBG_INTERRUPT,
26221 - "receive FIFO overrun interrupt\n");
26222 - }
26223 -
26224 - if (!AR_SREV_9100(ah)) {
26225 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
26226 - u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
26227 - if (isr5 & AR_ISR_S5_TIM_TIMER)
26228 - *masked |= ATH9K_INT_TIM_TIMER;
26229 - }
26230 - }
26231 -
26232 - *masked |= mask2;
26233 - }
26234 -
26235 - if (AR_SREV_9100(ah))
26236 - return true;
26237 -
26238 - if (isr & AR_ISR_GENTMR) {
26239 - u32 s5_s;
26240 -
26241 - s5_s = REG_READ(ah, AR_ISR_S5_S);
26242 - if (isr & AR_ISR_GENTMR) {
26243 - ah->intr_gen_timer_trigger =
26244 - MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
26245 -
26246 - ah->intr_gen_timer_thresh =
26247 - MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
26248 -
26249 - if (ah->intr_gen_timer_trigger)
26250 - *masked |= ATH9K_INT_GENTIMER;
26251 -
26252 - }
26253 - }
26254 -
26255 - if (sync_cause) {
26256 - fatal_int =
26257 - (sync_cause &
26258 - (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
26259 - ? true : false;
26260 -
26261 - if (fatal_int) {
26262 - if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
26263 - ath_print(common, ATH_DBG_ANY,
26264 - "received PCI FATAL interrupt\n");
26265 - }
26266 - if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
26267 - ath_print(common, ATH_DBG_ANY,
26268 - "received PCI PERR interrupt\n");
26269 - }
26270 - *masked |= ATH9K_INT_FATAL;
26271 - }
26272 - if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
26273 - ath_print(common, ATH_DBG_INTERRUPT,
26274 - "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
26275 - REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
26276 - REG_WRITE(ah, AR_RC, 0);
26277 - *masked |= ATH9K_INT_FATAL;
26278 - }
26279 - if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
26280 - ath_print(common, ATH_DBG_INTERRUPT,
26281 - "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
26282 - }
26283 -
26284 - REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
26285 - (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
26286 - }
26287 -
26288 - return true;
26289 -}
26290 -EXPORT_SYMBOL(ath9k_hw_getisr);
26291 -
26292 -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
26293 -{
26294 - enum ath9k_int omask = ah->imask;
26295 - u32 mask, mask2;
26296 - struct ath9k_hw_capabilities *pCap = &ah->caps;
26297 - struct ath_common *common = ath9k_hw_common(ah);
26298 -
26299 - ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
26300 -
26301 - if (omask & ATH9K_INT_GLOBAL) {
26302 - ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
26303 - REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
26304 - (void) REG_READ(ah, AR_IER);
26305 - if (!AR_SREV_9100(ah)) {
26306 - REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
26307 - (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
26308 -
26309 - REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
26310 - (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
26311 - }
26312 - }
26313 -
26314 - mask = ints & ATH9K_INT_COMMON;
26315 - mask2 = 0;
26316 -
26317 - if (ints & ATH9K_INT_TX) {
26318 - if (ah->txok_interrupt_mask)
26319 - mask |= AR_IMR_TXOK;
26320 - if (ah->txdesc_interrupt_mask)
26321 - mask |= AR_IMR_TXDESC;
26322 - if (ah->txerr_interrupt_mask)
26323 - mask |= AR_IMR_TXERR;
26324 - if (ah->txeol_interrupt_mask)
26325 - mask |= AR_IMR_TXEOL;
26326 - }
26327 - if (ints & ATH9K_INT_RX) {
26328 - mask |= AR_IMR_RXERR;
26329 - if (ah->config.rx_intr_mitigation)
26330 - mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
26331 - else
26332 - mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
26333 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
26334 - mask |= AR_IMR_GENTMR;
26335 - }
26336 -
26337 - if (ints & (ATH9K_INT_BMISC)) {
26338 - mask |= AR_IMR_BCNMISC;
26339 - if (ints & ATH9K_INT_TIM)
26340 - mask2 |= AR_IMR_S2_TIM;
26341 - if (ints & ATH9K_INT_DTIM)
26342 - mask2 |= AR_IMR_S2_DTIM;
26343 - if (ints & ATH9K_INT_DTIMSYNC)
26344 - mask2 |= AR_IMR_S2_DTIMSYNC;
26345 - if (ints & ATH9K_INT_CABEND)
26346 - mask2 |= AR_IMR_S2_CABEND;
26347 - if (ints & ATH9K_INT_TSFOOR)
26348 - mask2 |= AR_IMR_S2_TSFOOR;
26349 - }
26350 -
26351 - if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
26352 - mask |= AR_IMR_BCNMISC;
26353 - if (ints & ATH9K_INT_GTT)
26354 - mask2 |= AR_IMR_S2_GTT;
26355 - if (ints & ATH9K_INT_CST)
26356 - mask2 |= AR_IMR_S2_CST;
26357 - }
26358 -
26359 - ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
26360 - REG_WRITE(ah, AR_IMR, mask);
26361 - ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
26362 - AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
26363 - AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
26364 - ah->imrs2_reg |= mask2;
26365 - REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
26366 -
26367 - if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
26368 - if (ints & ATH9K_INT_TIM_TIMER)
26369 - REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
26370 - else
26371 - REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
26372 - }
26373 -
26374 - if (ints & ATH9K_INT_GLOBAL) {
26375 - ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
26376 - REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
26377 - if (!AR_SREV_9100(ah)) {
26378 - REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
26379 - AR_INTR_MAC_IRQ);
26380 - REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
26381 -
26382 -
26383 - REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
26384 - AR_INTR_SYNC_DEFAULT);
26385 - REG_WRITE(ah, AR_INTR_SYNC_MASK,
26386 - AR_INTR_SYNC_DEFAULT);
26387 - }
26388 - ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
26389 - REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
26390 - }
26391 -
26392 - return omask;
26393 -}
26394 -EXPORT_SYMBOL(ath9k_hw_set_interrupts);
26395 -
26396 /*******************/
26397 /* Beacon Handling */
26398 /*******************/
26399 @@ -3240,6 +2085,20 @@ int ath9k_hw_fill_cap_info(struct ath_hw
26400 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
26401 }
26402
26403 + if (AR_SREV_9300_20_OR_LATER(ah)) {
26404 + pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
26405 + pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
26406 + pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
26407 + pCap->rx_status_len = sizeof(struct ar9003_rxs);
26408 + pCap->tx_desc_len = sizeof(struct ar9003_txc);
26409 + pCap->txs_len = sizeof(struct ar9003_txs);
26410 + } else {
26411 + pCap->tx_desc_len = sizeof(struct ath_desc);
26412 + }
26413 +
26414 + if (AR_SREV_9300_20_OR_LATER(ah))
26415 + pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
26416 +
26417 return 0;
26418 }
26419
26420 @@ -3272,10 +2131,6 @@ bool ath9k_hw_getcapability(struct ath_h
26421 case ATH9K_CAP_TKIP_SPLIT:
26422 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
26423 false : true;
26424 - case ATH9K_CAP_DIVERSITY:
26425 - return (REG_READ(ah, AR_PHY_CCK_DETECT) &
26426 - AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
26427 - true : false;
26428 case ATH9K_CAP_MCAST_KEYSRCH:
26429 switch (capability) {
26430 case 0:
26431 @@ -3318,8 +2173,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability);
26432 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
26433 u32 capability, u32 setting, int *status)
26434 {
26435 - u32 v;
26436 -
26437 switch (type) {
26438 case ATH9K_CAP_TKIP_MIC:
26439 if (setting)
26440 @@ -3329,14 +2182,6 @@ bool ath9k_hw_setcapability(struct ath_h
26441 ah->sta_id1_defaults &=
26442 ~AR_STA_ID1_CRPT_MIC_ENABLE;
26443 return true;
26444 - case ATH9K_CAP_DIVERSITY:
26445 - v = REG_READ(ah, AR_PHY_CCK_DETECT);
26446 - if (setting)
26447 - v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
26448 - else
26449 - v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
26450 - REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
26451 - return true;
26452 case ATH9K_CAP_MCAST_KEYSRCH:
26453 if (setting)
26454 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
26455 @@ -3404,7 +2249,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah,
26456 if (gpio >= ah->caps.num_gpio_pins)
26457 return 0xffffffff;
26458
26459 - if (AR_SREV_9271(ah))
26460 + if (AR_SREV_9300_20_OR_LATER(ah))
26461 + return MS_REG_READ(AR9300, gpio) != 0;
26462 + else if (AR_SREV_9271(ah))
26463 return MS_REG_READ(AR9271, gpio) != 0;
26464 else if (AR_SREV_9287_10_OR_LATER(ah))
26465 return MS_REG_READ(AR9287, gpio) != 0;
26466 @@ -3846,6 +2693,7 @@ static struct {
26467 { AR_SREV_VERSION_9285, "9285" },
26468 { AR_SREV_VERSION_9287, "9287" },
26469 { AR_SREV_VERSION_9271, "9271" },
26470 + { AR_SREV_VERSION_9300, "9300" },
26471 };
26472
26473 /* For devices with external radios */
26474 --- a/drivers/net/wireless/ath/ath9k/hw.h
26475 +++ b/drivers/net/wireless/ath/ath9k/hw.h
26476 @@ -1,5 +1,5 @@
26477 /*
26478 - * Copyright (c) 2008-2009 Atheros Communications Inc.
26479 + * Copyright (c) 2008-2010 Atheros Communications Inc.
26480 *
26481 * Permission to use, copy, modify, and/or distribute this software for any
26482 * purpose with or without fee is hereby granted, provided that the above
26483 @@ -28,6 +28,7 @@
26484 #include "reg.h"
26485 #include "phy.h"
26486 #include "btcoex.h"
26487 +#include "ar9003_mac.h"
26488
26489 #include "../regd.h"
26490 #include "../debug.h"
26491 @@ -41,6 +42,9 @@
26492 #define AR9280_DEVID_PCIE 0x002a
26493 #define AR9285_DEVID_PCIE 0x002b
26494 #define AR2427_DEVID_PCIE 0x002c
26495 +#define AR9287_DEVID_PCI 0x002d
26496 +#define AR9287_DEVID_PCIE 0x002e
26497 +#define AR9300_DEVID_PCIE 0x0030
26498
26499 #define AR5416_AR9100_DEVID 0x000b
26500
26501 @@ -48,9 +52,6 @@
26502 #define AR_SUBVENDOR_ID_NEW_A 0x7065
26503 #define AR5416_MAGIC 0x19641014
26504
26505 -#define AR5416_DEVID_AR9287_PCI 0x002D
26506 -#define AR5416_DEVID_AR9287_PCIE 0x002E
26507 -
26508 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
26509 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
26510 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
26511 @@ -75,6 +76,8 @@
26512 #define REG_RMW_FIELD(_a, _r, _f, _v) \
26513 REG_WRITE(_a, _r, \
26514 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
26515 +#define REG_READ_FIELD(_a, _r, _f) \
26516 + (((REG_READ(_a, _r) & _f) >> _f##_S))
26517 #define REG_SET_BIT(_a, _r, _f) \
26518 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
26519 #define REG_CLR_BIT(_a, _r, _f) \
26520 @@ -135,6 +138,16 @@
26521
26522 #define TU_TO_USEC(_tu) ((_tu) << 10)
26523
26524 +#define ATH9K_HW_RX_HP_QDEPTH 16
26525 +#define ATH9K_HW_RX_LP_QDEPTH 128
26526 +
26527 +enum ath_ini_subsys {
26528 + ATH_INI_PRE = 0,
26529 + ATH_INI_CORE,
26530 + ATH_INI_POST,
26531 + ATH_INI_NUM_SPLIT,
26532 +};
26533 +
26534 enum wireless_mode {
26535 ATH9K_MODE_11A = 0,
26536 ATH9K_MODE_11G,
26537 @@ -165,13 +178,15 @@ enum ath9k_hw_caps {
26538 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
26539 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
26540 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
26541 + ATH9K_HW_CAP_EDMA = BIT(17),
26542 + ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
26543 + ATH9K_HW_CAP_LDPC = BIT(19),
26544 };
26545
26546 enum ath9k_capability_type {
26547 ATH9K_CAP_CIPHER = 0,
26548 ATH9K_CAP_TKIP_MIC,
26549 ATH9K_CAP_TKIP_SPLIT,
26550 - ATH9K_CAP_DIVERSITY,
26551 ATH9K_CAP_TXPOW,
26552 ATH9K_CAP_MCAST_KEYSRCH,
26553 ATH9K_CAP_DS
26554 @@ -192,6 +207,11 @@ struct ath9k_hw_capabilities {
26555 u8 num_gpio_pins;
26556 u8 num_antcfg_2ghz;
26557 u8 num_antcfg_5ghz;
26558 + u8 rx_hp_qdepth;
26559 + u8 rx_lp_qdepth;
26560 + u8 rx_status_len;
26561 + u8 tx_desc_len;
26562 + u8 txs_len;
26563 };
26564
26565 struct ath9k_ops_config {
26566 @@ -212,6 +232,7 @@ struct ath9k_ops_config {
26567 u32 enable_ani;
26568 int serialize_regmode;
26569 bool rx_intr_mitigation;
26570 + bool tx_intr_mitigation;
26571 #define SPUR_DISABLE 0
26572 #define SPUR_ENABLE_IOCTL 1
26573 #define SPUR_ENABLE_EEPROM 2
26574 @@ -231,6 +252,8 @@ struct ath9k_ops_config {
26575 enum ath9k_int {
26576 ATH9K_INT_RX = 0x00000001,
26577 ATH9K_INT_RXDESC = 0x00000002,
26578 + ATH9K_INT_RXHP = 0x00000001,
26579 + ATH9K_INT_RXLP = 0x00000002,
26580 ATH9K_INT_RXNOFRM = 0x00000008,
26581 ATH9K_INT_RXEOL = 0x00000010,
26582 ATH9K_INT_RXORN = 0x00000020,
26583 @@ -440,6 +463,125 @@ struct ath_gen_timer_table {
26584 } timer_mask;
26585 };
26586
26587 +/**
26588 + * struct ath_hw_private_ops - callbacks used internally by hardware code
26589 + *
26590 + * This structure contains private callbacks designed to only be used internally
26591 + * by the hardware core.
26592 + *
26593 + * @init_cal_settings: setup types of calibrations supported
26594 + * @init_cal: starts actual calibration
26595 + *
26596 + * @init_mode_regs: Initializes mode registers
26597 + * @init_mode_gain_regs: Initialize TX/RX gain registers
26598 + * @macversion_supported: If this specific mac revision is supported
26599 + *
26600 + * @rf_set_freq: change frequency
26601 + * @spur_mitigate_freq: spur mitigation
26602 + * @rf_alloc_ext_banks:
26603 + * @rf_free_ext_banks:
26604 + * @set_rf_regs:
26605 + * @compute_pll_control: compute the PLL control value to use for
26606 + * AR_RTC_PLL_CONTROL for a given channel
26607 + * @setup_calibration: set up calibration
26608 + * @iscal_supported: used to query if a type of calibration is supported
26609 + * @loadnf: load noise floor read from each chain on the CCA registers
26610 + */
26611 +struct ath_hw_private_ops {
26612 + /* Calibration ops */
26613 + void (*init_cal_settings)(struct ath_hw *ah);
26614 + bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
26615 +
26616 + void (*init_mode_regs)(struct ath_hw *ah);
26617 + void (*init_mode_gain_regs)(struct ath_hw *ah);
26618 + bool (*macversion_supported)(u32 macversion);
26619 + void (*setup_calibration)(struct ath_hw *ah,
26620 + struct ath9k_cal_list *currCal);
26621 + bool (*iscal_supported)(struct ath_hw *ah,
26622 + enum ath9k_cal_types calType);
26623 +
26624 + /* PHY ops */
26625 + int (*rf_set_freq)(struct ath_hw *ah,
26626 + struct ath9k_channel *chan);
26627 + void (*spur_mitigate_freq)(struct ath_hw *ah,
26628 + struct ath9k_channel *chan);
26629 + int (*rf_alloc_ext_banks)(struct ath_hw *ah);
26630 + void (*rf_free_ext_banks)(struct ath_hw *ah);
26631 + bool (*set_rf_regs)(struct ath_hw *ah,
26632 + struct ath9k_channel *chan,
26633 + u16 modesIndex);
26634 + void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
26635 + void (*init_bb)(struct ath_hw *ah,
26636 + struct ath9k_channel *chan);
26637 + int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
26638 + void (*olc_init)(struct ath_hw *ah);
26639 + void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
26640 + void (*mark_phy_inactive)(struct ath_hw *ah);
26641 + void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
26642 + bool (*rfbus_req)(struct ath_hw *ah);
26643 + void (*rfbus_done)(struct ath_hw *ah);
26644 + void (*enable_rfkill)(struct ath_hw *ah);
26645 + void (*restore_chainmask)(struct ath_hw *ah);
26646 + void (*set_diversity)(struct ath_hw *ah, bool value);
26647 + u32 (*compute_pll_control)(struct ath_hw *ah,
26648 + struct ath9k_channel *chan);
26649 + bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
26650 + int param);
26651 + void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
26652 + void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
26653 +};
26654 +
26655 +/**
26656 + * struct ath_hw_ops - callbacks used by hardware code and driver code
26657 + *
26658 + * This structure contains callbacks designed to to be used internally by
26659 + * hardware code and also by the lower level driver.
26660 + *
26661 + * @config_pci_powersave:
26662 + * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
26663 + */
26664 +struct ath_hw_ops {
26665 + void (*config_pci_powersave)(struct ath_hw *ah,
26666 + int restore,
26667 + int power_off);
26668 + void (*rx_enable)(struct ath_hw *ah);
26669 + void (*set_desc_link)(void *ds, u32 link);
26670 + void (*get_desc_link)(void *ds, u32 **link);
26671 + bool (*calibrate)(struct ath_hw *ah,
26672 + struct ath9k_channel *chan,
26673 + u8 rxchainmask,
26674 + bool longcal);
26675 + bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
26676 + void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
26677 + bool is_firstseg, bool is_is_lastseg,
26678 + const void *ds0, dma_addr_t buf_addr,
26679 + unsigned int qcu);
26680 + void (*clear_txdesc)(struct ath_hw *ah, void *ds);
26681 + int (*proc_txdesc)(struct ath_hw *ah, void *ds,
26682 + struct ath_tx_status *ts);
26683 + void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
26684 + u32 pktLen, enum ath9k_pkt_type type,
26685 + u32 txPower, u32 keyIx,
26686 + enum ath9k_key_type keyType,
26687 + u32 flags);
26688 + void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
26689 + void *lastds,
26690 + u32 durUpdateEn, u32 rtsctsRate,
26691 + u32 rtsctsDuration,
26692 + struct ath9k_11n_rate_series series[],
26693 + u32 nseries, u32 flags);
26694 + void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
26695 + u32 aggrLen);
26696 + void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
26697 + u32 numDelims);
26698 + void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
26699 + void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
26700 + void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
26701 + u32 burstDuration);
26702 + void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
26703 + u32 vmf);
26704 +};
26705 +
26706 struct ath_hw {
26707 struct ieee80211_hw *hw;
26708 struct ath_common common;
26709 @@ -453,14 +595,18 @@ struct ath_hw {
26710 struct ar5416_eeprom_def def;
26711 struct ar5416_eeprom_4k map4k;
26712 struct ar9287_eeprom map9287;
26713 + struct ar9300_eeprom ar9300_eep;
26714 } eeprom;
26715 const struct eeprom_ops *eep_ops;
26716 - enum ath9k_eep_map eep_map;
26717
26718 bool sw_mgmt_crypto;
26719 bool is_pciexpress;
26720 bool need_an_top2_fixup;
26721 u16 tx_trig_level;
26722 + s16 nf_2g_max;
26723 + s16 nf_2g_min;
26724 + s16 nf_5g_max;
26725 + s16 nf_5g_min;
26726 u16 rfsilent;
26727 u32 rfkill_gpio;
26728 u32 rfkill_polarity;
26729 @@ -493,6 +639,7 @@ struct ath_hw {
26730 struct ath9k_cal_list adcgain_caldata;
26731 struct ath9k_cal_list adcdc_calinitdata;
26732 struct ath9k_cal_list adcdc_caldata;
26733 + struct ath9k_cal_list tempCompCalData;
26734 struct ath9k_cal_list *cal_list;
26735 struct ath9k_cal_list *cal_list_last;
26736 struct ath9k_cal_list *cal_list_curr;
26737 @@ -533,12 +680,10 @@ struct ath_hw {
26738 DONT_USE_32KHZ,
26739 } enable_32kHz_clock;
26740
26741 - /* Callback for radio frequency change */
26742 - int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
26743 -
26744 - /* Callback for baseband spur frequency */
26745 - void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
26746 - struct ath9k_channel *chan);
26747 + /* Private to hardware code */
26748 + struct ath_hw_private_ops private_ops;
26749 + /* Accessed by the lower level driver */
26750 + struct ath_hw_ops ops;
26751
26752 /* Used to program the radio on non single-chip devices */
26753 u32 *analogBank0Data;
26754 @@ -592,6 +737,7 @@ struct ath_hw {
26755 struct ar5416IniArray iniBank7;
26756 struct ar5416IniArray iniAddac;
26757 struct ar5416IniArray iniPcieSerdes;
26758 + struct ar5416IniArray iniPcieSerdesLowPower;
26759 struct ar5416IniArray iniModesAdditional;
26760 struct ar5416IniArray iniModesRxGain;
26761 struct ar5416IniArray iniModesTxGain;
26762 @@ -604,9 +750,21 @@ struct ath_hw {
26763 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
26764 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
26765
26766 + struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
26767 + struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
26768 + struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
26769 + struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
26770 +
26771 u32 intr_gen_timer_trigger;
26772 u32 intr_gen_timer_thresh;
26773 struct ath_gen_timer_table hw_gen_timers;
26774 +
26775 + struct ar9003_txs *ts_ring;
26776 + void *ts_start;
26777 + u32 ts_paddr_start;
26778 + u32 ts_paddr_end;
26779 + u16 ts_tail;
26780 + u8 ts_size;
26781 };
26782
26783 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
26784 @@ -619,6 +777,16 @@ static inline struct ath_regulatory *ath
26785 return &(ath9k_hw_common(ah)->regulatory);
26786 }
26787
26788 +static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
26789 +{
26790 + return &ah->private_ops;
26791 +}
26792 +
26793 +static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
26794 +{
26795 + return &ah->ops;
26796 +}
26797 +
26798 /* Initialization, Detach, Reset */
26799 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
26800 void ath9k_hw_deinit(struct ath_hw *ah);
26801 @@ -630,6 +798,7 @@ bool ath9k_hw_getcapability(struct ath_h
26802 u32 capability, u32 *result);
26803 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
26804 u32 capability, u32 setting, int *status);
26805 +u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
26806
26807 /* Key Cache Management */
26808 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
26809 @@ -681,13 +850,6 @@ void ath9k_hw_set_sta_beacon_timers(stru
26810
26811 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
26812
26813 -void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
26814 -
26815 -/* Interrupt Handling */
26816 -bool ath9k_hw_intrpend(struct ath_hw *ah);
26817 -bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
26818 -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
26819 -
26820 /* Generic hw timer primitives */
26821 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
26822 void (*trigger)(void *),
26823 @@ -709,6 +871,36 @@ void ath9k_hw_name(struct ath_hw *ah, ch
26824 /* HTC */
26825 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
26826
26827 +/* PHY */
26828 +void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
26829 + u32 *coef_mantissa, u32 *coef_exponent);
26830 +
26831 +/*
26832 + * Code Specific to AR5008, AR9001 or AR9002,
26833 + * we stuff these here to avoid callbacks for AR9003.
26834 + */
26835 +void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
26836 +int ar9002_hw_rf_claim(struct ath_hw *ah);
26837 +void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
26838 +void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
26839 +
26840 +/*
26841 + * Code specifric to AR9003, we stuff these here to avoid callbacks
26842 + * for older families
26843 + */
26844 +void ar9003_hw_set_nf_limits(struct ath_hw *ah);
26845 +
26846 +/* Hardware family op attach helpers */
26847 +void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
26848 +void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
26849 +void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
26850 +
26851 +void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
26852 +void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
26853 +
26854 +void ar9002_hw_attach_ops(struct ath_hw *ah);
26855 +void ar9003_hw_attach_ops(struct ath_hw *ah);
26856 +
26857 #define ATH_PCIE_CAP_LINK_CTRL 0x70
26858 #define ATH_PCIE_CAP_LINK_L0S 1
26859 #define ATH_PCIE_CAP_LINK_L1 2
26860 --- a/drivers/net/wireless/ath/ath9k/init.c
26861 +++ b/drivers/net/wireless/ath/ath9k/init.c
26862 @@ -189,6 +189,9 @@ static void setup_ht_cap(struct ath_soft
26863 IEEE80211_HT_CAP_SGI_40 |
26864 IEEE80211_HT_CAP_DSSSCCK40;
26865
26866 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
26867 + ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
26868 +
26869 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
26870 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
26871
26872 @@ -233,31 +236,37 @@ static int ath9k_reg_notifier(struct wip
26873 */
26874 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
26875 struct list_head *head, const char *name,
26876 - int nbuf, int ndesc)
26877 + int nbuf, int ndesc, bool is_tx)
26878 {
26879 #define DS2PHYS(_dd, _ds) \
26880 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
26881 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
26882 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
26883 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
26884 - struct ath_desc *ds;
26885 + u8 *ds;
26886 struct ath_buf *bf;
26887 - int i, bsize, error;
26888 + int i, bsize, error, desc_len;
26889
26890 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
26891 name, nbuf, ndesc);
26892
26893 INIT_LIST_HEAD(head);
26894 +
26895 + if (is_tx)
26896 + desc_len = sc->sc_ah->caps.tx_desc_len;
26897 + else
26898 + desc_len = sizeof(struct ath_desc);
26899 +
26900 /* ath_desc must be a multiple of DWORDs */
26901 - if ((sizeof(struct ath_desc) % 4) != 0) {
26902 + if ((desc_len % 4) != 0) {
26903 ath_print(common, ATH_DBG_FATAL,
26904 "ath_desc not DWORD aligned\n");
26905 - BUG_ON((sizeof(struct ath_desc) % 4) != 0);
26906 + BUG_ON((desc_len % 4) != 0);
26907 error = -ENOMEM;
26908 goto fail;
26909 }
26910
26911 - dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
26912 + dd->dd_desc_len = desc_len * nbuf * ndesc;
26913
26914 /*
26915 * Need additional DMA memory because we can't use
26916 @@ -270,7 +279,7 @@ int ath_descdma_setup(struct ath_softc *
26917 u32 dma_len;
26918
26919 while (ndesc_skipped) {
26920 - dma_len = ndesc_skipped * sizeof(struct ath_desc);
26921 + dma_len = ndesc_skipped * desc_len;
26922 dd->dd_desc_len += dma_len;
26923
26924 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
26925 @@ -284,7 +293,7 @@ int ath_descdma_setup(struct ath_softc *
26926 error = -ENOMEM;
26927 goto fail;
26928 }
26929 - ds = dd->dd_desc;
26930 + ds = (u8 *) dd->dd_desc;
26931 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
26932 name, ds, (u32) dd->dd_desc_len,
26933 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
26934 @@ -298,7 +307,7 @@ int ath_descdma_setup(struct ath_softc *
26935 }
26936 dd->dd_bufptr = bf;
26937
26938 - for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
26939 + for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
26940 bf->bf_desc = ds;
26941 bf->bf_daddr = DS2PHYS(dd, ds);
26942
26943 @@ -314,7 +323,7 @@ int ath_descdma_setup(struct ath_softc *
26944 ((caddr_t) dd->dd_desc +
26945 dd->dd_desc_len));
26946
26947 - ds += ndesc;
26948 + ds += (desc_len * ndesc);
26949 bf->bf_desc = ds;
26950 bf->bf_daddr = DS2PHYS(dd, ds);
26951 }
26952 @@ -512,7 +521,7 @@ static void ath9k_init_misc(struct ath_s
26953 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
26954 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
26955
26956 - ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
26957 + ath9k_hw_set_diversity(sc->sc_ah, true);
26958 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
26959
26960 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
26961 @@ -566,13 +575,10 @@ static int ath9k_init_softc(u16 devid, s
26962 ath_read_cachesize(common, &csz);
26963 common->cachelsz = csz << 2; /* convert to bytes */
26964
26965 + /* Initializes the hardware for all supported chipsets */
26966 ret = ath9k_hw_init(ah);
26967 - if (ret) {
26968 - ath_print(common, ATH_DBG_FATAL,
26969 - "Unable to initialize hardware; "
26970 - "initialization status: %d\n", ret);
26971 + if (ret)
26972 goto err_hw;
26973 - }
26974
26975 ret = ath9k_init_debug(ah);
26976 if (ret) {
26977 --- a/drivers/net/wireless/ath/ath9k/initvals.h
26978 +++ /dev/null
26979 @@ -1,7200 +0,0 @@
26980 -/*
26981 - * Copyright (c) 2008-2009 Atheros Communications Inc.
26982 - *
26983 - * Permission to use, copy, modify, and/or distribute this software for any
26984 - * purpose with or without fee is hereby granted, provided that the above
26985 - * copyright notice and this permission notice appear in all copies.
26986 - *
26987 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
26988 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
26989 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
26990 - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
26991 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
26992 - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
26993 - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
26994 - */
26995 -
26996 -static const u32 ar5416Modes[][6] = {
26997 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
26998 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
26999 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
27000 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
27001 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
27002 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27003 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
27004 - { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
27005 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
27006 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
27007 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27008 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
27009 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27010 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
27011 - { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
27012 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27013 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27014 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27015 - { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
27016 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
27017 - { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
27018 - { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
27019 - { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
27020 - { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
27021 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
27022 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
27023 - { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
27024 - { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
27025 - { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
27026 - { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
27027 - { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
27028 - { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
27029 - { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
27030 - { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
27031 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
27032 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
27033 - { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
27034 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
27035 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
27036 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27037 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27038 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
27039 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
27040 - { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
27041 - { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
27042 - { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
27043 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
27044 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
27045 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
27046 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
27047 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
27048 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
27049 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
27050 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
27051 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
27052 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
27053 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
27054 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
27055 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
27056 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
27057 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27058 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27059 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27060 -};
27061 -
27062 -static const u32 ar5416Common[][2] = {
27063 - { 0x0000000c, 0x00000000 },
27064 - { 0x00000030, 0x00020015 },
27065 - { 0x00000034, 0x00000005 },
27066 - { 0x00000040, 0x00000000 },
27067 - { 0x00000044, 0x00000008 },
27068 - { 0x00000048, 0x00000008 },
27069 - { 0x0000004c, 0x00000010 },
27070 - { 0x00000050, 0x00000000 },
27071 - { 0x00000054, 0x0000001f },
27072 - { 0x00000800, 0x00000000 },
27073 - { 0x00000804, 0x00000000 },
27074 - { 0x00000808, 0x00000000 },
27075 - { 0x0000080c, 0x00000000 },
27076 - { 0x00000810, 0x00000000 },
27077 - { 0x00000814, 0x00000000 },
27078 - { 0x00000818, 0x00000000 },
27079 - { 0x0000081c, 0x00000000 },
27080 - { 0x00000820, 0x00000000 },
27081 - { 0x00000824, 0x00000000 },
27082 - { 0x00001040, 0x002ffc0f },
27083 - { 0x00001044, 0x002ffc0f },
27084 - { 0x00001048, 0x002ffc0f },
27085 - { 0x0000104c, 0x002ffc0f },
27086 - { 0x00001050, 0x002ffc0f },
27087 - { 0x00001054, 0x002ffc0f },
27088 - { 0x00001058, 0x002ffc0f },
27089 - { 0x0000105c, 0x002ffc0f },
27090 - { 0x00001060, 0x002ffc0f },
27091 - { 0x00001064, 0x002ffc0f },
27092 - { 0x00001230, 0x00000000 },
27093 - { 0x00001270, 0x00000000 },
27094 - { 0x00001038, 0x00000000 },
27095 - { 0x00001078, 0x00000000 },
27096 - { 0x000010b8, 0x00000000 },
27097 - { 0x000010f8, 0x00000000 },
27098 - { 0x00001138, 0x00000000 },
27099 - { 0x00001178, 0x00000000 },
27100 - { 0x000011b8, 0x00000000 },
27101 - { 0x000011f8, 0x00000000 },
27102 - { 0x00001238, 0x00000000 },
27103 - { 0x00001278, 0x00000000 },
27104 - { 0x000012b8, 0x00000000 },
27105 - { 0x000012f8, 0x00000000 },
27106 - { 0x00001338, 0x00000000 },
27107 - { 0x00001378, 0x00000000 },
27108 - { 0x000013b8, 0x00000000 },
27109 - { 0x000013f8, 0x00000000 },
27110 - { 0x00001438, 0x00000000 },
27111 - { 0x00001478, 0x00000000 },
27112 - { 0x000014b8, 0x00000000 },
27113 - { 0x000014f8, 0x00000000 },
27114 - { 0x00001538, 0x00000000 },
27115 - { 0x00001578, 0x00000000 },
27116 - { 0x000015b8, 0x00000000 },
27117 - { 0x000015f8, 0x00000000 },
27118 - { 0x00001638, 0x00000000 },
27119 - { 0x00001678, 0x00000000 },
27120 - { 0x000016b8, 0x00000000 },
27121 - { 0x000016f8, 0x00000000 },
27122 - { 0x00001738, 0x00000000 },
27123 - { 0x00001778, 0x00000000 },
27124 - { 0x000017b8, 0x00000000 },
27125 - { 0x000017f8, 0x00000000 },
27126 - { 0x0000103c, 0x00000000 },
27127 - { 0x0000107c, 0x00000000 },
27128 - { 0x000010bc, 0x00000000 },
27129 - { 0x000010fc, 0x00000000 },
27130 - { 0x0000113c, 0x00000000 },
27131 - { 0x0000117c, 0x00000000 },
27132 - { 0x000011bc, 0x00000000 },
27133 - { 0x000011fc, 0x00000000 },
27134 - { 0x0000123c, 0x00000000 },
27135 - { 0x0000127c, 0x00000000 },
27136 - { 0x000012bc, 0x00000000 },
27137 - { 0x000012fc, 0x00000000 },
27138 - { 0x0000133c, 0x00000000 },
27139 - { 0x0000137c, 0x00000000 },
27140 - { 0x000013bc, 0x00000000 },
27141 - { 0x000013fc, 0x00000000 },
27142 - { 0x0000143c, 0x00000000 },
27143 - { 0x0000147c, 0x00000000 },
27144 - { 0x00004030, 0x00000002 },
27145 - { 0x0000403c, 0x00000002 },
27146 - { 0x00007010, 0x00000000 },
27147 - { 0x00007038, 0x000004c2 },
27148 - { 0x00008004, 0x00000000 },
27149 - { 0x00008008, 0x00000000 },
27150 - { 0x0000800c, 0x00000000 },
27151 - { 0x00008018, 0x00000700 },
27152 - { 0x00008020, 0x00000000 },
27153 - { 0x00008038, 0x00000000 },
27154 - { 0x0000803c, 0x00000000 },
27155 - { 0x00008048, 0x40000000 },
27156 - { 0x00008054, 0x00000000 },
27157 - { 0x00008058, 0x00000000 },
27158 - { 0x0000805c, 0x000fc78f },
27159 - { 0x00008060, 0x0000000f },
27160 - { 0x00008064, 0x00000000 },
27161 - { 0x000080c0, 0x2a82301a },
27162 - { 0x000080c4, 0x05dc01e0 },
27163 - { 0x000080c8, 0x1f402710 },
27164 - { 0x000080cc, 0x01f40000 },
27165 - { 0x000080d0, 0x00001e00 },
27166 - { 0x000080d4, 0x00000000 },
27167 - { 0x000080d8, 0x00400000 },
27168 - { 0x000080e0, 0xffffffff },
27169 - { 0x000080e4, 0x0000ffff },
27170 - { 0x000080e8, 0x003f3f3f },
27171 - { 0x000080ec, 0x00000000 },
27172 - { 0x000080f0, 0x00000000 },
27173 - { 0x000080f4, 0x00000000 },
27174 - { 0x000080f8, 0x00000000 },
27175 - { 0x000080fc, 0x00020000 },
27176 - { 0x00008100, 0x00020000 },
27177 - { 0x00008104, 0x00000001 },
27178 - { 0x00008108, 0x00000052 },
27179 - { 0x0000810c, 0x00000000 },
27180 - { 0x00008110, 0x00000168 },
27181 - { 0x00008118, 0x000100aa },
27182 - { 0x0000811c, 0x00003210 },
27183 - { 0x00008124, 0x00000000 },
27184 - { 0x00008128, 0x00000000 },
27185 - { 0x0000812c, 0x00000000 },
27186 - { 0x00008130, 0x00000000 },
27187 - { 0x00008134, 0x00000000 },
27188 - { 0x00008138, 0x00000000 },
27189 - { 0x0000813c, 0x00000000 },
27190 - { 0x00008144, 0xffffffff },
27191 - { 0x00008168, 0x00000000 },
27192 - { 0x0000816c, 0x00000000 },
27193 - { 0x00008170, 0x32143320 },
27194 - { 0x00008174, 0xfaa4fa50 },
27195 - { 0x00008178, 0x00000100 },
27196 - { 0x0000817c, 0x00000000 },
27197 - { 0x000081c4, 0x00000000 },
27198 - { 0x000081ec, 0x00000000 },
27199 - { 0x000081f0, 0x00000000 },
27200 - { 0x000081f4, 0x00000000 },
27201 - { 0x000081f8, 0x00000000 },
27202 - { 0x000081fc, 0x00000000 },
27203 - { 0x00008200, 0x00000000 },
27204 - { 0x00008204, 0x00000000 },
27205 - { 0x00008208, 0x00000000 },
27206 - { 0x0000820c, 0x00000000 },
27207 - { 0x00008210, 0x00000000 },
27208 - { 0x00008214, 0x00000000 },
27209 - { 0x00008218, 0x00000000 },
27210 - { 0x0000821c, 0x00000000 },
27211 - { 0x00008220, 0x00000000 },
27212 - { 0x00008224, 0x00000000 },
27213 - { 0x00008228, 0x00000000 },
27214 - { 0x0000822c, 0x00000000 },
27215 - { 0x00008230, 0x00000000 },
27216 - { 0x00008234, 0x00000000 },
27217 - { 0x00008238, 0x00000000 },
27218 - { 0x0000823c, 0x00000000 },
27219 - { 0x00008240, 0x00100000 },
27220 - { 0x00008244, 0x0010f400 },
27221 - { 0x00008248, 0x00000100 },
27222 - { 0x0000824c, 0x0001e800 },
27223 - { 0x00008250, 0x00000000 },
27224 - { 0x00008254, 0x00000000 },
27225 - { 0x00008258, 0x00000000 },
27226 - { 0x0000825c, 0x400000ff },
27227 - { 0x00008260, 0x00080922 },
27228 - { 0x00008264, 0xa8000010 },
27229 - { 0x00008270, 0x00000000 },
27230 - { 0x00008274, 0x40000000 },
27231 - { 0x00008278, 0x003e4180 },
27232 - { 0x0000827c, 0x00000000 },
27233 - { 0x00008284, 0x0000002c },
27234 - { 0x00008288, 0x0000002c },
27235 - { 0x0000828c, 0x00000000 },
27236 - { 0x00008294, 0x00000000 },
27237 - { 0x00008298, 0x00000000 },
27238 - { 0x00008300, 0x00000000 },
27239 - { 0x00008304, 0x00000000 },
27240 - { 0x00008308, 0x00000000 },
27241 - { 0x0000830c, 0x00000000 },
27242 - { 0x00008310, 0x00000000 },
27243 - { 0x00008314, 0x00000000 },
27244 - { 0x00008318, 0x00000000 },
27245 - { 0x00008328, 0x00000000 },
27246 - { 0x0000832c, 0x00000007 },
27247 - { 0x00008330, 0x00000302 },
27248 - { 0x00008334, 0x00000e00 },
27249 - { 0x00008338, 0x00070000 },
27250 - { 0x0000833c, 0x00000000 },
27251 - { 0x00008340, 0x000107ff },
27252 - { 0x00009808, 0x00000000 },
27253 - { 0x0000980c, 0xad848e19 },
27254 - { 0x00009810, 0x7d14e000 },
27255 - { 0x00009814, 0x9c0a9f6b },
27256 - { 0x0000981c, 0x00000000 },
27257 - { 0x0000982c, 0x0000a000 },
27258 - { 0x00009830, 0x00000000 },
27259 - { 0x0000983c, 0x00200400 },
27260 - { 0x00009840, 0x206a002e },
27261 - { 0x0000984c, 0x1284233c },
27262 - { 0x00009854, 0x00000859 },
27263 - { 0x00009900, 0x00000000 },
27264 - { 0x00009904, 0x00000000 },
27265 - { 0x00009908, 0x00000000 },
27266 - { 0x0000990c, 0x00000000 },
27267 - { 0x0000991c, 0x10000fff },
27268 - { 0x00009920, 0x05100000 },
27269 - { 0x0000a920, 0x05100000 },
27270 - { 0x0000b920, 0x05100000 },
27271 - { 0x00009928, 0x00000001 },
27272 - { 0x0000992c, 0x00000004 },
27273 - { 0x00009934, 0x1e1f2022 },
27274 - { 0x00009938, 0x0a0b0c0d },
27275 - { 0x0000993c, 0x00000000 },
27276 - { 0x00009948, 0x9280b212 },
27277 - { 0x0000994c, 0x00020028 },
27278 - { 0x00009954, 0x5d50e188 },
27279 - { 0x00009958, 0x00081fff },
27280 - { 0x0000c95c, 0x004b6a8e },
27281 - { 0x0000c968, 0x000003ce },
27282 - { 0x00009970, 0x190fb515 },
27283 - { 0x00009974, 0x00000000 },
27284 - { 0x00009978, 0x00000001 },
27285 - { 0x0000997c, 0x00000000 },
27286 - { 0x00009980, 0x00000000 },
27287 - { 0x00009984, 0x00000000 },
27288 - { 0x00009988, 0x00000000 },
27289 - { 0x0000998c, 0x00000000 },
27290 - { 0x00009990, 0x00000000 },
27291 - { 0x00009994, 0x00000000 },
27292 - { 0x00009998, 0x00000000 },
27293 - { 0x0000999c, 0x00000000 },
27294 - { 0x000099a0, 0x00000000 },
27295 - { 0x000099a4, 0x00000001 },
27296 - { 0x000099a8, 0x001fff00 },
27297 - { 0x000099ac, 0x00000000 },
27298 - { 0x000099b0, 0x03051000 },
27299 - { 0x000099dc, 0x00000000 },
27300 - { 0x000099e0, 0x00000200 },
27301 - { 0x000099e4, 0xaaaaaaaa },
27302 - { 0x000099e8, 0x3c466478 },
27303 - { 0x000099ec, 0x000000aa },
27304 - { 0x000099fc, 0x00001042 },
27305 - { 0x00009b00, 0x00000000 },
27306 - { 0x00009b04, 0x00000001 },
27307 - { 0x00009b08, 0x00000002 },
27308 - { 0x00009b0c, 0x00000003 },
27309 - { 0x00009b10, 0x00000004 },
27310 - { 0x00009b14, 0x00000005 },
27311 - { 0x00009b18, 0x00000008 },
27312 - { 0x00009b1c, 0x00000009 },
27313 - { 0x00009b20, 0x0000000a },
27314 - { 0x00009b24, 0x0000000b },
27315 - { 0x00009b28, 0x0000000c },
27316 - { 0x00009b2c, 0x0000000d },
27317 - { 0x00009b30, 0x00000010 },
27318 - { 0x00009b34, 0x00000011 },
27319 - { 0x00009b38, 0x00000012 },
27320 - { 0x00009b3c, 0x00000013 },
27321 - { 0x00009b40, 0x00000014 },
27322 - { 0x00009b44, 0x00000015 },
27323 - { 0x00009b48, 0x00000018 },
27324 - { 0x00009b4c, 0x00000019 },
27325 - { 0x00009b50, 0x0000001a },
27326 - { 0x00009b54, 0x0000001b },
27327 - { 0x00009b58, 0x0000001c },
27328 - { 0x00009b5c, 0x0000001d },
27329 - { 0x00009b60, 0x00000020 },
27330 - { 0x00009b64, 0x00000021 },
27331 - { 0x00009b68, 0x00000022 },
27332 - { 0x00009b6c, 0x00000023 },
27333 - { 0x00009b70, 0x00000024 },
27334 - { 0x00009b74, 0x00000025 },
27335 - { 0x00009b78, 0x00000028 },
27336 - { 0x00009b7c, 0x00000029 },
27337 - { 0x00009b80, 0x0000002a },
27338 - { 0x00009b84, 0x0000002b },
27339 - { 0x00009b88, 0x0000002c },
27340 - { 0x00009b8c, 0x0000002d },
27341 - { 0x00009b90, 0x00000030 },
27342 - { 0x00009b94, 0x00000031 },
27343 - { 0x00009b98, 0x00000032 },
27344 - { 0x00009b9c, 0x00000033 },
27345 - { 0x00009ba0, 0x00000034 },
27346 - { 0x00009ba4, 0x00000035 },
27347 - { 0x00009ba8, 0x00000035 },
27348 - { 0x00009bac, 0x00000035 },
27349 - { 0x00009bb0, 0x00000035 },
27350 - { 0x00009bb4, 0x00000035 },
27351 - { 0x00009bb8, 0x00000035 },
27352 - { 0x00009bbc, 0x00000035 },
27353 - { 0x00009bc0, 0x00000035 },
27354 - { 0x00009bc4, 0x00000035 },
27355 - { 0x00009bc8, 0x00000035 },
27356 - { 0x00009bcc, 0x00000035 },
27357 - { 0x00009bd0, 0x00000035 },
27358 - { 0x00009bd4, 0x00000035 },
27359 - { 0x00009bd8, 0x00000035 },
27360 - { 0x00009bdc, 0x00000035 },
27361 - { 0x00009be0, 0x00000035 },
27362 - { 0x00009be4, 0x00000035 },
27363 - { 0x00009be8, 0x00000035 },
27364 - { 0x00009bec, 0x00000035 },
27365 - { 0x00009bf0, 0x00000035 },
27366 - { 0x00009bf4, 0x00000035 },
27367 - { 0x00009bf8, 0x00000010 },
27368 - { 0x00009bfc, 0x0000001a },
27369 - { 0x0000a210, 0x40806333 },
27370 - { 0x0000a214, 0x00106c10 },
27371 - { 0x0000a218, 0x009c4060 },
27372 - { 0x0000a220, 0x018830c6 },
27373 - { 0x0000a224, 0x00000400 },
27374 - { 0x0000a228, 0x00000bb5 },
27375 - { 0x0000a22c, 0x00000011 },
27376 - { 0x0000a234, 0x20202020 },
27377 - { 0x0000a238, 0x20202020 },
27378 - { 0x0000a23c, 0x13c889af },
27379 - { 0x0000a240, 0x38490a20 },
27380 - { 0x0000a244, 0x00007bb6 },
27381 - { 0x0000a248, 0x0fff3ffc },
27382 - { 0x0000a24c, 0x00000001 },
27383 - { 0x0000a250, 0x0000a000 },
27384 - { 0x0000a254, 0x00000000 },
27385 - { 0x0000a258, 0x0cc75380 },
27386 - { 0x0000a25c, 0x0f0f0f01 },
27387 - { 0x0000a260, 0xdfa91f01 },
27388 - { 0x0000a268, 0x00000000 },
27389 - { 0x0000a26c, 0x0e79e5c6 },
27390 - { 0x0000b26c, 0x0e79e5c6 },
27391 - { 0x0000c26c, 0x0e79e5c6 },
27392 - { 0x0000d270, 0x00820820 },
27393 - { 0x0000a278, 0x1ce739ce },
27394 - { 0x0000a27c, 0x051701ce },
27395 - { 0x0000a338, 0x00000000 },
27396 - { 0x0000a33c, 0x00000000 },
27397 - { 0x0000a340, 0x00000000 },
27398 - { 0x0000a344, 0x00000000 },
27399 - { 0x0000a348, 0x3fffffff },
27400 - { 0x0000a34c, 0x3fffffff },
27401 - { 0x0000a350, 0x3fffffff },
27402 - { 0x0000a354, 0x0003ffff },
27403 - { 0x0000a358, 0x79a8aa1f },
27404 - { 0x0000d35c, 0x07ffffef },
27405 - { 0x0000d360, 0x0fffffe7 },
27406 - { 0x0000d364, 0x17ffffe5 },
27407 - { 0x0000d368, 0x1fffffe4 },
27408 - { 0x0000d36c, 0x37ffffe3 },
27409 - { 0x0000d370, 0x3fffffe3 },
27410 - { 0x0000d374, 0x57ffffe3 },
27411 - { 0x0000d378, 0x5fffffe2 },
27412 - { 0x0000d37c, 0x7fffffe2 },
27413 - { 0x0000d380, 0x7f3c7bba },
27414 - { 0x0000d384, 0xf3307ff0 },
27415 - { 0x0000a388, 0x08000000 },
27416 - { 0x0000a38c, 0x20202020 },
27417 - { 0x0000a390, 0x20202020 },
27418 - { 0x0000a394, 0x1ce739ce },
27419 - { 0x0000a398, 0x000001ce },
27420 - { 0x0000a39c, 0x00000001 },
27421 - { 0x0000a3a0, 0x00000000 },
27422 - { 0x0000a3a4, 0x00000000 },
27423 - { 0x0000a3a8, 0x00000000 },
27424 - { 0x0000a3ac, 0x00000000 },
27425 - { 0x0000a3b0, 0x00000000 },
27426 - { 0x0000a3b4, 0x00000000 },
27427 - { 0x0000a3b8, 0x00000000 },
27428 - { 0x0000a3bc, 0x00000000 },
27429 - { 0x0000a3c0, 0x00000000 },
27430 - { 0x0000a3c4, 0x00000000 },
27431 - { 0x0000a3c8, 0x00000246 },
27432 - { 0x0000a3cc, 0x20202020 },
27433 - { 0x0000a3d0, 0x20202020 },
27434 - { 0x0000a3d4, 0x20202020 },
27435 - { 0x0000a3dc, 0x1ce739ce },
27436 - { 0x0000a3e0, 0x000001ce },
27437 -};
27438 -
27439 -static const u32 ar5416Bank0[][2] = {
27440 - { 0x000098b0, 0x1e5795e5 },
27441 - { 0x000098e0, 0x02008020 },
27442 -};
27443 -
27444 -static const u32 ar5416BB_RfGain[][3] = {
27445 - { 0x00009a00, 0x00000000, 0x00000000 },
27446 - { 0x00009a04, 0x00000040, 0x00000040 },
27447 - { 0x00009a08, 0x00000080, 0x00000080 },
27448 - { 0x00009a0c, 0x000001a1, 0x00000141 },
27449 - { 0x00009a10, 0x000001e1, 0x00000181 },
27450 - { 0x00009a14, 0x00000021, 0x000001c1 },
27451 - { 0x00009a18, 0x00000061, 0x00000001 },
27452 - { 0x00009a1c, 0x00000168, 0x00000041 },
27453 - { 0x00009a20, 0x000001a8, 0x000001a8 },
27454 - { 0x00009a24, 0x000001e8, 0x000001e8 },
27455 - { 0x00009a28, 0x00000028, 0x00000028 },
27456 - { 0x00009a2c, 0x00000068, 0x00000068 },
27457 - { 0x00009a30, 0x00000189, 0x000000a8 },
27458 - { 0x00009a34, 0x000001c9, 0x00000169 },
27459 - { 0x00009a38, 0x00000009, 0x000001a9 },
27460 - { 0x00009a3c, 0x00000049, 0x000001e9 },
27461 - { 0x00009a40, 0x00000089, 0x00000029 },
27462 - { 0x00009a44, 0x00000170, 0x00000069 },
27463 - { 0x00009a48, 0x000001b0, 0x00000190 },
27464 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
27465 - { 0x00009a50, 0x00000030, 0x00000010 },
27466 - { 0x00009a54, 0x00000070, 0x00000050 },
27467 - { 0x00009a58, 0x00000191, 0x00000090 },
27468 - { 0x00009a5c, 0x000001d1, 0x00000151 },
27469 - { 0x00009a60, 0x00000011, 0x00000191 },
27470 - { 0x00009a64, 0x00000051, 0x000001d1 },
27471 - { 0x00009a68, 0x00000091, 0x00000011 },
27472 - { 0x00009a6c, 0x000001b8, 0x00000051 },
27473 - { 0x00009a70, 0x000001f8, 0x00000198 },
27474 - { 0x00009a74, 0x00000038, 0x000001d8 },
27475 - { 0x00009a78, 0x00000078, 0x00000018 },
27476 - { 0x00009a7c, 0x00000199, 0x00000058 },
27477 - { 0x00009a80, 0x000001d9, 0x00000098 },
27478 - { 0x00009a84, 0x00000019, 0x00000159 },
27479 - { 0x00009a88, 0x00000059, 0x00000199 },
27480 - { 0x00009a8c, 0x00000099, 0x000001d9 },
27481 - { 0x00009a90, 0x000000d9, 0x00000019 },
27482 - { 0x00009a94, 0x000000f9, 0x00000059 },
27483 - { 0x00009a98, 0x000000f9, 0x00000099 },
27484 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
27485 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
27486 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
27487 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
27488 - { 0x00009aac, 0x000000f9, 0x000000f9 },
27489 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
27490 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
27491 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
27492 - { 0x00009abc, 0x000000f9, 0x000000f9 },
27493 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
27494 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
27495 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
27496 - { 0x00009acc, 0x000000f9, 0x000000f9 },
27497 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
27498 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
27499 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
27500 - { 0x00009adc, 0x000000f9, 0x000000f9 },
27501 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
27502 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
27503 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
27504 - { 0x00009aec, 0x000000f9, 0x000000f9 },
27505 - { 0x00009af0, 0x000000f9, 0x000000f9 },
27506 - { 0x00009af4, 0x000000f9, 0x000000f9 },
27507 - { 0x00009af8, 0x000000f9, 0x000000f9 },
27508 - { 0x00009afc, 0x000000f9, 0x000000f9 },
27509 -};
27510 -
27511 -static const u32 ar5416Bank1[][2] = {
27512 - { 0x000098b0, 0x02108421 },
27513 - { 0x000098ec, 0x00000008 },
27514 -};
27515 -
27516 -static const u32 ar5416Bank2[][2] = {
27517 - { 0x000098b0, 0x0e73ff17 },
27518 - { 0x000098e0, 0x00000420 },
27519 -};
27520 -
27521 -static const u32 ar5416Bank3[][3] = {
27522 - { 0x000098f0, 0x01400018, 0x01c00018 },
27523 -};
27524 -
27525 -static const u32 ar5416Bank6[][3] = {
27526 -
27527 - { 0x0000989c, 0x00000000, 0x00000000 },
27528 - { 0x0000989c, 0x00000000, 0x00000000 },
27529 - { 0x0000989c, 0x00000000, 0x00000000 },
27530 - { 0x0000989c, 0x00e00000, 0x00e00000 },
27531 - { 0x0000989c, 0x005e0000, 0x005e0000 },
27532 - { 0x0000989c, 0x00120000, 0x00120000 },
27533 - { 0x0000989c, 0x00620000, 0x00620000 },
27534 - { 0x0000989c, 0x00020000, 0x00020000 },
27535 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27536 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27537 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27538 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
27539 - { 0x0000989c, 0x005f0000, 0x005f0000 },
27540 - { 0x0000989c, 0x00870000, 0x00870000 },
27541 - { 0x0000989c, 0x00f90000, 0x00f90000 },
27542 - { 0x0000989c, 0x007b0000, 0x007b0000 },
27543 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27544 - { 0x0000989c, 0x00f50000, 0x00f50000 },
27545 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
27546 - { 0x0000989c, 0x00110000, 0x00110000 },
27547 - { 0x0000989c, 0x006100a8, 0x006100a8 },
27548 - { 0x0000989c, 0x004210a2, 0x004210a2 },
27549 - { 0x0000989c, 0x0014008f, 0x0014008f },
27550 - { 0x0000989c, 0x00c40003, 0x00c40003 },
27551 - { 0x0000989c, 0x003000f2, 0x003000f2 },
27552 - { 0x0000989c, 0x00440016, 0x00440016 },
27553 - { 0x0000989c, 0x00410040, 0x00410040 },
27554 - { 0x0000989c, 0x0001805e, 0x0001805e },
27555 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
27556 - { 0x0000989c, 0x000000f1, 0x000000f1 },
27557 - { 0x0000989c, 0x00002081, 0x00002081 },
27558 - { 0x0000989c, 0x000000d4, 0x000000d4 },
27559 - { 0x000098d0, 0x0000000f, 0x0010000f },
27560 -};
27561 -
27562 -static const u32 ar5416Bank6TPC[][3] = {
27563 - { 0x0000989c, 0x00000000, 0x00000000 },
27564 - { 0x0000989c, 0x00000000, 0x00000000 },
27565 - { 0x0000989c, 0x00000000, 0x00000000 },
27566 - { 0x0000989c, 0x00e00000, 0x00e00000 },
27567 - { 0x0000989c, 0x005e0000, 0x005e0000 },
27568 - { 0x0000989c, 0x00120000, 0x00120000 },
27569 - { 0x0000989c, 0x00620000, 0x00620000 },
27570 - { 0x0000989c, 0x00020000, 0x00020000 },
27571 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27572 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27573 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27574 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
27575 - { 0x0000989c, 0x005f0000, 0x005f0000 },
27576 - { 0x0000989c, 0x00870000, 0x00870000 },
27577 - { 0x0000989c, 0x00f90000, 0x00f90000 },
27578 - { 0x0000989c, 0x007b0000, 0x007b0000 },
27579 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
27580 - { 0x0000989c, 0x00f50000, 0x00f50000 },
27581 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
27582 - { 0x0000989c, 0x00110000, 0x00110000 },
27583 - { 0x0000989c, 0x006100a8, 0x006100a8 },
27584 - { 0x0000989c, 0x00423022, 0x00423022 },
27585 - { 0x0000989c, 0x201400df, 0x201400df },
27586 - { 0x0000989c, 0x00c40002, 0x00c40002 },
27587 - { 0x0000989c, 0x003000f2, 0x003000f2 },
27588 - { 0x0000989c, 0x00440016, 0x00440016 },
27589 - { 0x0000989c, 0x00410040, 0x00410040 },
27590 - { 0x0000989c, 0x0001805e, 0x0001805e },
27591 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
27592 - { 0x0000989c, 0x000000e1, 0x000000e1 },
27593 - { 0x0000989c, 0x00007081, 0x00007081 },
27594 - { 0x0000989c, 0x000000d4, 0x000000d4 },
27595 - { 0x000098d0, 0x0000000f, 0x0010000f },
27596 -};
27597 -
27598 -static const u32 ar5416Bank7[][2] = {
27599 - { 0x0000989c, 0x00000500 },
27600 - { 0x0000989c, 0x00000800 },
27601 - { 0x000098cc, 0x0000000e },
27602 -};
27603 -
27604 -static const u32 ar5416Addac[][2] = {
27605 - {0x0000989c, 0x00000000 },
27606 - {0x0000989c, 0x00000003 },
27607 - {0x0000989c, 0x00000000 },
27608 - {0x0000989c, 0x0000000c },
27609 - {0x0000989c, 0x00000000 },
27610 - {0x0000989c, 0x00000030 },
27611 - {0x0000989c, 0x00000000 },
27612 - {0x0000989c, 0x00000000 },
27613 - {0x0000989c, 0x00000000 },
27614 - {0x0000989c, 0x00000000 },
27615 - {0x0000989c, 0x00000000 },
27616 - {0x0000989c, 0x00000000 },
27617 - {0x0000989c, 0x00000000 },
27618 - {0x0000989c, 0x00000000 },
27619 - {0x0000989c, 0x00000000 },
27620 - {0x0000989c, 0x00000000 },
27621 - {0x0000989c, 0x00000000 },
27622 - {0x0000989c, 0x00000000 },
27623 - {0x0000989c, 0x00000060 },
27624 - {0x0000989c, 0x00000000 },
27625 - {0x0000989c, 0x00000000 },
27626 - {0x0000989c, 0x00000000 },
27627 - {0x0000989c, 0x00000000 },
27628 - {0x0000989c, 0x00000000 },
27629 - {0x0000989c, 0x00000000 },
27630 - {0x0000989c, 0x00000000 },
27631 - {0x0000989c, 0x00000000 },
27632 - {0x0000989c, 0x00000000 },
27633 - {0x0000989c, 0x00000000 },
27634 - {0x0000989c, 0x00000000 },
27635 - {0x0000989c, 0x00000000 },
27636 - {0x0000989c, 0x00000058 },
27637 - {0x0000989c, 0x00000000 },
27638 - {0x0000989c, 0x00000000 },
27639 - {0x0000989c, 0x00000000 },
27640 - {0x0000989c, 0x00000000 },
27641 - {0x000098cc, 0x00000000 },
27642 -};
27643 -
27644 -static const u32 ar5416Modes_9100[][6] = {
27645 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
27646 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
27647 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
27648 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
27649 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
27650 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27651 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
27652 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
27653 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27654 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
27655 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
27656 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
27657 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
27658 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27659 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27660 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
27661 - { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
27662 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
27663 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
27664 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
27665 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
27666 - { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
27667 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
27668 - { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
27669 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
27670 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
27671 - { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
27672 - { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
27673 - { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
27674 - { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
27675 -#ifdef TB243
27676 - { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
27677 - { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
27678 - { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
27679 - { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
27680 -#else
27681 - { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
27682 - { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
27683 - { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
27684 - { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
27685 -#endif
27686 - { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
27687 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
27688 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
27689 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
27690 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
27691 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
27692 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27693 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27694 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
27695 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
27696 - { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
27697 - { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
27698 - { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
27699 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
27700 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
27701 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
27702 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
27703 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
27704 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
27705 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
27706 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
27707 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
27708 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
27709 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
27710 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
27711 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
27712 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
27713 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27714 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27715 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
27716 -};
27717 -
27718 -static const u32 ar5416Common_9100[][2] = {
27719 - { 0x0000000c, 0x00000000 },
27720 - { 0x00000030, 0x00020015 },
27721 - { 0x00000034, 0x00000005 },
27722 - { 0x00000040, 0x00000000 },
27723 - { 0x00000044, 0x00000008 },
27724 - { 0x00000048, 0x00000008 },
27725 - { 0x0000004c, 0x00000010 },
27726 - { 0x00000050, 0x00000000 },
27727 - { 0x00000054, 0x0000001f },
27728 - { 0x00000800, 0x00000000 },
27729 - { 0x00000804, 0x00000000 },
27730 - { 0x00000808, 0x00000000 },
27731 - { 0x0000080c, 0x00000000 },
27732 - { 0x00000810, 0x00000000 },
27733 - { 0x00000814, 0x00000000 },
27734 - { 0x00000818, 0x00000000 },
27735 - { 0x0000081c, 0x00000000 },
27736 - { 0x00000820, 0x00000000 },
27737 - { 0x00000824, 0x00000000 },
27738 - { 0x00001040, 0x002ffc0f },
27739 - { 0x00001044, 0x002ffc0f },
27740 - { 0x00001048, 0x002ffc0f },
27741 - { 0x0000104c, 0x002ffc0f },
27742 - { 0x00001050, 0x002ffc0f },
27743 - { 0x00001054, 0x002ffc0f },
27744 - { 0x00001058, 0x002ffc0f },
27745 - { 0x0000105c, 0x002ffc0f },
27746 - { 0x00001060, 0x002ffc0f },
27747 - { 0x00001064, 0x002ffc0f },
27748 - { 0x00001230, 0x00000000 },
27749 - { 0x00001270, 0x00000000 },
27750 - { 0x00001038, 0x00000000 },
27751 - { 0x00001078, 0x00000000 },
27752 - { 0x000010b8, 0x00000000 },
27753 - { 0x000010f8, 0x00000000 },
27754 - { 0x00001138, 0x00000000 },
27755 - { 0x00001178, 0x00000000 },
27756 - { 0x000011b8, 0x00000000 },
27757 - { 0x000011f8, 0x00000000 },
27758 - { 0x00001238, 0x00000000 },
27759 - { 0x00001278, 0x00000000 },
27760 - { 0x000012b8, 0x00000000 },
27761 - { 0x000012f8, 0x00000000 },
27762 - { 0x00001338, 0x00000000 },
27763 - { 0x00001378, 0x00000000 },
27764 - { 0x000013b8, 0x00000000 },
27765 - { 0x000013f8, 0x00000000 },
27766 - { 0x00001438, 0x00000000 },
27767 - { 0x00001478, 0x00000000 },
27768 - { 0x000014b8, 0x00000000 },
27769 - { 0x000014f8, 0x00000000 },
27770 - { 0x00001538, 0x00000000 },
27771 - { 0x00001578, 0x00000000 },
27772 - { 0x000015b8, 0x00000000 },
27773 - { 0x000015f8, 0x00000000 },
27774 - { 0x00001638, 0x00000000 },
27775 - { 0x00001678, 0x00000000 },
27776 - { 0x000016b8, 0x00000000 },
27777 - { 0x000016f8, 0x00000000 },
27778 - { 0x00001738, 0x00000000 },
27779 - { 0x00001778, 0x00000000 },
27780 - { 0x000017b8, 0x00000000 },
27781 - { 0x000017f8, 0x00000000 },
27782 - { 0x0000103c, 0x00000000 },
27783 - { 0x0000107c, 0x00000000 },
27784 - { 0x000010bc, 0x00000000 },
27785 - { 0x000010fc, 0x00000000 },
27786 - { 0x0000113c, 0x00000000 },
27787 - { 0x0000117c, 0x00000000 },
27788 - { 0x000011bc, 0x00000000 },
27789 - { 0x000011fc, 0x00000000 },
27790 - { 0x0000123c, 0x00000000 },
27791 - { 0x0000127c, 0x00000000 },
27792 - { 0x000012bc, 0x00000000 },
27793 - { 0x000012fc, 0x00000000 },
27794 - { 0x0000133c, 0x00000000 },
27795 - { 0x0000137c, 0x00000000 },
27796 - { 0x000013bc, 0x00000000 },
27797 - { 0x000013fc, 0x00000000 },
27798 - { 0x0000143c, 0x00000000 },
27799 - { 0x0000147c, 0x00000000 },
27800 - { 0x00020010, 0x00000003 },
27801 - { 0x00020038, 0x000004c2 },
27802 - { 0x00008004, 0x00000000 },
27803 - { 0x00008008, 0x00000000 },
27804 - { 0x0000800c, 0x00000000 },
27805 - { 0x00008018, 0x00000700 },
27806 - { 0x00008020, 0x00000000 },
27807 - { 0x00008038, 0x00000000 },
27808 - { 0x0000803c, 0x00000000 },
27809 - { 0x00008048, 0x40000000 },
27810 - { 0x00008054, 0x00004000 },
27811 - { 0x00008058, 0x00000000 },
27812 - { 0x0000805c, 0x000fc78f },
27813 - { 0x00008060, 0x0000000f },
27814 - { 0x00008064, 0x00000000 },
27815 - { 0x000080c0, 0x2a82301a },
27816 - { 0x000080c4, 0x05dc01e0 },
27817 - { 0x000080c8, 0x1f402710 },
27818 - { 0x000080cc, 0x01f40000 },
27819 - { 0x000080d0, 0x00001e00 },
27820 - { 0x000080d4, 0x00000000 },
27821 - { 0x000080d8, 0x00400000 },
27822 - { 0x000080e0, 0xffffffff },
27823 - { 0x000080e4, 0x0000ffff },
27824 - { 0x000080e8, 0x003f3f3f },
27825 - { 0x000080ec, 0x00000000 },
27826 - { 0x000080f0, 0x00000000 },
27827 - { 0x000080f4, 0x00000000 },
27828 - { 0x000080f8, 0x00000000 },
27829 - { 0x000080fc, 0x00020000 },
27830 - { 0x00008100, 0x00020000 },
27831 - { 0x00008104, 0x00000001 },
27832 - { 0x00008108, 0x00000052 },
27833 - { 0x0000810c, 0x00000000 },
27834 - { 0x00008110, 0x00000168 },
27835 - { 0x00008118, 0x000100aa },
27836 - { 0x0000811c, 0x00003210 },
27837 - { 0x00008120, 0x08f04800 },
27838 - { 0x00008124, 0x00000000 },
27839 - { 0x00008128, 0x00000000 },
27840 - { 0x0000812c, 0x00000000 },
27841 - { 0x00008130, 0x00000000 },
27842 - { 0x00008134, 0x00000000 },
27843 - { 0x00008138, 0x00000000 },
27844 - { 0x0000813c, 0x00000000 },
27845 - { 0x00008144, 0x00000000 },
27846 - { 0x00008168, 0x00000000 },
27847 - { 0x0000816c, 0x00000000 },
27848 - { 0x00008170, 0x32143320 },
27849 - { 0x00008174, 0xfaa4fa50 },
27850 - { 0x00008178, 0x00000100 },
27851 - { 0x0000817c, 0x00000000 },
27852 - { 0x000081c4, 0x00000000 },
27853 - { 0x000081d0, 0x00003210 },
27854 - { 0x000081ec, 0x00000000 },
27855 - { 0x000081f0, 0x00000000 },
27856 - { 0x000081f4, 0x00000000 },
27857 - { 0x000081f8, 0x00000000 },
27858 - { 0x000081fc, 0x00000000 },
27859 - { 0x00008200, 0x00000000 },
27860 - { 0x00008204, 0x00000000 },
27861 - { 0x00008208, 0x00000000 },
27862 - { 0x0000820c, 0x00000000 },
27863 - { 0x00008210, 0x00000000 },
27864 - { 0x00008214, 0x00000000 },
27865 - { 0x00008218, 0x00000000 },
27866 - { 0x0000821c, 0x00000000 },
27867 - { 0x00008220, 0x00000000 },
27868 - { 0x00008224, 0x00000000 },
27869 - { 0x00008228, 0x00000000 },
27870 - { 0x0000822c, 0x00000000 },
27871 - { 0x00008230, 0x00000000 },
27872 - { 0x00008234, 0x00000000 },
27873 - { 0x00008238, 0x00000000 },
27874 - { 0x0000823c, 0x00000000 },
27875 - { 0x00008240, 0x00100000 },
27876 - { 0x00008244, 0x0010f400 },
27877 - { 0x00008248, 0x00000100 },
27878 - { 0x0000824c, 0x0001e800 },
27879 - { 0x00008250, 0x00000000 },
27880 - { 0x00008254, 0x00000000 },
27881 - { 0x00008258, 0x00000000 },
27882 - { 0x0000825c, 0x400000ff },
27883 - { 0x00008260, 0x00080922 },
27884 - { 0x00008270, 0x00000000 },
27885 - { 0x00008274, 0x40000000 },
27886 - { 0x00008278, 0x003e4180 },
27887 - { 0x0000827c, 0x00000000 },
27888 - { 0x00008284, 0x0000002c },
27889 - { 0x00008288, 0x0000002c },
27890 - { 0x0000828c, 0x00000000 },
27891 - { 0x00008294, 0x00000000 },
27892 - { 0x00008298, 0x00000000 },
27893 - { 0x00008300, 0x00000000 },
27894 - { 0x00008304, 0x00000000 },
27895 - { 0x00008308, 0x00000000 },
27896 - { 0x0000830c, 0x00000000 },
27897 - { 0x00008310, 0x00000000 },
27898 - { 0x00008314, 0x00000000 },
27899 - { 0x00008318, 0x00000000 },
27900 - { 0x00008328, 0x00000000 },
27901 - { 0x0000832c, 0x00000007 },
27902 - { 0x00008330, 0x00000302 },
27903 - { 0x00008334, 0x00000e00 },
27904 - { 0x00008338, 0x00000000 },
27905 - { 0x0000833c, 0x00000000 },
27906 - { 0x00008340, 0x000107ff },
27907 - { 0x00009808, 0x00000000 },
27908 - { 0x0000980c, 0xad848e19 },
27909 - { 0x00009810, 0x7d14e000 },
27910 - { 0x00009814, 0x9c0a9f6b },
27911 - { 0x0000981c, 0x00000000 },
27912 - { 0x0000982c, 0x0000a000 },
27913 - { 0x00009830, 0x00000000 },
27914 - { 0x0000983c, 0x00200400 },
27915 - { 0x00009840, 0x206a01ae },
27916 - { 0x0000984c, 0x1284233c },
27917 - { 0x00009854, 0x00000859 },
27918 - { 0x00009900, 0x00000000 },
27919 - { 0x00009904, 0x00000000 },
27920 - { 0x00009908, 0x00000000 },
27921 - { 0x0000990c, 0x00000000 },
27922 - { 0x0000991c, 0x10000fff },
27923 - { 0x00009920, 0x05100000 },
27924 - { 0x0000a920, 0x05100000 },
27925 - { 0x0000b920, 0x05100000 },
27926 - { 0x00009928, 0x00000001 },
27927 - { 0x0000992c, 0x00000004 },
27928 - { 0x00009934, 0x1e1f2022 },
27929 - { 0x00009938, 0x0a0b0c0d },
27930 - { 0x0000993c, 0x00000000 },
27931 - { 0x00009948, 0x9280b212 },
27932 - { 0x0000994c, 0x00020028 },
27933 - { 0x0000c95c, 0x004b6a8e },
27934 - { 0x0000c968, 0x000003ce },
27935 - { 0x00009970, 0x190fb515 },
27936 - { 0x00009974, 0x00000000 },
27937 - { 0x00009978, 0x00000001 },
27938 - { 0x0000997c, 0x00000000 },
27939 - { 0x00009980, 0x00000000 },
27940 - { 0x00009984, 0x00000000 },
27941 - { 0x00009988, 0x00000000 },
27942 - { 0x0000998c, 0x00000000 },
27943 - { 0x00009990, 0x00000000 },
27944 - { 0x00009994, 0x00000000 },
27945 - { 0x00009998, 0x00000000 },
27946 - { 0x0000999c, 0x00000000 },
27947 - { 0x000099a0, 0x00000000 },
27948 - { 0x000099a4, 0x00000001 },
27949 - { 0x000099a8, 0x201fff00 },
27950 - { 0x000099ac, 0x006f0000 },
27951 - { 0x000099b0, 0x03051000 },
27952 - { 0x000099dc, 0x00000000 },
27953 - { 0x000099e0, 0x00000200 },
27954 - { 0x000099e4, 0xaaaaaaaa },
27955 - { 0x000099e8, 0x3c466478 },
27956 - { 0x000099ec, 0x0cc80caa },
27957 - { 0x000099fc, 0x00001042 },
27958 - { 0x00009b00, 0x00000000 },
27959 - { 0x00009b04, 0x00000001 },
27960 - { 0x00009b08, 0x00000002 },
27961 - { 0x00009b0c, 0x00000003 },
27962 - { 0x00009b10, 0x00000004 },
27963 - { 0x00009b14, 0x00000005 },
27964 - { 0x00009b18, 0x00000008 },
27965 - { 0x00009b1c, 0x00000009 },
27966 - { 0x00009b20, 0x0000000a },
27967 - { 0x00009b24, 0x0000000b },
27968 - { 0x00009b28, 0x0000000c },
27969 - { 0x00009b2c, 0x0000000d },
27970 - { 0x00009b30, 0x00000010 },
27971 - { 0x00009b34, 0x00000011 },
27972 - { 0x00009b38, 0x00000012 },
27973 - { 0x00009b3c, 0x00000013 },
27974 - { 0x00009b40, 0x00000014 },
27975 - { 0x00009b44, 0x00000015 },
27976 - { 0x00009b48, 0x00000018 },
27977 - { 0x00009b4c, 0x00000019 },
27978 - { 0x00009b50, 0x0000001a },
27979 - { 0x00009b54, 0x0000001b },
27980 - { 0x00009b58, 0x0000001c },
27981 - { 0x00009b5c, 0x0000001d },
27982 - { 0x00009b60, 0x00000020 },
27983 - { 0x00009b64, 0x00000021 },
27984 - { 0x00009b68, 0x00000022 },
27985 - { 0x00009b6c, 0x00000023 },
27986 - { 0x00009b70, 0x00000024 },
27987 - { 0x00009b74, 0x00000025 },
27988 - { 0x00009b78, 0x00000028 },
27989 - { 0x00009b7c, 0x00000029 },
27990 - { 0x00009b80, 0x0000002a },
27991 - { 0x00009b84, 0x0000002b },
27992 - { 0x00009b88, 0x0000002c },
27993 - { 0x00009b8c, 0x0000002d },
27994 - { 0x00009b90, 0x00000030 },
27995 - { 0x00009b94, 0x00000031 },
27996 - { 0x00009b98, 0x00000032 },
27997 - { 0x00009b9c, 0x00000033 },
27998 - { 0x00009ba0, 0x00000034 },
27999 - { 0x00009ba4, 0x00000035 },
28000 - { 0x00009ba8, 0x00000035 },
28001 - { 0x00009bac, 0x00000035 },
28002 - { 0x00009bb0, 0x00000035 },
28003 - { 0x00009bb4, 0x00000035 },
28004 - { 0x00009bb8, 0x00000035 },
28005 - { 0x00009bbc, 0x00000035 },
28006 - { 0x00009bc0, 0x00000035 },
28007 - { 0x00009bc4, 0x00000035 },
28008 - { 0x00009bc8, 0x00000035 },
28009 - { 0x00009bcc, 0x00000035 },
28010 - { 0x00009bd0, 0x00000035 },
28011 - { 0x00009bd4, 0x00000035 },
28012 - { 0x00009bd8, 0x00000035 },
28013 - { 0x00009bdc, 0x00000035 },
28014 - { 0x00009be0, 0x00000035 },
28015 - { 0x00009be4, 0x00000035 },
28016 - { 0x00009be8, 0x00000035 },
28017 - { 0x00009bec, 0x00000035 },
28018 - { 0x00009bf0, 0x00000035 },
28019 - { 0x00009bf4, 0x00000035 },
28020 - { 0x00009bf8, 0x00000010 },
28021 - { 0x00009bfc, 0x0000001a },
28022 - { 0x0000a210, 0x40806333 },
28023 - { 0x0000a214, 0x00106c10 },
28024 - { 0x0000a218, 0x009c4060 },
28025 - { 0x0000a220, 0x018830c6 },
28026 - { 0x0000a224, 0x00000400 },
28027 - { 0x0000a228, 0x001a0bb5 },
28028 - { 0x0000a22c, 0x00000000 },
28029 - { 0x0000a234, 0x20202020 },
28030 - { 0x0000a238, 0x20202020 },
28031 - { 0x0000a23c, 0x13c889ae },
28032 - { 0x0000a240, 0x38490a20 },
28033 - { 0x0000a244, 0x00007bb6 },
28034 - { 0x0000a248, 0x0fff3ffc },
28035 - { 0x0000a24c, 0x00000001 },
28036 - { 0x0000a250, 0x0000a000 },
28037 - { 0x0000a254, 0x00000000 },
28038 - { 0x0000a258, 0x0cc75380 },
28039 - { 0x0000a25c, 0x0f0f0f01 },
28040 - { 0x0000a260, 0xdfa91f01 },
28041 - { 0x0000a268, 0x00000001 },
28042 - { 0x0000a26c, 0x0ebae9c6 },
28043 - { 0x0000b26c, 0x0ebae9c6 },
28044 - { 0x0000c26c, 0x0ebae9c6 },
28045 - { 0x0000d270, 0x00820820 },
28046 - { 0x0000a278, 0x1ce739ce },
28047 - { 0x0000a27c, 0x050701ce },
28048 - { 0x0000a338, 0x00000000 },
28049 - { 0x0000a33c, 0x00000000 },
28050 - { 0x0000a340, 0x00000000 },
28051 - { 0x0000a344, 0x00000000 },
28052 - { 0x0000a348, 0x3fffffff },
28053 - { 0x0000a34c, 0x3fffffff },
28054 - { 0x0000a350, 0x3fffffff },
28055 - { 0x0000a354, 0x0003ffff },
28056 - { 0x0000a358, 0x79a8aa33 },
28057 - { 0x0000d35c, 0x07ffffef },
28058 - { 0x0000d360, 0x0fffffe7 },
28059 - { 0x0000d364, 0x17ffffe5 },
28060 - { 0x0000d368, 0x1fffffe4 },
28061 - { 0x0000d36c, 0x37ffffe3 },
28062 - { 0x0000d370, 0x3fffffe3 },
28063 - { 0x0000d374, 0x57ffffe3 },
28064 - { 0x0000d378, 0x5fffffe2 },
28065 - { 0x0000d37c, 0x7fffffe2 },
28066 - { 0x0000d380, 0x7f3c7bba },
28067 - { 0x0000d384, 0xf3307ff0 },
28068 - { 0x0000a388, 0x0c000000 },
28069 - { 0x0000a38c, 0x20202020 },
28070 - { 0x0000a390, 0x20202020 },
28071 - { 0x0000a394, 0x1ce739ce },
28072 - { 0x0000a398, 0x000001ce },
28073 - { 0x0000a39c, 0x00000001 },
28074 - { 0x0000a3a0, 0x00000000 },
28075 - { 0x0000a3a4, 0x00000000 },
28076 - { 0x0000a3a8, 0x00000000 },
28077 - { 0x0000a3ac, 0x00000000 },
28078 - { 0x0000a3b0, 0x00000000 },
28079 - { 0x0000a3b4, 0x00000000 },
28080 - { 0x0000a3b8, 0x00000000 },
28081 - { 0x0000a3bc, 0x00000000 },
28082 - { 0x0000a3c0, 0x00000000 },
28083 - { 0x0000a3c4, 0x00000000 },
28084 - { 0x0000a3c8, 0x00000246 },
28085 - { 0x0000a3cc, 0x20202020 },
28086 - { 0x0000a3d0, 0x20202020 },
28087 - { 0x0000a3d4, 0x20202020 },
28088 - { 0x0000a3dc, 0x1ce739ce },
28089 - { 0x0000a3e0, 0x000001ce },
28090 -};
28091 -
28092 -static const u32 ar5416Bank0_9100[][2] = {
28093 - { 0x000098b0, 0x1e5795e5 },
28094 - { 0x000098e0, 0x02008020 },
28095 -};
28096 -
28097 -static const u32 ar5416BB_RfGain_9100[][3] = {
28098 - { 0x00009a00, 0x00000000, 0x00000000 },
28099 - { 0x00009a04, 0x00000040, 0x00000040 },
28100 - { 0x00009a08, 0x00000080, 0x00000080 },
28101 - { 0x00009a0c, 0x000001a1, 0x00000141 },
28102 - { 0x00009a10, 0x000001e1, 0x00000181 },
28103 - { 0x00009a14, 0x00000021, 0x000001c1 },
28104 - { 0x00009a18, 0x00000061, 0x00000001 },
28105 - { 0x00009a1c, 0x00000168, 0x00000041 },
28106 - { 0x00009a20, 0x000001a8, 0x000001a8 },
28107 - { 0x00009a24, 0x000001e8, 0x000001e8 },
28108 - { 0x00009a28, 0x00000028, 0x00000028 },
28109 - { 0x00009a2c, 0x00000068, 0x00000068 },
28110 - { 0x00009a30, 0x00000189, 0x000000a8 },
28111 - { 0x00009a34, 0x000001c9, 0x00000169 },
28112 - { 0x00009a38, 0x00000009, 0x000001a9 },
28113 - { 0x00009a3c, 0x00000049, 0x000001e9 },
28114 - { 0x00009a40, 0x00000089, 0x00000029 },
28115 - { 0x00009a44, 0x00000170, 0x00000069 },
28116 - { 0x00009a48, 0x000001b0, 0x00000190 },
28117 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
28118 - { 0x00009a50, 0x00000030, 0x00000010 },
28119 - { 0x00009a54, 0x00000070, 0x00000050 },
28120 - { 0x00009a58, 0x00000191, 0x00000090 },
28121 - { 0x00009a5c, 0x000001d1, 0x00000151 },
28122 - { 0x00009a60, 0x00000011, 0x00000191 },
28123 - { 0x00009a64, 0x00000051, 0x000001d1 },
28124 - { 0x00009a68, 0x00000091, 0x00000011 },
28125 - { 0x00009a6c, 0x000001b8, 0x00000051 },
28126 - { 0x00009a70, 0x000001f8, 0x00000198 },
28127 - { 0x00009a74, 0x00000038, 0x000001d8 },
28128 - { 0x00009a78, 0x00000078, 0x00000018 },
28129 - { 0x00009a7c, 0x00000199, 0x00000058 },
28130 - { 0x00009a80, 0x000001d9, 0x00000098 },
28131 - { 0x00009a84, 0x00000019, 0x00000159 },
28132 - { 0x00009a88, 0x00000059, 0x00000199 },
28133 - { 0x00009a8c, 0x00000099, 0x000001d9 },
28134 - { 0x00009a90, 0x000000d9, 0x00000019 },
28135 - { 0x00009a94, 0x000000f9, 0x00000059 },
28136 - { 0x00009a98, 0x000000f9, 0x00000099 },
28137 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
28138 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
28139 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
28140 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
28141 - { 0x00009aac, 0x000000f9, 0x000000f9 },
28142 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
28143 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
28144 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
28145 - { 0x00009abc, 0x000000f9, 0x000000f9 },
28146 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
28147 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
28148 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
28149 - { 0x00009acc, 0x000000f9, 0x000000f9 },
28150 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
28151 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
28152 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
28153 - { 0x00009adc, 0x000000f9, 0x000000f9 },
28154 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
28155 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
28156 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
28157 - { 0x00009aec, 0x000000f9, 0x000000f9 },
28158 - { 0x00009af0, 0x000000f9, 0x000000f9 },
28159 - { 0x00009af4, 0x000000f9, 0x000000f9 },
28160 - { 0x00009af8, 0x000000f9, 0x000000f9 },
28161 - { 0x00009afc, 0x000000f9, 0x000000f9 },
28162 -};
28163 -
28164 -static const u32 ar5416Bank1_9100[][2] = {
28165 - { 0x000098b0, 0x02108421},
28166 - { 0x000098ec, 0x00000008},
28167 -};
28168 -
28169 -static const u32 ar5416Bank2_9100[][2] = {
28170 - { 0x000098b0, 0x0e73ff17},
28171 - { 0x000098e0, 0x00000420},
28172 -};
28173 -
28174 -static const u32 ar5416Bank3_9100[][3] = {
28175 - { 0x000098f0, 0x01400018, 0x01c00018 },
28176 -};
28177 -
28178 -static const u32 ar5416Bank6_9100[][3] = {
28179 -
28180 - { 0x0000989c, 0x00000000, 0x00000000 },
28181 - { 0x0000989c, 0x00000000, 0x00000000 },
28182 - { 0x0000989c, 0x00000000, 0x00000000 },
28183 - { 0x0000989c, 0x00e00000, 0x00e00000 },
28184 - { 0x0000989c, 0x005e0000, 0x005e0000 },
28185 - { 0x0000989c, 0x00120000, 0x00120000 },
28186 - { 0x0000989c, 0x00620000, 0x00620000 },
28187 - { 0x0000989c, 0x00020000, 0x00020000 },
28188 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28189 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28190 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28191 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28192 - { 0x0000989c, 0x005f0000, 0x005f0000 },
28193 - { 0x0000989c, 0x00870000, 0x00870000 },
28194 - { 0x0000989c, 0x00f90000, 0x00f90000 },
28195 - { 0x0000989c, 0x007b0000, 0x007b0000 },
28196 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28197 - { 0x0000989c, 0x00f50000, 0x00f50000 },
28198 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
28199 - { 0x0000989c, 0x00110000, 0x00110000 },
28200 - { 0x0000989c, 0x006100a8, 0x006100a8 },
28201 - { 0x0000989c, 0x004210a2, 0x004210a2 },
28202 - { 0x0000989c, 0x0014000f, 0x0014000f },
28203 - { 0x0000989c, 0x00c40002, 0x00c40002 },
28204 - { 0x0000989c, 0x003000f2, 0x003000f2 },
28205 - { 0x0000989c, 0x00440016, 0x00440016 },
28206 - { 0x0000989c, 0x00410040, 0x00410040 },
28207 - { 0x0000989c, 0x000180d6, 0x000180d6 },
28208 - { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
28209 - { 0x0000989c, 0x000000b1, 0x000000b1 },
28210 - { 0x0000989c, 0x00002000, 0x00002000 },
28211 - { 0x0000989c, 0x000000d4, 0x000000d4 },
28212 - { 0x000098d0, 0x0000000f, 0x0010000f },
28213 -};
28214 -
28215 -
28216 -static const u32 ar5416Bank6TPC_9100[][3] = {
28217 -
28218 - { 0x0000989c, 0x00000000, 0x00000000 },
28219 - { 0x0000989c, 0x00000000, 0x00000000 },
28220 - { 0x0000989c, 0x00000000, 0x00000000 },
28221 - { 0x0000989c, 0x00e00000, 0x00e00000 },
28222 - { 0x0000989c, 0x005e0000, 0x005e0000 },
28223 - { 0x0000989c, 0x00120000, 0x00120000 },
28224 - { 0x0000989c, 0x00620000, 0x00620000 },
28225 - { 0x0000989c, 0x00020000, 0x00020000 },
28226 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28227 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28228 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28229 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
28230 - { 0x0000989c, 0x005f0000, 0x005f0000 },
28231 - { 0x0000989c, 0x00870000, 0x00870000 },
28232 - { 0x0000989c, 0x00f90000, 0x00f90000 },
28233 - { 0x0000989c, 0x007b0000, 0x007b0000 },
28234 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28235 - { 0x0000989c, 0x00f50000, 0x00f50000 },
28236 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
28237 - { 0x0000989c, 0x00110000, 0x00110000 },
28238 - { 0x0000989c, 0x006100a8, 0x006100a8 },
28239 - { 0x0000989c, 0x00423022, 0x00423022 },
28240 - { 0x0000989c, 0x2014008f, 0x2014008f },
28241 - { 0x0000989c, 0x00c40002, 0x00c40002 },
28242 - { 0x0000989c, 0x003000f2, 0x003000f2 },
28243 - { 0x0000989c, 0x00440016, 0x00440016 },
28244 - { 0x0000989c, 0x00410040, 0x00410040 },
28245 - { 0x0000989c, 0x0001805e, 0x0001805e },
28246 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
28247 - { 0x0000989c, 0x000000e1, 0x000000e1 },
28248 - { 0x0000989c, 0x00007080, 0x00007080 },
28249 - { 0x0000989c, 0x000000d4, 0x000000d4 },
28250 - { 0x000098d0, 0x0000000f, 0x0010000f },
28251 -};
28252 -
28253 -static const u32 ar5416Bank7_9100[][2] = {
28254 - { 0x0000989c, 0x00000500 },
28255 - { 0x0000989c, 0x00000800 },
28256 - { 0x000098cc, 0x0000000e },
28257 -};
28258 -
28259 -static const u32 ar5416Addac_9100[][2] = {
28260 - {0x0000989c, 0x00000000 },
28261 - {0x0000989c, 0x00000000 },
28262 - {0x0000989c, 0x00000000 },
28263 - {0x0000989c, 0x00000000 },
28264 - {0x0000989c, 0x00000000 },
28265 - {0x0000989c, 0x00000000 },
28266 - {0x0000989c, 0x00000000 },
28267 - {0x0000989c, 0x00000010 },
28268 - {0x0000989c, 0x00000000 },
28269 - {0x0000989c, 0x00000000 },
28270 - {0x0000989c, 0x00000000 },
28271 - {0x0000989c, 0x00000000 },
28272 - {0x0000989c, 0x00000000 },
28273 - {0x0000989c, 0x00000000 },
28274 - {0x0000989c, 0x00000000 },
28275 - {0x0000989c, 0x00000000 },
28276 - {0x0000989c, 0x00000000 },
28277 - {0x0000989c, 0x00000000 },
28278 - {0x0000989c, 0x00000000 },
28279 - {0x0000989c, 0x00000000 },
28280 - {0x0000989c, 0x00000000 },
28281 - {0x0000989c, 0x000000c0 },
28282 - {0x0000989c, 0x00000015 },
28283 - {0x0000989c, 0x00000000 },
28284 - {0x0000989c, 0x00000000 },
28285 - {0x0000989c, 0x00000000 },
28286 - {0x0000989c, 0x00000000 },
28287 - {0x0000989c, 0x00000000 },
28288 - {0x0000989c, 0x00000000 },
28289 - {0x0000989c, 0x00000000 },
28290 - {0x0000989c, 0x00000000 },
28291 - {0x000098cc, 0x00000000 },
28292 -};
28293 -
28294 -static const u32 ar5416Modes_9160[][6] = {
28295 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
28296 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
28297 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
28298 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
28299 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
28300 - { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
28301 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
28302 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
28303 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
28304 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
28305 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
28306 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
28307 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
28308 - { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
28309 - { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
28310 - { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
28311 - { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
28312 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
28313 - { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
28314 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
28315 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
28316 - { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
28317 - { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
28318 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
28319 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
28320 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
28321 - { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
28322 - { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
28323 - { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
28324 - { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
28325 - { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
28326 - { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
28327 - { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
28328 - { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
28329 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
28330 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
28331 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
28332 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
28333 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28334 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28335 - { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
28336 - { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
28337 - { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
28338 - { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
28339 - { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
28340 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
28341 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
28342 - { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
28343 - { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
28344 - { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
28345 - { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
28346 - { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
28347 - { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
28348 - { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
28349 - { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
28350 - { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
28351 - { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
28352 - { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
28353 - { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
28354 - { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28355 - { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28356 - { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
28357 -};
28358 -
28359 -static const u32 ar5416Common_9160[][2] = {
28360 - { 0x0000000c, 0x00000000 },
28361 - { 0x00000030, 0x00020015 },
28362 - { 0x00000034, 0x00000005 },
28363 - { 0x00000040, 0x00000000 },
28364 - { 0x00000044, 0x00000008 },
28365 - { 0x00000048, 0x00000008 },
28366 - { 0x0000004c, 0x00000010 },
28367 - { 0x00000050, 0x00000000 },
28368 - { 0x00000054, 0x0000001f },
28369 - { 0x00000800, 0x00000000 },
28370 - { 0x00000804, 0x00000000 },
28371 - { 0x00000808, 0x00000000 },
28372 - { 0x0000080c, 0x00000000 },
28373 - { 0x00000810, 0x00000000 },
28374 - { 0x00000814, 0x00000000 },
28375 - { 0x00000818, 0x00000000 },
28376 - { 0x0000081c, 0x00000000 },
28377 - { 0x00000820, 0x00000000 },
28378 - { 0x00000824, 0x00000000 },
28379 - { 0x00001040, 0x002ffc0f },
28380 - { 0x00001044, 0x002ffc0f },
28381 - { 0x00001048, 0x002ffc0f },
28382 - { 0x0000104c, 0x002ffc0f },
28383 - { 0x00001050, 0x002ffc0f },
28384 - { 0x00001054, 0x002ffc0f },
28385 - { 0x00001058, 0x002ffc0f },
28386 - { 0x0000105c, 0x002ffc0f },
28387 - { 0x00001060, 0x002ffc0f },
28388 - { 0x00001064, 0x002ffc0f },
28389 - { 0x00001230, 0x00000000 },
28390 - { 0x00001270, 0x00000000 },
28391 - { 0x00001038, 0x00000000 },
28392 - { 0x00001078, 0x00000000 },
28393 - { 0x000010b8, 0x00000000 },
28394 - { 0x000010f8, 0x00000000 },
28395 - { 0x00001138, 0x00000000 },
28396 - { 0x00001178, 0x00000000 },
28397 - { 0x000011b8, 0x00000000 },
28398 - { 0x000011f8, 0x00000000 },
28399 - { 0x00001238, 0x00000000 },
28400 - { 0x00001278, 0x00000000 },
28401 - { 0x000012b8, 0x00000000 },
28402 - { 0x000012f8, 0x00000000 },
28403 - { 0x00001338, 0x00000000 },
28404 - { 0x00001378, 0x00000000 },
28405 - { 0x000013b8, 0x00000000 },
28406 - { 0x000013f8, 0x00000000 },
28407 - { 0x00001438, 0x00000000 },
28408 - { 0x00001478, 0x00000000 },
28409 - { 0x000014b8, 0x00000000 },
28410 - { 0x000014f8, 0x00000000 },
28411 - { 0x00001538, 0x00000000 },
28412 - { 0x00001578, 0x00000000 },
28413 - { 0x000015b8, 0x00000000 },
28414 - { 0x000015f8, 0x00000000 },
28415 - { 0x00001638, 0x00000000 },
28416 - { 0x00001678, 0x00000000 },
28417 - { 0x000016b8, 0x00000000 },
28418 - { 0x000016f8, 0x00000000 },
28419 - { 0x00001738, 0x00000000 },
28420 - { 0x00001778, 0x00000000 },
28421 - { 0x000017b8, 0x00000000 },
28422 - { 0x000017f8, 0x00000000 },
28423 - { 0x0000103c, 0x00000000 },
28424 - { 0x0000107c, 0x00000000 },
28425 - { 0x000010bc, 0x00000000 },
28426 - { 0x000010fc, 0x00000000 },
28427 - { 0x0000113c, 0x00000000 },
28428 - { 0x0000117c, 0x00000000 },
28429 - { 0x000011bc, 0x00000000 },
28430 - { 0x000011fc, 0x00000000 },
28431 - { 0x0000123c, 0x00000000 },
28432 - { 0x0000127c, 0x00000000 },
28433 - { 0x000012bc, 0x00000000 },
28434 - { 0x000012fc, 0x00000000 },
28435 - { 0x0000133c, 0x00000000 },
28436 - { 0x0000137c, 0x00000000 },
28437 - { 0x000013bc, 0x00000000 },
28438 - { 0x000013fc, 0x00000000 },
28439 - { 0x0000143c, 0x00000000 },
28440 - { 0x0000147c, 0x00000000 },
28441 - { 0x00004030, 0x00000002 },
28442 - { 0x0000403c, 0x00000002 },
28443 - { 0x00007010, 0x00000020 },
28444 - { 0x00007038, 0x000004c2 },
28445 - { 0x00008004, 0x00000000 },
28446 - { 0x00008008, 0x00000000 },
28447 - { 0x0000800c, 0x00000000 },
28448 - { 0x00008018, 0x00000700 },
28449 - { 0x00008020, 0x00000000 },
28450 - { 0x00008038, 0x00000000 },
28451 - { 0x0000803c, 0x00000000 },
28452 - { 0x00008048, 0x40000000 },
28453 - { 0x00008054, 0x00000000 },
28454 - { 0x00008058, 0x00000000 },
28455 - { 0x0000805c, 0x000fc78f },
28456 - { 0x00008060, 0x0000000f },
28457 - { 0x00008064, 0x00000000 },
28458 - { 0x000080c0, 0x2a82301a },
28459 - { 0x000080c4, 0x05dc01e0 },
28460 - { 0x000080c8, 0x1f402710 },
28461 - { 0x000080cc, 0x01f40000 },
28462 - { 0x000080d0, 0x00001e00 },
28463 - { 0x000080d4, 0x00000000 },
28464 - { 0x000080d8, 0x00400000 },
28465 - { 0x000080e0, 0xffffffff },
28466 - { 0x000080e4, 0x0000ffff },
28467 - { 0x000080e8, 0x003f3f3f },
28468 - { 0x000080ec, 0x00000000 },
28469 - { 0x000080f0, 0x00000000 },
28470 - { 0x000080f4, 0x00000000 },
28471 - { 0x000080f8, 0x00000000 },
28472 - { 0x000080fc, 0x00020000 },
28473 - { 0x00008100, 0x00020000 },
28474 - { 0x00008104, 0x00000001 },
28475 - { 0x00008108, 0x00000052 },
28476 - { 0x0000810c, 0x00000000 },
28477 - { 0x00008110, 0x00000168 },
28478 - { 0x00008118, 0x000100aa },
28479 - { 0x0000811c, 0x00003210 },
28480 - { 0x00008120, 0x08f04800 },
28481 - { 0x00008124, 0x00000000 },
28482 - { 0x00008128, 0x00000000 },
28483 - { 0x0000812c, 0x00000000 },
28484 - { 0x00008130, 0x00000000 },
28485 - { 0x00008134, 0x00000000 },
28486 - { 0x00008138, 0x00000000 },
28487 - { 0x0000813c, 0x00000000 },
28488 - { 0x00008144, 0xffffffff },
28489 - { 0x00008168, 0x00000000 },
28490 - { 0x0000816c, 0x00000000 },
28491 - { 0x00008170, 0x32143320 },
28492 - { 0x00008174, 0xfaa4fa50 },
28493 - { 0x00008178, 0x00000100 },
28494 - { 0x0000817c, 0x00000000 },
28495 - { 0x000081c4, 0x00000000 },
28496 - { 0x000081d0, 0x00003210 },
28497 - { 0x000081ec, 0x00000000 },
28498 - { 0x000081f0, 0x00000000 },
28499 - { 0x000081f4, 0x00000000 },
28500 - { 0x000081f8, 0x00000000 },
28501 - { 0x000081fc, 0x00000000 },
28502 - { 0x00008200, 0x00000000 },
28503 - { 0x00008204, 0x00000000 },
28504 - { 0x00008208, 0x00000000 },
28505 - { 0x0000820c, 0x00000000 },
28506 - { 0x00008210, 0x00000000 },
28507 - { 0x00008214, 0x00000000 },
28508 - { 0x00008218, 0x00000000 },
28509 - { 0x0000821c, 0x00000000 },
28510 - { 0x00008220, 0x00000000 },
28511 - { 0x00008224, 0x00000000 },
28512 - { 0x00008228, 0x00000000 },
28513 - { 0x0000822c, 0x00000000 },
28514 - { 0x00008230, 0x00000000 },
28515 - { 0x00008234, 0x00000000 },
28516 - { 0x00008238, 0x00000000 },
28517 - { 0x0000823c, 0x00000000 },
28518 - { 0x00008240, 0x00100000 },
28519 - { 0x00008244, 0x0010f400 },
28520 - { 0x00008248, 0x00000100 },
28521 - { 0x0000824c, 0x0001e800 },
28522 - { 0x00008250, 0x00000000 },
28523 - { 0x00008254, 0x00000000 },
28524 - { 0x00008258, 0x00000000 },
28525 - { 0x0000825c, 0x400000ff },
28526 - { 0x00008260, 0x00080922 },
28527 - { 0x00008270, 0x00000000 },
28528 - { 0x00008274, 0x40000000 },
28529 - { 0x00008278, 0x003e4180 },
28530 - { 0x0000827c, 0x00000000 },
28531 - { 0x00008284, 0x0000002c },
28532 - { 0x00008288, 0x0000002c },
28533 - { 0x0000828c, 0x00000000 },
28534 - { 0x00008294, 0x00000000 },
28535 - { 0x00008298, 0x00000000 },
28536 - { 0x00008300, 0x00000000 },
28537 - { 0x00008304, 0x00000000 },
28538 - { 0x00008308, 0x00000000 },
28539 - { 0x0000830c, 0x00000000 },
28540 - { 0x00008310, 0x00000000 },
28541 - { 0x00008314, 0x00000000 },
28542 - { 0x00008318, 0x00000000 },
28543 - { 0x00008328, 0x00000000 },
28544 - { 0x0000832c, 0x00000007 },
28545 - { 0x00008330, 0x00000302 },
28546 - { 0x00008334, 0x00000e00 },
28547 - { 0x00008338, 0x00ff0000 },
28548 - { 0x0000833c, 0x00000000 },
28549 - { 0x00008340, 0x000107ff },
28550 - { 0x00009808, 0x00000000 },
28551 - { 0x0000980c, 0xad848e19 },
28552 - { 0x00009810, 0x7d14e000 },
28553 - { 0x00009814, 0x9c0a9f6b },
28554 - { 0x0000981c, 0x00000000 },
28555 - { 0x0000982c, 0x0000a000 },
28556 - { 0x00009830, 0x00000000 },
28557 - { 0x0000983c, 0x00200400 },
28558 - { 0x00009840, 0x206a01ae },
28559 - { 0x0000984c, 0x1284233c },
28560 - { 0x00009854, 0x00000859 },
28561 - { 0x00009900, 0x00000000 },
28562 - { 0x00009904, 0x00000000 },
28563 - { 0x00009908, 0x00000000 },
28564 - { 0x0000990c, 0x00000000 },
28565 - { 0x0000991c, 0x10000fff },
28566 - { 0x00009920, 0x05100000 },
28567 - { 0x0000a920, 0x05100000 },
28568 - { 0x0000b920, 0x05100000 },
28569 - { 0x00009928, 0x00000001 },
28570 - { 0x0000992c, 0x00000004 },
28571 - { 0x00009934, 0x1e1f2022 },
28572 - { 0x00009938, 0x0a0b0c0d },
28573 - { 0x0000993c, 0x00000000 },
28574 - { 0x00009948, 0x9280b212 },
28575 - { 0x0000994c, 0x00020028 },
28576 - { 0x00009954, 0x5f3ca3de },
28577 - { 0x00009958, 0x2108ecff },
28578 - { 0x00009940, 0x00750604 },
28579 - { 0x0000c95c, 0x004b6a8e },
28580 - { 0x00009970, 0x190fb515 },
28581 - { 0x00009974, 0x00000000 },
28582 - { 0x00009978, 0x00000001 },
28583 - { 0x0000997c, 0x00000000 },
28584 - { 0x00009980, 0x00000000 },
28585 - { 0x00009984, 0x00000000 },
28586 - { 0x00009988, 0x00000000 },
28587 - { 0x0000998c, 0x00000000 },
28588 - { 0x00009990, 0x00000000 },
28589 - { 0x00009994, 0x00000000 },
28590 - { 0x00009998, 0x00000000 },
28591 - { 0x0000999c, 0x00000000 },
28592 - { 0x000099a0, 0x00000000 },
28593 - { 0x000099a4, 0x00000001 },
28594 - { 0x000099a8, 0x201fff00 },
28595 - { 0x000099ac, 0x006f0000 },
28596 - { 0x000099b0, 0x03051000 },
28597 - { 0x000099dc, 0x00000000 },
28598 - { 0x000099e0, 0x00000200 },
28599 - { 0x000099e4, 0xaaaaaaaa },
28600 - { 0x000099e8, 0x3c466478 },
28601 - { 0x000099ec, 0x0cc80caa },
28602 - { 0x000099fc, 0x00001042 },
28603 - { 0x00009b00, 0x00000000 },
28604 - { 0x00009b04, 0x00000001 },
28605 - { 0x00009b08, 0x00000002 },
28606 - { 0x00009b0c, 0x00000003 },
28607 - { 0x00009b10, 0x00000004 },
28608 - { 0x00009b14, 0x00000005 },
28609 - { 0x00009b18, 0x00000008 },
28610 - { 0x00009b1c, 0x00000009 },
28611 - { 0x00009b20, 0x0000000a },
28612 - { 0x00009b24, 0x0000000b },
28613 - { 0x00009b28, 0x0000000c },
28614 - { 0x00009b2c, 0x0000000d },
28615 - { 0x00009b30, 0x00000010 },
28616 - { 0x00009b34, 0x00000011 },
28617 - { 0x00009b38, 0x00000012 },
28618 - { 0x00009b3c, 0x00000013 },
28619 - { 0x00009b40, 0x00000014 },
28620 - { 0x00009b44, 0x00000015 },
28621 - { 0x00009b48, 0x00000018 },
28622 - { 0x00009b4c, 0x00000019 },
28623 - { 0x00009b50, 0x0000001a },
28624 - { 0x00009b54, 0x0000001b },
28625 - { 0x00009b58, 0x0000001c },
28626 - { 0x00009b5c, 0x0000001d },
28627 - { 0x00009b60, 0x00000020 },
28628 - { 0x00009b64, 0x00000021 },
28629 - { 0x00009b68, 0x00000022 },
28630 - { 0x00009b6c, 0x00000023 },
28631 - { 0x00009b70, 0x00000024 },
28632 - { 0x00009b74, 0x00000025 },
28633 - { 0x00009b78, 0x00000028 },
28634 - { 0x00009b7c, 0x00000029 },
28635 - { 0x00009b80, 0x0000002a },
28636 - { 0x00009b84, 0x0000002b },
28637 - { 0x00009b88, 0x0000002c },
28638 - { 0x00009b8c, 0x0000002d },
28639 - { 0x00009b90, 0x00000030 },
28640 - { 0x00009b94, 0x00000031 },
28641 - { 0x00009b98, 0x00000032 },
28642 - { 0x00009b9c, 0x00000033 },
28643 - { 0x00009ba0, 0x00000034 },
28644 - { 0x00009ba4, 0x00000035 },
28645 - { 0x00009ba8, 0x00000035 },
28646 - { 0x00009bac, 0x00000035 },
28647 - { 0x00009bb0, 0x00000035 },
28648 - { 0x00009bb4, 0x00000035 },
28649 - { 0x00009bb8, 0x00000035 },
28650 - { 0x00009bbc, 0x00000035 },
28651 - { 0x00009bc0, 0x00000035 },
28652 - { 0x00009bc4, 0x00000035 },
28653 - { 0x00009bc8, 0x00000035 },
28654 - { 0x00009bcc, 0x00000035 },
28655 - { 0x00009bd0, 0x00000035 },
28656 - { 0x00009bd4, 0x00000035 },
28657 - { 0x00009bd8, 0x00000035 },
28658 - { 0x00009bdc, 0x00000035 },
28659 - { 0x00009be0, 0x00000035 },
28660 - { 0x00009be4, 0x00000035 },
28661 - { 0x00009be8, 0x00000035 },
28662 - { 0x00009bec, 0x00000035 },
28663 - { 0x00009bf0, 0x00000035 },
28664 - { 0x00009bf4, 0x00000035 },
28665 - { 0x00009bf8, 0x00000010 },
28666 - { 0x00009bfc, 0x0000001a },
28667 - { 0x0000a210, 0x40806333 },
28668 - { 0x0000a214, 0x00106c10 },
28669 - { 0x0000a218, 0x009c4060 },
28670 - { 0x0000a220, 0x018830c6 },
28671 - { 0x0000a224, 0x00000400 },
28672 - { 0x0000a228, 0x001a0bb5 },
28673 - { 0x0000a22c, 0x00000000 },
28674 - { 0x0000a234, 0x20202020 },
28675 - { 0x0000a238, 0x20202020 },
28676 - { 0x0000a23c, 0x13c889af },
28677 - { 0x0000a240, 0x38490a20 },
28678 - { 0x0000a244, 0x00007bb6 },
28679 - { 0x0000a248, 0x0fff3ffc },
28680 - { 0x0000a24c, 0x00000001 },
28681 - { 0x0000a250, 0x0000e000 },
28682 - { 0x0000a254, 0x00000000 },
28683 - { 0x0000a258, 0x0cc75380 },
28684 - { 0x0000a25c, 0x0f0f0f01 },
28685 - { 0x0000a260, 0xdfa91f01 },
28686 - { 0x0000a268, 0x00000001 },
28687 - { 0x0000a26c, 0x0ebae9c6 },
28688 - { 0x0000b26c, 0x0ebae9c6 },
28689 - { 0x0000c26c, 0x0ebae9c6 },
28690 - { 0x0000d270, 0x00820820 },
28691 - { 0x0000a278, 0x1ce739ce },
28692 - { 0x0000a27c, 0x050701ce },
28693 - { 0x0000a338, 0x00000000 },
28694 - { 0x0000a33c, 0x00000000 },
28695 - { 0x0000a340, 0x00000000 },
28696 - { 0x0000a344, 0x00000000 },
28697 - { 0x0000a348, 0x3fffffff },
28698 - { 0x0000a34c, 0x3fffffff },
28699 - { 0x0000a350, 0x3fffffff },
28700 - { 0x0000a354, 0x0003ffff },
28701 - { 0x0000a358, 0x79bfaa03 },
28702 - { 0x0000d35c, 0x07ffffef },
28703 - { 0x0000d360, 0x0fffffe7 },
28704 - { 0x0000d364, 0x17ffffe5 },
28705 - { 0x0000d368, 0x1fffffe4 },
28706 - { 0x0000d36c, 0x37ffffe3 },
28707 - { 0x0000d370, 0x3fffffe3 },
28708 - { 0x0000d374, 0x57ffffe3 },
28709 - { 0x0000d378, 0x5fffffe2 },
28710 - { 0x0000d37c, 0x7fffffe2 },
28711 - { 0x0000d380, 0x7f3c7bba },
28712 - { 0x0000d384, 0xf3307ff0 },
28713 - { 0x0000a388, 0x0c000000 },
28714 - { 0x0000a38c, 0x20202020 },
28715 - { 0x0000a390, 0x20202020 },
28716 - { 0x0000a394, 0x1ce739ce },
28717 - { 0x0000a398, 0x000001ce },
28718 - { 0x0000a39c, 0x00000001 },
28719 - { 0x0000a3a0, 0x00000000 },
28720 - { 0x0000a3a4, 0x00000000 },
28721 - { 0x0000a3a8, 0x00000000 },
28722 - { 0x0000a3ac, 0x00000000 },
28723 - { 0x0000a3b0, 0x00000000 },
28724 - { 0x0000a3b4, 0x00000000 },
28725 - { 0x0000a3b8, 0x00000000 },
28726 - { 0x0000a3bc, 0x00000000 },
28727 - { 0x0000a3c0, 0x00000000 },
28728 - { 0x0000a3c4, 0x00000000 },
28729 - { 0x0000a3c8, 0x00000246 },
28730 - { 0x0000a3cc, 0x20202020 },
28731 - { 0x0000a3d0, 0x20202020 },
28732 - { 0x0000a3d4, 0x20202020 },
28733 - { 0x0000a3dc, 0x1ce739ce },
28734 - { 0x0000a3e0, 0x000001ce },
28735 -};
28736 -
28737 -static const u32 ar5416Bank0_9160[][2] = {
28738 - { 0x000098b0, 0x1e5795e5 },
28739 - { 0x000098e0, 0x02008020 },
28740 -};
28741 -
28742 -static const u32 ar5416BB_RfGain_9160[][3] = {
28743 - { 0x00009a00, 0x00000000, 0x00000000 },
28744 - { 0x00009a04, 0x00000040, 0x00000040 },
28745 - { 0x00009a08, 0x00000080, 0x00000080 },
28746 - { 0x00009a0c, 0x000001a1, 0x00000141 },
28747 - { 0x00009a10, 0x000001e1, 0x00000181 },
28748 - { 0x00009a14, 0x00000021, 0x000001c1 },
28749 - { 0x00009a18, 0x00000061, 0x00000001 },
28750 - { 0x00009a1c, 0x00000168, 0x00000041 },
28751 - { 0x00009a20, 0x000001a8, 0x000001a8 },
28752 - { 0x00009a24, 0x000001e8, 0x000001e8 },
28753 - { 0x00009a28, 0x00000028, 0x00000028 },
28754 - { 0x00009a2c, 0x00000068, 0x00000068 },
28755 - { 0x00009a30, 0x00000189, 0x000000a8 },
28756 - { 0x00009a34, 0x000001c9, 0x00000169 },
28757 - { 0x00009a38, 0x00000009, 0x000001a9 },
28758 - { 0x00009a3c, 0x00000049, 0x000001e9 },
28759 - { 0x00009a40, 0x00000089, 0x00000029 },
28760 - { 0x00009a44, 0x00000170, 0x00000069 },
28761 - { 0x00009a48, 0x000001b0, 0x00000190 },
28762 - { 0x00009a4c, 0x000001f0, 0x000001d0 },
28763 - { 0x00009a50, 0x00000030, 0x00000010 },
28764 - { 0x00009a54, 0x00000070, 0x00000050 },
28765 - { 0x00009a58, 0x00000191, 0x00000090 },
28766 - { 0x00009a5c, 0x000001d1, 0x00000151 },
28767 - { 0x00009a60, 0x00000011, 0x00000191 },
28768 - { 0x00009a64, 0x00000051, 0x000001d1 },
28769 - { 0x00009a68, 0x00000091, 0x00000011 },
28770 - { 0x00009a6c, 0x000001b8, 0x00000051 },
28771 - { 0x00009a70, 0x000001f8, 0x00000198 },
28772 - { 0x00009a74, 0x00000038, 0x000001d8 },
28773 - { 0x00009a78, 0x00000078, 0x00000018 },
28774 - { 0x00009a7c, 0x00000199, 0x00000058 },
28775 - { 0x00009a80, 0x000001d9, 0x00000098 },
28776 - { 0x00009a84, 0x00000019, 0x00000159 },
28777 - { 0x00009a88, 0x00000059, 0x00000199 },
28778 - { 0x00009a8c, 0x00000099, 0x000001d9 },
28779 - { 0x00009a90, 0x000000d9, 0x00000019 },
28780 - { 0x00009a94, 0x000000f9, 0x00000059 },
28781 - { 0x00009a98, 0x000000f9, 0x00000099 },
28782 - { 0x00009a9c, 0x000000f9, 0x000000d9 },
28783 - { 0x00009aa0, 0x000000f9, 0x000000f9 },
28784 - { 0x00009aa4, 0x000000f9, 0x000000f9 },
28785 - { 0x00009aa8, 0x000000f9, 0x000000f9 },
28786 - { 0x00009aac, 0x000000f9, 0x000000f9 },
28787 - { 0x00009ab0, 0x000000f9, 0x000000f9 },
28788 - { 0x00009ab4, 0x000000f9, 0x000000f9 },
28789 - { 0x00009ab8, 0x000000f9, 0x000000f9 },
28790 - { 0x00009abc, 0x000000f9, 0x000000f9 },
28791 - { 0x00009ac0, 0x000000f9, 0x000000f9 },
28792 - { 0x00009ac4, 0x000000f9, 0x000000f9 },
28793 - { 0x00009ac8, 0x000000f9, 0x000000f9 },
28794 - { 0x00009acc, 0x000000f9, 0x000000f9 },
28795 - { 0x00009ad0, 0x000000f9, 0x000000f9 },
28796 - { 0x00009ad4, 0x000000f9, 0x000000f9 },
28797 - { 0x00009ad8, 0x000000f9, 0x000000f9 },
28798 - { 0x00009adc, 0x000000f9, 0x000000f9 },
28799 - { 0x00009ae0, 0x000000f9, 0x000000f9 },
28800 - { 0x00009ae4, 0x000000f9, 0x000000f9 },
28801 - { 0x00009ae8, 0x000000f9, 0x000000f9 },
28802 - { 0x00009aec, 0x000000f9, 0x000000f9 },
28803 - { 0x00009af0, 0x000000f9, 0x000000f9 },
28804 - { 0x00009af4, 0x000000f9, 0x000000f9 },
28805 - { 0x00009af8, 0x000000f9, 0x000000f9 },
28806 - { 0x00009afc, 0x000000f9, 0x000000f9 },
28807 -};
28808 -
28809 -static const u32 ar5416Bank1_9160[][2] = {
28810 - { 0x000098b0, 0x02108421 },
28811 - { 0x000098ec, 0x00000008 },
28812 -};
28813 -
28814 -static const u32 ar5416Bank2_9160[][2] = {
28815 - { 0x000098b0, 0x0e73ff17 },
28816 - { 0x000098e0, 0x00000420 },
28817 -};
28818 -
28819 -static const u32 ar5416Bank3_9160[][3] = {
28820 - { 0x000098f0, 0x01400018, 0x01c00018 },
28821 -};
28822 -
28823 -static const u32 ar5416Bank6_9160[][3] = {
28824 - { 0x0000989c, 0x00000000, 0x00000000 },
28825 - { 0x0000989c, 0x00000000, 0x00000000 },
28826 - { 0x0000989c, 0x00000000, 0x00000000 },
28827 - { 0x0000989c, 0x00e00000, 0x00e00000 },
28828 - { 0x0000989c, 0x005e0000, 0x005e0000 },
28829 - { 0x0000989c, 0x00120000, 0x00120000 },
28830 - { 0x0000989c, 0x00620000, 0x00620000 },
28831 - { 0x0000989c, 0x00020000, 0x00020000 },
28832 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28833 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28834 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28835 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
28836 - { 0x0000989c, 0x005f0000, 0x005f0000 },
28837 - { 0x0000989c, 0x00870000, 0x00870000 },
28838 - { 0x0000989c, 0x00f90000, 0x00f90000 },
28839 - { 0x0000989c, 0x007b0000, 0x007b0000 },
28840 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28841 - { 0x0000989c, 0x00f50000, 0x00f50000 },
28842 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
28843 - { 0x0000989c, 0x00110000, 0x00110000 },
28844 - { 0x0000989c, 0x006100a8, 0x006100a8 },
28845 - { 0x0000989c, 0x004210a2, 0x004210a2 },
28846 - { 0x0000989c, 0x0014008f, 0x0014008f },
28847 - { 0x0000989c, 0x00c40003, 0x00c40003 },
28848 - { 0x0000989c, 0x003000f2, 0x003000f2 },
28849 - { 0x0000989c, 0x00440016, 0x00440016 },
28850 - { 0x0000989c, 0x00410040, 0x00410040 },
28851 - { 0x0000989c, 0x0001805e, 0x0001805e },
28852 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
28853 - { 0x0000989c, 0x000000f1, 0x000000f1 },
28854 - { 0x0000989c, 0x00002081, 0x00002081 },
28855 - { 0x0000989c, 0x000000d4, 0x000000d4 },
28856 - { 0x000098d0, 0x0000000f, 0x0010000f },
28857 -};
28858 -
28859 -static const u32 ar5416Bank6TPC_9160[][3] = {
28860 - { 0x0000989c, 0x00000000, 0x00000000 },
28861 - { 0x0000989c, 0x00000000, 0x00000000 },
28862 - { 0x0000989c, 0x00000000, 0x00000000 },
28863 - { 0x0000989c, 0x00e00000, 0x00e00000 },
28864 - { 0x0000989c, 0x005e0000, 0x005e0000 },
28865 - { 0x0000989c, 0x00120000, 0x00120000 },
28866 - { 0x0000989c, 0x00620000, 0x00620000 },
28867 - { 0x0000989c, 0x00020000, 0x00020000 },
28868 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28869 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28870 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28871 - { 0x0000989c, 0x40ff0000, 0x40ff0000 },
28872 - { 0x0000989c, 0x005f0000, 0x005f0000 },
28873 - { 0x0000989c, 0x00870000, 0x00870000 },
28874 - { 0x0000989c, 0x00f90000, 0x00f90000 },
28875 - { 0x0000989c, 0x007b0000, 0x007b0000 },
28876 - { 0x0000989c, 0x00ff0000, 0x00ff0000 },
28877 - { 0x0000989c, 0x00f50000, 0x00f50000 },
28878 - { 0x0000989c, 0x00dc0000, 0x00dc0000 },
28879 - { 0x0000989c, 0x00110000, 0x00110000 },
28880 - { 0x0000989c, 0x006100a8, 0x006100a8 },
28881 - { 0x0000989c, 0x00423022, 0x00423022 },
28882 - { 0x0000989c, 0x2014008f, 0x2014008f },
28883 - { 0x0000989c, 0x00c40002, 0x00c40002 },
28884 - { 0x0000989c, 0x003000f2, 0x003000f2 },
28885 - { 0x0000989c, 0x00440016, 0x00440016 },
28886 - { 0x0000989c, 0x00410040, 0x00410040 },
28887 - { 0x0000989c, 0x0001805e, 0x0001805e },
28888 - { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
28889 - { 0x0000989c, 0x000000e1, 0x000000e1 },
28890 - { 0x0000989c, 0x00007080, 0x00007080 },
28891 - { 0x0000989c, 0x000000d4, 0x000000d4 },
28892 - { 0x000098d0, 0x0000000f, 0x0010000f },
28893 -};
28894 -
28895 -static const u32 ar5416Bank7_9160[][2] = {
28896 - { 0x0000989c, 0x00000500 },
28897 - { 0x0000989c, 0x00000800 },
28898 - { 0x000098cc, 0x0000000e },
28899 -};
28900 -
28901 -static u32 ar5416Addac_9160[][2] = {
28902 - {0x0000989c, 0x00000000 },
28903 - {0x0000989c, 0x00000000 },
28904 - {0x0000989c, 0x00000000 },
28905 - {0x0000989c, 0x00000000 },
28906 - {0x0000989c, 0x00000000 },
28907 - {0x0000989c, 0x00000000 },
28908 - {0x0000989c, 0x000000c0 },
28909 - {0x0000989c, 0x00000018 },
28910 - {0x0000989c, 0x00000004 },
28911 - {0x0000989c, 0x00000000 },
28912 - {0x0000989c, 0x00000000 },
28913 - {0x0000989c, 0x00000000 },
28914 - {0x0000989c, 0x00000000 },
28915 - {0x0000989c, 0x00000000 },
28916 - {0x0000989c, 0x00000000 },
28917 - {0x0000989c, 0x00000000 },
28918 - {0x0000989c, 0x00000000 },
28919 - {0x0000989c, 0x00000000 },
28920 - {0x0000989c, 0x00000000 },
28921 - {0x0000989c, 0x00000000 },
28922 - {0x0000989c, 0x00000000 },
28923 - {0x0000989c, 0x000000c0 },
28924 - {0x0000989c, 0x00000019 },
28925 - {0x0000989c, 0x00000004 },
28926 - {0x0000989c, 0x00000000 },
28927 - {0x0000989c, 0x00000000 },
28928 - {0x0000989c, 0x00000000 },
28929 - {0x0000989c, 0x00000004 },
28930 - {0x0000989c, 0x00000003 },
28931 - {0x0000989c, 0x00000008 },
28932 - {0x0000989c, 0x00000000 },
28933 - {0x000098cc, 0x00000000 },
28934 -};
28935 -
28936 -static u32 ar5416Addac_91601_1[][2] = {
28937 - {0x0000989c, 0x00000000 },
28938 - {0x0000989c, 0x00000000 },
28939 - {0x0000989c, 0x00000000 },
28940 - {0x0000989c, 0x00000000 },
28941 - {0x0000989c, 0x00000000 },
28942 - {0x0000989c, 0x00000000 },
28943 - {0x0000989c, 0x000000c0 },
28944 - {0x0000989c, 0x00000018 },
28945 - {0x0000989c, 0x00000004 },
28946 - {0x0000989c, 0x00000000 },
28947 - {0x0000989c, 0x00000000 },
28948 - {0x0000989c, 0x00000000 },
28949 - {0x0000989c, 0x00000000 },
28950 - {0x0000989c, 0x00000000 },
28951 - {0x0000989c, 0x00000000 },
28952 - {0x0000989c, 0x00000000 },
28953 - {0x0000989c, 0x00000000 },
28954 - {0x0000989c, 0x00000000 },
28955 - {0x0000989c, 0x00000000 },
28956 - {0x0000989c, 0x00000000 },
28957 - {0x0000989c, 0x00000000 },
28958 - {0x0000989c, 0x000000c0 },
28959 - {0x0000989c, 0x00000019 },
28960 - {0x0000989c, 0x00000004 },
28961 - {0x0000989c, 0x00000000 },
28962 - {0x0000989c, 0x00000000 },
28963 - {0x0000989c, 0x00000000 },
28964 - {0x0000989c, 0x00000000 },
28965 - {0x0000989c, 0x00000000 },
28966 - {0x0000989c, 0x00000000 },
28967 - {0x0000989c, 0x00000000 },
28968 - {0x000098cc, 0x00000000 },
28969 -};
28970 -
28971 -/* XXX 9280 1 */
28972 -static const u32 ar9280Modes_9280[][6] = {
28973 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
28974 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
28975 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
28976 - { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
28977 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801080, 0x08400840, 0x06e006e0 },
28978 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
28979 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
28980 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
28981 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
28982 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
28983 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
28984 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
28985 - { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
28986 - { 0x00009848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
28987 - { 0x0000a848, 0x00028566, 0x00028566, 0x00028563, 0x00028563, 0x00028563 },
28988 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
28989 - { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
28990 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
28991 - { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d20, 0x00049d20, 0x00049d18 },
28992 - { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
28993 - { 0x00009868, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190, 0x5ac64190 },
28994 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
28995 - { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
28996 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
28997 - { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
28998 - { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010, 0xdfbc1010 },
28999 - { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
29000 - { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
29001 - { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
29002 - { 0x0000c9b8, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a },
29003 - { 0x0000c9bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
29004 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
29005 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
29006 - { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c },
29007 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
29008 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
29009 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29010 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29011 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000214, 0x00000214, 0x00000214 },
29012 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000218, 0x00000218, 0x00000218 },
29013 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000224, 0x00000224, 0x00000224 },
29014 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000228, 0x00000228, 0x00000228 },
29015 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000022c, 0x0000022c, 0x0000022c },
29016 - { 0x00009a14, 0x00008200, 0x00008200, 0x00000230, 0x00000230, 0x00000230 },
29017 - { 0x00009a18, 0x00008204, 0x00008204, 0x000002a4, 0x000002a4, 0x000002a4 },
29018 - { 0x00009a1c, 0x00008208, 0x00008208, 0x000002a8, 0x000002a8, 0x000002a8 },
29019 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x000002ac, 0x000002ac, 0x000002ac },
29020 - { 0x00009a24, 0x00008210, 0x00008210, 0x000002b0, 0x000002b0, 0x000002b0 },
29021 - { 0x00009a28, 0x00008214, 0x00008214, 0x000002b4, 0x000002b4, 0x000002b4 },
29022 - { 0x00009a2c, 0x00008280, 0x00008280, 0x000002b8, 0x000002b8, 0x000002b8 },
29023 - { 0x00009a30, 0x00008284, 0x00008284, 0x00000390, 0x00000390, 0x00000390 },
29024 - { 0x00009a34, 0x00008288, 0x00008288, 0x00000394, 0x00000394, 0x00000394 },
29025 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00000398, 0x00000398, 0x00000398 },
29026 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00000334, 0x00000334, 0x00000334 },
29027 - { 0x00009a40, 0x00008300, 0x00008300, 0x00000338, 0x00000338, 0x00000338 },
29028 - { 0x00009a44, 0x00008304, 0x00008304, 0x000003ac, 0x000003ac, 0x000003ac },
29029 - { 0x00009a48, 0x00008308, 0x00008308, 0x000003b0, 0x000003b0, 0x000003b0 },
29030 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x000003b4, 0x000003b4, 0x000003b4 },
29031 - { 0x00009a50, 0x00008310, 0x00008310, 0x000003b8, 0x000003b8, 0x000003b8 },
29032 - { 0x00009a54, 0x00008314, 0x00008314, 0x000003a5, 0x000003a5, 0x000003a5 },
29033 - { 0x00009a58, 0x00008380, 0x00008380, 0x000003a9, 0x000003a9, 0x000003a9 },
29034 - { 0x00009a5c, 0x00008384, 0x00008384, 0x000003ad, 0x000003ad, 0x000003ad },
29035 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
29036 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
29037 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
29038 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
29039 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
29040 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
29041 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
29042 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
29043 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
29044 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
29045 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
29046 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
29047 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
29048 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
29049 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
29050 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
29051 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
29052 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
29053 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
29054 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
29055 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
29056 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
29057 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
29058 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
29059 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
29060 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
29061 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
29062 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
29063 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
29064 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
29065 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
29066 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
29067 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
29068 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
29069 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
29070 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
29071 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
29072 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
29073 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
29074 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
29075 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
29076 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
29077 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
29078 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
29079 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
29080 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
29081 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
29082 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
29083 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
29084 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
29085 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
29086 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
29087 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
29088 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
29089 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
29090 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
29091 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
29092 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
29093 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
29094 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
29095 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
29096 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
29097 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
29098 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
29099 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
29100 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
29101 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
29102 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
29103 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
29104 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
29105 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
29106 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
29107 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
29108 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
29109 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
29110 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
29111 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
29112 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
29113 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29114 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29115 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29116 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29117 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29118 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29119 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29120 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29121 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29122 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29123 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29124 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29125 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29126 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29127 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29128 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29129 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29130 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29131 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29132 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29133 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29134 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29135 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29136 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29137 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29138 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
29139 - { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
29140 - { 0x0000a208, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788, 0x803e4788 },
29141 - { 0x0000a20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
29142 - { 0x0000b20c, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019, 0x000c6019 },
29143 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
29144 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
29145 - { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
29146 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29147 - { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
29148 - { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
29149 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
29150 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
29151 - { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
29152 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
29153 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
29154 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
29155 - { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
29156 - { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
29157 - { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
29158 - { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
29159 - { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
29160 - { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
29161 - { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
29162 - { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
29163 - { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
29164 - { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
29165 - { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
29166 - { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
29167 - { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
29168 - { 0x0000784c, 0x0e4f048c, 0x0e4f048c, 0x0e4d048c, 0x0e4d048c, 0x0e4d048c },
29169 - { 0x00007854, 0x12031828, 0x12031828, 0x12035828, 0x12035828, 0x12035828 },
29170 - { 0x00007870, 0x807ec400, 0x807ec400, 0x807ec000, 0x807ec000, 0x807ec000 },
29171 - { 0x0000788c, 0x00010000, 0x00010000, 0x00110000, 0x00110000, 0x00110000 },
29172 -};
29173 -
29174 -static const u32 ar9280Common_9280[][2] = {
29175 - { 0x0000000c, 0x00000000 },
29176 - { 0x00000030, 0x00020015 },
29177 - { 0x00000034, 0x00000005 },
29178 - { 0x00000040, 0x00000000 },
29179 - { 0x00000044, 0x00000008 },
29180 - { 0x00000048, 0x00000008 },
29181 - { 0x0000004c, 0x00000010 },
29182 - { 0x00000050, 0x00000000 },
29183 - { 0x00000054, 0x0000001f },
29184 - { 0x00000800, 0x00000000 },
29185 - { 0x00000804, 0x00000000 },
29186 - { 0x00000808, 0x00000000 },
29187 - { 0x0000080c, 0x00000000 },
29188 - { 0x00000810, 0x00000000 },
29189 - { 0x00000814, 0x00000000 },
29190 - { 0x00000818, 0x00000000 },
29191 - { 0x0000081c, 0x00000000 },
29192 - { 0x00000820, 0x00000000 },
29193 - { 0x00000824, 0x00000000 },
29194 - { 0x00001040, 0x002ffc0f },
29195 - { 0x00001044, 0x002ffc0f },
29196 - { 0x00001048, 0x002ffc0f },
29197 - { 0x0000104c, 0x002ffc0f },
29198 - { 0x00001050, 0x002ffc0f },
29199 - { 0x00001054, 0x002ffc0f },
29200 - { 0x00001058, 0x002ffc0f },
29201 - { 0x0000105c, 0x002ffc0f },
29202 - { 0x00001060, 0x002ffc0f },
29203 - { 0x00001064, 0x002ffc0f },
29204 - { 0x00001230, 0x00000000 },
29205 - { 0x00001270, 0x00000000 },
29206 - { 0x00001038, 0x00000000 },
29207 - { 0x00001078, 0x00000000 },
29208 - { 0x000010b8, 0x00000000 },
29209 - { 0x000010f8, 0x00000000 },
29210 - { 0x00001138, 0x00000000 },
29211 - { 0x00001178, 0x00000000 },
29212 - { 0x000011b8, 0x00000000 },
29213 - { 0x000011f8, 0x00000000 },
29214 - { 0x00001238, 0x00000000 },
29215 - { 0x00001278, 0x00000000 },
29216 - { 0x000012b8, 0x00000000 },
29217 - { 0x000012f8, 0x00000000 },
29218 - { 0x00001338, 0x00000000 },
29219 - { 0x00001378, 0x00000000 },
29220 - { 0x000013b8, 0x00000000 },
29221 - { 0x000013f8, 0x00000000 },
29222 - { 0x00001438, 0x00000000 },
29223 - { 0x00001478, 0x00000000 },
29224 - { 0x000014b8, 0x00000000 },
29225 - { 0x000014f8, 0x00000000 },
29226 - { 0x00001538, 0x00000000 },
29227 - { 0x00001578, 0x00000000 },
29228 - { 0x000015b8, 0x00000000 },
29229 - { 0x000015f8, 0x00000000 },
29230 - { 0x00001638, 0x00000000 },
29231 - { 0x00001678, 0x00000000 },
29232 - { 0x000016b8, 0x00000000 },
29233 - { 0x000016f8, 0x00000000 },
29234 - { 0x00001738, 0x00000000 },
29235 - { 0x00001778, 0x00000000 },
29236 - { 0x000017b8, 0x00000000 },
29237 - { 0x000017f8, 0x00000000 },
29238 - { 0x0000103c, 0x00000000 },
29239 - { 0x0000107c, 0x00000000 },
29240 - { 0x000010bc, 0x00000000 },
29241 - { 0x000010fc, 0x00000000 },
29242 - { 0x0000113c, 0x00000000 },
29243 - { 0x0000117c, 0x00000000 },
29244 - { 0x000011bc, 0x00000000 },
29245 - { 0x000011fc, 0x00000000 },
29246 - { 0x0000123c, 0x00000000 },
29247 - { 0x0000127c, 0x00000000 },
29248 - { 0x000012bc, 0x00000000 },
29249 - { 0x000012fc, 0x00000000 },
29250 - { 0x0000133c, 0x00000000 },
29251 - { 0x0000137c, 0x00000000 },
29252 - { 0x000013bc, 0x00000000 },
29253 - { 0x000013fc, 0x00000000 },
29254 - { 0x0000143c, 0x00000000 },
29255 - { 0x0000147c, 0x00000000 },
29256 - { 0x00004030, 0x00000002 },
29257 - { 0x0000403c, 0x00000002 },
29258 - { 0x00004024, 0x0000001f },
29259 - { 0x00007010, 0x00000033 },
29260 - { 0x00007038, 0x000004c2 },
29261 - { 0x00008004, 0x00000000 },
29262 - { 0x00008008, 0x00000000 },
29263 - { 0x0000800c, 0x00000000 },
29264 - { 0x00008018, 0x00000700 },
29265 - { 0x00008020, 0x00000000 },
29266 - { 0x00008038, 0x00000000 },
29267 - { 0x0000803c, 0x00000000 },
29268 - { 0x00008048, 0x40000000 },
29269 - { 0x00008054, 0x00000000 },
29270 - { 0x00008058, 0x00000000 },
29271 - { 0x0000805c, 0x000fc78f },
29272 - { 0x00008060, 0x0000000f },
29273 - { 0x00008064, 0x00000000 },
29274 - { 0x00008070, 0x00000000 },
29275 - { 0x000080c0, 0x2a82301a },
29276 - { 0x000080c4, 0x05dc01e0 },
29277 - { 0x000080c8, 0x1f402710 },
29278 - { 0x000080cc, 0x01f40000 },
29279 - { 0x000080d0, 0x00001e00 },
29280 - { 0x000080d4, 0x00000000 },
29281 - { 0x000080d8, 0x00400000 },
29282 - { 0x000080e0, 0xffffffff },
29283 - { 0x000080e4, 0x0000ffff },
29284 - { 0x000080e8, 0x003f3f3f },
29285 - { 0x000080ec, 0x00000000 },
29286 - { 0x000080f0, 0x00000000 },
29287 - { 0x000080f4, 0x00000000 },
29288 - { 0x000080f8, 0x00000000 },
29289 - { 0x000080fc, 0x00020000 },
29290 - { 0x00008100, 0x00020000 },
29291 - { 0x00008104, 0x00000001 },
29292 - { 0x00008108, 0x00000052 },
29293 - { 0x0000810c, 0x00000000 },
29294 - { 0x00008110, 0x00000168 },
29295 - { 0x00008118, 0x000100aa },
29296 - { 0x0000811c, 0x00003210 },
29297 - { 0x00008120, 0x08f04800 },
29298 - { 0x00008124, 0x00000000 },
29299 - { 0x00008128, 0x00000000 },
29300 - { 0x0000812c, 0x00000000 },
29301 - { 0x00008130, 0x00000000 },
29302 - { 0x00008134, 0x00000000 },
29303 - { 0x00008138, 0x00000000 },
29304 - { 0x0000813c, 0x00000000 },
29305 - { 0x00008144, 0x00000000 },
29306 - { 0x00008168, 0x00000000 },
29307 - { 0x0000816c, 0x00000000 },
29308 - { 0x00008170, 0x32143320 },
29309 - { 0x00008174, 0xfaa4fa50 },
29310 - { 0x00008178, 0x00000100 },
29311 - { 0x0000817c, 0x00000000 },
29312 - { 0x000081c4, 0x00000000 },
29313 - { 0x000081d0, 0x00003210 },
29314 - { 0x000081ec, 0x00000000 },
29315 - { 0x000081f0, 0x00000000 },
29316 - { 0x000081f4, 0x00000000 },
29317 - { 0x000081f8, 0x00000000 },
29318 - { 0x000081fc, 0x00000000 },
29319 - { 0x00008200, 0x00000000 },
29320 - { 0x00008204, 0x00000000 },
29321 - { 0x00008208, 0x00000000 },
29322 - { 0x0000820c, 0x00000000 },
29323 - { 0x00008210, 0x00000000 },
29324 - { 0x00008214, 0x00000000 },
29325 - { 0x00008218, 0x00000000 },
29326 - { 0x0000821c, 0x00000000 },
29327 - { 0x00008220, 0x00000000 },
29328 - { 0x00008224, 0x00000000 },
29329 - { 0x00008228, 0x00000000 },
29330 - { 0x0000822c, 0x00000000 },
29331 - { 0x00008230, 0x00000000 },
29332 - { 0x00008234, 0x00000000 },
29333 - { 0x00008238, 0x00000000 },
29334 - { 0x0000823c, 0x00000000 },
29335 - { 0x00008240, 0x00100000 },
29336 - { 0x00008244, 0x0010f400 },
29337 - { 0x00008248, 0x00000100 },
29338 - { 0x0000824c, 0x0001e800 },
29339 - { 0x00008250, 0x00000000 },
29340 - { 0x00008254, 0x00000000 },
29341 - { 0x00008258, 0x00000000 },
29342 - { 0x0000825c, 0x400000ff },
29343 - { 0x00008260, 0x00080922 },
29344 - { 0x00008270, 0x00000000 },
29345 - { 0x00008274, 0x40000000 },
29346 - { 0x00008278, 0x003e4180 },
29347 - { 0x0000827c, 0x00000000 },
29348 - { 0x00008284, 0x0000002c },
29349 - { 0x00008288, 0x0000002c },
29350 - { 0x0000828c, 0x00000000 },
29351 - { 0x00008294, 0x00000000 },
29352 - { 0x00008298, 0x00000000 },
29353 - { 0x00008300, 0x00000000 },
29354 - { 0x00008304, 0x00000000 },
29355 - { 0x00008308, 0x00000000 },
29356 - { 0x0000830c, 0x00000000 },
29357 - { 0x00008310, 0x00000000 },
29358 - { 0x00008314, 0x00000000 },
29359 - { 0x00008318, 0x00000000 },
29360 - { 0x00008328, 0x00000000 },
29361 - { 0x0000832c, 0x00000007 },
29362 - { 0x00008330, 0x00000302 },
29363 - { 0x00008334, 0x00000e00 },
29364 - { 0x00008338, 0x00000000 },
29365 - { 0x0000833c, 0x00000000 },
29366 - { 0x00008340, 0x000107ff },
29367 - { 0x00008344, 0x00000000 },
29368 - { 0x00009808, 0x00000000 },
29369 - { 0x0000980c, 0xaf268e30 },
29370 - { 0x00009810, 0xfd14e000 },
29371 - { 0x00009814, 0x9c0a9f6b },
29372 - { 0x0000981c, 0x00000000 },
29373 - { 0x0000982c, 0x0000a000 },
29374 - { 0x00009830, 0x00000000 },
29375 - { 0x0000983c, 0x00200400 },
29376 - { 0x00009840, 0x206a01ae },
29377 - { 0x0000984c, 0x0040233c },
29378 - { 0x0000a84c, 0x0040233c },
29379 - { 0x00009854, 0x00000044 },
29380 - { 0x00009900, 0x00000000 },
29381 - { 0x00009904, 0x00000000 },
29382 - { 0x00009908, 0x00000000 },
29383 - { 0x0000990c, 0x00000000 },
29384 - { 0x0000991c, 0x10000fff },
29385 - { 0x00009920, 0x04900000 },
29386 - { 0x0000a920, 0x04900000 },
29387 - { 0x00009928, 0x00000001 },
29388 - { 0x0000992c, 0x00000004 },
29389 - { 0x00009934, 0x1e1f2022 },
29390 - { 0x00009938, 0x0a0b0c0d },
29391 - { 0x0000993c, 0x00000000 },
29392 - { 0x00009948, 0x9280c00a },
29393 - { 0x0000994c, 0x00020028 },
29394 - { 0x00009954, 0xe250a51e },
29395 - { 0x00009958, 0x3388ffff },
29396 - { 0x00009940, 0x00781204 },
29397 - { 0x0000c95c, 0x004b6a8e },
29398 - { 0x0000c968, 0x000003ce },
29399 - { 0x00009970, 0x190fb514 },
29400 - { 0x00009974, 0x00000000 },
29401 - { 0x00009978, 0x00000001 },
29402 - { 0x0000997c, 0x00000000 },
29403 - { 0x00009980, 0x00000000 },
29404 - { 0x00009984, 0x00000000 },
29405 - { 0x00009988, 0x00000000 },
29406 - { 0x0000998c, 0x00000000 },
29407 - { 0x00009990, 0x00000000 },
29408 - { 0x00009994, 0x00000000 },
29409 - { 0x00009998, 0x00000000 },
29410 - { 0x0000999c, 0x00000000 },
29411 - { 0x000099a0, 0x00000000 },
29412 - { 0x000099a4, 0x00000001 },
29413 - { 0x000099a8, 0x201fff00 },
29414 - { 0x000099ac, 0x006f00c4 },
29415 - { 0x000099b0, 0x03051000 },
29416 - { 0x000099b4, 0x00000820 },
29417 - { 0x000099dc, 0x00000000 },
29418 - { 0x000099e0, 0x00000000 },
29419 - { 0x000099e4, 0xaaaaaaaa },
29420 - { 0x000099e8, 0x3c466478 },
29421 - { 0x000099ec, 0x0cc80caa },
29422 - { 0x000099fc, 0x00001042 },
29423 - { 0x0000a210, 0x4080a333 },
29424 - { 0x0000a214, 0x40206c10 },
29425 - { 0x0000a218, 0x009c4060 },
29426 - { 0x0000a220, 0x01834061 },
29427 - { 0x0000a224, 0x00000400 },
29428 - { 0x0000a228, 0x000003b5 },
29429 - { 0x0000a22c, 0x23277200 },
29430 - { 0x0000a234, 0x20202020 },
29431 - { 0x0000a238, 0x20202020 },
29432 - { 0x0000a23c, 0x13c889af },
29433 - { 0x0000a240, 0x38490a20 },
29434 - { 0x0000a244, 0x00007bb6 },
29435 - { 0x0000a248, 0x0fff3ffc },
29436 - { 0x0000a24c, 0x00000001 },
29437 - { 0x0000a250, 0x001da000 },
29438 - { 0x0000a254, 0x00000000 },
29439 - { 0x0000a258, 0x0cdbd380 },
29440 - { 0x0000a25c, 0x0f0f0f01 },
29441 - { 0x0000a260, 0xdfa91f01 },
29442 - { 0x0000a268, 0x00000000 },
29443 - { 0x0000a26c, 0x0ebae9c6 },
29444 - { 0x0000b26c, 0x0ebae9c6 },
29445 - { 0x0000d270, 0x00820820 },
29446 - { 0x0000a278, 0x1ce739ce },
29447 - { 0x0000a27c, 0x050701ce },
29448 - { 0x0000a358, 0x7999aa0f },
29449 - { 0x0000d35c, 0x07ffffef },
29450 - { 0x0000d360, 0x0fffffe7 },
29451 - { 0x0000d364, 0x17ffffe5 },
29452 - { 0x0000d368, 0x1fffffe4 },
29453 - { 0x0000d36c, 0x37ffffe3 },
29454 - { 0x0000d370, 0x3fffffe3 },
29455 - { 0x0000d374, 0x57ffffe3 },
29456 - { 0x0000d378, 0x5fffffe2 },
29457 - { 0x0000d37c, 0x7fffffe2 },
29458 - { 0x0000d380, 0x7f3c7bba },
29459 - { 0x0000d384, 0xf3307ff0 },
29460 - { 0x0000a388, 0x0c000000 },
29461 - { 0x0000a38c, 0x20202020 },
29462 - { 0x0000a390, 0x20202020 },
29463 - { 0x0000a394, 0x1ce739ce },
29464 - { 0x0000a398, 0x000001ce },
29465 - { 0x0000a39c, 0x00000001 },
29466 - { 0x0000a3a0, 0x00000000 },
29467 - { 0x0000a3a4, 0x00000000 },
29468 - { 0x0000a3a8, 0x00000000 },
29469 - { 0x0000a3ac, 0x00000000 },
29470 - { 0x0000a3b0, 0x00000000 },
29471 - { 0x0000a3b4, 0x00000000 },
29472 - { 0x0000a3b8, 0x00000000 },
29473 - { 0x0000a3bc, 0x00000000 },
29474 - { 0x0000a3c0, 0x00000000 },
29475 - { 0x0000a3c4, 0x00000000 },
29476 - { 0x0000a3c8, 0x00000246 },
29477 - { 0x0000a3cc, 0x20202020 },
29478 - { 0x0000a3d0, 0x20202020 },
29479 - { 0x0000a3d4, 0x20202020 },
29480 - { 0x0000a3dc, 0x1ce739ce },
29481 - { 0x0000a3e0, 0x000001ce },
29482 - { 0x0000a3e4, 0x00000000 },
29483 - { 0x0000a3e8, 0x18c43433 },
29484 - { 0x0000a3ec, 0x00f38081 },
29485 - { 0x00007800, 0x00040000 },
29486 - { 0x00007804, 0xdb005012 },
29487 - { 0x00007808, 0x04924914 },
29488 - { 0x0000780c, 0x21084210 },
29489 - { 0x00007810, 0x6d801300 },
29490 - { 0x00007814, 0x0019beff },
29491 - { 0x00007818, 0x07e40000 },
29492 - { 0x0000781c, 0x00492000 },
29493 - { 0x00007820, 0x92492480 },
29494 - { 0x00007824, 0x00040000 },
29495 - { 0x00007828, 0xdb005012 },
29496 - { 0x0000782c, 0x04924914 },
29497 - { 0x00007830, 0x21084210 },
29498 - { 0x00007834, 0x6d801300 },
29499 - { 0x00007838, 0x0019beff },
29500 - { 0x0000783c, 0x07e40000 },
29501 - { 0x00007840, 0x00492000 },
29502 - { 0x00007844, 0x92492480 },
29503 - { 0x00007848, 0x00120000 },
29504 - { 0x00007850, 0x54214514 },
29505 - { 0x00007858, 0x92592692 },
29506 - { 0x00007860, 0x52802000 },
29507 - { 0x00007864, 0x0a8e370e },
29508 - { 0x00007868, 0xc0102850 },
29509 - { 0x0000786c, 0x812d4000 },
29510 - { 0x00007874, 0x001b6db0 },
29511 - { 0x00007878, 0x00376b63 },
29512 - { 0x0000787c, 0x06db6db6 },
29513 - { 0x00007880, 0x006d8000 },
29514 - { 0x00007884, 0xffeffffe },
29515 - { 0x00007888, 0xffeffffe },
29516 - { 0x00007890, 0x00060aeb },
29517 - { 0x00007894, 0x5a108000 },
29518 - { 0x00007898, 0x2a850160 },
29519 -};
29520 -
29521 -/* XXX 9280 2 */
29522 -static const u32 ar9280Modes_9280_2[][6] = {
29523 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
29524 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
29525 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
29526 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
29527 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
29528 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
29529 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
29530 - { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
29531 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
29532 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
29533 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
29534 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
29535 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
29536 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29537 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
29538 - { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
29539 - { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
29540 - { 0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
29541 - { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
29542 - { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
29543 - { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
29544 - { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
29545 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
29546 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
29547 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
29548 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016 },
29549 - { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
29550 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
29551 - { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
29552 - { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
29553 - { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
29554 - { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
29555 - { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
29556 - { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
29557 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
29558 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
29559 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
29560 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
29561 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
29562 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29563 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29564 - { 0x0000a204, 0x00000444, 0x00000444, 0x00000444, 0x00000444, 0x00000444 },
29565 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
29566 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
29567 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
29568 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
29569 - { 0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000 },
29570 - { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
29571 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
29572 - { 0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000 },
29573 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
29574 - { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
29575 -};
29576 -
29577 -static const u32 ar9280Common_9280_2[][2] = {
29578 - { 0x0000000c, 0x00000000 },
29579 - { 0x00000030, 0x00020015 },
29580 - { 0x00000034, 0x00000005 },
29581 - { 0x00000040, 0x00000000 },
29582 - { 0x00000044, 0x00000008 },
29583 - { 0x00000048, 0x00000008 },
29584 - { 0x0000004c, 0x00000010 },
29585 - { 0x00000050, 0x00000000 },
29586 - { 0x00000054, 0x0000001f },
29587 - { 0x00000800, 0x00000000 },
29588 - { 0x00000804, 0x00000000 },
29589 - { 0x00000808, 0x00000000 },
29590 - { 0x0000080c, 0x00000000 },
29591 - { 0x00000810, 0x00000000 },
29592 - { 0x00000814, 0x00000000 },
29593 - { 0x00000818, 0x00000000 },
29594 - { 0x0000081c, 0x00000000 },
29595 - { 0x00000820, 0x00000000 },
29596 - { 0x00000824, 0x00000000 },
29597 - { 0x00001040, 0x002ffc0f },
29598 - { 0x00001044, 0x002ffc0f },
29599 - { 0x00001048, 0x002ffc0f },
29600 - { 0x0000104c, 0x002ffc0f },
29601 - { 0x00001050, 0x002ffc0f },
29602 - { 0x00001054, 0x002ffc0f },
29603 - { 0x00001058, 0x002ffc0f },
29604 - { 0x0000105c, 0x002ffc0f },
29605 - { 0x00001060, 0x002ffc0f },
29606 - { 0x00001064, 0x002ffc0f },
29607 - { 0x00001230, 0x00000000 },
29608 - { 0x00001270, 0x00000000 },
29609 - { 0x00001038, 0x00000000 },
29610 - { 0x00001078, 0x00000000 },
29611 - { 0x000010b8, 0x00000000 },
29612 - { 0x000010f8, 0x00000000 },
29613 - { 0x00001138, 0x00000000 },
29614 - { 0x00001178, 0x00000000 },
29615 - { 0x000011b8, 0x00000000 },
29616 - { 0x000011f8, 0x00000000 },
29617 - { 0x00001238, 0x00000000 },
29618 - { 0x00001278, 0x00000000 },
29619 - { 0x000012b8, 0x00000000 },
29620 - { 0x000012f8, 0x00000000 },
29621 - { 0x00001338, 0x00000000 },
29622 - { 0x00001378, 0x00000000 },
29623 - { 0x000013b8, 0x00000000 },
29624 - { 0x000013f8, 0x00000000 },
29625 - { 0x00001438, 0x00000000 },
29626 - { 0x00001478, 0x00000000 },
29627 - { 0x000014b8, 0x00000000 },
29628 - { 0x000014f8, 0x00000000 },
29629 - { 0x00001538, 0x00000000 },
29630 - { 0x00001578, 0x00000000 },
29631 - { 0x000015b8, 0x00000000 },
29632 - { 0x000015f8, 0x00000000 },
29633 - { 0x00001638, 0x00000000 },
29634 - { 0x00001678, 0x00000000 },
29635 - { 0x000016b8, 0x00000000 },
29636 - { 0x000016f8, 0x00000000 },
29637 - { 0x00001738, 0x00000000 },
29638 - { 0x00001778, 0x00000000 },
29639 - { 0x000017b8, 0x00000000 },
29640 - { 0x000017f8, 0x00000000 },
29641 - { 0x0000103c, 0x00000000 },
29642 - { 0x0000107c, 0x00000000 },
29643 - { 0x000010bc, 0x00000000 },
29644 - { 0x000010fc, 0x00000000 },
29645 - { 0x0000113c, 0x00000000 },
29646 - { 0x0000117c, 0x00000000 },
29647 - { 0x000011bc, 0x00000000 },
29648 - { 0x000011fc, 0x00000000 },
29649 - { 0x0000123c, 0x00000000 },
29650 - { 0x0000127c, 0x00000000 },
29651 - { 0x000012bc, 0x00000000 },
29652 - { 0x000012fc, 0x00000000 },
29653 - { 0x0000133c, 0x00000000 },
29654 - { 0x0000137c, 0x00000000 },
29655 - { 0x000013bc, 0x00000000 },
29656 - { 0x000013fc, 0x00000000 },
29657 - { 0x0000143c, 0x00000000 },
29658 - { 0x0000147c, 0x00000000 },
29659 - { 0x00004030, 0x00000002 },
29660 - { 0x0000403c, 0x00000002 },
29661 - { 0x00004024, 0x0000001f },
29662 - { 0x00004060, 0x00000000 },
29663 - { 0x00004064, 0x00000000 },
29664 - { 0x00007010, 0x00000033 },
29665 - { 0x00007034, 0x00000002 },
29666 - { 0x00007038, 0x000004c2 },
29667 - { 0x00008004, 0x00000000 },
29668 - { 0x00008008, 0x00000000 },
29669 - { 0x0000800c, 0x00000000 },
29670 - { 0x00008018, 0x00000700 },
29671 - { 0x00008020, 0x00000000 },
29672 - { 0x00008038, 0x00000000 },
29673 - { 0x0000803c, 0x00000000 },
29674 - { 0x00008048, 0x40000000 },
29675 - { 0x00008054, 0x00000000 },
29676 - { 0x00008058, 0x00000000 },
29677 - { 0x0000805c, 0x000fc78f },
29678 - { 0x00008060, 0x0000000f },
29679 - { 0x00008064, 0x00000000 },
29680 - { 0x00008070, 0x00000000 },
29681 - { 0x000080c0, 0x2a80001a },
29682 - { 0x000080c4, 0x05dc01e0 },
29683 - { 0x000080c8, 0x1f402710 },
29684 - { 0x000080cc, 0x01f40000 },
29685 - { 0x000080d0, 0x00001e00 },
29686 - { 0x000080d4, 0x00000000 },
29687 - { 0x000080d8, 0x00400000 },
29688 - { 0x000080e0, 0xffffffff },
29689 - { 0x000080e4, 0x0000ffff },
29690 - { 0x000080e8, 0x003f3f3f },
29691 - { 0x000080ec, 0x00000000 },
29692 - { 0x000080f0, 0x00000000 },
29693 - { 0x000080f4, 0x00000000 },
29694 - { 0x000080f8, 0x00000000 },
29695 - { 0x000080fc, 0x00020000 },
29696 - { 0x00008100, 0x00020000 },
29697 - { 0x00008104, 0x00000001 },
29698 - { 0x00008108, 0x00000052 },
29699 - { 0x0000810c, 0x00000000 },
29700 - { 0x00008110, 0x00000168 },
29701 - { 0x00008118, 0x000100aa },
29702 - { 0x0000811c, 0x00003210 },
29703 - { 0x00008124, 0x00000000 },
29704 - { 0x00008128, 0x00000000 },
29705 - { 0x0000812c, 0x00000000 },
29706 - { 0x00008130, 0x00000000 },
29707 - { 0x00008134, 0x00000000 },
29708 - { 0x00008138, 0x00000000 },
29709 - { 0x0000813c, 0x00000000 },
29710 - { 0x00008144, 0xffffffff },
29711 - { 0x00008168, 0x00000000 },
29712 - { 0x0000816c, 0x00000000 },
29713 - { 0x00008170, 0x32143320 },
29714 - { 0x00008174, 0xfaa4fa50 },
29715 - { 0x00008178, 0x00000100 },
29716 - { 0x0000817c, 0x00000000 },
29717 - { 0x000081c0, 0x00000000 },
29718 - { 0x000081ec, 0x00000000 },
29719 - { 0x000081f0, 0x00000000 },
29720 - { 0x000081f4, 0x00000000 },
29721 - { 0x000081f8, 0x00000000 },
29722 - { 0x000081fc, 0x00000000 },
29723 - { 0x00008200, 0x00000000 },
29724 - { 0x00008204, 0x00000000 },
29725 - { 0x00008208, 0x00000000 },
29726 - { 0x0000820c, 0x00000000 },
29727 - { 0x00008210, 0x00000000 },
29728 - { 0x00008214, 0x00000000 },
29729 - { 0x00008218, 0x00000000 },
29730 - { 0x0000821c, 0x00000000 },
29731 - { 0x00008220, 0x00000000 },
29732 - { 0x00008224, 0x00000000 },
29733 - { 0x00008228, 0x00000000 },
29734 - { 0x0000822c, 0x00000000 },
29735 - { 0x00008230, 0x00000000 },
29736 - { 0x00008234, 0x00000000 },
29737 - { 0x00008238, 0x00000000 },
29738 - { 0x0000823c, 0x00000000 },
29739 - { 0x00008240, 0x00100000 },
29740 - { 0x00008244, 0x0010f400 },
29741 - { 0x00008248, 0x00000100 },
29742 - { 0x0000824c, 0x0001e800 },
29743 - { 0x00008250, 0x00000000 },
29744 - { 0x00008254, 0x00000000 },
29745 - { 0x00008258, 0x00000000 },
29746 - { 0x0000825c, 0x400000ff },
29747 - { 0x00008260, 0x00080922 },
29748 - { 0x00008264, 0xa8a00010 },
29749 - { 0x00008270, 0x00000000 },
29750 - { 0x00008274, 0x40000000 },
29751 - { 0x00008278, 0x003e4180 },
29752 - { 0x0000827c, 0x00000000 },
29753 - { 0x00008284, 0x0000002c },
29754 - { 0x00008288, 0x0000002c },
29755 - { 0x0000828c, 0x00000000 },
29756 - { 0x00008294, 0x00000000 },
29757 - { 0x00008298, 0x00000000 },
29758 - { 0x0000829c, 0x00000000 },
29759 - { 0x00008300, 0x00000040 },
29760 - { 0x00008314, 0x00000000 },
29761 - { 0x00008328, 0x00000000 },
29762 - { 0x0000832c, 0x00000007 },
29763 - { 0x00008330, 0x00000302 },
29764 - { 0x00008334, 0x00000e00 },
29765 - { 0x00008338, 0x00ff0000 },
29766 - { 0x0000833c, 0x00000000 },
29767 - { 0x00008340, 0x000107ff },
29768 - { 0x00008344, 0x00481043 },
29769 - { 0x00009808, 0x00000000 },
29770 - { 0x0000980c, 0xafa68e30 },
29771 - { 0x00009810, 0xfd14e000 },
29772 - { 0x00009814, 0x9c0a9f6b },
29773 - { 0x0000981c, 0x00000000 },
29774 - { 0x0000982c, 0x0000a000 },
29775 - { 0x00009830, 0x00000000 },
29776 - { 0x0000983c, 0x00200400 },
29777 - { 0x0000984c, 0x0040233c },
29778 - { 0x0000a84c, 0x0040233c },
29779 - { 0x00009854, 0x00000044 },
29780 - { 0x00009900, 0x00000000 },
29781 - { 0x00009904, 0x00000000 },
29782 - { 0x00009908, 0x00000000 },
29783 - { 0x0000990c, 0x00000000 },
29784 - { 0x00009910, 0x01002310 },
29785 - { 0x0000991c, 0x10000fff },
29786 - { 0x00009920, 0x04900000 },
29787 - { 0x0000a920, 0x04900000 },
29788 - { 0x00009928, 0x00000001 },
29789 - { 0x0000992c, 0x00000004 },
29790 - { 0x00009934, 0x1e1f2022 },
29791 - { 0x00009938, 0x0a0b0c0d },
29792 - { 0x0000993c, 0x00000000 },
29793 - { 0x00009948, 0x9280c00a },
29794 - { 0x0000994c, 0x00020028 },
29795 - { 0x00009954, 0x5f3ca3de },
29796 - { 0x00009958, 0x2108ecff },
29797 - { 0x00009940, 0x14750604 },
29798 - { 0x0000c95c, 0x004b6a8e },
29799 - { 0x00009970, 0x190fb515 },
29800 - { 0x00009974, 0x00000000 },
29801 - { 0x00009978, 0x00000001 },
29802 - { 0x0000997c, 0x00000000 },
29803 - { 0x00009980, 0x00000000 },
29804 - { 0x00009984, 0x00000000 },
29805 - { 0x00009988, 0x00000000 },
29806 - { 0x0000998c, 0x00000000 },
29807 - { 0x00009990, 0x00000000 },
29808 - { 0x00009994, 0x00000000 },
29809 - { 0x00009998, 0x00000000 },
29810 - { 0x0000999c, 0x00000000 },
29811 - { 0x000099a0, 0x00000000 },
29812 - { 0x000099a4, 0x00000001 },
29813 - { 0x000099a8, 0x201fff00 },
29814 - { 0x000099ac, 0x006f0000 },
29815 - { 0x000099b0, 0x03051000 },
29816 - { 0x000099b4, 0x00000820 },
29817 - { 0x000099dc, 0x00000000 },
29818 - { 0x000099e0, 0x00000000 },
29819 - { 0x000099e4, 0xaaaaaaaa },
29820 - { 0x000099e8, 0x3c466478 },
29821 - { 0x000099ec, 0x0cc80caa },
29822 - { 0x000099f0, 0x00000000 },
29823 - { 0x000099fc, 0x00001042 },
29824 - { 0x0000a208, 0x803e4788 },
29825 - { 0x0000a210, 0x4080a333 },
29826 - { 0x0000a214, 0x40206c10 },
29827 - { 0x0000a218, 0x009c4060 },
29828 - { 0x0000a220, 0x01834061 },
29829 - { 0x0000a224, 0x00000400 },
29830 - { 0x0000a228, 0x000003b5 },
29831 - { 0x0000a22c, 0x233f7180 },
29832 - { 0x0000a234, 0x20202020 },
29833 - { 0x0000a238, 0x20202020 },
29834 - { 0x0000a240, 0x38490a20 },
29835 - { 0x0000a244, 0x00007bb6 },
29836 - { 0x0000a248, 0x0fff3ffc },
29837 - { 0x0000a24c, 0x00000000 },
29838 - { 0x0000a254, 0x00000000 },
29839 - { 0x0000a258, 0x0cdbd380 },
29840 - { 0x0000a25c, 0x0f0f0f01 },
29841 - { 0x0000a260, 0xdfa91f01 },
29842 - { 0x0000a268, 0x00000000 },
29843 - { 0x0000a26c, 0x0e79e5c6 },
29844 - { 0x0000b26c, 0x0e79e5c6 },
29845 - { 0x0000d270, 0x00820820 },
29846 - { 0x0000a278, 0x1ce739ce },
29847 - { 0x0000d35c, 0x07ffffef },
29848 - { 0x0000d360, 0x0fffffe7 },
29849 - { 0x0000d364, 0x17ffffe5 },
29850 - { 0x0000d368, 0x1fffffe4 },
29851 - { 0x0000d36c, 0x37ffffe3 },
29852 - { 0x0000d370, 0x3fffffe3 },
29853 - { 0x0000d374, 0x57ffffe3 },
29854 - { 0x0000d378, 0x5fffffe2 },
29855 - { 0x0000d37c, 0x7fffffe2 },
29856 - { 0x0000d380, 0x7f3c7bba },
29857 - { 0x0000d384, 0xf3307ff0 },
29858 - { 0x0000a38c, 0x20202020 },
29859 - { 0x0000a390, 0x20202020 },
29860 - { 0x0000a394, 0x1ce739ce },
29861 - { 0x0000a398, 0x000001ce },
29862 - { 0x0000a39c, 0x00000001 },
29863 - { 0x0000a3a0, 0x00000000 },
29864 - { 0x0000a3a4, 0x00000000 },
29865 - { 0x0000a3a8, 0x00000000 },
29866 - { 0x0000a3ac, 0x00000000 },
29867 - { 0x0000a3b0, 0x00000000 },
29868 - { 0x0000a3b4, 0x00000000 },
29869 - { 0x0000a3b8, 0x00000000 },
29870 - { 0x0000a3bc, 0x00000000 },
29871 - { 0x0000a3c0, 0x00000000 },
29872 - { 0x0000a3c4, 0x00000000 },
29873 - { 0x0000a3c8, 0x00000246 },
29874 - { 0x0000a3cc, 0x20202020 },
29875 - { 0x0000a3d0, 0x20202020 },
29876 - { 0x0000a3d4, 0x20202020 },
29877 - { 0x0000a3dc, 0x1ce739ce },
29878 - { 0x0000a3e0, 0x000001ce },
29879 - { 0x0000a3e4, 0x00000000 },
29880 - { 0x0000a3e8, 0x18c43433 },
29881 - { 0x0000a3ec, 0x00f70081 },
29882 - { 0x00007800, 0x00040000 },
29883 - { 0x00007804, 0xdb005012 },
29884 - { 0x00007808, 0x04924914 },
29885 - { 0x0000780c, 0x21084210 },
29886 - { 0x00007810, 0x6d801300 },
29887 - { 0x00007818, 0x07e41000 },
29888 - { 0x00007824, 0x00040000 },
29889 - { 0x00007828, 0xdb005012 },
29890 - { 0x0000782c, 0x04924914 },
29891 - { 0x00007830, 0x21084210 },
29892 - { 0x00007834, 0x6d801300 },
29893 - { 0x0000783c, 0x07e40000 },
29894 - { 0x00007848, 0x00100000 },
29895 - { 0x0000784c, 0x773f0567 },
29896 - { 0x00007850, 0x54214514 },
29897 - { 0x00007854, 0x12035828 },
29898 - { 0x00007858, 0x9259269a },
29899 - { 0x00007860, 0x52802000 },
29900 - { 0x00007864, 0x0a8e370e },
29901 - { 0x00007868, 0xc0102850 },
29902 - { 0x0000786c, 0x812d4000 },
29903 - { 0x00007870, 0x807ec400 },
29904 - { 0x00007874, 0x001b6db0 },
29905 - { 0x00007878, 0x00376b63 },
29906 - { 0x0000787c, 0x06db6db6 },
29907 - { 0x00007880, 0x006d8000 },
29908 - { 0x00007884, 0xffeffffe },
29909 - { 0x00007888, 0xffeffffe },
29910 - { 0x0000788c, 0x00010000 },
29911 - { 0x00007890, 0x02060aeb },
29912 - { 0x00007898, 0x2a850160 },
29913 -};
29914 -
29915 -static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
29916 - { 0x00001030, 0x00000268, 0x000004d0 },
29917 - { 0x00001070, 0x0000018c, 0x00000318 },
29918 - { 0x000010b0, 0x00000fd0, 0x00001fa0 },
29919 - { 0x00008014, 0x044c044c, 0x08980898 },
29920 - { 0x0000801c, 0x148ec02b, 0x148ec057 },
29921 - { 0x00008318, 0x000044c0, 0x00008980 },
29922 - { 0x00009820, 0x02020200, 0x02020200 },
29923 - { 0x00009824, 0x01000f0f, 0x01000f0f },
29924 - { 0x00009828, 0x0b020001, 0x0b020001 },
29925 - { 0x00009834, 0x00000f0f, 0x00000f0f },
29926 - { 0x00009844, 0x03721821, 0x03721821 },
29927 - { 0x00009914, 0x00000898, 0x00001130 },
29928 - { 0x00009918, 0x0000000b, 0x00000016 },
29929 -};
29930 -
29931 -static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
29932 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
29933 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
29934 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
29935 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
29936 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
29937 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
29938 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
29939 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
29940 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
29941 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
29942 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
29943 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
29944 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
29945 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
29946 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
29947 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
29948 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
29949 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
29950 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
29951 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
29952 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
29953 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
29954 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
29955 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
29956 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
29957 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
29958 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
29959 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
29960 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
29961 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
29962 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
29963 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
29964 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
29965 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
29966 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
29967 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
29968 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
29969 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
29970 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
29971 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
29972 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
29973 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
29974 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
29975 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
29976 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
29977 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
29978 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
29979 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
29980 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b10, 0x00008b10, 0x00008b10 },
29981 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b14, 0x00008b14, 0x00008b14 },
29982 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b01, 0x00008b01, 0x00008b01 },
29983 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b05, 0x00008b05, 0x00008b05 },
29984 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b09, 0x00008b09, 0x00008b09 },
29985 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008b0d, 0x00008b0d, 0x00008b0d },
29986 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008b11, 0x00008b11, 0x00008b11 },
29987 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008b15, 0x00008b15, 0x00008b15 },
29988 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008b02, 0x00008b02, 0x00008b02 },
29989 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008b06, 0x00008b06, 0x00008b06 },
29990 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00008b0a, 0x00008b0a, 0x00008b0a },
29991 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00008b0e, 0x00008b0e, 0x00008b0e },
29992 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00008b12, 0x00008b12, 0x00008b12 },
29993 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00008b16, 0x00008b16, 0x00008b16 },
29994 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00008b03, 0x00008b03, 0x00008b03 },
29995 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00008b07, 0x00008b07, 0x00008b07 },
29996 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x00008b0b, 0x00008b0b, 0x00008b0b },
29997 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x00008b0f, 0x00008b0f, 0x00008b0f },
29998 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00008b13, 0x00008b13, 0x00008b13 },
29999 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00008b17, 0x00008b17, 0x00008b17 },
30000 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00008b23, 0x00008b23, 0x00008b23 },
30001 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00008b27, 0x00008b27, 0x00008b27 },
30002 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00008b2b, 0x00008b2b, 0x00008b2b },
30003 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00008b2f, 0x00008b2f, 0x00008b2f },
30004 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00008b33, 0x00008b33, 0x00008b33 },
30005 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x00008b37, 0x00008b37, 0x00008b37 },
30006 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x00008b43, 0x00008b43, 0x00008b43 },
30007 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x00008b47, 0x00008b47, 0x00008b47 },
30008 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00008b4b, 0x00008b4b, 0x00008b4b },
30009 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00008b4f, 0x00008b4f, 0x00008b4f },
30010 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00008b53, 0x00008b53, 0x00008b53 },
30011 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00008b57, 0x00008b57, 0x00008b57 },
30012 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30013 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30014 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30015 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30016 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30017 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30018 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30019 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30020 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30021 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30022 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30023 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30024 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30025 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30026 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30027 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30028 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30029 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30030 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30031 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30032 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30033 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30034 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30035 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30036 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30037 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30038 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30039 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30040 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30041 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30042 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30043 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30044 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30045 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30046 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30047 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30048 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30049 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30050 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30051 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30052 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30053 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30054 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30055 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30056 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30057 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30058 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30059 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x00008b5b, 0x00008b5b, 0x00008b5b },
30060 - { 0x00009848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
30061 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001050, 0x00001050, 0x00001050 },
30062 -};
30063 -
30064 -static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
30065 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
30066 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
30067 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
30068 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
30069 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
30070 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
30071 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
30072 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
30073 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
30074 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
30075 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
30076 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
30077 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
30078 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
30079 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
30080 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
30081 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
30082 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
30083 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
30084 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
30085 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
30086 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
30087 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
30088 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
30089 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
30090 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
30091 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
30092 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
30093 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
30094 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
30095 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
30096 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
30097 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
30098 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
30099 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
30100 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
30101 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
30102 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
30103 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
30104 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
30105 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
30106 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
30107 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
30108 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
30109 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
30110 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
30111 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
30112 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
30113 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
30114 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
30115 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
30116 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
30117 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
30118 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
30119 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
30120 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
30121 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
30122 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
30123 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x0000930c, 0x0000930c, 0x0000930c },
30124 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009310, 0x00009310, 0x00009310 },
30125 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009384, 0x00009384, 0x00009384 },
30126 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009388, 0x00009388, 0x00009388 },
30127 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009324, 0x00009324, 0x00009324 },
30128 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x00009704, 0x00009704, 0x00009704 },
30129 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x000096a4, 0x000096a4, 0x000096a4 },
30130 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x000096a8, 0x000096a8, 0x000096a8 },
30131 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009710, 0x00009710, 0x00009710 },
30132 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009714, 0x00009714, 0x00009714 },
30133 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009720, 0x00009720, 0x00009720 },
30134 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x00009724, 0x00009724, 0x00009724 },
30135 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009728, 0x00009728, 0x00009728 },
30136 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x0000972c, 0x0000972c, 0x0000972c },
30137 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x000097a0, 0x000097a0, 0x000097a0 },
30138 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x000097a4, 0x000097a4, 0x000097a4 },
30139 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x000097a8, 0x000097a8, 0x000097a8 },
30140 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x000097b0, 0x000097b0, 0x000097b0 },
30141 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x000097b4, 0x000097b4, 0x000097b4 },
30142 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x000097b8, 0x000097b8, 0x000097b8 },
30143 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x000097a5, 0x000097a5, 0x000097a5 },
30144 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x000097a9, 0x000097a9, 0x000097a9 },
30145 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x000097ad, 0x000097ad, 0x000097ad },
30146 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x000097b1, 0x000097b1, 0x000097b1 },
30147 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x000097b5, 0x000097b5, 0x000097b5 },
30148 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x000097b9, 0x000097b9, 0x000097b9 },
30149 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x000097c5, 0x000097c5, 0x000097c5 },
30150 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x000097c9, 0x000097c9, 0x000097c9 },
30151 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x000097d1, 0x000097d1, 0x000097d1 },
30152 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x000097d5, 0x000097d5, 0x000097d5 },
30153 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x000097d9, 0x000097d9, 0x000097d9 },
30154 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x000097c6, 0x000097c6, 0x000097c6 },
30155 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x000097ca, 0x000097ca, 0x000097ca },
30156 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x000097ce, 0x000097ce, 0x000097ce },
30157 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x000097d2, 0x000097d2, 0x000097d2 },
30158 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x000097d6, 0x000097d6, 0x000097d6 },
30159 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x000097c3, 0x000097c3, 0x000097c3 },
30160 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x000097c7, 0x000097c7, 0x000097c7 },
30161 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x000097cb, 0x000097cb, 0x000097cb },
30162 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x000097cf, 0x000097cf, 0x000097cf },
30163 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x000097d7, 0x000097d7, 0x000097d7 },
30164 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x000097db, 0x000097db, 0x000097db },
30165 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x000097db, 0x000097db, 0x000097db },
30166 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x000097db, 0x000097db, 0x000097db },
30167 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30168 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30169 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30170 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30171 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30172 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30173 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30174 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30175 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30176 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30177 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30178 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30179 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30180 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30181 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30182 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30183 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30184 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30185 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30186 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30187 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30188 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30189 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30190 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30191 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30192 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x000097db, 0x000097db, 0x000097db },
30193 - { 0x00009848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
30194 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063 },
30195 -};
30196 -
30197 -static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
30198 - { 0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290 },
30199 - { 0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300 },
30200 - { 0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304 },
30201 - { 0x00009a0c, 0x00008190, 0x00008190, 0x00000308, 0x00000308, 0x00000308 },
30202 - { 0x00009a10, 0x00008194, 0x00008194, 0x0000030c, 0x0000030c, 0x0000030c },
30203 - { 0x00009a14, 0x00008200, 0x00008200, 0x00008000, 0x00008000, 0x00008000 },
30204 - { 0x00009a18, 0x00008204, 0x00008204, 0x00008004, 0x00008004, 0x00008004 },
30205 - { 0x00009a1c, 0x00008208, 0x00008208, 0x00008008, 0x00008008, 0x00008008 },
30206 - { 0x00009a20, 0x0000820c, 0x0000820c, 0x0000800c, 0x0000800c, 0x0000800c },
30207 - { 0x00009a24, 0x00008210, 0x00008210, 0x00008080, 0x00008080, 0x00008080 },
30208 - { 0x00009a28, 0x00008214, 0x00008214, 0x00008084, 0x00008084, 0x00008084 },
30209 - { 0x00009a2c, 0x00008280, 0x00008280, 0x00008088, 0x00008088, 0x00008088 },
30210 - { 0x00009a30, 0x00008284, 0x00008284, 0x0000808c, 0x0000808c, 0x0000808c },
30211 - { 0x00009a34, 0x00008288, 0x00008288, 0x00008100, 0x00008100, 0x00008100 },
30212 - { 0x00009a38, 0x0000828c, 0x0000828c, 0x00008104, 0x00008104, 0x00008104 },
30213 - { 0x00009a3c, 0x00008290, 0x00008290, 0x00008108, 0x00008108, 0x00008108 },
30214 - { 0x00009a40, 0x00008300, 0x00008300, 0x0000810c, 0x0000810c, 0x0000810c },
30215 - { 0x00009a44, 0x00008304, 0x00008304, 0x00008110, 0x00008110, 0x00008110 },
30216 - { 0x00009a48, 0x00008308, 0x00008308, 0x00008114, 0x00008114, 0x00008114 },
30217 - { 0x00009a4c, 0x0000830c, 0x0000830c, 0x00008180, 0x00008180, 0x00008180 },
30218 - { 0x00009a50, 0x00008310, 0x00008310, 0x00008184, 0x00008184, 0x00008184 },
30219 - { 0x00009a54, 0x00008314, 0x00008314, 0x00008188, 0x00008188, 0x00008188 },
30220 - { 0x00009a58, 0x00008380, 0x00008380, 0x0000818c, 0x0000818c, 0x0000818c },
30221 - { 0x00009a5c, 0x00008384, 0x00008384, 0x00008190, 0x00008190, 0x00008190 },
30222 - { 0x00009a60, 0x00008388, 0x00008388, 0x00008194, 0x00008194, 0x00008194 },
30223 - { 0x00009a64, 0x0000838c, 0x0000838c, 0x000081a0, 0x000081a0, 0x000081a0 },
30224 - { 0x00009a68, 0x00008390, 0x00008390, 0x0000820c, 0x0000820c, 0x0000820c },
30225 - { 0x00009a6c, 0x00008394, 0x00008394, 0x000081a8, 0x000081a8, 0x000081a8 },
30226 - { 0x00009a70, 0x0000a380, 0x0000a380, 0x00008284, 0x00008284, 0x00008284 },
30227 - { 0x00009a74, 0x0000a384, 0x0000a384, 0x00008288, 0x00008288, 0x00008288 },
30228 - { 0x00009a78, 0x0000a388, 0x0000a388, 0x00008224, 0x00008224, 0x00008224 },
30229 - { 0x00009a7c, 0x0000a38c, 0x0000a38c, 0x00008290, 0x00008290, 0x00008290 },
30230 - { 0x00009a80, 0x0000a390, 0x0000a390, 0x00008300, 0x00008300, 0x00008300 },
30231 - { 0x00009a84, 0x0000a394, 0x0000a394, 0x00008304, 0x00008304, 0x00008304 },
30232 - { 0x00009a88, 0x0000a780, 0x0000a780, 0x00008308, 0x00008308, 0x00008308 },
30233 - { 0x00009a8c, 0x0000a784, 0x0000a784, 0x0000830c, 0x0000830c, 0x0000830c },
30234 - { 0x00009a90, 0x0000a788, 0x0000a788, 0x00008380, 0x00008380, 0x00008380 },
30235 - { 0x00009a94, 0x0000a78c, 0x0000a78c, 0x00008384, 0x00008384, 0x00008384 },
30236 - { 0x00009a98, 0x0000a790, 0x0000a790, 0x00008700, 0x00008700, 0x00008700 },
30237 - { 0x00009a9c, 0x0000a794, 0x0000a794, 0x00008704, 0x00008704, 0x00008704 },
30238 - { 0x00009aa0, 0x0000ab84, 0x0000ab84, 0x00008708, 0x00008708, 0x00008708 },
30239 - { 0x00009aa4, 0x0000ab88, 0x0000ab88, 0x0000870c, 0x0000870c, 0x0000870c },
30240 - { 0x00009aa8, 0x0000ab8c, 0x0000ab8c, 0x00008780, 0x00008780, 0x00008780 },
30241 - { 0x00009aac, 0x0000ab90, 0x0000ab90, 0x00008784, 0x00008784, 0x00008784 },
30242 - { 0x00009ab0, 0x0000ab94, 0x0000ab94, 0x00008b00, 0x00008b00, 0x00008b00 },
30243 - { 0x00009ab4, 0x0000af80, 0x0000af80, 0x00008b04, 0x00008b04, 0x00008b04 },
30244 - { 0x00009ab8, 0x0000af84, 0x0000af84, 0x00008b08, 0x00008b08, 0x00008b08 },
30245 - { 0x00009abc, 0x0000af88, 0x0000af88, 0x00008b0c, 0x00008b0c, 0x00008b0c },
30246 - { 0x00009ac0, 0x0000af8c, 0x0000af8c, 0x00008b80, 0x00008b80, 0x00008b80 },
30247 - { 0x00009ac4, 0x0000af90, 0x0000af90, 0x00008b84, 0x00008b84, 0x00008b84 },
30248 - { 0x00009ac8, 0x0000af94, 0x0000af94, 0x00008b88, 0x00008b88, 0x00008b88 },
30249 - { 0x00009acc, 0x0000b380, 0x0000b380, 0x00008b8c, 0x00008b8c, 0x00008b8c },
30250 - { 0x00009ad0, 0x0000b384, 0x0000b384, 0x00008b90, 0x00008b90, 0x00008b90 },
30251 - { 0x00009ad4, 0x0000b388, 0x0000b388, 0x00008f80, 0x00008f80, 0x00008f80 },
30252 - { 0x00009ad8, 0x0000b38c, 0x0000b38c, 0x00008f84, 0x00008f84, 0x00008f84 },
30253 - { 0x00009adc, 0x0000b390, 0x0000b390, 0x00008f88, 0x00008f88, 0x00008f88 },
30254 - { 0x00009ae0, 0x0000b394, 0x0000b394, 0x00008f8c, 0x00008f8c, 0x00008f8c },
30255 - { 0x00009ae4, 0x0000b398, 0x0000b398, 0x00008f90, 0x00008f90, 0x00008f90 },
30256 - { 0x00009ae8, 0x0000b780, 0x0000b780, 0x00009310, 0x00009310, 0x00009310 },
30257 - { 0x00009aec, 0x0000b784, 0x0000b784, 0x00009314, 0x00009314, 0x00009314 },
30258 - { 0x00009af0, 0x0000b788, 0x0000b788, 0x00009320, 0x00009320, 0x00009320 },
30259 - { 0x00009af4, 0x0000b78c, 0x0000b78c, 0x00009324, 0x00009324, 0x00009324 },
30260 - { 0x00009af8, 0x0000b790, 0x0000b790, 0x00009328, 0x00009328, 0x00009328 },
30261 - { 0x00009afc, 0x0000b794, 0x0000b794, 0x0000932c, 0x0000932c, 0x0000932c },
30262 - { 0x00009b00, 0x0000b798, 0x0000b798, 0x00009330, 0x00009330, 0x00009330 },
30263 - { 0x00009b04, 0x0000d784, 0x0000d784, 0x00009334, 0x00009334, 0x00009334 },
30264 - { 0x00009b08, 0x0000d788, 0x0000d788, 0x00009321, 0x00009321, 0x00009321 },
30265 - { 0x00009b0c, 0x0000d78c, 0x0000d78c, 0x00009325, 0x00009325, 0x00009325 },
30266 - { 0x00009b10, 0x0000d790, 0x0000d790, 0x00009329, 0x00009329, 0x00009329 },
30267 - { 0x00009b14, 0x0000f780, 0x0000f780, 0x0000932d, 0x0000932d, 0x0000932d },
30268 - { 0x00009b18, 0x0000f784, 0x0000f784, 0x00009331, 0x00009331, 0x00009331 },
30269 - { 0x00009b1c, 0x0000f788, 0x0000f788, 0x00009335, 0x00009335, 0x00009335 },
30270 - { 0x00009b20, 0x0000f78c, 0x0000f78c, 0x00009322, 0x00009322, 0x00009322 },
30271 - { 0x00009b24, 0x0000f790, 0x0000f790, 0x00009326, 0x00009326, 0x00009326 },
30272 - { 0x00009b28, 0x0000f794, 0x0000f794, 0x0000932a, 0x0000932a, 0x0000932a },
30273 - { 0x00009b2c, 0x0000f7a4, 0x0000f7a4, 0x0000932e, 0x0000932e, 0x0000932e },
30274 - { 0x00009b30, 0x0000f7a8, 0x0000f7a8, 0x00009332, 0x00009332, 0x00009332 },
30275 - { 0x00009b34, 0x0000f7ac, 0x0000f7ac, 0x00009336, 0x00009336, 0x00009336 },
30276 - { 0x00009b38, 0x0000f7b0, 0x0000f7b0, 0x00009323, 0x00009323, 0x00009323 },
30277 - { 0x00009b3c, 0x0000f7b4, 0x0000f7b4, 0x00009327, 0x00009327, 0x00009327 },
30278 - { 0x00009b40, 0x0000f7a1, 0x0000f7a1, 0x0000932b, 0x0000932b, 0x0000932b },
30279 - { 0x00009b44, 0x0000f7a5, 0x0000f7a5, 0x0000932f, 0x0000932f, 0x0000932f },
30280 - { 0x00009b48, 0x0000f7a9, 0x0000f7a9, 0x00009333, 0x00009333, 0x00009333 },
30281 - { 0x00009b4c, 0x0000f7ad, 0x0000f7ad, 0x00009337, 0x00009337, 0x00009337 },
30282 - { 0x00009b50, 0x0000f7b1, 0x0000f7b1, 0x00009343, 0x00009343, 0x00009343 },
30283 - { 0x00009b54, 0x0000f7b5, 0x0000f7b5, 0x00009347, 0x00009347, 0x00009347 },
30284 - { 0x00009b58, 0x0000f7c5, 0x0000f7c5, 0x0000934b, 0x0000934b, 0x0000934b },
30285 - { 0x00009b5c, 0x0000f7c9, 0x0000f7c9, 0x0000934f, 0x0000934f, 0x0000934f },
30286 - { 0x00009b60, 0x0000f7cd, 0x0000f7cd, 0x00009353, 0x00009353, 0x00009353 },
30287 - { 0x00009b64, 0x0000f7d1, 0x0000f7d1, 0x00009357, 0x00009357, 0x00009357 },
30288 - { 0x00009b68, 0x0000f7d5, 0x0000f7d5, 0x0000935b, 0x0000935b, 0x0000935b },
30289 - { 0x00009b6c, 0x0000f7c2, 0x0000f7c2, 0x0000935b, 0x0000935b, 0x0000935b },
30290 - { 0x00009b70, 0x0000f7c6, 0x0000f7c6, 0x0000935b, 0x0000935b, 0x0000935b },
30291 - { 0x00009b74, 0x0000f7ca, 0x0000f7ca, 0x0000935b, 0x0000935b, 0x0000935b },
30292 - { 0x00009b78, 0x0000f7ce, 0x0000f7ce, 0x0000935b, 0x0000935b, 0x0000935b },
30293 - { 0x00009b7c, 0x0000f7d2, 0x0000f7d2, 0x0000935b, 0x0000935b, 0x0000935b },
30294 - { 0x00009b80, 0x0000f7d6, 0x0000f7d6, 0x0000935b, 0x0000935b, 0x0000935b },
30295 - { 0x00009b84, 0x0000f7c3, 0x0000f7c3, 0x0000935b, 0x0000935b, 0x0000935b },
30296 - { 0x00009b88, 0x0000f7c7, 0x0000f7c7, 0x0000935b, 0x0000935b, 0x0000935b },
30297 - { 0x00009b8c, 0x0000f7cb, 0x0000f7cb, 0x0000935b, 0x0000935b, 0x0000935b },
30298 - { 0x00009b90, 0x0000f7d3, 0x0000f7d3, 0x0000935b, 0x0000935b, 0x0000935b },
30299 - { 0x00009b94, 0x0000f7d7, 0x0000f7d7, 0x0000935b, 0x0000935b, 0x0000935b },
30300 - { 0x00009b98, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30301 - { 0x00009b9c, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30302 - { 0x00009ba0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30303 - { 0x00009ba4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30304 - { 0x00009ba8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30305 - { 0x00009bac, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30306 - { 0x00009bb0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30307 - { 0x00009bb4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30308 - { 0x00009bb8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30309 - { 0x00009bbc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30310 - { 0x00009bc0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30311 - { 0x00009bc4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30312 - { 0x00009bc8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30313 - { 0x00009bcc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30314 - { 0x00009bd0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30315 - { 0x00009bd4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30316 - { 0x00009bd8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30317 - { 0x00009bdc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30318 - { 0x00009be0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30319 - { 0x00009be4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30320 - { 0x00009be8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30321 - { 0x00009bec, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30322 - { 0x00009bf0, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30323 - { 0x00009bf4, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30324 - { 0x00009bf8, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30325 - { 0x00009bfc, 0x0000f7db, 0x0000f7db, 0x0000935b, 0x0000935b, 0x0000935b },
30326 - { 0x00009848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
30327 - { 0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a },
30328 -};
30329 -
30330 -static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
30331 - { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
30332 - { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
30333 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30334 - { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
30335 - { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
30336 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000c010, 0x0000c010, 0x0000c010 },
30337 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x00010012, 0x00010012, 0x00010012 },
30338 - { 0x0000a314, 0x00011014, 0x00011014, 0x00013014, 0x00013014, 0x00013014 },
30339 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001820a, 0x0001820a, 0x0001820a },
30340 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001b211, 0x0001b211, 0x0001b211 },
30341 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
30342 - { 0x0000a324, 0x00021092, 0x00021092, 0x00022411, 0x00022411, 0x00022411 },
30343 - { 0x0000a328, 0x0002510a, 0x0002510a, 0x00025413, 0x00025413, 0x00025413 },
30344 - { 0x0000a32c, 0x0002910c, 0x0002910c, 0x00029811, 0x00029811, 0x00029811 },
30345 - { 0x0000a330, 0x0002c18b, 0x0002c18b, 0x0002c813, 0x0002c813, 0x0002c813 },
30346 - { 0x0000a334, 0x0002f1cc, 0x0002f1cc, 0x00030a14, 0x00030a14, 0x00030a14 },
30347 - { 0x0000a338, 0x000321eb, 0x000321eb, 0x00035a50, 0x00035a50, 0x00035a50 },
30348 - { 0x0000a33c, 0x000341ec, 0x000341ec, 0x00039c4c, 0x00039c4c, 0x00039c4c },
30349 - { 0x0000a340, 0x000341ec, 0x000341ec, 0x0003de8a, 0x0003de8a, 0x0003de8a },
30350 - { 0x0000a344, 0x000341ec, 0x000341ec, 0x00042e92, 0x00042e92, 0x00042e92 },
30351 - { 0x0000a348, 0x000341ec, 0x000341ec, 0x00046ed2, 0x00046ed2, 0x00046ed2 },
30352 - { 0x0000a34c, 0x000341ec, 0x000341ec, 0x0004bed5, 0x0004bed5, 0x0004bed5 },
30353 - { 0x0000a350, 0x000341ec, 0x000341ec, 0x0004ff54, 0x0004ff54, 0x0004ff54 },
30354 - { 0x0000a354, 0x000341ec, 0x000341ec, 0x00055fd5, 0x00055fd5, 0x00055fd5 },
30355 - { 0x00007814, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
30356 - { 0x00007838, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff, 0x00198eff },
30357 - { 0x0000781c, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
30358 - { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
30359 - { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
30360 - { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
30361 -};
30362 -
30363 -static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
30364 - { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
30365 - { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
30366 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30367 - { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
30368 - { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
30369 - { 0x0000a30c, 0x0000a006, 0x0000a006, 0x0000b00b, 0x0000b00b, 0x0000b00b },
30370 - { 0x0000a310, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012, 0x0000e012 },
30371 - { 0x0000a314, 0x00011014, 0x00011014, 0x00012048, 0x00012048, 0x00012048 },
30372 - { 0x0000a318, 0x0001504a, 0x0001504a, 0x0001604a, 0x0001604a, 0x0001604a },
30373 - { 0x0000a31c, 0x0001904c, 0x0001904c, 0x0001a211, 0x0001a211, 0x0001a211 },
30374 - { 0x0000a320, 0x0001c04e, 0x0001c04e, 0x0001e213, 0x0001e213, 0x0001e213 },
30375 - { 0x0000a324, 0x00020092, 0x00020092, 0x0002121b, 0x0002121b, 0x0002121b },
30376 - { 0x0000a328, 0x0002410a, 0x0002410a, 0x00024412, 0x00024412, 0x00024412 },
30377 - { 0x0000a32c, 0x0002710c, 0x0002710c, 0x00028414, 0x00028414, 0x00028414 },
30378 - { 0x0000a330, 0x0002b18b, 0x0002b18b, 0x0002b44a, 0x0002b44a, 0x0002b44a },
30379 - { 0x0000a334, 0x0002e1cc, 0x0002e1cc, 0x00030649, 0x00030649, 0x00030649 },
30380 - { 0x0000a338, 0x000321ec, 0x000321ec, 0x0003364b, 0x0003364b, 0x0003364b },
30381 - { 0x0000a33c, 0x000321ec, 0x000321ec, 0x00038a49, 0x00038a49, 0x00038a49 },
30382 - { 0x0000a340, 0x000321ec, 0x000321ec, 0x0003be48, 0x0003be48, 0x0003be48 },
30383 - { 0x0000a344, 0x000321ec, 0x000321ec, 0x0003ee4a, 0x0003ee4a, 0x0003ee4a },
30384 - { 0x0000a348, 0x000321ec, 0x000321ec, 0x00042e88, 0x00042e88, 0x00042e88 },
30385 - { 0x0000a34c, 0x000321ec, 0x000321ec, 0x00046e8a, 0x00046e8a, 0x00046e8a },
30386 - { 0x0000a350, 0x000321ec, 0x000321ec, 0x00049ec9, 0x00049ec9, 0x00049ec9 },
30387 - { 0x0000a354, 0x000321ec, 0x000321ec, 0x0004bf42, 0x0004bf42, 0x0004bf42 },
30388 - { 0x00007814, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
30389 - { 0x00007838, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff, 0x0019beff },
30390 - { 0x0000781c, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
30391 - { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
30392 - { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
30393 - { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
30394 -};
30395 -
30396 -static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
30397 - {0x00004040, 0x9248fd00 },
30398 - {0x00004040, 0x24924924 },
30399 - {0x00004040, 0xa8000019 },
30400 - {0x00004040, 0x13160820 },
30401 - {0x00004040, 0xe5980560 },
30402 - {0x00004040, 0xc01dcffc },
30403 - {0x00004040, 0x1aaabe41 },
30404 - {0x00004040, 0xbe105554 },
30405 - {0x00004040, 0x00043007 },
30406 - {0x00004044, 0x00000000 },
30407 -};
30408 -
30409 -static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
30410 - {0x00004040, 0x9248fd00 },
30411 - {0x00004040, 0x24924924 },
30412 - {0x00004040, 0xa8000019 },
30413 - {0x00004040, 0x13160820 },
30414 - {0x00004040, 0xe5980560 },
30415 - {0x00004040, 0xc01dcffd },
30416 - {0x00004040, 0x1aaabe41 },
30417 - {0x00004040, 0xbe105554 },
30418 - {0x00004040, 0x00043007 },
30419 - {0x00004044, 0x00000000 },
30420 -};
30421 -
30422 -/* AR9285 Revsion 10*/
30423 -static const u_int32_t ar9285Modes_9285[][6] = {
30424 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
30425 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
30426 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
30427 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
30428 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
30429 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
30430 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
30431 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
30432 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
30433 - { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30434 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
30435 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
30436 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
30437 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
30438 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
30439 - { 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
30440 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
30441 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
30442 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
30443 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
30444 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
30445 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
30446 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
30447 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
30448 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
30449 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
30450 - { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
30451 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30452 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30453 - { 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
30454 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
30455 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
30456 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
30457 - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
30458 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
30459 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
30460 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30461 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30462 - { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
30463 - { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
30464 - { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
30465 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
30466 - { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
30467 - { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
30468 - { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
30469 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
30470 - { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
30471 - { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
30472 - { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
30473 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
30474 - { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
30475 - { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
30476 - { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
30477 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
30478 - { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
30479 - { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
30480 - { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
30481 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
30482 - { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
30483 - { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
30484 - { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
30485 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
30486 - { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
30487 - { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
30488 - { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
30489 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
30490 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
30491 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
30492 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
30493 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
30494 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
30495 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
30496 - { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
30497 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
30498 - { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
30499 - { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
30500 - { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
30501 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
30502 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
30503 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
30504 - { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
30505 - { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
30506 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
30507 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
30508 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
30509 - { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
30510 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
30511 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
30512 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
30513 - { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
30514 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
30515 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
30516 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
30517 - { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
30518 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
30519 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
30520 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
30521 - { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
30522 - { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
30523 - { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
30524 - { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
30525 - { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
30526 - { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
30527 - { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
30528 - { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
30529 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
30530 - { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
30531 - { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
30532 - { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
30533 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
30534 - { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
30535 - { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
30536 - { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
30537 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
30538 - { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
30539 - { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
30540 - { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
30541 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
30542 - { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
30543 - { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
30544 - { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
30545 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
30546 - { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
30547 - { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
30548 - { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
30549 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
30550 - { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
30551 - { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30552 - { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30553 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30554 - { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30555 - { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30556 - { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30557 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30558 - { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30559 - { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30560 - { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30561 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30562 - { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30563 - { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30564 - { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30565 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30566 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30567 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30568 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30569 - { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30570 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30571 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30572 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30573 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30574 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30575 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30576 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30577 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30578 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30579 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30580 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30581 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30582 - { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30583 - { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30584 - { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30585 - { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30586 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30587 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30588 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30589 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
30590 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
30591 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
30592 - { 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
30593 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
30594 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
30595 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
30596 - { 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
30597 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
30598 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
30599 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
30600 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
30601 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
30602 - { 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
30603 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
30604 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
30605 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
30606 - { 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
30607 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
30608 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
30609 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
30610 - { 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
30611 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
30612 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
30613 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
30614 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
30615 - { 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
30616 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
30617 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
30618 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
30619 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
30620 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
30621 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
30622 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
30623 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
30624 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
30625 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
30626 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
30627 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
30628 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
30629 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
30630 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
30631 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
30632 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
30633 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
30634 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
30635 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
30636 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
30637 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
30638 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
30639 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
30640 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
30641 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
30642 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
30643 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
30644 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
30645 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
30646 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
30647 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
30648 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
30649 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
30650 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
30651 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
30652 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
30653 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
30654 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
30655 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
30656 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
30657 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
30658 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
30659 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
30660 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
30661 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
30662 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
30663 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
30664 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
30665 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
30666 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
30667 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
30668 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
30669 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
30670 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
30671 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
30672 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
30673 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
30674 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
30675 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
30676 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
30677 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
30678 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
30679 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30680 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30681 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30682 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30683 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30684 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30685 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30686 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30687 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30688 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30689 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30690 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30691 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30692 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30693 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30694 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30695 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30696 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30697 - { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30698 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30699 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30700 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30701 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30702 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30703 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30704 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30705 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30706 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30707 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30708 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30709 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30710 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30711 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30712 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30713 - { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30714 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30715 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30716 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30717 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
30718 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
30719 - { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
30720 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
30721 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
30722 - { 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
30723 - { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
30724 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
30725 - { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
30726 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
30727 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
30728 - { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
30729 - { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
30730 - { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
30731 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
30732 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
30733 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
30734 - { 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
30735 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
30736 - { 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
30737 - { 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
30738 - { 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
30739 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
30740 - { 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
30741 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
30742 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
30743 -};
30744 -
30745 -static const u_int32_t ar9285Common_9285[][2] = {
30746 - { 0x0000000c, 0x00000000 },
30747 - { 0x00000030, 0x00020045 },
30748 - { 0x00000034, 0x00000005 },
30749 - { 0x00000040, 0x00000000 },
30750 - { 0x00000044, 0x00000008 },
30751 - { 0x00000048, 0x00000008 },
30752 - { 0x0000004c, 0x00000010 },
30753 - { 0x00000050, 0x00000000 },
30754 - { 0x00000054, 0x0000001f },
30755 - { 0x00000800, 0x00000000 },
30756 - { 0x00000804, 0x00000000 },
30757 - { 0x00000808, 0x00000000 },
30758 - { 0x0000080c, 0x00000000 },
30759 - { 0x00000810, 0x00000000 },
30760 - { 0x00000814, 0x00000000 },
30761 - { 0x00000818, 0x00000000 },
30762 - { 0x0000081c, 0x00000000 },
30763 - { 0x00000820, 0x00000000 },
30764 - { 0x00000824, 0x00000000 },
30765 - { 0x00001040, 0x002ffc0f },
30766 - { 0x00001044, 0x002ffc0f },
30767 - { 0x00001048, 0x002ffc0f },
30768 - { 0x0000104c, 0x002ffc0f },
30769 - { 0x00001050, 0x002ffc0f },
30770 - { 0x00001054, 0x002ffc0f },
30771 - { 0x00001058, 0x002ffc0f },
30772 - { 0x0000105c, 0x002ffc0f },
30773 - { 0x00001060, 0x002ffc0f },
30774 - { 0x00001064, 0x002ffc0f },
30775 - { 0x00001230, 0x00000000 },
30776 - { 0x00001270, 0x00000000 },
30777 - { 0x00001038, 0x00000000 },
30778 - { 0x00001078, 0x00000000 },
30779 - { 0x000010b8, 0x00000000 },
30780 - { 0x000010f8, 0x00000000 },
30781 - { 0x00001138, 0x00000000 },
30782 - { 0x00001178, 0x00000000 },
30783 - { 0x000011b8, 0x00000000 },
30784 - { 0x000011f8, 0x00000000 },
30785 - { 0x00001238, 0x00000000 },
30786 - { 0x00001278, 0x00000000 },
30787 - { 0x000012b8, 0x00000000 },
30788 - { 0x000012f8, 0x00000000 },
30789 - { 0x00001338, 0x00000000 },
30790 - { 0x00001378, 0x00000000 },
30791 - { 0x000013b8, 0x00000000 },
30792 - { 0x000013f8, 0x00000000 },
30793 - { 0x00001438, 0x00000000 },
30794 - { 0x00001478, 0x00000000 },
30795 - { 0x000014b8, 0x00000000 },
30796 - { 0x000014f8, 0x00000000 },
30797 - { 0x00001538, 0x00000000 },
30798 - { 0x00001578, 0x00000000 },
30799 - { 0x000015b8, 0x00000000 },
30800 - { 0x000015f8, 0x00000000 },
30801 - { 0x00001638, 0x00000000 },
30802 - { 0x00001678, 0x00000000 },
30803 - { 0x000016b8, 0x00000000 },
30804 - { 0x000016f8, 0x00000000 },
30805 - { 0x00001738, 0x00000000 },
30806 - { 0x00001778, 0x00000000 },
30807 - { 0x000017b8, 0x00000000 },
30808 - { 0x000017f8, 0x00000000 },
30809 - { 0x0000103c, 0x00000000 },
30810 - { 0x0000107c, 0x00000000 },
30811 - { 0x000010bc, 0x00000000 },
30812 - { 0x000010fc, 0x00000000 },
30813 - { 0x0000113c, 0x00000000 },
30814 - { 0x0000117c, 0x00000000 },
30815 - { 0x000011bc, 0x00000000 },
30816 - { 0x000011fc, 0x00000000 },
30817 - { 0x0000123c, 0x00000000 },
30818 - { 0x0000127c, 0x00000000 },
30819 - { 0x000012bc, 0x00000000 },
30820 - { 0x000012fc, 0x00000000 },
30821 - { 0x0000133c, 0x00000000 },
30822 - { 0x0000137c, 0x00000000 },
30823 - { 0x000013bc, 0x00000000 },
30824 - { 0x000013fc, 0x00000000 },
30825 - { 0x0000143c, 0x00000000 },
30826 - { 0x0000147c, 0x00000000 },
30827 - { 0x00004030, 0x00000002 },
30828 - { 0x0000403c, 0x00000002 },
30829 - { 0x00004024, 0x0000001f },
30830 - { 0x00004060, 0x00000000 },
30831 - { 0x00004064, 0x00000000 },
30832 - { 0x00007010, 0x00000031 },
30833 - { 0x00007034, 0x00000002 },
30834 - { 0x00007038, 0x000004c2 },
30835 - { 0x00008004, 0x00000000 },
30836 - { 0x00008008, 0x00000000 },
30837 - { 0x0000800c, 0x00000000 },
30838 - { 0x00008018, 0x00000700 },
30839 - { 0x00008020, 0x00000000 },
30840 - { 0x00008038, 0x00000000 },
30841 - { 0x0000803c, 0x00000000 },
30842 - { 0x00008048, 0x00000000 },
30843 - { 0x00008054, 0x00000000 },
30844 - { 0x00008058, 0x00000000 },
30845 - { 0x0000805c, 0x000fc78f },
30846 - { 0x00008060, 0x0000000f },
30847 - { 0x00008064, 0x00000000 },
30848 - { 0x00008070, 0x00000000 },
30849 - { 0x000080c0, 0x2a80001a },
30850 - { 0x000080c4, 0x05dc01e0 },
30851 - { 0x000080c8, 0x1f402710 },
30852 - { 0x000080cc, 0x01f40000 },
30853 - { 0x000080d0, 0x00001e00 },
30854 - { 0x000080d4, 0x00000000 },
30855 - { 0x000080d8, 0x00400000 },
30856 - { 0x000080e0, 0xffffffff },
30857 - { 0x000080e4, 0x0000ffff },
30858 - { 0x000080e8, 0x003f3f3f },
30859 - { 0x000080ec, 0x00000000 },
30860 - { 0x000080f0, 0x00000000 },
30861 - { 0x000080f4, 0x00000000 },
30862 - { 0x000080f8, 0x00000000 },
30863 - { 0x000080fc, 0x00020000 },
30864 - { 0x00008100, 0x00020000 },
30865 - { 0x00008104, 0x00000001 },
30866 - { 0x00008108, 0x00000052 },
30867 - { 0x0000810c, 0x00000000 },
30868 - { 0x00008110, 0x00000168 },
30869 - { 0x00008118, 0x000100aa },
30870 - { 0x0000811c, 0x00003210 },
30871 - { 0x00008120, 0x08f04800 },
30872 - { 0x00008124, 0x00000000 },
30873 - { 0x00008128, 0x00000000 },
30874 - { 0x0000812c, 0x00000000 },
30875 - { 0x00008130, 0x00000000 },
30876 - { 0x00008134, 0x00000000 },
30877 - { 0x00008138, 0x00000000 },
30878 - { 0x0000813c, 0x00000000 },
30879 - { 0x00008144, 0x00000000 },
30880 - { 0x00008168, 0x00000000 },
30881 - { 0x0000816c, 0x00000000 },
30882 - { 0x00008170, 0x32143320 },
30883 - { 0x00008174, 0xfaa4fa50 },
30884 - { 0x00008178, 0x00000100 },
30885 - { 0x0000817c, 0x00000000 },
30886 - { 0x000081c0, 0x00000000 },
30887 - { 0x000081d0, 0x00003210 },
30888 - { 0x000081ec, 0x00000000 },
30889 - { 0x000081f0, 0x00000000 },
30890 - { 0x000081f4, 0x00000000 },
30891 - { 0x000081f8, 0x00000000 },
30892 - { 0x000081fc, 0x00000000 },
30893 - { 0x00008200, 0x00000000 },
30894 - { 0x00008204, 0x00000000 },
30895 - { 0x00008208, 0x00000000 },
30896 - { 0x0000820c, 0x00000000 },
30897 - { 0x00008210, 0x00000000 },
30898 - { 0x00008214, 0x00000000 },
30899 - { 0x00008218, 0x00000000 },
30900 - { 0x0000821c, 0x00000000 },
30901 - { 0x00008220, 0x00000000 },
30902 - { 0x00008224, 0x00000000 },
30903 - { 0x00008228, 0x00000000 },
30904 - { 0x0000822c, 0x00000000 },
30905 - { 0x00008230, 0x00000000 },
30906 - { 0x00008234, 0x00000000 },
30907 - { 0x00008238, 0x00000000 },
30908 - { 0x0000823c, 0x00000000 },
30909 - { 0x00008240, 0x00100000 },
30910 - { 0x00008244, 0x0010f400 },
30911 - { 0x00008248, 0x00000100 },
30912 - { 0x0000824c, 0x0001e800 },
30913 - { 0x00008250, 0x00000000 },
30914 - { 0x00008254, 0x00000000 },
30915 - { 0x00008258, 0x00000000 },
30916 - { 0x0000825c, 0x400000ff },
30917 - { 0x00008260, 0x00080922 },
30918 - { 0x00008264, 0xa8a00010 },
30919 - { 0x00008270, 0x00000000 },
30920 - { 0x00008274, 0x40000000 },
30921 - { 0x00008278, 0x003e4180 },
30922 - { 0x0000827c, 0x00000000 },
30923 - { 0x00008284, 0x0000002c },
30924 - { 0x00008288, 0x0000002c },
30925 - { 0x0000828c, 0x00000000 },
30926 - { 0x00008294, 0x00000000 },
30927 - { 0x00008298, 0x00000000 },
30928 - { 0x0000829c, 0x00000000 },
30929 - { 0x00008300, 0x00000040 },
30930 - { 0x00008314, 0x00000000 },
30931 - { 0x00008328, 0x00000000 },
30932 - { 0x0000832c, 0x00000001 },
30933 - { 0x00008330, 0x00000302 },
30934 - { 0x00008334, 0x00000e00 },
30935 - { 0x00008338, 0x00000000 },
30936 - { 0x0000833c, 0x00000000 },
30937 - { 0x00008340, 0x00010380 },
30938 - { 0x00008344, 0x00481043 },
30939 - { 0x00009808, 0x00000000 },
30940 - { 0x0000980c, 0xafe68e30 },
30941 - { 0x00009810, 0xfd14e000 },
30942 - { 0x00009814, 0x9c0a9f6b },
30943 - { 0x0000981c, 0x00000000 },
30944 - { 0x0000982c, 0x0000a000 },
30945 - { 0x00009830, 0x00000000 },
30946 - { 0x0000983c, 0x00200400 },
30947 - { 0x0000984c, 0x0040233c },
30948 - { 0x00009854, 0x00000044 },
30949 - { 0x00009900, 0x00000000 },
30950 - { 0x00009904, 0x00000000 },
30951 - { 0x00009908, 0x00000000 },
30952 - { 0x0000990c, 0x00000000 },
30953 - { 0x00009910, 0x01002310 },
30954 - { 0x0000991c, 0x10000fff },
30955 - { 0x00009920, 0x04900000 },
30956 - { 0x00009928, 0x00000001 },
30957 - { 0x0000992c, 0x00000004 },
30958 - { 0x00009934, 0x1e1f2022 },
30959 - { 0x00009938, 0x0a0b0c0d },
30960 - { 0x0000993c, 0x00000000 },
30961 - { 0x00009940, 0x14750604 },
30962 - { 0x00009948, 0x9280c00a },
30963 - { 0x0000994c, 0x00020028 },
30964 - { 0x00009954, 0x5f3ca3de },
30965 - { 0x00009958, 0x2108ecff },
30966 - { 0x00009968, 0x000003ce },
30967 - { 0x00009970, 0x1927b515 },
30968 - { 0x00009974, 0x00000000 },
30969 - { 0x00009978, 0x00000001 },
30970 - { 0x0000997c, 0x00000000 },
30971 - { 0x00009980, 0x00000000 },
30972 - { 0x00009984, 0x00000000 },
30973 - { 0x00009988, 0x00000000 },
30974 - { 0x0000998c, 0x00000000 },
30975 - { 0x00009990, 0x00000000 },
30976 - { 0x00009994, 0x00000000 },
30977 - { 0x00009998, 0x00000000 },
30978 - { 0x0000999c, 0x00000000 },
30979 - { 0x000099a0, 0x00000000 },
30980 - { 0x000099a4, 0x00000001 },
30981 - { 0x000099a8, 0x201fff00 },
30982 - { 0x000099ac, 0x2def0a00 },
30983 - { 0x000099b0, 0x03051000 },
30984 - { 0x000099b4, 0x00000820 },
30985 - { 0x000099dc, 0x00000000 },
30986 - { 0x000099e0, 0x00000000 },
30987 - { 0x000099e4, 0xaaaaaaaa },
30988 - { 0x000099e8, 0x3c466478 },
30989 - { 0x000099ec, 0x0cc80caa },
30990 - { 0x000099f0, 0x00000000 },
30991 - { 0x0000a208, 0x803e6788 },
30992 - { 0x0000a210, 0x4080a333 },
30993 - { 0x0000a214, 0x00206c10 },
30994 - { 0x0000a218, 0x009c4060 },
30995 - { 0x0000a220, 0x01834061 },
30996 - { 0x0000a224, 0x00000400 },
30997 - { 0x0000a228, 0x000003b5 },
30998 - { 0x0000a22c, 0x00000000 },
30999 - { 0x0000a234, 0x20202020 },
31000 - { 0x0000a238, 0x20202020 },
31001 - { 0x0000a244, 0x00000000 },
31002 - { 0x0000a248, 0xfffffffc },
31003 - { 0x0000a24c, 0x00000000 },
31004 - { 0x0000a254, 0x00000000 },
31005 - { 0x0000a258, 0x0ccb5380 },
31006 - { 0x0000a25c, 0x15151501 },
31007 - { 0x0000a260, 0xdfa90f01 },
31008 - { 0x0000a268, 0x00000000 },
31009 - { 0x0000a26c, 0x0ebae9e6 },
31010 - { 0x0000d270, 0x0d820820 },
31011 - { 0x0000a278, 0x39ce739c },
31012 - { 0x0000a27c, 0x050e039c },
31013 - { 0x0000d35c, 0x07ffffef },
31014 - { 0x0000d360, 0x0fffffe7 },
31015 - { 0x0000d364, 0x17ffffe5 },
31016 - { 0x0000d368, 0x1fffffe4 },
31017 - { 0x0000d36c, 0x37ffffe3 },
31018 - { 0x0000d370, 0x3fffffe3 },
31019 - { 0x0000d374, 0x57ffffe3 },
31020 - { 0x0000d378, 0x5fffffe2 },
31021 - { 0x0000d37c, 0x7fffffe2 },
31022 - { 0x0000d380, 0x7f3c7bba },
31023 - { 0x0000d384, 0xf3307ff0 },
31024 - { 0x0000a388, 0x0c000000 },
31025 - { 0x0000a38c, 0x20202020 },
31026 - { 0x0000a390, 0x20202020 },
31027 - { 0x0000a394, 0x39ce739c },
31028 - { 0x0000a398, 0x0000039c },
31029 - { 0x0000a39c, 0x00000001 },
31030 - { 0x0000a3a0, 0x00000000 },
31031 - { 0x0000a3a4, 0x00000000 },
31032 - { 0x0000a3a8, 0x00000000 },
31033 - { 0x0000a3ac, 0x00000000 },
31034 - { 0x0000a3b0, 0x00000000 },
31035 - { 0x0000a3b4, 0x00000000 },
31036 - { 0x0000a3b8, 0x00000000 },
31037 - { 0x0000a3bc, 0x00000000 },
31038 - { 0x0000a3c0, 0x00000000 },
31039 - { 0x0000a3c4, 0x00000000 },
31040 - { 0x0000a3cc, 0x20202020 },
31041 - { 0x0000a3d0, 0x20202020 },
31042 - { 0x0000a3d4, 0x20202020 },
31043 - { 0x0000a3dc, 0x39ce739c },
31044 - { 0x0000a3e0, 0x0000039c },
31045 - { 0x0000a3e4, 0x00000000 },
31046 - { 0x0000a3e8, 0x18c43433 },
31047 - { 0x0000a3ec, 0x00f70081 },
31048 - { 0x00007800, 0x00140000 },
31049 - { 0x00007804, 0x0e4548d8 },
31050 - { 0x00007808, 0x54214514 },
31051 - { 0x0000780c, 0x02025820 },
31052 - { 0x00007810, 0x71c0d388 },
31053 - { 0x00007814, 0x924934a8 },
31054 - { 0x0000781c, 0x00000000 },
31055 - { 0x00007820, 0x00000c04 },
31056 - { 0x00007824, 0x00d86fff },
31057 - { 0x00007828, 0x26d2491b },
31058 - { 0x0000782c, 0x6e36d97b },
31059 - { 0x00007830, 0xedb6d96c },
31060 - { 0x00007834, 0x71400086 },
31061 - { 0x00007838, 0xfac68800 },
31062 - { 0x0000783c, 0x0001fffe },
31063 - { 0x00007840, 0xffeb1a20 },
31064 - { 0x00007844, 0x000c0db6 },
31065 - { 0x00007848, 0x6db61b6f },
31066 - { 0x0000784c, 0x6d9b66db },
31067 - { 0x00007850, 0x6d8c6dba },
31068 - { 0x00007854, 0x00040000 },
31069 - { 0x00007858, 0xdb003012 },
31070 - { 0x0000785c, 0x04924914 },
31071 - { 0x00007860, 0x21084210 },
31072 - { 0x00007864, 0xf7d7ffde },
31073 - { 0x00007868, 0xc2034080 },
31074 - { 0x0000786c, 0x48609eb4 },
31075 - { 0x00007870, 0x10142c00 },
31076 -};
31077 -
31078 -static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
31079 - {0x00004040, 0x9248fd00 },
31080 - {0x00004040, 0x24924924 },
31081 - {0x00004040, 0xa8000019 },
31082 - {0x00004040, 0x13160820 },
31083 - {0x00004040, 0xe5980560 },
31084 - {0x00004040, 0xc01dcffd },
31085 - {0x00004040, 0x1aaabe41 },
31086 - {0x00004040, 0xbe105554 },
31087 - {0x00004040, 0x00043007 },
31088 - {0x00004044, 0x00000000 },
31089 -};
31090 -
31091 -static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
31092 - {0x00004040, 0x9248fd00 },
31093 - {0x00004040, 0x24924924 },
31094 - {0x00004040, 0xa8000019 },
31095 - {0x00004040, 0x13160820 },
31096 - {0x00004040, 0xe5980560 },
31097 - {0x00004040, 0xc01dcffc },
31098 - {0x00004040, 0x1aaabe41 },
31099 - {0x00004040, 0xbe105554 },
31100 - {0x00004040, 0x00043007 },
31101 - {0x00004044, 0x00000000 },
31102 -};
31103 -
31104 -/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
31105 -static const u_int32_t ar9285Modes_9285_1_2[][6] = {
31106 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
31107 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
31108 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
31109 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
31110 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
31111 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
31112 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
31113 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
31114 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
31115 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
31116 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
31117 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
31118 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
31119 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
31120 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
31121 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
31122 - { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
31123 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
31124 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
31125 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
31126 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
31127 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
31128 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
31129 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
31130 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
31131 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
31132 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
31133 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
31134 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
31135 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31136 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31137 - { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
31138 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
31139 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
31140 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
31141 - { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
31142 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
31143 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
31144 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31145 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31146 - { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
31147 - { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
31148 - { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
31149 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
31150 - { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
31151 - { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
31152 - { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
31153 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
31154 - { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
31155 - { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
31156 - { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
31157 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
31158 - { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
31159 - { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
31160 - { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
31161 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
31162 - { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
31163 - { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
31164 - { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
31165 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
31166 - { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
31167 - { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
31168 - { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
31169 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
31170 - { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
31171 - { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
31172 - { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
31173 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
31174 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
31175 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
31176 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
31177 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
31178 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
31179 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
31180 - { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
31181 - { 0x00009a8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
31182 - { 0x00009a90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
31183 - { 0x00009a94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
31184 - { 0x00009a98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
31185 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
31186 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
31187 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
31188 - { 0x00009aa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
31189 - { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
31190 - { 0x00009ab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
31191 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
31192 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
31193 - { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
31194 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
31195 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
31196 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
31197 - { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
31198 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
31199 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
31200 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
31201 - { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
31202 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
31203 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
31204 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
31205 - { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
31206 - { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
31207 - { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
31208 - { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
31209 - { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
31210 - { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
31211 - { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
31212 - { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
31213 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
31214 - { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
31215 - { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
31216 - { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
31217 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
31218 - { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
31219 - { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
31220 - { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
31221 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
31222 - { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
31223 - { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
31224 - { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
31225 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
31226 - { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
31227 - { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
31228 - { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
31229 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
31230 - { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
31231 - { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
31232 - { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
31233 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
31234 - { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
31235 - { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31236 - { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31237 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31238 - { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31239 - { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31240 - { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31241 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31242 - { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31243 - { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31244 - { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31245 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31246 - { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31247 - { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31248 - { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31249 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31250 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31251 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31252 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31253 - { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31254 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31255 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31256 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31257 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31258 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31259 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31260 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31261 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31262 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31263 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31264 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31265 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31266 - { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31267 - { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31268 - { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31269 - { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31270 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31271 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31272 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31273 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31274 - { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
31275 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
31276 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
31277 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
31278 - { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
31279 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
31280 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
31281 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
31282 - { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
31283 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
31284 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
31285 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
31286 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
31287 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
31288 - { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
31289 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
31290 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
31291 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
31292 - { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
31293 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
31294 - { 0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
31295 - { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
31296 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
31297 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
31298 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
31299 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
31300 - { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
31301 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
31302 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
31303 - { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
31304 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
31305 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
31306 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
31307 - { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
31308 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
31309 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
31310 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
31311 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
31312 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
31313 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
31314 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
31315 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
31316 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
31317 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
31318 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
31319 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
31320 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
31321 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
31322 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
31323 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
31324 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
31325 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
31326 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
31327 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
31328 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
31329 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
31330 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
31331 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
31332 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
31333 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
31334 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
31335 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
31336 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
31337 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
31338 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
31339 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
31340 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
31341 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
31342 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
31343 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
31344 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
31345 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
31346 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
31347 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
31348 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
31349 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
31350 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
31351 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
31352 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
31353 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
31354 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
31355 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
31356 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
31357 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
31358 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
31359 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
31360 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
31361 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
31362 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
31363 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31364 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31365 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31366 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31367 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31368 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31369 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31370 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31371 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31372 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31373 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31374 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31375 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31376 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31377 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31378 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31379 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31380 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31381 - { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31382 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31383 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31384 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31385 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31386 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31387 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31388 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31389 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31390 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31391 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31392 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31393 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31394 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31395 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31396 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31397 - { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31398 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31399 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31400 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31401 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
31402 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
31403 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
31404 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
31405 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
31406 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
31407 - { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
31408 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
31409 -};
31410 -
31411 -static const u_int32_t ar9285Common_9285_1_2[][2] = {
31412 - { 0x0000000c, 0x00000000 },
31413 - { 0x00000030, 0x00020045 },
31414 - { 0x00000034, 0x00000005 },
31415 - { 0x00000040, 0x00000000 },
31416 - { 0x00000044, 0x00000008 },
31417 - { 0x00000048, 0x00000008 },
31418 - { 0x0000004c, 0x00000010 },
31419 - { 0x00000050, 0x00000000 },
31420 - { 0x00000054, 0x0000001f },
31421 - { 0x00000800, 0x00000000 },
31422 - { 0x00000804, 0x00000000 },
31423 - { 0x00000808, 0x00000000 },
31424 - { 0x0000080c, 0x00000000 },
31425 - { 0x00000810, 0x00000000 },
31426 - { 0x00000814, 0x00000000 },
31427 - { 0x00000818, 0x00000000 },
31428 - { 0x0000081c, 0x00000000 },
31429 - { 0x00000820, 0x00000000 },
31430 - { 0x00000824, 0x00000000 },
31431 - { 0x00001040, 0x002ffc0f },
31432 - { 0x00001044, 0x002ffc0f },
31433 - { 0x00001048, 0x002ffc0f },
31434 - { 0x0000104c, 0x002ffc0f },
31435 - { 0x00001050, 0x002ffc0f },
31436 - { 0x00001054, 0x002ffc0f },
31437 - { 0x00001058, 0x002ffc0f },
31438 - { 0x0000105c, 0x002ffc0f },
31439 - { 0x00001060, 0x002ffc0f },
31440 - { 0x00001064, 0x002ffc0f },
31441 - { 0x00001230, 0x00000000 },
31442 - { 0x00001270, 0x00000000 },
31443 - { 0x00001038, 0x00000000 },
31444 - { 0x00001078, 0x00000000 },
31445 - { 0x000010b8, 0x00000000 },
31446 - { 0x000010f8, 0x00000000 },
31447 - { 0x00001138, 0x00000000 },
31448 - { 0x00001178, 0x00000000 },
31449 - { 0x000011b8, 0x00000000 },
31450 - { 0x000011f8, 0x00000000 },
31451 - { 0x00001238, 0x00000000 },
31452 - { 0x00001278, 0x00000000 },
31453 - { 0x000012b8, 0x00000000 },
31454 - { 0x000012f8, 0x00000000 },
31455 - { 0x00001338, 0x00000000 },
31456 - { 0x00001378, 0x00000000 },
31457 - { 0x000013b8, 0x00000000 },
31458 - { 0x000013f8, 0x00000000 },
31459 - { 0x00001438, 0x00000000 },
31460 - { 0x00001478, 0x00000000 },
31461 - { 0x000014b8, 0x00000000 },
31462 - { 0x000014f8, 0x00000000 },
31463 - { 0x00001538, 0x00000000 },
31464 - { 0x00001578, 0x00000000 },
31465 - { 0x000015b8, 0x00000000 },
31466 - { 0x000015f8, 0x00000000 },
31467 - { 0x00001638, 0x00000000 },
31468 - { 0x00001678, 0x00000000 },
31469 - { 0x000016b8, 0x00000000 },
31470 - { 0x000016f8, 0x00000000 },
31471 - { 0x00001738, 0x00000000 },
31472 - { 0x00001778, 0x00000000 },
31473 - { 0x000017b8, 0x00000000 },
31474 - { 0x000017f8, 0x00000000 },
31475 - { 0x0000103c, 0x00000000 },
31476 - { 0x0000107c, 0x00000000 },
31477 - { 0x000010bc, 0x00000000 },
31478 - { 0x000010fc, 0x00000000 },
31479 - { 0x0000113c, 0x00000000 },
31480 - { 0x0000117c, 0x00000000 },
31481 - { 0x000011bc, 0x00000000 },
31482 - { 0x000011fc, 0x00000000 },
31483 - { 0x0000123c, 0x00000000 },
31484 - { 0x0000127c, 0x00000000 },
31485 - { 0x000012bc, 0x00000000 },
31486 - { 0x000012fc, 0x00000000 },
31487 - { 0x0000133c, 0x00000000 },
31488 - { 0x0000137c, 0x00000000 },
31489 - { 0x000013bc, 0x00000000 },
31490 - { 0x000013fc, 0x00000000 },
31491 - { 0x0000143c, 0x00000000 },
31492 - { 0x0000147c, 0x00000000 },
31493 - { 0x00004030, 0x00000002 },
31494 - { 0x0000403c, 0x00000002 },
31495 - { 0x00004024, 0x0000001f },
31496 - { 0x00004060, 0x00000000 },
31497 - { 0x00004064, 0x00000000 },
31498 - { 0x00007010, 0x00000031 },
31499 - { 0x00007034, 0x00000002 },
31500 - { 0x00007038, 0x000004c2 },
31501 - { 0x00008004, 0x00000000 },
31502 - { 0x00008008, 0x00000000 },
31503 - { 0x0000800c, 0x00000000 },
31504 - { 0x00008018, 0x00000700 },
31505 - { 0x00008020, 0x00000000 },
31506 - { 0x00008038, 0x00000000 },
31507 - { 0x0000803c, 0x00000000 },
31508 - { 0x00008048, 0x00000000 },
31509 - { 0x00008054, 0x00000000 },
31510 - { 0x00008058, 0x00000000 },
31511 - { 0x0000805c, 0x000fc78f },
31512 - { 0x00008060, 0x0000000f },
31513 - { 0x00008064, 0x00000000 },
31514 - { 0x00008070, 0x00000000 },
31515 - { 0x000080c0, 0x2a80001a },
31516 - { 0x000080c4, 0x05dc01e0 },
31517 - { 0x000080c8, 0x1f402710 },
31518 - { 0x000080cc, 0x01f40000 },
31519 - { 0x000080d0, 0x00001e00 },
31520 - { 0x000080d4, 0x00000000 },
31521 - { 0x000080d8, 0x00400000 },
31522 - { 0x000080e0, 0xffffffff },
31523 - { 0x000080e4, 0x0000ffff },
31524 - { 0x000080e8, 0x003f3f3f },
31525 - { 0x000080ec, 0x00000000 },
31526 - { 0x000080f0, 0x00000000 },
31527 - { 0x000080f4, 0x00000000 },
31528 - { 0x000080f8, 0x00000000 },
31529 - { 0x000080fc, 0x00020000 },
31530 - { 0x00008100, 0x00020000 },
31531 - { 0x00008104, 0x00000001 },
31532 - { 0x00008108, 0x00000052 },
31533 - { 0x0000810c, 0x00000000 },
31534 - { 0x00008110, 0x00000168 },
31535 - { 0x00008118, 0x000100aa },
31536 - { 0x0000811c, 0x00003210 },
31537 - { 0x00008120, 0x08f04810 },
31538 - { 0x00008124, 0x00000000 },
31539 - { 0x00008128, 0x00000000 },
31540 - { 0x0000812c, 0x00000000 },
31541 - { 0x00008130, 0x00000000 },
31542 - { 0x00008134, 0x00000000 },
31543 - { 0x00008138, 0x00000000 },
31544 - { 0x0000813c, 0x00000000 },
31545 - { 0x00008144, 0xffffffff },
31546 - { 0x00008168, 0x00000000 },
31547 - { 0x0000816c, 0x00000000 },
31548 - { 0x00008170, 0x32143320 },
31549 - { 0x00008174, 0xfaa4fa50 },
31550 - { 0x00008178, 0x00000100 },
31551 - { 0x0000817c, 0x00000000 },
31552 - { 0x000081c0, 0x00000000 },
31553 - { 0x000081d0, 0x0000320a },
31554 - { 0x000081ec, 0x00000000 },
31555 - { 0x000081f0, 0x00000000 },
31556 - { 0x000081f4, 0x00000000 },
31557 - { 0x000081f8, 0x00000000 },
31558 - { 0x000081fc, 0x00000000 },
31559 - { 0x00008200, 0x00000000 },
31560 - { 0x00008204, 0x00000000 },
31561 - { 0x00008208, 0x00000000 },
31562 - { 0x0000820c, 0x00000000 },
31563 - { 0x00008210, 0x00000000 },
31564 - { 0x00008214, 0x00000000 },
31565 - { 0x00008218, 0x00000000 },
31566 - { 0x0000821c, 0x00000000 },
31567 - { 0x00008220, 0x00000000 },
31568 - { 0x00008224, 0x00000000 },
31569 - { 0x00008228, 0x00000000 },
31570 - { 0x0000822c, 0x00000000 },
31571 - { 0x00008230, 0x00000000 },
31572 - { 0x00008234, 0x00000000 },
31573 - { 0x00008238, 0x00000000 },
31574 - { 0x0000823c, 0x00000000 },
31575 - { 0x00008240, 0x00100000 },
31576 - { 0x00008244, 0x0010f400 },
31577 - { 0x00008248, 0x00000100 },
31578 - { 0x0000824c, 0x0001e800 },
31579 - { 0x00008250, 0x00000000 },
31580 - { 0x00008254, 0x00000000 },
31581 - { 0x00008258, 0x00000000 },
31582 - { 0x0000825c, 0x400000ff },
31583 - { 0x00008260, 0x00080922 },
31584 - { 0x00008264, 0x88a00010 },
31585 - { 0x00008270, 0x00000000 },
31586 - { 0x00008274, 0x40000000 },
31587 - { 0x00008278, 0x003e4180 },
31588 - { 0x0000827c, 0x00000000 },
31589 - { 0x00008284, 0x0000002c },
31590 - { 0x00008288, 0x0000002c },
31591 - { 0x0000828c, 0x00000000 },
31592 - { 0x00008294, 0x00000000 },
31593 - { 0x00008298, 0x00000000 },
31594 - { 0x0000829c, 0x00000000 },
31595 - { 0x00008300, 0x00000040 },
31596 - { 0x00008314, 0x00000000 },
31597 - { 0x00008328, 0x00000000 },
31598 - { 0x0000832c, 0x00000001 },
31599 - { 0x00008330, 0x00000302 },
31600 - { 0x00008334, 0x00000e00 },
31601 - { 0x00008338, 0x00ff0000 },
31602 - { 0x0000833c, 0x00000000 },
31603 - { 0x00008340, 0x00010380 },
31604 - { 0x00008344, 0x00481043 },
31605 - { 0x00009808, 0x00000000 },
31606 - { 0x0000980c, 0xafe68e30 },
31607 - { 0x00009810, 0xfd14e000 },
31608 - { 0x00009814, 0x9c0a9f6b },
31609 - { 0x0000981c, 0x00000000 },
31610 - { 0x0000982c, 0x0000a000 },
31611 - { 0x00009830, 0x00000000 },
31612 - { 0x0000983c, 0x00200400 },
31613 - { 0x0000984c, 0x0040233c },
31614 - { 0x00009854, 0x00000044 },
31615 - { 0x00009900, 0x00000000 },
31616 - { 0x00009904, 0x00000000 },
31617 - { 0x00009908, 0x00000000 },
31618 - { 0x0000990c, 0x00000000 },
31619 - { 0x00009910, 0x01002310 },
31620 - { 0x0000991c, 0x10000fff },
31621 - { 0x00009920, 0x04900000 },
31622 - { 0x00009928, 0x00000001 },
31623 - { 0x0000992c, 0x00000004 },
31624 - { 0x00009934, 0x1e1f2022 },
31625 - { 0x00009938, 0x0a0b0c0d },
31626 - { 0x0000993c, 0x00000000 },
31627 - { 0x00009940, 0x14750604 },
31628 - { 0x00009948, 0x9280c00a },
31629 - { 0x0000994c, 0x00020028 },
31630 - { 0x00009954, 0x5f3ca3de },
31631 - { 0x00009958, 0x2108ecff },
31632 - { 0x00009968, 0x000003ce },
31633 - { 0x00009970, 0x192bb514 },
31634 - { 0x00009974, 0x00000000 },
31635 - { 0x00009978, 0x00000001 },
31636 - { 0x0000997c, 0x00000000 },
31637 - { 0x00009980, 0x00000000 },
31638 - { 0x00009984, 0x00000000 },
31639 - { 0x00009988, 0x00000000 },
31640 - { 0x0000998c, 0x00000000 },
31641 - { 0x00009990, 0x00000000 },
31642 - { 0x00009994, 0x00000000 },
31643 - { 0x00009998, 0x00000000 },
31644 - { 0x0000999c, 0x00000000 },
31645 - { 0x000099a0, 0x00000000 },
31646 - { 0x000099a4, 0x00000001 },
31647 - { 0x000099a8, 0x201fff00 },
31648 - { 0x000099ac, 0x2def0400 },
31649 - { 0x000099b0, 0x03051000 },
31650 - { 0x000099b4, 0x00000820 },
31651 - { 0x000099dc, 0x00000000 },
31652 - { 0x000099e0, 0x00000000 },
31653 - { 0x000099e4, 0xaaaaaaaa },
31654 - { 0x000099e8, 0x3c466478 },
31655 - { 0x000099ec, 0x0cc80caa },
31656 - { 0x000099f0, 0x00000000 },
31657 - { 0x0000a208, 0x803e68c8 },
31658 - { 0x0000a210, 0x4080a333 },
31659 - { 0x0000a214, 0x00206c10 },
31660 - { 0x0000a218, 0x009c4060 },
31661 - { 0x0000a220, 0x01834061 },
31662 - { 0x0000a224, 0x00000400 },
31663 - { 0x0000a228, 0x000003b5 },
31664 - { 0x0000a22c, 0x00000000 },
31665 - { 0x0000a234, 0x20202020 },
31666 - { 0x0000a238, 0x20202020 },
31667 - { 0x0000a244, 0x00000000 },
31668 - { 0x0000a248, 0xfffffffc },
31669 - { 0x0000a24c, 0x00000000 },
31670 - { 0x0000a254, 0x00000000 },
31671 - { 0x0000a258, 0x0ccb5380 },
31672 - { 0x0000a25c, 0x15151501 },
31673 - { 0x0000a260, 0xdfa90f01 },
31674 - { 0x0000a268, 0x00000000 },
31675 - { 0x0000a26c, 0x0ebae9e6 },
31676 - { 0x0000d270, 0x0d820820 },
31677 - { 0x0000d35c, 0x07ffffef },
31678 - { 0x0000d360, 0x0fffffe7 },
31679 - { 0x0000d364, 0x17ffffe5 },
31680 - { 0x0000d368, 0x1fffffe4 },
31681 - { 0x0000d36c, 0x37ffffe3 },
31682 - { 0x0000d370, 0x3fffffe3 },
31683 - { 0x0000d374, 0x57ffffe3 },
31684 - { 0x0000d378, 0x5fffffe2 },
31685 - { 0x0000d37c, 0x7fffffe2 },
31686 - { 0x0000d380, 0x7f3c7bba },
31687 - { 0x0000d384, 0xf3307ff0 },
31688 - { 0x0000a388, 0x0c000000 },
31689 - { 0x0000a38c, 0x20202020 },
31690 - { 0x0000a390, 0x20202020 },
31691 - { 0x0000a39c, 0x00000001 },
31692 - { 0x0000a3a0, 0x00000000 },
31693 - { 0x0000a3a4, 0x00000000 },
31694 - { 0x0000a3a8, 0x00000000 },
31695 - { 0x0000a3ac, 0x00000000 },
31696 - { 0x0000a3b0, 0x00000000 },
31697 - { 0x0000a3b4, 0x00000000 },
31698 - { 0x0000a3b8, 0x00000000 },
31699 - { 0x0000a3bc, 0x00000000 },
31700 - { 0x0000a3c0, 0x00000000 },
31701 - { 0x0000a3c4, 0x00000000 },
31702 - { 0x0000a3cc, 0x20202020 },
31703 - { 0x0000a3d0, 0x20202020 },
31704 - { 0x0000a3d4, 0x20202020 },
31705 - { 0x0000a3e4, 0x00000000 },
31706 - { 0x0000a3e8, 0x18c43433 },
31707 - { 0x0000a3ec, 0x00f70081 },
31708 - { 0x00007800, 0x00140000 },
31709 - { 0x00007804, 0x0e4548d8 },
31710 - { 0x00007808, 0x54214514 },
31711 - { 0x0000780c, 0x02025830 },
31712 - { 0x00007810, 0x71c0d388 },
31713 - { 0x0000781c, 0x00000000 },
31714 - { 0x00007824, 0x00d86fff },
31715 - { 0x0000782c, 0x6e36d97b },
31716 - { 0x00007834, 0x71400087 },
31717 - { 0x00007844, 0x000c0db6 },
31718 - { 0x00007848, 0x6db6246f },
31719 - { 0x0000784c, 0x6d9b66db },
31720 - { 0x00007850, 0x6d8c6dba },
31721 - { 0x00007854, 0x00040000 },
31722 - { 0x00007858, 0xdb003012 },
31723 - { 0x0000785c, 0x04924914 },
31724 - { 0x00007860, 0x21084210 },
31725 - { 0x00007864, 0xf7d7ffde },
31726 - { 0x00007868, 0xc2034080 },
31727 - { 0x00007870, 0x10142c00 },
31728 -};
31729 -
31730 -static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
31731 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
31732 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31733 - { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
31734 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
31735 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
31736 - { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
31737 - { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
31738 - { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
31739 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
31740 - { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
31741 - { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
31742 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
31743 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
31744 - { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
31745 - { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
31746 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31747 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31748 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31749 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31750 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31751 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31752 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31753 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31754 - { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
31755 - { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
31756 - { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
31757 - { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
31758 - { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
31759 - { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
31760 - { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
31761 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
31762 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
31763 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31764 - { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
31765 - { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31766 - { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
31767 - { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31768 - { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
31769 -};
31770 -
31771 -static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
31772 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
31773 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31774 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
31775 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
31776 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
31777 - { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
31778 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
31779 - { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
31780 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
31781 - { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
31782 - { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
31783 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
31784 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
31785 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
31786 - { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
31787 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31788 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31789 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31790 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31791 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31792 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31793 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31794 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31795 - { 0x00007814, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8, 0x924934a8 },
31796 - { 0x00007828, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b, 0x26d2491b },
31797 - { 0x00007830, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e, 0xedb6d96e },
31798 - { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
31799 - { 0x0000783c, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe, 0x0001fffe },
31800 - { 0x00007840, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20, 0xffeb1a20 },
31801 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
31802 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
31803 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
31804 - { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31805 - { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
31806 - { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31807 - { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
31808 - { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31809 - { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
31810 -};
31811 -
31812 -static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
31813 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31814 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
31815 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
31816 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
31817 - { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
31818 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
31819 - { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
31820 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
31821 - { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
31822 - { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
31823 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
31824 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
31825 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
31826 - { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
31827 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31828 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31829 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31830 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31831 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31832 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31833 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31834 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31835 - { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
31836 - { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
31837 - { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6dbae },
31838 - { 0x00007838, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441, 0xdac71441 },
31839 - { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
31840 - { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
31841 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
31842 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
31843 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
31844 - { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31845 - { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
31846 - { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31847 - { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
31848 - { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
31849 - { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
31850 -};
31851 -
31852 -static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
31853 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31854 - { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
31855 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
31856 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
31857 - { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
31858 - { 0x0000a314, 0x00000000, 0x00000000, 0x0000f600, 0x0000f600, 0x00000000 },
31859 - { 0x0000a318, 0x00000000, 0x00000000, 0x00012800, 0x00012800, 0x00000000 },
31860 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00016802, 0x00016802, 0x00000000 },
31861 - { 0x0000a320, 0x00000000, 0x00000000, 0x0001b805, 0x0001b805, 0x00000000 },
31862 - { 0x0000a324, 0x00000000, 0x00000000, 0x00021a80, 0x00021a80, 0x00000000 },
31863 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028b00, 0x00028b00, 0x00000000 },
31864 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
31865 - { 0x0000a330, 0x00000000, 0x00000000, 0x0002cd80, 0x0002cd80, 0x00000000 },
31866 - { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
31867 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
31868 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
31869 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31870 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31871 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31872 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31873 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31874 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
31875 - { 0x00007814, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8, 0x92497ca8 },
31876 - { 0x00007828, 0x4ad2491b, 0x4ad2491b, 0x2ad2491b, 0x4ad2491b, 0x4ad2491b },
31877 - { 0x00007830, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e, 0xedb6da6e },
31878 - { 0x00007838, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443, 0xdac71443 },
31879 - { 0x0000783c, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe, 0x2481f6fe },
31880 - { 0x00007840, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c, 0xba5f638c },
31881 - { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
31882 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
31883 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a216652, 0x0a216652, 0x0a22a652 },
31884 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31885 - { 0x0000a27c, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7, 0x050380e7 },
31886 - { 0x0000a394, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31887 - { 0x0000a398, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
31888 - { 0x0000a3dc, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
31889 - { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
31890 -};
31891 -
31892 -static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
31893 - {0x00004040, 0x9248fd00 },
31894 - {0x00004040, 0x24924924 },
31895 - {0x00004040, 0xa8000019 },
31896 - {0x00004040, 0x13160820 },
31897 - {0x00004040, 0xe5980560 },
31898 - {0x00004040, 0xc01dcffd },
31899 - {0x00004040, 0x1aaabe41 },
31900 - {0x00004040, 0xbe105554 },
31901 - {0x00004040, 0x00043007 },
31902 - {0x00004044, 0x00000000 },
31903 -};
31904 -
31905 -static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
31906 - {0x00004040, 0x9248fd00 },
31907 - {0x00004040, 0x24924924 },
31908 - {0x00004040, 0xa8000019 },
31909 - {0x00004040, 0x13160820 },
31910 - {0x00004040, 0xe5980560 },
31911 - {0x00004040, 0xc01dcffc },
31912 - {0x00004040, 0x1aaabe41 },
31913 - {0x00004040, 0xbe105554 },
31914 - {0x00004040, 0x00043007 },
31915 - {0x00004044, 0x00000000 },
31916 -};
31917 -
31918 -/* AR9287 Revision 10 */
31919 -static const u_int32_t ar9287Modes_9287_1_0[][6] = {
31920 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
31921 - { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
31922 - { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
31923 - { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
31924 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
31925 - { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
31926 - { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
31927 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
31928 - { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
31929 - { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
31930 - { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
31931 - { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
31932 - { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
31933 - { 0x00009828, 0x00000000, 0x00000000, 0x0a020001, 0x0a020001, 0x0a020001 },
31934 - { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
31935 - { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
31936 - { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
31937 - { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
31938 - { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
31939 - { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
31940 - { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
31941 - { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
31942 - { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
31943 - { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
31944 - { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
31945 - { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
31946 - { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
31947 - { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
31948 - { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
31949 - { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
31950 - { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
31951 - { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
31952 - { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
31953 - { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
31954 - { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
31955 - { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
31956 - { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
31957 - { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31958 - { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31959 - { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
31960 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
31961 - { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
31962 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
31963 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
31964 -};
31965 -
31966 -static const u_int32_t ar9287Common_9287_1_0[][2] = {
31967 - { 0x0000000c, 0x00000000 },
31968 - { 0x00000030, 0x00020015 },
31969 - { 0x00000034, 0x00000005 },
31970 - { 0x00000040, 0x00000000 },
31971 - { 0x00000044, 0x00000008 },
31972 - { 0x00000048, 0x00000008 },
31973 - { 0x0000004c, 0x00000010 },
31974 - { 0x00000050, 0x00000000 },
31975 - { 0x00000054, 0x0000001f },
31976 - { 0x00000800, 0x00000000 },
31977 - { 0x00000804, 0x00000000 },
31978 - { 0x00000808, 0x00000000 },
31979 - { 0x0000080c, 0x00000000 },
31980 - { 0x00000810, 0x00000000 },
31981 - { 0x00000814, 0x00000000 },
31982 - { 0x00000818, 0x00000000 },
31983 - { 0x0000081c, 0x00000000 },
31984 - { 0x00000820, 0x00000000 },
31985 - { 0x00000824, 0x00000000 },
31986 - { 0x00001040, 0x002ffc0f },
31987 - { 0x00001044, 0x002ffc0f },
31988 - { 0x00001048, 0x002ffc0f },
31989 - { 0x0000104c, 0x002ffc0f },
31990 - { 0x00001050, 0x002ffc0f },
31991 - { 0x00001054, 0x002ffc0f },
31992 - { 0x00001058, 0x002ffc0f },
31993 - { 0x0000105c, 0x002ffc0f },
31994 - { 0x00001060, 0x002ffc0f },
31995 - { 0x00001064, 0x002ffc0f },
31996 - { 0x00001230, 0x00000000 },
31997 - { 0x00001270, 0x00000000 },
31998 - { 0x00001038, 0x00000000 },
31999 - { 0x00001078, 0x00000000 },
32000 - { 0x000010b8, 0x00000000 },
32001 - { 0x000010f8, 0x00000000 },
32002 - { 0x00001138, 0x00000000 },
32003 - { 0x00001178, 0x00000000 },
32004 - { 0x000011b8, 0x00000000 },
32005 - { 0x000011f8, 0x00000000 },
32006 - { 0x00001238, 0x00000000 },
32007 - { 0x00001278, 0x00000000 },
32008 - { 0x000012b8, 0x00000000 },
32009 - { 0x000012f8, 0x00000000 },
32010 - { 0x00001338, 0x00000000 },
32011 - { 0x00001378, 0x00000000 },
32012 - { 0x000013b8, 0x00000000 },
32013 - { 0x000013f8, 0x00000000 },
32014 - { 0x00001438, 0x00000000 },
32015 - { 0x00001478, 0x00000000 },
32016 - { 0x000014b8, 0x00000000 },
32017 - { 0x000014f8, 0x00000000 },
32018 - { 0x00001538, 0x00000000 },
32019 - { 0x00001578, 0x00000000 },
32020 - { 0x000015b8, 0x00000000 },
32021 - { 0x000015f8, 0x00000000 },
32022 - { 0x00001638, 0x00000000 },
32023 - { 0x00001678, 0x00000000 },
32024 - { 0x000016b8, 0x00000000 },
32025 - { 0x000016f8, 0x00000000 },
32026 - { 0x00001738, 0x00000000 },
32027 - { 0x00001778, 0x00000000 },
32028 - { 0x000017b8, 0x00000000 },
32029 - { 0x000017f8, 0x00000000 },
32030 - { 0x0000103c, 0x00000000 },
32031 - { 0x0000107c, 0x00000000 },
32032 - { 0x000010bc, 0x00000000 },
32033 - { 0x000010fc, 0x00000000 },
32034 - { 0x0000113c, 0x00000000 },
32035 - { 0x0000117c, 0x00000000 },
32036 - { 0x000011bc, 0x00000000 },
32037 - { 0x000011fc, 0x00000000 },
32038 - { 0x0000123c, 0x00000000 },
32039 - { 0x0000127c, 0x00000000 },
32040 - { 0x000012bc, 0x00000000 },
32041 - { 0x000012fc, 0x00000000 },
32042 - { 0x0000133c, 0x00000000 },
32043 - { 0x0000137c, 0x00000000 },
32044 - { 0x000013bc, 0x00000000 },
32045 - { 0x000013fc, 0x00000000 },
32046 - { 0x0000143c, 0x00000000 },
32047 - { 0x0000147c, 0x00000000 },
32048 - { 0x00004030, 0x00000002 },
32049 - { 0x0000403c, 0x00000002 },
32050 - { 0x00004024, 0x0000001f },
32051 - { 0x00004060, 0x00000000 },
32052 - { 0x00004064, 0x00000000 },
32053 - { 0x00007010, 0x00000033 },
32054 - { 0x00007020, 0x00000000 },
32055 - { 0x00007034, 0x00000002 },
32056 - { 0x00007038, 0x000004c2 },
32057 - { 0x00008004, 0x00000000 },
32058 - { 0x00008008, 0x00000000 },
32059 - { 0x0000800c, 0x00000000 },
32060 - { 0x00008018, 0x00000700 },
32061 - { 0x00008020, 0x00000000 },
32062 - { 0x00008038, 0x00000000 },
32063 - { 0x0000803c, 0x00000000 },
32064 - { 0x00008048, 0x40000000 },
32065 - { 0x00008054, 0x00000000 },
32066 - { 0x00008058, 0x00000000 },
32067 - { 0x0000805c, 0x000fc78f },
32068 - { 0x00008060, 0x0000000f },
32069 - { 0x00008064, 0x00000000 },
32070 - { 0x00008070, 0x00000000 },
32071 - { 0x000080c0, 0x2a80001a },
32072 - { 0x000080c4, 0x05dc01e0 },
32073 - { 0x000080c8, 0x1f402710 },
32074 - { 0x000080cc, 0x01f40000 },
32075 - { 0x000080d0, 0x00001e00 },
32076 - { 0x000080d4, 0x00000000 },
32077 - { 0x000080d8, 0x00400000 },
32078 - { 0x000080e0, 0xffffffff },
32079 - { 0x000080e4, 0x0000ffff },
32080 - { 0x000080e8, 0x003f3f3f },
32081 - { 0x000080ec, 0x00000000 },
32082 - { 0x000080f0, 0x00000000 },
32083 - { 0x000080f4, 0x00000000 },
32084 - { 0x000080f8, 0x00000000 },
32085 - { 0x000080fc, 0x00020000 },
32086 - { 0x00008100, 0x00020000 },
32087 - { 0x00008104, 0x00000001 },
32088 - { 0x00008108, 0x00000052 },
32089 - { 0x0000810c, 0x00000000 },
32090 - { 0x00008110, 0x00000168 },
32091 - { 0x00008118, 0x000100aa },
32092 - { 0x0000811c, 0x00003210 },
32093 - { 0x00008124, 0x00000000 },
32094 - { 0x00008128, 0x00000000 },
32095 - { 0x0000812c, 0x00000000 },
32096 - { 0x00008130, 0x00000000 },
32097 - { 0x00008134, 0x00000000 },
32098 - { 0x00008138, 0x00000000 },
32099 - { 0x0000813c, 0x00000000 },
32100 - { 0x00008144, 0xffffffff },
32101 - { 0x00008168, 0x00000000 },
32102 - { 0x0000816c, 0x00000000 },
32103 - { 0x00008170, 0x18487320 },
32104 - { 0x00008174, 0xfaa4fa50 },
32105 - { 0x00008178, 0x00000100 },
32106 - { 0x0000817c, 0x00000000 },
32107 - { 0x000081c0, 0x00000000 },
32108 - { 0x000081c4, 0x00000000 },
32109 - { 0x000081d4, 0x00000000 },
32110 - { 0x000081ec, 0x00000000 },
32111 - { 0x000081f0, 0x00000000 },
32112 - { 0x000081f4, 0x00000000 },
32113 - { 0x000081f8, 0x00000000 },
32114 - { 0x000081fc, 0x00000000 },
32115 - { 0x00008200, 0x00000000 },
32116 - { 0x00008204, 0x00000000 },
32117 - { 0x00008208, 0x00000000 },
32118 - { 0x0000820c, 0x00000000 },
32119 - { 0x00008210, 0x00000000 },
32120 - { 0x00008214, 0x00000000 },
32121 - { 0x00008218, 0x00000000 },
32122 - { 0x0000821c, 0x00000000 },
32123 - { 0x00008220, 0x00000000 },
32124 - { 0x00008224, 0x00000000 },
32125 - { 0x00008228, 0x00000000 },
32126 - { 0x0000822c, 0x00000000 },
32127 - { 0x00008230, 0x00000000 },
32128 - { 0x00008234, 0x00000000 },
32129 - { 0x00008238, 0x00000000 },
32130 - { 0x0000823c, 0x00000000 },
32131 - { 0x00008240, 0x00100000 },
32132 - { 0x00008244, 0x0010f400 },
32133 - { 0x00008248, 0x00000100 },
32134 - { 0x0000824c, 0x0001e800 },
32135 - { 0x00008250, 0x00000000 },
32136 - { 0x00008254, 0x00000000 },
32137 - { 0x00008258, 0x00000000 },
32138 - { 0x0000825c, 0x400000ff },
32139 - { 0x00008260, 0x00080922 },
32140 - { 0x00008264, 0xa8a00010 },
32141 - { 0x00008270, 0x00000000 },
32142 - { 0x00008274, 0x40000000 },
32143 - { 0x00008278, 0x003e4180 },
32144 - { 0x0000827c, 0x00000000 },
32145 - { 0x00008284, 0x0000002c },
32146 - { 0x00008288, 0x0000002c },
32147 - { 0x0000828c, 0x000000ff },
32148 - { 0x00008294, 0x00000000 },
32149 - { 0x00008298, 0x00000000 },
32150 - { 0x0000829c, 0x00000000 },
32151 - { 0x00008300, 0x00000040 },
32152 - { 0x00008314, 0x00000000 },
32153 - { 0x00008328, 0x00000000 },
32154 - { 0x0000832c, 0x00000007 },
32155 - { 0x00008330, 0x00000302 },
32156 - { 0x00008334, 0x00000e00 },
32157 - { 0x00008338, 0x00ff0000 },
32158 - { 0x0000833c, 0x00000000 },
32159 - { 0x00008340, 0x000107ff },
32160 - { 0x00008344, 0x01c81043 },
32161 - { 0x00008360, 0xffffffff },
32162 - { 0x00008364, 0xffffffff },
32163 - { 0x00008368, 0x00000000 },
32164 - { 0x00008370, 0x00000000 },
32165 - { 0x00008374, 0x000000ff },
32166 - { 0x00008378, 0x00000000 },
32167 - { 0x0000837c, 0x00000000 },
32168 - { 0x00008380, 0xffffffff },
32169 - { 0x00008384, 0xffffffff },
32170 - { 0x00008390, 0x0fffffff },
32171 - { 0x00008394, 0x0fffffff },
32172 - { 0x00008398, 0x00000000 },
32173 - { 0x0000839c, 0x00000000 },
32174 - { 0x000083a0, 0x00000000 },
32175 - { 0x00009808, 0x00000000 },
32176 - { 0x0000980c, 0xafe68e30 },
32177 - { 0x00009810, 0xfd14e000 },
32178 - { 0x00009814, 0x9c0a9f6b },
32179 - { 0x0000981c, 0x00000000 },
32180 - { 0x0000982c, 0x0000a000 },
32181 - { 0x00009830, 0x00000000 },
32182 - { 0x0000983c, 0x00200400 },
32183 - { 0x0000984c, 0x0040233c },
32184 - { 0x0000a84c, 0x0040233c },
32185 - { 0x00009854, 0x00000044 },
32186 - { 0x00009900, 0x00000000 },
32187 - { 0x00009904, 0x00000000 },
32188 - { 0x00009908, 0x00000000 },
32189 - { 0x0000990c, 0x00000000 },
32190 - { 0x00009910, 0x10002310 },
32191 - { 0x0000991c, 0x10000fff },
32192 - { 0x00009920, 0x04900000 },
32193 - { 0x0000a920, 0x04900000 },
32194 - { 0x00009928, 0x00000001 },
32195 - { 0x0000992c, 0x00000004 },
32196 - { 0x00009930, 0x00000000 },
32197 - { 0x0000a930, 0x00000000 },
32198 - { 0x00009934, 0x1e1f2022 },
32199 - { 0x00009938, 0x0a0b0c0d },
32200 - { 0x0000993c, 0x00000000 },
32201 - { 0x00009948, 0x9280c00a },
32202 - { 0x0000994c, 0x00020028 },
32203 - { 0x00009954, 0x5f3ca3de },
32204 - { 0x00009958, 0x0108ecff },
32205 - { 0x00009940, 0x14750604 },
32206 - { 0x0000c95c, 0x004b6a8e },
32207 - { 0x00009970, 0x990bb515 },
32208 - { 0x00009974, 0x00000000 },
32209 - { 0x00009978, 0x00000001 },
32210 - { 0x0000997c, 0x00000000 },
32211 - { 0x000099a0, 0x00000000 },
32212 - { 0x000099a4, 0x00000001 },
32213 - { 0x000099a8, 0x201fff00 },
32214 - { 0x000099ac, 0x0c6f0000 },
32215 - { 0x000099b0, 0x03051000 },
32216 - { 0x000099b4, 0x00000820 },
32217 - { 0x000099c4, 0x06336f77 },
32218 - { 0x000099c8, 0x6af65329 },
32219 - { 0x000099cc, 0x08f186c8 },
32220 - { 0x000099d0, 0x00046384 },
32221 - { 0x000099dc, 0x00000000 },
32222 - { 0x000099e0, 0x00000000 },
32223 - { 0x000099e4, 0xaaaaaaaa },
32224 - { 0x000099e8, 0x3c466478 },
32225 - { 0x000099ec, 0x0cc80caa },
32226 - { 0x000099f0, 0x00000000 },
32227 - { 0x000099fc, 0x00001042 },
32228 - { 0x0000a1f4, 0x00fffeff },
32229 - { 0x0000a1f8, 0x00f5f9ff },
32230 - { 0x0000a1fc, 0xb79f6427 },
32231 - { 0x0000a208, 0x803e4788 },
32232 - { 0x0000a210, 0x4080a333 },
32233 - { 0x0000a214, 0x40206c10 },
32234 - { 0x0000a218, 0x009c4060 },
32235 - { 0x0000a220, 0x01834061 },
32236 - { 0x0000a224, 0x00000400 },
32237 - { 0x0000a228, 0x000003b5 },
32238 - { 0x0000a22c, 0x233f7180 },
32239 - { 0x0000a234, 0x20202020 },
32240 - { 0x0000a238, 0x20202020 },
32241 - { 0x0000a23c, 0x13c889af },
32242 - { 0x0000a240, 0x38490a20 },
32243 - { 0x0000a244, 0x00000000 },
32244 - { 0x0000a248, 0xfffffffc },
32245 - { 0x0000a24c, 0x00000000 },
32246 - { 0x0000a254, 0x00000000 },
32247 - { 0x0000a258, 0x0cdbd380 },
32248 - { 0x0000a25c, 0x0f0f0f01 },
32249 - { 0x0000a260, 0xdfa91f01 },
32250 - { 0x0000a264, 0x00418a11 },
32251 - { 0x0000b264, 0x00418a11 },
32252 - { 0x0000a268, 0x00000000 },
32253 - { 0x0000a26c, 0x0e79e5c6 },
32254 - { 0x0000b26c, 0x0e79e5c6 },
32255 - { 0x0000d270, 0x00820820 },
32256 - { 0x0000a278, 0x1ce739ce },
32257 - { 0x0000a27c, 0x050701ce },
32258 - { 0x0000d35c, 0x07ffffef },
32259 - { 0x0000d360, 0x0fffffe7 },
32260 - { 0x0000d364, 0x17ffffe5 },
32261 - { 0x0000d368, 0x1fffffe4 },
32262 - { 0x0000d36c, 0x37ffffe3 },
32263 - { 0x0000d370, 0x3fffffe3 },
32264 - { 0x0000d374, 0x57ffffe3 },
32265 - { 0x0000d378, 0x5fffffe2 },
32266 - { 0x0000d37c, 0x7fffffe2 },
32267 - { 0x0000d380, 0x7f3c7bba },
32268 - { 0x0000d384, 0xf3307ff0 },
32269 - { 0x0000a388, 0x0c000000 },
32270 - { 0x0000a38c, 0x20202020 },
32271 - { 0x0000a390, 0x20202020 },
32272 - { 0x0000a394, 0x1ce739ce },
32273 - { 0x0000a398, 0x000001ce },
32274 - { 0x0000b398, 0x000001ce },
32275 - { 0x0000a39c, 0x00000001 },
32276 - { 0x0000a3c8, 0x00000246 },
32277 - { 0x0000a3cc, 0x20202020 },
32278 - { 0x0000a3d0, 0x20202020 },
32279 - { 0x0000a3d4, 0x20202020 },
32280 - { 0x0000a3dc, 0x1ce739ce },
32281 - { 0x0000a3e0, 0x000001ce },
32282 - { 0x0000a3e4, 0x00000000 },
32283 - { 0x0000a3e8, 0x18c43433 },
32284 - { 0x0000a3ec, 0x00f70081 },
32285 - { 0x0000a3f0, 0x01036a1e },
32286 - { 0x0000a3f4, 0x00000000 },
32287 - { 0x0000b3f4, 0x00000000 },
32288 - { 0x0000a7d8, 0x00000001 },
32289 - { 0x00007800, 0x00000800 },
32290 - { 0x00007804, 0x6c35ffb0 },
32291 - { 0x00007808, 0x6db6c000 },
32292 - { 0x0000780c, 0x6db6cb30 },
32293 - { 0x00007810, 0x6db6cb6c },
32294 - { 0x00007814, 0x0501e200 },
32295 - { 0x00007818, 0x0094128d },
32296 - { 0x0000781c, 0x976ee392 },
32297 - { 0x00007820, 0xf75ff6fc },
32298 - { 0x00007824, 0x00040000 },
32299 - { 0x00007828, 0xdb003012 },
32300 - { 0x0000782c, 0x04924914 },
32301 - { 0x00007830, 0x21084210 },
32302 - { 0x00007834, 0x00140000 },
32303 - { 0x00007838, 0x0e4548d8 },
32304 - { 0x0000783c, 0x54214514 },
32305 - { 0x00007840, 0x02025820 },
32306 - { 0x00007844, 0x71c0d388 },
32307 - { 0x00007848, 0x934934a8 },
32308 - { 0x00007850, 0x00000000 },
32309 - { 0x00007854, 0x00000800 },
32310 - { 0x00007858, 0x6c35ffb0 },
32311 - { 0x0000785c, 0x6db6c000 },
32312 - { 0x00007860, 0x6db6cb2c },
32313 - { 0x00007864, 0x6db6cb6c },
32314 - { 0x00007868, 0x0501e200 },
32315 - { 0x0000786c, 0x0094128d },
32316 - { 0x00007870, 0x976ee392 },
32317 - { 0x00007874, 0xf75ff6fc },
32318 - { 0x00007878, 0x00040000 },
32319 - { 0x0000787c, 0xdb003012 },
32320 - { 0x00007880, 0x04924914 },
32321 - { 0x00007884, 0x21084210 },
32322 - { 0x00007888, 0x001b6db0 },
32323 - { 0x0000788c, 0x00376b63 },
32324 - { 0x00007890, 0x06db6db6 },
32325 - { 0x00007894, 0x006d8000 },
32326 - { 0x00007898, 0x48100000 },
32327 - { 0x0000789c, 0x00000000 },
32328 - { 0x000078a0, 0x08000000 },
32329 - { 0x000078a4, 0x0007ffd8 },
32330 - { 0x000078a8, 0x0007ffd8 },
32331 - { 0x000078ac, 0x001c0020 },
32332 - { 0x000078b0, 0x000611eb },
32333 - { 0x000078b4, 0x40008080 },
32334 - { 0x000078b8, 0x2a850160 },
32335 -};
32336 -
32337 -static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
32338 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
32339 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32340 - { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
32341 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
32342 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
32343 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
32344 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
32345 - { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
32346 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
32347 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
32348 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
32349 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
32350 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
32351 - { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
32352 - { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
32353 - { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
32354 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
32355 - { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
32356 - { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
32357 - { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
32358 - { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
32359 - { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
32360 - { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
32361 - { 0x0000a780, 0x00000000, 0x00000000, 0x00000060, 0x00000060, 0x00000060 },
32362 - { 0x0000a784, 0x00000000, 0x00000000, 0x00004062, 0x00004062, 0x00004062 },
32363 - { 0x0000a788, 0x00000000, 0x00000000, 0x00008064, 0x00008064, 0x00008064 },
32364 - { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0a4, 0x0000c0a4, 0x0000c0a4 },
32365 - { 0x0000a790, 0x00000000, 0x00000000, 0x000100b0, 0x000100b0, 0x000100b0 },
32366 - { 0x0000a794, 0x00000000, 0x00000000, 0x000140b2, 0x000140b2, 0x000140b2 },
32367 - { 0x0000a798, 0x00000000, 0x00000000, 0x000180b4, 0x000180b4, 0x000180b4 },
32368 - { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c0f4, 0x0001c0f4, 0x0001c0f4 },
32369 - { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020134, 0x00020134, 0x00020134 },
32370 - { 0x0000a7a4, 0x00000000, 0x00000000, 0x000240fe, 0x000240fe, 0x000240fe },
32371 - { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002813e, 0x0002813e, 0x0002813e },
32372 - { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c17e, 0x0002c17e, 0x0002c17e },
32373 - { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301be, 0x000301be, 0x000301be },
32374 - { 0x0000a7b4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32375 - { 0x0000a7b8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32376 - { 0x0000a7bc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32377 - { 0x0000a7c0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32378 - { 0x0000a7c4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32379 - { 0x0000a7c8, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32380 - { 0x0000a7cc, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32381 - { 0x0000a7d0, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32382 - { 0x0000a7d4, 0x00000000, 0x00000000, 0x000341fe, 0x000341fe, 0x000341fe },
32383 - { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
32384 -};
32385 -
32386 -
32387 -static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
32388 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
32389 - { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
32390 - { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
32391 - { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
32392 - { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
32393 - { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
32394 - { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
32395 - { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
32396 - { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
32397 - { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
32398 - { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
32399 - { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
32400 - { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
32401 - { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
32402 - { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
32403 - { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
32404 - { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
32405 - { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
32406 - { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
32407 - { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
32408 - { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
32409 - { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
32410 - { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
32411 - { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
32412 - { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
32413 - { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
32414 - { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
32415 - { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
32416 - { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
32417 - { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
32418 - { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
32419 - { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
32420 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
32421 - { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
32422 - { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
32423 - { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
32424 - { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
32425 - { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
32426 - { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
32427 - { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
32428 - { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
32429 - { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
32430 - { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
32431 - { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
32432 - { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
32433 - { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
32434 - { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
32435 - { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
32436 - { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
32437 - { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
32438 - { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
32439 - { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
32440 - { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
32441 - { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
32442 - { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
32443 - { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
32444 - { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
32445 - { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
32446 - { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
32447 - { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
32448 - { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
32449 - { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
32450 - { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
32451 - { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
32452 - { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
32453 - { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
32454 - { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
32455 - { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
32456 - { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
32457 - { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
32458 - { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
32459 - { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
32460 - { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
32461 - { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
32462 - { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
32463 - { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
32464 - { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
32465 - { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
32466 - { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
32467 - { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
32468 - { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
32469 - { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
32470 - { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
32471 - { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
32472 - { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
32473 - { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
32474 - { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
32475 - { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
32476 - { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
32477 - { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
32478 - { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
32479 - { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
32480 - { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
32481 - { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
32482 - { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
32483 - { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
32484 - { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
32485 - { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
32486 - { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
32487 - { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
32488 - { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
32489 - { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
32490 - { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
32491 - { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
32492 - { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32493 - { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32494 - { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32495 - { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32496 - { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32497 - { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32498 - { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32499 - { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32500 - { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32501 - { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32502 - { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32503 - { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32504 - { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32505 - { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32506 - { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32507 - { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32508 - { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32509 - { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32510 - { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32511 - { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32512 - { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32513 - { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32514 - { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32515 - { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32516 - { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32517 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
32518 - { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
32519 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
32520 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
32521 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
32522 - { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
32523 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
32524 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
32525 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
32526 - { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
32527 - { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
32528 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
32529 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
32530 - { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
32531 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
32532 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
32533 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
32534 - { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
32535 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
32536 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
32537 - { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
32538 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
32539 - { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
32540 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
32541 - { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
32542 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
32543 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
32544 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
32545 - { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
32546 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
32547 - { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
32548 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
32549 - { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
32550 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
32551 - { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
32552 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
32553 - { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
32554 - { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
32555 - { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
32556 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
32557 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
32558 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
32559 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
32560 - { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
32561 - { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
32562 - { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
32563 - { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
32564 - { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
32565 - { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
32566 - { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
32567 - { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
32568 - { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
32569 - { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
32570 - { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
32571 - { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
32572 - { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
32573 - { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
32574 - { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
32575 - { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
32576 - { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
32577 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
32578 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
32579 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
32580 - { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
32581 - { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
32582 - { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
32583 - { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
32584 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
32585 - { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
32586 - { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
32587 - { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
32588 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
32589 - { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
32590 - { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
32591 - { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
32592 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
32593 - { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
32594 - { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
32595 - { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
32596 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
32597 - { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
32598 - { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
32599 - { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
32600 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
32601 - { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
32602 - { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
32603 - { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
32604 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
32605 - { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
32606 - { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
32607 - { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
32608 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
32609 - { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
32610 - { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
32611 - { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
32612 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
32613 - { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
32614 - { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
32615 - { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
32616 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
32617 - { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
32618 - { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
32619 - { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
32620 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32621 - { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32622 - { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32623 - { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32624 - { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32625 - { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32626 - { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32627 - { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32628 - { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32629 - { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32630 - { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32631 - { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32632 - { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32633 - { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32634 - { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32635 - { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32636 - { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32637 - { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32638 - { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32639 - { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32640 - { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32641 - { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32642 - { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32643 - { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32644 - { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
32645 - { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
32646 - { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
32647 -};
32648 -
32649 -static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
32650 - {0x00004040, 0x9248fd00 },
32651 - {0x00004040, 0x24924924 },
32652 - {0x00004040, 0xa8000019 },
32653 - {0x00004040, 0x13160820 },
32654 - {0x00004040, 0xe5980560 },
32655 - {0x00004040, 0xc01dcffd },
32656 - {0x00004040, 0x1aaabe41 },
32657 - {0x00004040, 0xbe105554 },
32658 - {0x00004040, 0x00043007 },
32659 - {0x00004044, 0x00000000 },
32660 -};
32661 -
32662 -static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
32663 - {0x00004040, 0x9248fd00 },
32664 - {0x00004040, 0x24924924 },
32665 - {0x00004040, 0xa8000019 },
32666 - {0x00004040, 0x13160820 },
32667 - {0x00004040, 0xe5980560 },
32668 - {0x00004040, 0xc01dcffc },
32669 - {0x00004040, 0x1aaabe41 },
32670 - {0x00004040, 0xbe105554 },
32671 - {0x00004040, 0x00043007 },
32672 - {0x00004044, 0x00000000 },
32673 -};
32674 -
32675 -/* AR9287 Revision 11 */
32676 -
32677 -static const u_int32_t ar9287Modes_9287_1_1[][6] = {
32678 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
32679 - { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
32680 - { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
32681 - { 0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180 },
32682 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
32683 - { 0x00008014, 0x00000000, 0x00000000, 0x10801600, 0x08400b00, 0x06e006e0 },
32684 - { 0x0000801c, 0x00000000, 0x00000000, 0x12e00057, 0x12e0002b, 0x0988004f },
32685 - { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
32686 - { 0x000081d0, 0x00003200, 0x00003200, 0x0000320a, 0x0000320a, 0x0000320a },
32687 - { 0x00008318, 0x00000000, 0x00000000, 0x00006880, 0x00003440, 0x00006880 },
32688 - { 0x00009804, 0x00000000, 0x00000000, 0x000003c4, 0x00000300, 0x00000303 },
32689 - { 0x00009820, 0x00000000, 0x00000000, 0x02020200, 0x02020200, 0x02020200 },
32690 - { 0x00009824, 0x00000000, 0x00000000, 0x01000e0e, 0x01000e0e, 0x01000e0e },
32691 - { 0x00009828, 0x00000000, 0x00000000, 0x3a020001, 0x3a020001, 0x3a020001 },
32692 - { 0x00009834, 0x00000000, 0x00000000, 0x00000e0e, 0x00000e0e, 0x00000e0e },
32693 - { 0x00009838, 0x00000003, 0x00000003, 0x00000007, 0x00000007, 0x00000007 },
32694 - { 0x00009840, 0x206a002e, 0x206a002e, 0x206a012e, 0x206a012e, 0x206a012e },
32695 - { 0x00009844, 0x03720000, 0x03720000, 0x037216a0, 0x037216a0, 0x037216a0 },
32696 - { 0x00009850, 0x60000000, 0x60000000, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
32697 - { 0x00009858, 0x7c000d00, 0x7c000d00, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
32698 - { 0x0000985c, 0x3100005e, 0x3100005e, 0x3139605e, 0x31395d5e, 0x31395d5e },
32699 - { 0x00009860, 0x00058d00, 0x00058d00, 0x00058d20, 0x00058d20, 0x00058d18 },
32700 - { 0x00009864, 0x00000e00, 0x00000e00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
32701 - { 0x00009868, 0x000040c0, 0x000040c0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
32702 - { 0x0000986c, 0x00000080, 0x00000080, 0x06903881, 0x06903881, 0x06903881 },
32703 - { 0x00009914, 0x00000000, 0x00000000, 0x00001130, 0x00000898, 0x000007d0 },
32704 - { 0x00009918, 0x00000000, 0x00000000, 0x00000016, 0x0000000b, 0x00000016 },
32705 - { 0x00009924, 0xd00a8a01, 0xd00a8a01, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
32706 - { 0x00009944, 0xefbc0000, 0xefbc0000, 0xefbc1010, 0xefbc1010, 0xefbc1010 },
32707 - { 0x00009960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
32708 - { 0x0000a960, 0x00000000, 0x00000000, 0x00000010, 0x00000010, 0x00000010 },
32709 - { 0x00009964, 0x00000000, 0x00000000, 0x00000210, 0x00000210, 0x00000210 },
32710 - { 0x0000c968, 0x00000200, 0x00000200, 0x000003ce, 0x000003ce, 0x000003ce },
32711 - { 0x000099b8, 0x00000000, 0x00000000, 0x0000001c, 0x0000001c, 0x0000001c },
32712 - { 0x000099bc, 0x00000000, 0x00000000, 0x00000c00, 0x00000c00, 0x00000c00 },
32713 - { 0x000099c0, 0x00000000, 0x00000000, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
32714 - { 0x0000a204, 0x00000440, 0x00000440, 0x00000444, 0x00000444, 0x00000444 },
32715 - { 0x0000a20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32716 - { 0x0000b20c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32717 - { 0x0000a21c, 0x1803800a, 0x1803800a, 0x1883800a, 0x1883800a, 0x1883800a },
32718 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
32719 - { 0x0000a250, 0x00000000, 0x00000000, 0x0004a000, 0x0004a000, 0x0004a000 },
32720 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
32721 - { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
32722 -};
32723 -
32724 -static const u_int32_t ar9287Common_9287_1_1[][2] = {
32725 - { 0x0000000c, 0x00000000 },
32726 - { 0x00000030, 0x00020015 },
32727 - { 0x00000034, 0x00000005 },
32728 - { 0x00000040, 0x00000000 },
32729 - { 0x00000044, 0x00000008 },
32730 - { 0x00000048, 0x00000008 },
32731 - { 0x0000004c, 0x00000010 },
32732 - { 0x00000050, 0x00000000 },
32733 - { 0x00000054, 0x0000001f },
32734 - { 0x00000800, 0x00000000 },
32735 - { 0x00000804, 0x00000000 },
32736 - { 0x00000808, 0x00000000 },
32737 - { 0x0000080c, 0x00000000 },
32738 - { 0x00000810, 0x00000000 },
32739 - { 0x00000814, 0x00000000 },
32740 - { 0x00000818, 0x00000000 },
32741 - { 0x0000081c, 0x00000000 },
32742 - { 0x00000820, 0x00000000 },
32743 - { 0x00000824, 0x00000000 },
32744 - { 0x00001040, 0x002ffc0f },
32745 - { 0x00001044, 0x002ffc0f },
32746 - { 0x00001048, 0x002ffc0f },
32747 - { 0x0000104c, 0x002ffc0f },
32748 - { 0x00001050, 0x002ffc0f },
32749 - { 0x00001054, 0x002ffc0f },
32750 - { 0x00001058, 0x002ffc0f },
32751 - { 0x0000105c, 0x002ffc0f },
32752 - { 0x00001060, 0x002ffc0f },
32753 - { 0x00001064, 0x002ffc0f },
32754 - { 0x00001230, 0x00000000 },
32755 - { 0x00001270, 0x00000000 },
32756 - { 0x00001038, 0x00000000 },
32757 - { 0x00001078, 0x00000000 },
32758 - { 0x000010b8, 0x00000000 },
32759 - { 0x000010f8, 0x00000000 },
32760 - { 0x00001138, 0x00000000 },
32761 - { 0x00001178, 0x00000000 },
32762 - { 0x000011b8, 0x00000000 },
32763 - { 0x000011f8, 0x00000000 },
32764 - { 0x00001238, 0x00000000 },
32765 - { 0x00001278, 0x00000000 },
32766 - { 0x000012b8, 0x00000000 },
32767 - { 0x000012f8, 0x00000000 },
32768 - { 0x00001338, 0x00000000 },
32769 - { 0x00001378, 0x00000000 },
32770 - { 0x000013b8, 0x00000000 },
32771 - { 0x000013f8, 0x00000000 },
32772 - { 0x00001438, 0x00000000 },
32773 - { 0x00001478, 0x00000000 },
32774 - { 0x000014b8, 0x00000000 },
32775 - { 0x000014f8, 0x00000000 },
32776 - { 0x00001538, 0x00000000 },
32777 - { 0x00001578, 0x00000000 },
32778 - { 0x000015b8, 0x00000000 },
32779 - { 0x000015f8, 0x00000000 },
32780 - { 0x00001638, 0x00000000 },
32781 - { 0x00001678, 0x00000000 },
32782 - { 0x000016b8, 0x00000000 },
32783 - { 0x000016f8, 0x00000000 },
32784 - { 0x00001738, 0x00000000 },
32785 - { 0x00001778, 0x00000000 },
32786 - { 0x000017b8, 0x00000000 },
32787 - { 0x000017f8, 0x00000000 },
32788 - { 0x0000103c, 0x00000000 },
32789 - { 0x0000107c, 0x00000000 },
32790 - { 0x000010bc, 0x00000000 },
32791 - { 0x000010fc, 0x00000000 },
32792 - { 0x0000113c, 0x00000000 },
32793 - { 0x0000117c, 0x00000000 },
32794 - { 0x000011bc, 0x00000000 },
32795 - { 0x000011fc, 0x00000000 },
32796 - { 0x0000123c, 0x00000000 },
32797 - { 0x0000127c, 0x00000000 },
32798 - { 0x000012bc, 0x00000000 },
32799 - { 0x000012fc, 0x00000000 },
32800 - { 0x0000133c, 0x00000000 },
32801 - { 0x0000137c, 0x00000000 },
32802 - { 0x000013bc, 0x00000000 },
32803 - { 0x000013fc, 0x00000000 },
32804 - { 0x0000143c, 0x00000000 },
32805 - { 0x0000147c, 0x00000000 },
32806 - { 0x00004030, 0x00000002 },
32807 - { 0x0000403c, 0x00000002 },
32808 - { 0x00004024, 0x0000001f },
32809 - { 0x00004060, 0x00000000 },
32810 - { 0x00004064, 0x00000000 },
32811 - { 0x00007010, 0x00000033 },
32812 - { 0x00007020, 0x00000000 },
32813 - { 0x00007034, 0x00000002 },
32814 - { 0x00007038, 0x000004c2 },
32815 - { 0x00008004, 0x00000000 },
32816 - { 0x00008008, 0x00000000 },
32817 - { 0x0000800c, 0x00000000 },
32818 - { 0x00008018, 0x00000700 },
32819 - { 0x00008020, 0x00000000 },
32820 - { 0x00008038, 0x00000000 },
32821 - { 0x0000803c, 0x00000000 },
32822 - { 0x00008048, 0x40000000 },
32823 - { 0x00008054, 0x00000000 },
32824 - { 0x00008058, 0x00000000 },
32825 - { 0x0000805c, 0x000fc78f },
32826 - { 0x00008060, 0x0000000f },
32827 - { 0x00008064, 0x00000000 },
32828 - { 0x00008070, 0x00000000 },
32829 - { 0x000080c0, 0x2a80001a },
32830 - { 0x000080c4, 0x05dc01e0 },
32831 - { 0x000080c8, 0x1f402710 },
32832 - { 0x000080cc, 0x01f40000 },
32833 - { 0x000080d0, 0x00001e00 },
32834 - { 0x000080d4, 0x00000000 },
32835 - { 0x000080d8, 0x00400000 },
32836 - { 0x000080e0, 0xffffffff },
32837 - { 0x000080e4, 0x0000ffff },
32838 - { 0x000080e8, 0x003f3f3f },
32839 - { 0x000080ec, 0x00000000 },
32840 - { 0x000080f0, 0x00000000 },
32841 - { 0x000080f4, 0x00000000 },
32842 - { 0x000080f8, 0x00000000 },
32843 - { 0x000080fc, 0x00020000 },
32844 - { 0x00008100, 0x00020000 },
32845 - { 0x00008104, 0x00000001 },
32846 - { 0x00008108, 0x00000052 },
32847 - { 0x0000810c, 0x00000000 },
32848 - { 0x00008110, 0x00000168 },
32849 - { 0x00008118, 0x000100aa },
32850 - { 0x0000811c, 0x00003210 },
32851 - { 0x00008124, 0x00000000 },
32852 - { 0x00008128, 0x00000000 },
32853 - { 0x0000812c, 0x00000000 },
32854 - { 0x00008130, 0x00000000 },
32855 - { 0x00008134, 0x00000000 },
32856 - { 0x00008138, 0x00000000 },
32857 - { 0x0000813c, 0x00000000 },
32858 - { 0x00008144, 0xffffffff },
32859 - { 0x00008168, 0x00000000 },
32860 - { 0x0000816c, 0x00000000 },
32861 - { 0x00008170, 0x18487320 },
32862 - { 0x00008174, 0xfaa4fa50 },
32863 - { 0x00008178, 0x00000100 },
32864 - { 0x0000817c, 0x00000000 },
32865 - { 0x000081c0, 0x00000000 },
32866 - { 0x000081c4, 0x00000000 },
32867 - { 0x000081d4, 0x00000000 },
32868 - { 0x000081ec, 0x00000000 },
32869 - { 0x000081f0, 0x00000000 },
32870 - { 0x000081f4, 0x00000000 },
32871 - { 0x000081f8, 0x00000000 },
32872 - { 0x000081fc, 0x00000000 },
32873 - { 0x00008200, 0x00000000 },
32874 - { 0x00008204, 0x00000000 },
32875 - { 0x00008208, 0x00000000 },
32876 - { 0x0000820c, 0x00000000 },
32877 - { 0x00008210, 0x00000000 },
32878 - { 0x00008214, 0x00000000 },
32879 - { 0x00008218, 0x00000000 },
32880 - { 0x0000821c, 0x00000000 },
32881 - { 0x00008220, 0x00000000 },
32882 - { 0x00008224, 0x00000000 },
32883 - { 0x00008228, 0x00000000 },
32884 - { 0x0000822c, 0x00000000 },
32885 - { 0x00008230, 0x00000000 },
32886 - { 0x00008234, 0x00000000 },
32887 - { 0x00008238, 0x00000000 },
32888 - { 0x0000823c, 0x00000000 },
32889 - { 0x00008240, 0x00100000 },
32890 - { 0x00008244, 0x0010f400 },
32891 - { 0x00008248, 0x00000100 },
32892 - { 0x0000824c, 0x0001e800 },
32893 - { 0x00008250, 0x00000000 },
32894 - { 0x00008254, 0x00000000 },
32895 - { 0x00008258, 0x00000000 },
32896 - { 0x0000825c, 0x400000ff },
32897 - { 0x00008260, 0x00080922 },
32898 - { 0x00008264, 0x88a00010 },
32899 - { 0x00008270, 0x00000000 },
32900 - { 0x00008274, 0x40000000 },
32901 - { 0x00008278, 0x003e4180 },
32902 - { 0x0000827c, 0x00000000 },
32903 - { 0x00008284, 0x0000002c },
32904 - { 0x00008288, 0x0000002c },
32905 - { 0x0000828c, 0x000000ff },
32906 - { 0x00008294, 0x00000000 },
32907 - { 0x00008298, 0x00000000 },
32908 - { 0x0000829c, 0x00000000 },
32909 - { 0x00008300, 0x00000040 },
32910 - { 0x00008314, 0x00000000 },
32911 - { 0x00008328, 0x00000000 },
32912 - { 0x0000832c, 0x00000007 },
32913 - { 0x00008330, 0x00000302 },
32914 - { 0x00008334, 0x00000e00 },
32915 - { 0x00008338, 0x00ff0000 },
32916 - { 0x0000833c, 0x00000000 },
32917 - { 0x00008340, 0x000107ff },
32918 - { 0x00008344, 0x01c81043 },
32919 - { 0x00008360, 0xffffffff },
32920 - { 0x00008364, 0xffffffff },
32921 - { 0x00008368, 0x00000000 },
32922 - { 0x00008370, 0x00000000 },
32923 - { 0x00008374, 0x000000ff },
32924 - { 0x00008378, 0x00000000 },
32925 - { 0x0000837c, 0x00000000 },
32926 - { 0x00008380, 0xffffffff },
32927 - { 0x00008384, 0xffffffff },
32928 - { 0x00008390, 0x0fffffff },
32929 - { 0x00008394, 0x0fffffff },
32930 - { 0x00008398, 0x00000000 },
32931 - { 0x0000839c, 0x00000000 },
32932 - { 0x000083a0, 0x00000000 },
32933 - { 0x00009808, 0x00000000 },
32934 - { 0x0000980c, 0xafe68e30 },
32935 - { 0x00009810, 0xfd14e000 },
32936 - { 0x00009814, 0x9c0a9f6b },
32937 - { 0x0000981c, 0x00000000 },
32938 - { 0x0000982c, 0x0000a000 },
32939 - { 0x00009830, 0x00000000 },
32940 - { 0x0000983c, 0x00200400 },
32941 - { 0x0000984c, 0x0040233c },
32942 - { 0x0000a84c, 0x0040233c },
32943 - { 0x00009854, 0x00000044 },
32944 - { 0x00009900, 0x00000000 },
32945 - { 0x00009904, 0x00000000 },
32946 - { 0x00009908, 0x00000000 },
32947 - { 0x0000990c, 0x00000000 },
32948 - { 0x00009910, 0x10002310 },
32949 - { 0x0000991c, 0x10000fff },
32950 - { 0x00009920, 0x04900000 },
32951 - { 0x0000a920, 0x04900000 },
32952 - { 0x00009928, 0x00000001 },
32953 - { 0x0000992c, 0x00000004 },
32954 - { 0x00009930, 0x00000000 },
32955 - { 0x0000a930, 0x00000000 },
32956 - { 0x00009934, 0x1e1f2022 },
32957 - { 0x00009938, 0x0a0b0c0d },
32958 - { 0x0000993c, 0x00000000 },
32959 - { 0x00009948, 0x9280c00a },
32960 - { 0x0000994c, 0x00020028 },
32961 - { 0x00009954, 0x5f3ca3de },
32962 - { 0x00009958, 0x0108ecff },
32963 - { 0x00009940, 0x14750604 },
32964 - { 0x0000c95c, 0x004b6a8e },
32965 - { 0x00009970, 0x990bb514 },
32966 - { 0x00009974, 0x00000000 },
32967 - { 0x00009978, 0x00000001 },
32968 - { 0x0000997c, 0x00000000 },
32969 - { 0x000099a0, 0x00000000 },
32970 - { 0x000099a4, 0x00000001 },
32971 - { 0x000099a8, 0x201fff00 },
32972 - { 0x000099ac, 0x0c6f0000 },
32973 - { 0x000099b0, 0x03051000 },
32974 - { 0x000099b4, 0x00000820 },
32975 - { 0x000099c4, 0x06336f77 },
32976 - { 0x000099c8, 0x6af6532f },
32977 - { 0x000099cc, 0x08f186c8 },
32978 - { 0x000099d0, 0x00046384 },
32979 - { 0x000099dc, 0x00000000 },
32980 - { 0x000099e0, 0x00000000 },
32981 - { 0x000099e4, 0xaaaaaaaa },
32982 - { 0x000099e8, 0x3c466478 },
32983 - { 0x000099ec, 0x0cc80caa },
32984 - { 0x000099f0, 0x00000000 },
32985 - { 0x000099fc, 0x00001042 },
32986 - { 0x0000a208, 0x803e4788 },
32987 - { 0x0000a210, 0x4080a333 },
32988 - { 0x0000a214, 0x40206c10 },
32989 - { 0x0000a218, 0x009c4060 },
32990 - { 0x0000a220, 0x01834061 },
32991 - { 0x0000a224, 0x00000400 },
32992 - { 0x0000a228, 0x000003b5 },
32993 - { 0x0000a22c, 0x233f7180 },
32994 - { 0x0000a234, 0x20202020 },
32995 - { 0x0000a238, 0x20202020 },
32996 - { 0x0000a23c, 0x13c889af },
32997 - { 0x0000a240, 0x38490a20 },
32998 - { 0x0000a244, 0x00000000 },
32999 - { 0x0000a248, 0xfffffffc },
33000 - { 0x0000a24c, 0x00000000 },
33001 - { 0x0000a254, 0x00000000 },
33002 - { 0x0000a258, 0x0cdbd380 },
33003 - { 0x0000a25c, 0x0f0f0f01 },
33004 - { 0x0000a260, 0xdfa91f01 },
33005 - { 0x0000a264, 0x00418a11 },
33006 - { 0x0000b264, 0x00418a11 },
33007 - { 0x0000a268, 0x00000000 },
33008 - { 0x0000a26c, 0x0e79e5c6 },
33009 - { 0x0000b26c, 0x0e79e5c6 },
33010 - { 0x0000d270, 0x00820820 },
33011 - { 0x0000a278, 0x1ce739ce },
33012 - { 0x0000a27c, 0x050701ce },
33013 - { 0x0000d35c, 0x07ffffef },
33014 - { 0x0000d360, 0x0fffffe7 },
33015 - { 0x0000d364, 0x17ffffe5 },
33016 - { 0x0000d368, 0x1fffffe4 },
33017 - { 0x0000d36c, 0x37ffffe3 },
33018 - { 0x0000d370, 0x3fffffe3 },
33019 - { 0x0000d374, 0x57ffffe3 },
33020 - { 0x0000d378, 0x5fffffe2 },
33021 - { 0x0000d37c, 0x7fffffe2 },
33022 - { 0x0000d380, 0x7f3c7bba },
33023 - { 0x0000d384, 0xf3307ff0 },
33024 - { 0x0000a388, 0x0c000000 },
33025 - { 0x0000a38c, 0x20202020 },
33026 - { 0x0000a390, 0x20202020 },
33027 - { 0x0000a394, 0x1ce739ce },
33028 - { 0x0000a398, 0x000001ce },
33029 - { 0x0000b398, 0x000001ce },
33030 - { 0x0000a39c, 0x00000001 },
33031 - { 0x0000a3c8, 0x00000246 },
33032 - { 0x0000a3cc, 0x20202020 },
33033 - { 0x0000a3d0, 0x20202020 },
33034 - { 0x0000a3d4, 0x20202020 },
33035 - { 0x0000a3dc, 0x1ce739ce },
33036 - { 0x0000a3e0, 0x000001ce },
33037 - { 0x0000a3e4, 0x00000000 },
33038 - { 0x0000a3e8, 0x18c43433 },
33039 - { 0x0000a3ec, 0x00f70081 },
33040 - { 0x0000a3f0, 0x01036a1e },
33041 - { 0x0000a3f4, 0x00000000 },
33042 - { 0x0000b3f4, 0x00000000 },
33043 - { 0x0000a7d8, 0x000003f1 },
33044 - { 0x00007800, 0x00000800 },
33045 - { 0x00007804, 0x6c35ffd2 },
33046 - { 0x00007808, 0x6db6c000 },
33047 - { 0x0000780c, 0x6db6cb30 },
33048 - { 0x00007810, 0x6db6cb6c },
33049 - { 0x00007814, 0x0501e200 },
33050 - { 0x00007818, 0x0094128d },
33051 - { 0x0000781c, 0x976ee392 },
33052 - { 0x00007820, 0xf75ff6fc },
33053 - { 0x00007824, 0x00040000 },
33054 - { 0x00007828, 0xdb003012 },
33055 - { 0x0000782c, 0x04924914 },
33056 - { 0x00007830, 0x21084210 },
33057 - { 0x00007834, 0x00140000 },
33058 - { 0x00007838, 0x0e4548d8 },
33059 - { 0x0000783c, 0x54214514 },
33060 - { 0x00007840, 0x02025830 },
33061 - { 0x00007844, 0x71c0d388 },
33062 - { 0x00007848, 0x934934a8 },
33063 - { 0x00007850, 0x00000000 },
33064 - { 0x00007854, 0x00000800 },
33065 - { 0x00007858, 0x6c35ffd2 },
33066 - { 0x0000785c, 0x6db6c000 },
33067 - { 0x00007860, 0x6db6cb30 },
33068 - { 0x00007864, 0x6db6cb6c },
33069 - { 0x00007868, 0x0501e200 },
33070 - { 0x0000786c, 0x0094128d },
33071 - { 0x00007870, 0x976ee392 },
33072 - { 0x00007874, 0xf75ff6fc },
33073 - { 0x00007878, 0x00040000 },
33074 - { 0x0000787c, 0xdb003012 },
33075 - { 0x00007880, 0x04924914 },
33076 - { 0x00007884, 0x21084210 },
33077 - { 0x00007888, 0x001b6db0 },
33078 - { 0x0000788c, 0x00376b63 },
33079 - { 0x00007890, 0x06db6db6 },
33080 - { 0x00007894, 0x006d8000 },
33081 - { 0x00007898, 0x48100000 },
33082 - { 0x0000789c, 0x00000000 },
33083 - { 0x000078a0, 0x08000000 },
33084 - { 0x000078a4, 0x0007ffd8 },
33085 - { 0x000078a8, 0x0007ffd8 },
33086 - { 0x000078ac, 0x001c0020 },
33087 - { 0x000078b0, 0x00060aeb },
33088 - { 0x000078b4, 0x40008080 },
33089 - { 0x000078b8, 0x2a850160 },
33090 -};
33091 -
33092 -/*
33093 - * For Japanese regulatory requirements, 2484 MHz requires the following three
33094 - * registers be programmed differently from the channel between 2412 and 2472 MHz.
33095 - */
33096 -static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
33097 - { 0x0000a1f4, 0x00fffeff },
33098 - { 0x0000a1f8, 0x00f5f9ff },
33099 - { 0x0000a1fc, 0xb79f6427 },
33100 -};
33101 -
33102 -static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
33103 - { 0x0000a1f4, 0x00000000 },
33104 - { 0x0000a1f8, 0xefff0301 },
33105 - { 0x0000a1fc, 0xca9228ee },
33106 -};
33107 -
33108 -static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
33109 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
33110 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33111 - { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
33112 - { 0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004 },
33113 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0000c00a, 0x0000c00a, 0x0000c00a },
33114 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001000c, 0x0001000c, 0x0001000c },
33115 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001420b, 0x0001420b, 0x0001420b },
33116 - { 0x0000a318, 0x00000000, 0x00000000, 0x0001824a, 0x0001824a, 0x0001824a },
33117 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0001c44a, 0x0001c44a, 0x0001c44a },
33118 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002064a, 0x0002064a, 0x0002064a },
33119 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002484a, 0x0002484a, 0x0002484a },
33120 - { 0x0000a328, 0x00000000, 0x00000000, 0x00028a4a, 0x00028a4a, 0x00028a4a },
33121 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0002cc4a, 0x0002cc4a, 0x0002cc4a },
33122 - { 0x0000a330, 0x00000000, 0x00000000, 0x00030e4a, 0x00030e4a, 0x00030e4a },
33123 - { 0x0000a334, 0x00000000, 0x00000000, 0x00034e8a, 0x00034e8a, 0x00034e8a },
33124 - { 0x0000a338, 0x00000000, 0x00000000, 0x00038e8c, 0x00038e8c, 0x00038e8c },
33125 - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003cecc, 0x0003cecc, 0x0003cecc },
33126 - { 0x0000a340, 0x00000000, 0x00000000, 0x00040ed4, 0x00040ed4, 0x00040ed4 },
33127 - { 0x0000a344, 0x00000000, 0x00000000, 0x00044edc, 0x00044edc, 0x00044edc },
33128 - { 0x0000a348, 0x00000000, 0x00000000, 0x00048ede, 0x00048ede, 0x00048ede },
33129 - { 0x0000a34c, 0x00000000, 0x00000000, 0x0004cf1e, 0x0004cf1e, 0x0004cf1e },
33130 - { 0x0000a350, 0x00000000, 0x00000000, 0x00050f5e, 0x00050f5e, 0x00050f5e },
33131 - { 0x0000a354, 0x00000000, 0x00000000, 0x00054f9e, 0x00054f9e, 0x00054f9e },
33132 - { 0x0000a780, 0x00000000, 0x00000000, 0x00000062, 0x00000062, 0x00000062 },
33133 - { 0x0000a784, 0x00000000, 0x00000000, 0x00004064, 0x00004064, 0x00004064 },
33134 - { 0x0000a788, 0x00000000, 0x00000000, 0x000080a4, 0x000080a4, 0x000080a4 },
33135 - { 0x0000a78c, 0x00000000, 0x00000000, 0x0000c0aa, 0x0000c0aa, 0x0000c0aa },
33136 - { 0x0000a790, 0x00000000, 0x00000000, 0x000100ac, 0x000100ac, 0x000100ac },
33137 - { 0x0000a794, 0x00000000, 0x00000000, 0x000140b4, 0x000140b4, 0x000140b4 },
33138 - { 0x0000a798, 0x00000000, 0x00000000, 0x000180f4, 0x000180f4, 0x000180f4 },
33139 - { 0x0000a79c, 0x00000000, 0x00000000, 0x0001c134, 0x0001c134, 0x0001c134 },
33140 - { 0x0000a7a0, 0x00000000, 0x00000000, 0x00020174, 0x00020174, 0x00020174 },
33141 - { 0x0000a7a4, 0x00000000, 0x00000000, 0x0002417c, 0x0002417c, 0x0002417c },
33142 - { 0x0000a7a8, 0x00000000, 0x00000000, 0x0002817e, 0x0002817e, 0x0002817e },
33143 - { 0x0000a7ac, 0x00000000, 0x00000000, 0x0002c1be, 0x0002c1be, 0x0002c1be },
33144 - { 0x0000a7b0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33145 - { 0x0000a7b4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33146 - { 0x0000a7b8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33147 - { 0x0000a7bc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33148 - { 0x0000a7c0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33149 - { 0x0000a7c4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33150 - { 0x0000a7c8, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33151 - { 0x0000a7cc, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33152 - { 0x0000a7d0, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33153 - { 0x0000a7d4, 0x00000000, 0x00000000, 0x000301fe, 0x000301fe, 0x000301fe },
33154 - { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
33155 -};
33156 -
33157 -static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
33158 - /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
33159 - { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
33160 - { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
33161 - { 0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
33162 - { 0x00009a0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
33163 - { 0x00009a10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
33164 - { 0x00009a14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
33165 - { 0x00009a18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
33166 - { 0x00009a1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
33167 - { 0x00009a20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
33168 - { 0x00009a24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
33169 - { 0x00009a28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
33170 - { 0x00009a2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
33171 - { 0x00009a30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
33172 - { 0x00009a34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
33173 - { 0x00009a38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
33174 - { 0x00009a3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
33175 - { 0x00009a40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
33176 - { 0x00009a44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
33177 - { 0x00009a48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
33178 - { 0x00009a4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
33179 - { 0x00009a50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
33180 - { 0x00009a54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
33181 - { 0x00009a58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
33182 - { 0x00009a5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
33183 - { 0x00009a60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
33184 - { 0x00009a64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
33185 - { 0x00009a68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
33186 - { 0x00009a6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
33187 - { 0x00009a70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
33188 - { 0x00009a74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
33189 - { 0x00009a78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
33190 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
33191 - { 0x00009a80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
33192 - { 0x00009a84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
33193 - { 0x00009a88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
33194 - { 0x00009a8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
33195 - { 0x00009a90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
33196 - { 0x00009a94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
33197 - { 0x00009a98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
33198 - { 0x00009a9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
33199 - { 0x00009aa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
33200 - { 0x00009aa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
33201 - { 0x00009aa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
33202 - { 0x00009aac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
33203 - { 0x00009ab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
33204 - { 0x00009ab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
33205 - { 0x00009ab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
33206 - { 0x00009abc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
33207 - { 0x00009ac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
33208 - { 0x00009ac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
33209 - { 0x00009ac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
33210 - { 0x00009acc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
33211 - { 0x00009ad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
33212 - { 0x00009ad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
33213 - { 0x00009ad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
33214 - { 0x00009adc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
33215 - { 0x00009ae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
33216 - { 0x00009ae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
33217 - { 0x00009ae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
33218 - { 0x00009aec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
33219 - { 0x00009af0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
33220 - { 0x00009af4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
33221 - { 0x00009af8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
33222 - { 0x00009afc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
33223 - { 0x00009b00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
33224 - { 0x00009b04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
33225 - { 0x00009b08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
33226 - { 0x00009b0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
33227 - { 0x00009b10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
33228 - { 0x00009b14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
33229 - { 0x00009b18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
33230 - { 0x00009b1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
33231 - { 0x00009b20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
33232 - { 0x00009b24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
33233 - { 0x00009b28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
33234 - { 0x00009b2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
33235 - { 0x00009b30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
33236 - { 0x00009b34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
33237 - { 0x00009b38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
33238 - { 0x00009b3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
33239 - { 0x00009b40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
33240 - { 0x00009b44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
33241 - { 0x00009b48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
33242 - { 0x00009b4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
33243 - { 0x00009b50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
33244 - { 0x00009b54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
33245 - { 0x00009b58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
33246 - { 0x00009b5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
33247 - { 0x00009b60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
33248 - { 0x00009b64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
33249 - { 0x00009b68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
33250 - { 0x00009b6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
33251 - { 0x00009b70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
33252 - { 0x00009b74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
33253 - { 0x00009b78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
33254 - { 0x00009b7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
33255 - { 0x00009b80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
33256 - { 0x00009b84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
33257 - { 0x00009b88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
33258 - { 0x00009b8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
33259 - { 0x00009b90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
33260 - { 0x00009b94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
33261 - { 0x00009b98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
33262 - { 0x00009b9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33263 - { 0x00009ba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33264 - { 0x00009ba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33265 - { 0x00009ba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33266 - { 0x00009bac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33267 - { 0x00009bb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33268 - { 0x00009bb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33269 - { 0x00009bb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33270 - { 0x00009bbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33271 - { 0x00009bc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33272 - { 0x00009bc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33273 - { 0x00009bc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33274 - { 0x00009bcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33275 - { 0x00009bd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33276 - { 0x00009bd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33277 - { 0x00009bd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33278 - { 0x00009bdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33279 - { 0x00009be0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33280 - { 0x00009be4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33281 - { 0x00009be8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33282 - { 0x00009bec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33283 - { 0x00009bf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33284 - { 0x00009bf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33285 - { 0x00009bf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33286 - { 0x00009bfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33287 - { 0x0000aa00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
33288 - { 0x0000aa04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
33289 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128 },
33290 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x0000a12c, 0x0000a12c, 0x0000a12c },
33291 - { 0x0000aa10, 0x00000000, 0x00000000, 0x0000a130, 0x0000a130, 0x0000a130 },
33292 - { 0x0000aa14, 0x00000000, 0x00000000, 0x0000a194, 0x0000a194, 0x0000a194 },
33293 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0000a198, 0x0000a198, 0x0000a198 },
33294 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x0000a20c, 0x0000a20c, 0x0000a20c },
33295 - { 0x0000aa20, 0x00000000, 0x00000000, 0x0000a210, 0x0000a210, 0x0000a210 },
33296 - { 0x0000aa24, 0x00000000, 0x00000000, 0x0000a284, 0x0000a284, 0x0000a284 },
33297 - { 0x0000aa28, 0x00000000, 0x00000000, 0x0000a288, 0x0000a288, 0x0000a288 },
33298 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x0000a28c, 0x0000a28c, 0x0000a28c },
33299 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0000a290, 0x0000a290, 0x0000a290 },
33300 - { 0x0000aa34, 0x00000000, 0x00000000, 0x0000a294, 0x0000a294, 0x0000a294 },
33301 - { 0x0000aa38, 0x00000000, 0x00000000, 0x0000a2a0, 0x0000a2a0, 0x0000a2a0 },
33302 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x0000a2a4, 0x0000a2a4, 0x0000a2a4 },
33303 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0000a2a8, 0x0000a2a8, 0x0000a2a8 },
33304 - { 0x0000aa44, 0x00000000, 0x00000000, 0x0000a2ac, 0x0000a2ac, 0x0000a2ac },
33305 - { 0x0000aa48, 0x00000000, 0x00000000, 0x0000a2b0, 0x0000a2b0, 0x0000a2b0 },
33306 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x0000a2b4, 0x0000a2b4, 0x0000a2b4 },
33307 - { 0x0000aa50, 0x00000000, 0x00000000, 0x0000a2b8, 0x0000a2b8, 0x0000a2b8 },
33308 - { 0x0000aa54, 0x00000000, 0x00000000, 0x0000a2c4, 0x0000a2c4, 0x0000a2c4 },
33309 - { 0x0000aa58, 0x00000000, 0x00000000, 0x0000a708, 0x0000a708, 0x0000a708 },
33310 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x0000a70c, 0x0000a70c, 0x0000a70c },
33311 - { 0x0000aa60, 0x00000000, 0x00000000, 0x0000a710, 0x0000a710, 0x0000a710 },
33312 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0000ab04, 0x0000ab04, 0x0000ab04 },
33313 - { 0x0000aa68, 0x00000000, 0x00000000, 0x0000ab08, 0x0000ab08, 0x0000ab08 },
33314 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x0000ab0c, 0x0000ab0c, 0x0000ab0c },
33315 - { 0x0000aa70, 0x00000000, 0x00000000, 0x0000ab10, 0x0000ab10, 0x0000ab10 },
33316 - { 0x0000aa74, 0x00000000, 0x00000000, 0x0000ab14, 0x0000ab14, 0x0000ab14 },
33317 - { 0x0000aa78, 0x00000000, 0x00000000, 0x0000ab18, 0x0000ab18, 0x0000ab18 },
33318 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0000ab8c, 0x0000ab8c, 0x0000ab8c },
33319 - { 0x0000aa80, 0x00000000, 0x00000000, 0x0000ab90, 0x0000ab90, 0x0000ab90 },
33320 - { 0x0000aa84, 0x00000000, 0x00000000, 0x0000ab94, 0x0000ab94, 0x0000ab94 },
33321 - { 0x0000aa88, 0x00000000, 0x00000000, 0x0000ab98, 0x0000ab98, 0x0000ab98 },
33322 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x0000aba4, 0x0000aba4, 0x0000aba4 },
33323 - { 0x0000aa90, 0x00000000, 0x00000000, 0x0000aba8, 0x0000aba8, 0x0000aba8 },
33324 - { 0x0000aa94, 0x00000000, 0x00000000, 0x0000cb04, 0x0000cb04, 0x0000cb04 },
33325 - { 0x0000aa98, 0x00000000, 0x00000000, 0x0000cb08, 0x0000cb08, 0x0000cb08 },
33326 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x0000cb0c, 0x0000cb0c, 0x0000cb0c },
33327 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x0000cb10, 0x0000cb10, 0x0000cb10 },
33328 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x0000cb14, 0x0000cb14, 0x0000cb14 },
33329 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x0000cb18, 0x0000cb18, 0x0000cb18 },
33330 - { 0x0000aaac, 0x00000000, 0x00000000, 0x0000cb8c, 0x0000cb8c, 0x0000cb8c },
33331 - { 0x0000aab0, 0x00000000, 0x00000000, 0x0000cb90, 0x0000cb90, 0x0000cb90 },
33332 - { 0x0000aab4, 0x00000000, 0x00000000, 0x0000cf18, 0x0000cf18, 0x0000cf18 },
33333 - { 0x0000aab8, 0x00000000, 0x00000000, 0x0000cf24, 0x0000cf24, 0x0000cf24 },
33334 - { 0x0000aabc, 0x00000000, 0x00000000, 0x0000cf28, 0x0000cf28, 0x0000cf28 },
33335 - { 0x0000aac0, 0x00000000, 0x00000000, 0x0000d314, 0x0000d314, 0x0000d314 },
33336 - { 0x0000aac4, 0x00000000, 0x00000000, 0x0000d318, 0x0000d318, 0x0000d318 },
33337 - { 0x0000aac8, 0x00000000, 0x00000000, 0x0000d38c, 0x0000d38c, 0x0000d38c },
33338 - { 0x0000aacc, 0x00000000, 0x00000000, 0x0000d390, 0x0000d390, 0x0000d390 },
33339 - { 0x0000aad0, 0x00000000, 0x00000000, 0x0000d394, 0x0000d394, 0x0000d394 },
33340 - { 0x0000aad4, 0x00000000, 0x00000000, 0x0000d398, 0x0000d398, 0x0000d398 },
33341 - { 0x0000aad8, 0x00000000, 0x00000000, 0x0000d3a4, 0x0000d3a4, 0x0000d3a4 },
33342 - { 0x0000aadc, 0x00000000, 0x00000000, 0x0000d3a8, 0x0000d3a8, 0x0000d3a8 },
33343 - { 0x0000aae0, 0x00000000, 0x00000000, 0x0000d3ac, 0x0000d3ac, 0x0000d3ac },
33344 - { 0x0000aae4, 0x00000000, 0x00000000, 0x0000d3b0, 0x0000d3b0, 0x0000d3b0 },
33345 - { 0x0000aae8, 0x00000000, 0x00000000, 0x0000f380, 0x0000f380, 0x0000f380 },
33346 - { 0x0000aaec, 0x00000000, 0x00000000, 0x0000f384, 0x0000f384, 0x0000f384 },
33347 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x0000f388, 0x0000f388, 0x0000f388 },
33348 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x0000f710, 0x0000f710, 0x0000f710 },
33349 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x0000f714, 0x0000f714, 0x0000f714 },
33350 - { 0x0000aafc, 0x00000000, 0x00000000, 0x0000f718, 0x0000f718, 0x0000f718 },
33351 - { 0x0000ab00, 0x00000000, 0x00000000, 0x0000fb10, 0x0000fb10, 0x0000fb10 },
33352 - { 0x0000ab04, 0x00000000, 0x00000000, 0x0000fb14, 0x0000fb14, 0x0000fb14 },
33353 - { 0x0000ab08, 0x00000000, 0x00000000, 0x0000fb18, 0x0000fb18, 0x0000fb18 },
33354 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x0000fb8c, 0x0000fb8c, 0x0000fb8c },
33355 - { 0x0000ab10, 0x00000000, 0x00000000, 0x0000fb90, 0x0000fb90, 0x0000fb90 },
33356 - { 0x0000ab14, 0x00000000, 0x00000000, 0x0000fb94, 0x0000fb94, 0x0000fb94 },
33357 - { 0x0000ab18, 0x00000000, 0x00000000, 0x0000ff8c, 0x0000ff8c, 0x0000ff8c },
33358 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x0000ff90, 0x0000ff90, 0x0000ff90 },
33359 - { 0x0000ab20, 0x00000000, 0x00000000, 0x0000ff94, 0x0000ff94, 0x0000ff94 },
33360 - { 0x0000ab24, 0x00000000, 0x00000000, 0x0000ffa0, 0x0000ffa0, 0x0000ffa0 },
33361 - { 0x0000ab28, 0x00000000, 0x00000000, 0x0000ffa4, 0x0000ffa4, 0x0000ffa4 },
33362 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x0000ffa8, 0x0000ffa8, 0x0000ffa8 },
33363 - { 0x0000ab30, 0x00000000, 0x00000000, 0x0000ffac, 0x0000ffac, 0x0000ffac },
33364 - { 0x0000ab34, 0x00000000, 0x00000000, 0x0000ffb0, 0x0000ffb0, 0x0000ffb0 },
33365 - { 0x0000ab38, 0x00000000, 0x00000000, 0x0000ffb4, 0x0000ffb4, 0x0000ffb4 },
33366 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x0000ffa1, 0x0000ffa1, 0x0000ffa1 },
33367 - { 0x0000ab40, 0x00000000, 0x00000000, 0x0000ffa5, 0x0000ffa5, 0x0000ffa5 },
33368 - { 0x0000ab44, 0x00000000, 0x00000000, 0x0000ffa9, 0x0000ffa9, 0x0000ffa9 },
33369 - { 0x0000ab48, 0x00000000, 0x00000000, 0x0000ffad, 0x0000ffad, 0x0000ffad },
33370 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x0000ffb1, 0x0000ffb1, 0x0000ffb1 },
33371 - { 0x0000ab50, 0x00000000, 0x00000000, 0x0000ffb5, 0x0000ffb5, 0x0000ffb5 },
33372 - { 0x0000ab54, 0x00000000, 0x00000000, 0x0000ffb9, 0x0000ffb9, 0x0000ffb9 },
33373 - { 0x0000ab58, 0x00000000, 0x00000000, 0x0000ffc5, 0x0000ffc5, 0x0000ffc5 },
33374 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x0000ffc9, 0x0000ffc9, 0x0000ffc9 },
33375 - { 0x0000ab60, 0x00000000, 0x00000000, 0x0000ffcd, 0x0000ffcd, 0x0000ffcd },
33376 - { 0x0000ab64, 0x00000000, 0x00000000, 0x0000ffd1, 0x0000ffd1, 0x0000ffd1 },
33377 - { 0x0000ab68, 0x00000000, 0x00000000, 0x0000ffd5, 0x0000ffd5, 0x0000ffd5 },
33378 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x0000ffc2, 0x0000ffc2, 0x0000ffc2 },
33379 - { 0x0000ab70, 0x00000000, 0x00000000, 0x0000ffc6, 0x0000ffc6, 0x0000ffc6 },
33380 - { 0x0000ab74, 0x00000000, 0x00000000, 0x0000ffca, 0x0000ffca, 0x0000ffca },
33381 - { 0x0000ab78, 0x00000000, 0x00000000, 0x0000ffce, 0x0000ffce, 0x0000ffce },
33382 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x0000ffd2, 0x0000ffd2, 0x0000ffd2 },
33383 - { 0x0000ab80, 0x00000000, 0x00000000, 0x0000ffd6, 0x0000ffd6, 0x0000ffd6 },
33384 - { 0x0000ab84, 0x00000000, 0x00000000, 0x0000ffda, 0x0000ffda, 0x0000ffda },
33385 - { 0x0000ab88, 0x00000000, 0x00000000, 0x0000ffc7, 0x0000ffc7, 0x0000ffc7 },
33386 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x0000ffcb, 0x0000ffcb, 0x0000ffcb },
33387 - { 0x0000ab90, 0x00000000, 0x00000000, 0x0000ffcf, 0x0000ffcf, 0x0000ffcf },
33388 - { 0x0000ab94, 0x00000000, 0x00000000, 0x0000ffd3, 0x0000ffd3, 0x0000ffd3 },
33389 - { 0x0000ab98, 0x00000000, 0x00000000, 0x0000ffd7, 0x0000ffd7, 0x0000ffd7 },
33390 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33391 - { 0x0000aba0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33392 - { 0x0000aba4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33393 - { 0x0000aba8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33394 - { 0x0000abac, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33395 - { 0x0000abb0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33396 - { 0x0000abb4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33397 - { 0x0000abb8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33398 - { 0x0000abbc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33399 - { 0x0000abc0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33400 - { 0x0000abc4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33401 - { 0x0000abc8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33402 - { 0x0000abcc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33403 - { 0x0000abd0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33404 - { 0x0000abd4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33405 - { 0x0000abd8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33406 - { 0x0000abdc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33407 - { 0x0000abe0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33408 - { 0x0000abe4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33409 - { 0x0000abe8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33410 - { 0x0000abec, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33411 - { 0x0000abf0, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33412 - { 0x0000abf4, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33413 - { 0x0000abf8, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33414 - { 0x0000abfc, 0x00000000, 0x00000000, 0x0000ffdb, 0x0000ffdb, 0x0000ffdb },
33415 - { 0x00009848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
33416 - { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
33417 -};
33418 -
33419 -static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
33420 - {0x00004040, 0x9248fd00 },
33421 - {0x00004040, 0x24924924 },
33422 - {0x00004040, 0xa8000019 },
33423 - {0x00004040, 0x13160820 },
33424 - {0x00004040, 0xe5980560 },
33425 - {0x00004040, 0xc01dcffd },
33426 - {0x00004040, 0x1aaabe41 },
33427 - {0x00004040, 0xbe105554 },
33428 - {0x00004040, 0x00043007 },
33429 - {0x00004044, 0x00000000 },
33430 -};
33431 -
33432 -static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
33433 - {0x00004040, 0x9248fd00 },
33434 - {0x00004040, 0x24924924 },
33435 - {0x00004040, 0xa8000019 },
33436 - {0x00004040, 0x13160820 },
33437 - {0x00004040, 0xe5980560 },
33438 - {0x00004040, 0xc01dcffc },
33439 - {0x00004040, 0x1aaabe41 },
33440 - {0x00004040, 0xbe105554 },
33441 - {0x00004040, 0x00043007 },
33442 - {0x00004044, 0x00000000 },
33443 -};
33444 -
33445 -
33446 -/* AR9271 initialization values automaticaly created: 06/04/09 */
33447 -static const u_int32_t ar9271Modes_9271[][6] = {
33448 - { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
33449 - { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
33450 - { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
33451 - { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
33452 - { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
33453 - { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
33454 - { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
33455 - { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
33456 - { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
33457 - { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
33458 - { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
33459 - { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
33460 - { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
33461 - { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
33462 - { 0x00009844, 0x0372161e, 0x0372161e, 0x03721620, 0x03721620, 0x037216a0 },
33463 - { 0x00009848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
33464 - { 0x0000a848, 0x00001066, 0x00001066, 0x00001053, 0x00001053, 0x00001059 },
33465 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
33466 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
33467 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
33468 - { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18 },
33469 - { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
33470 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
33471 - { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
33472 - { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
33473 - { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
33474 - { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
33475 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
33476 - { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
33477 - { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33478 - { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33479 - { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
33480 - { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
33481 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
33482 - { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
33483 - { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
33484 - { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
33485 - { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
33486 - { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33487 - { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
33488 - { 0x00009a00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
33489 - { 0x00009a04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
33490 - { 0x00009a08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
33491 - { 0x00009a0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
33492 - { 0x00009a10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
33493 - { 0x00009a14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
33494 - { 0x00009a18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
33495 - { 0x00009a1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
33496 - { 0x00009a20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
33497 - { 0x00009a24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
33498 - { 0x00009a28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
33499 - { 0x00009a2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
33500 - { 0x00009a30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
33501 - { 0x00009a34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
33502 - { 0x00009a38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
33503 - { 0x00009a3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
33504 - { 0x00009a40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
33505 - { 0x00009a44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
33506 - { 0x00009a48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
33507 - { 0x00009a4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
33508 - { 0x00009a50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
33509 - { 0x00009a54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
33510 - { 0x00009a58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
33511 - { 0x00009a5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
33512 - { 0x00009a60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
33513 - { 0x00009a64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
33514 - { 0x00009a68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
33515 - { 0x00009a6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
33516 - { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
33517 - { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
33518 - { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
33519 - { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
33520 - { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
33521 - { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
33522 - { 0x00009a88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
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33527 - { 0x00009a9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
33528 - { 0x00009aa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
33529 - { 0x00009aa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
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33531 - { 0x00009aac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
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33533 - { 0x00009ab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
33534 - { 0x00009ab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
33535 - { 0x00009abc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
33536 - { 0x00009ac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
33537 - { 0x00009ac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
33538 - { 0x00009ac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
33539 - { 0x00009acc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
33540 - { 0x00009ad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
33541 - { 0x00009ad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
33542 - { 0x00009ad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
33543 - { 0x00009adc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
33544 - { 0x00009ae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
33545 - { 0x00009ae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
33546 - { 0x00009ae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
33547 - { 0x00009aec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
33548 - { 0x00009af0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
33549 - { 0x00009af4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
33550 - { 0x00009af8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
33551 - { 0x00009afc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
33552 - { 0x00009b00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
33553 - { 0x00009b04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
33554 - { 0x00009b08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
33555 - { 0x00009b0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
33556 - { 0x00009b10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
33557 - { 0x00009b14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
33558 - { 0x00009b18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
33559 - { 0x00009b1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
33560 - { 0x00009b20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
33561 - { 0x00009b24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
33562 - { 0x00009b28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
33563 - { 0x00009b2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
33564 - { 0x00009b30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
33565 - { 0x00009b34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
33566 - { 0x00009b38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
33567 - { 0x00009b3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
33568 - { 0x00009b40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
33569 - { 0x00009b44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
33570 - { 0x00009b48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
33571 - { 0x00009b4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
33572 - { 0x00009b50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
33573 - { 0x00009b54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
33574 - { 0x00009b58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
33575 - { 0x00009b5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
33576 - { 0x00009b60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
33577 - { 0x00009b64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33578 - { 0x00009b68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33579 - { 0x00009b6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33580 - { 0x00009b70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33581 - { 0x00009b74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33582 - { 0x00009b78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33583 - { 0x00009b7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33584 - { 0x00009b80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33585 - { 0x00009b84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33586 - { 0x00009b88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33587 - { 0x00009b8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33588 - { 0x00009b90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33589 - { 0x00009b94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33590 - { 0x00009b98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33591 - { 0x00009b9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33592 - { 0x00009ba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33593 - { 0x00009ba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33594 - { 0x00009ba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33595 - { 0x00009bac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33596 - { 0x00009bb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33597 - { 0x00009bb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33598 - { 0x00009bb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33599 - { 0x00009bbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33600 - { 0x00009bc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33601 - { 0x00009bc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33602 - { 0x00009bc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33603 - { 0x00009bcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33604 - { 0x00009bd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33605 - { 0x00009bd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33606 - { 0x00009bd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33607 - { 0x00009bdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33608 - { 0x00009be0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33609 - { 0x00009be4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33610 - { 0x00009be8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33611 - { 0x00009bec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33612 - { 0x00009bf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33613 - { 0x00009bf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33614 - { 0x00009bf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33615 - { 0x00009bfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33616 - { 0x0000aa00, 0x00000000, 0x00000000, 0x00058084, 0x00058084, 0x00000000 },
33617 - { 0x0000aa04, 0x00000000, 0x00000000, 0x00058088, 0x00058088, 0x00000000 },
33618 - { 0x0000aa08, 0x00000000, 0x00000000, 0x0005808c, 0x0005808c, 0x00000000 },
33619 - { 0x0000aa0c, 0x00000000, 0x00000000, 0x00058100, 0x00058100, 0x00000000 },
33620 - { 0x0000aa10, 0x00000000, 0x00000000, 0x00058104, 0x00058104, 0x00000000 },
33621 - { 0x0000aa14, 0x00000000, 0x00000000, 0x00058108, 0x00058108, 0x00000000 },
33622 - { 0x0000aa18, 0x00000000, 0x00000000, 0x0005810c, 0x0005810c, 0x00000000 },
33623 - { 0x0000aa1c, 0x00000000, 0x00000000, 0x00058110, 0x00058110, 0x00000000 },
33624 - { 0x0000aa20, 0x00000000, 0x00000000, 0x00058114, 0x00058114, 0x00000000 },
33625 - { 0x0000aa24, 0x00000000, 0x00000000, 0x00058180, 0x00058180, 0x00000000 },
33626 - { 0x0000aa28, 0x00000000, 0x00000000, 0x00058184, 0x00058184, 0x00000000 },
33627 - { 0x0000aa2c, 0x00000000, 0x00000000, 0x00058188, 0x00058188, 0x00000000 },
33628 - { 0x0000aa30, 0x00000000, 0x00000000, 0x0005818c, 0x0005818c, 0x00000000 },
33629 - { 0x0000aa34, 0x00000000, 0x00000000, 0x00058190, 0x00058190, 0x00000000 },
33630 - { 0x0000aa38, 0x00000000, 0x00000000, 0x00058194, 0x00058194, 0x00000000 },
33631 - { 0x0000aa3c, 0x00000000, 0x00000000, 0x000581a0, 0x000581a0, 0x00000000 },
33632 - { 0x0000aa40, 0x00000000, 0x00000000, 0x0005820c, 0x0005820c, 0x00000000 },
33633 - { 0x0000aa44, 0x00000000, 0x00000000, 0x000581a8, 0x000581a8, 0x00000000 },
33634 - { 0x0000aa48, 0x00000000, 0x00000000, 0x00058284, 0x00058284, 0x00000000 },
33635 - { 0x0000aa4c, 0x00000000, 0x00000000, 0x00058288, 0x00058288, 0x00000000 },
33636 - { 0x0000aa50, 0x00000000, 0x00000000, 0x00058224, 0x00058224, 0x00000000 },
33637 - { 0x0000aa54, 0x00000000, 0x00000000, 0x00058290, 0x00058290, 0x00000000 },
33638 - { 0x0000aa58, 0x00000000, 0x00000000, 0x00058300, 0x00058300, 0x00000000 },
33639 - { 0x0000aa5c, 0x00000000, 0x00000000, 0x00058304, 0x00058304, 0x00000000 },
33640 - { 0x0000aa60, 0x00000000, 0x00000000, 0x00058308, 0x00058308, 0x00000000 },
33641 - { 0x0000aa64, 0x00000000, 0x00000000, 0x0005830c, 0x0005830c, 0x00000000 },
33642 - { 0x0000aa68, 0x00000000, 0x00000000, 0x00058380, 0x00058380, 0x00000000 },
33643 - { 0x0000aa6c, 0x00000000, 0x00000000, 0x00058384, 0x00058384, 0x00000000 },
33644 - { 0x0000aa70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
33645 - { 0x0000aa74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
33646 - { 0x0000aa78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
33647 - { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
33648 - { 0x0000aa80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
33649 - { 0x0000aa84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
33650 - { 0x0000aa88, 0x00000000, 0x00000000, 0x00078b00, 0x00078b00, 0x00000000 },
33651 - { 0x0000aa8c, 0x00000000, 0x00000000, 0x00078b04, 0x00078b04, 0x00000000 },
33652 - { 0x0000aa90, 0x00000000, 0x00000000, 0x00078b08, 0x00078b08, 0x00000000 },
33653 - { 0x0000aa94, 0x00000000, 0x00000000, 0x00078b0c, 0x00078b0c, 0x00000000 },
33654 - { 0x0000aa98, 0x00000000, 0x00000000, 0x00078b80, 0x00078b80, 0x00000000 },
33655 - { 0x0000aa9c, 0x00000000, 0x00000000, 0x00078b84, 0x00078b84, 0x00000000 },
33656 - { 0x0000aaa0, 0x00000000, 0x00000000, 0x00078b88, 0x00078b88, 0x00000000 },
33657 - { 0x0000aaa4, 0x00000000, 0x00000000, 0x00078b8c, 0x00078b8c, 0x00000000 },
33658 - { 0x0000aaa8, 0x00000000, 0x00000000, 0x00078b90, 0x00078b90, 0x00000000 },
33659 - { 0x0000aaac, 0x00000000, 0x00000000, 0x000caf80, 0x000caf80, 0x00000000 },
33660 - { 0x0000aab0, 0x00000000, 0x00000000, 0x000caf84, 0x000caf84, 0x00000000 },
33661 - { 0x0000aab4, 0x00000000, 0x00000000, 0x000caf88, 0x000caf88, 0x00000000 },
33662 - { 0x0000aab8, 0x00000000, 0x00000000, 0x000caf8c, 0x000caf8c, 0x00000000 },
33663 - { 0x0000aabc, 0x00000000, 0x00000000, 0x000caf90, 0x000caf90, 0x00000000 },
33664 - { 0x0000aac0, 0x00000000, 0x00000000, 0x000db30c, 0x000db30c, 0x00000000 },
33665 - { 0x0000aac4, 0x00000000, 0x00000000, 0x000db310, 0x000db310, 0x00000000 },
33666 - { 0x0000aac8, 0x00000000, 0x00000000, 0x000db384, 0x000db384, 0x00000000 },
33667 - { 0x0000aacc, 0x00000000, 0x00000000, 0x000db388, 0x000db388, 0x00000000 },
33668 - { 0x0000aad0, 0x00000000, 0x00000000, 0x000db324, 0x000db324, 0x00000000 },
33669 - { 0x0000aad4, 0x00000000, 0x00000000, 0x000eb704, 0x000eb704, 0x00000000 },
33670 - { 0x0000aad8, 0x00000000, 0x00000000, 0x000eb6a4, 0x000eb6a4, 0x00000000 },
33671 - { 0x0000aadc, 0x00000000, 0x00000000, 0x000eb6a8, 0x000eb6a8, 0x00000000 },
33672 - { 0x0000aae0, 0x00000000, 0x00000000, 0x000eb710, 0x000eb710, 0x00000000 },
33673 - { 0x0000aae4, 0x00000000, 0x00000000, 0x000eb714, 0x000eb714, 0x00000000 },
33674 - { 0x0000aae8, 0x00000000, 0x00000000, 0x000eb720, 0x000eb720, 0x00000000 },
33675 - { 0x0000aaec, 0x00000000, 0x00000000, 0x000eb724, 0x000eb724, 0x00000000 },
33676 - { 0x0000aaf0, 0x00000000, 0x00000000, 0x000eb728, 0x000eb728, 0x00000000 },
33677 - { 0x0000aaf4, 0x00000000, 0x00000000, 0x000eb72c, 0x000eb72c, 0x00000000 },
33678 - { 0x0000aaf8, 0x00000000, 0x00000000, 0x000eb7a0, 0x000eb7a0, 0x00000000 },
33679 - { 0x0000aafc, 0x00000000, 0x00000000, 0x000eb7a4, 0x000eb7a4, 0x00000000 },
33680 - { 0x0000ab00, 0x00000000, 0x00000000, 0x000eb7a8, 0x000eb7a8, 0x00000000 },
33681 - { 0x0000ab04, 0x00000000, 0x00000000, 0x000eb7b0, 0x000eb7b0, 0x00000000 },
33682 - { 0x0000ab08, 0x00000000, 0x00000000, 0x000eb7b4, 0x000eb7b4, 0x00000000 },
33683 - { 0x0000ab0c, 0x00000000, 0x00000000, 0x000eb7b8, 0x000eb7b8, 0x00000000 },
33684 - { 0x0000ab10, 0x00000000, 0x00000000, 0x000eb7a5, 0x000eb7a5, 0x00000000 },
33685 - { 0x0000ab14, 0x00000000, 0x00000000, 0x000eb7a9, 0x000eb7a9, 0x00000000 },
33686 - { 0x0000ab18, 0x00000000, 0x00000000, 0x000eb7ad, 0x000eb7ad, 0x00000000 },
33687 - { 0x0000ab1c, 0x00000000, 0x00000000, 0x000eb7b1, 0x000eb7b1, 0x00000000 },
33688 - { 0x0000ab20, 0x00000000, 0x00000000, 0x000eb7b5, 0x000eb7b5, 0x00000000 },
33689 - { 0x0000ab24, 0x00000000, 0x00000000, 0x000eb7b9, 0x000eb7b9, 0x00000000 },
33690 - { 0x0000ab28, 0x00000000, 0x00000000, 0x000eb7c5, 0x000eb7c5, 0x00000000 },
33691 - { 0x0000ab2c, 0x00000000, 0x00000000, 0x000eb7c9, 0x000eb7c9, 0x00000000 },
33692 - { 0x0000ab30, 0x00000000, 0x00000000, 0x000eb7d1, 0x000eb7d1, 0x00000000 },
33693 - { 0x0000ab34, 0x00000000, 0x00000000, 0x000eb7d5, 0x000eb7d5, 0x00000000 },
33694 - { 0x0000ab38, 0x00000000, 0x00000000, 0x000eb7d9, 0x000eb7d9, 0x00000000 },
33695 - { 0x0000ab3c, 0x00000000, 0x00000000, 0x000eb7c6, 0x000eb7c6, 0x00000000 },
33696 - { 0x0000ab40, 0x00000000, 0x00000000, 0x000eb7ca, 0x000eb7ca, 0x00000000 },
33697 - { 0x0000ab44, 0x00000000, 0x00000000, 0x000eb7ce, 0x000eb7ce, 0x00000000 },
33698 - { 0x0000ab48, 0x00000000, 0x00000000, 0x000eb7d2, 0x000eb7d2, 0x00000000 },
33699 - { 0x0000ab4c, 0x00000000, 0x00000000, 0x000eb7d6, 0x000eb7d6, 0x00000000 },
33700 - { 0x0000ab50, 0x00000000, 0x00000000, 0x000eb7c3, 0x000eb7c3, 0x00000000 },
33701 - { 0x0000ab54, 0x00000000, 0x00000000, 0x000eb7c7, 0x000eb7c7, 0x00000000 },
33702 - { 0x0000ab58, 0x00000000, 0x00000000, 0x000eb7cb, 0x000eb7cb, 0x00000000 },
33703 - { 0x0000ab5c, 0x00000000, 0x00000000, 0x000eb7cf, 0x000eb7cf, 0x00000000 },
33704 - { 0x0000ab60, 0x00000000, 0x00000000, 0x000eb7d7, 0x000eb7d7, 0x00000000 },
33705 - { 0x0000ab64, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33706 - { 0x0000ab68, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33707 - { 0x0000ab6c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33708 - { 0x0000ab70, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33709 - { 0x0000ab74, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33710 - { 0x0000ab78, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33711 - { 0x0000ab7c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33712 - { 0x0000ab80, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33713 - { 0x0000ab84, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33714 - { 0x0000ab88, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33715 - { 0x0000ab8c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33716 - { 0x0000ab90, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33717 - { 0x0000ab94, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33718 - { 0x0000ab98, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33719 - { 0x0000ab9c, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33720 - { 0x0000aba0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33721 - { 0x0000aba4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33722 - { 0x0000aba8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33723 - { 0x0000abac, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33724 - { 0x0000abb0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33725 - { 0x0000abb4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33726 - { 0x0000abb8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33727 - { 0x0000abbc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33728 - { 0x0000abc0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33729 - { 0x0000abc4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33730 - { 0x0000abc8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33731 - { 0x0000abcc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33732 - { 0x0000abd0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33733 - { 0x0000abd4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33734 - { 0x0000abd8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33735 - { 0x0000abdc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33736 - { 0x0000abe0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33737 - { 0x0000abe4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33738 - { 0x0000abe8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33739 - { 0x0000abec, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33740 - { 0x0000abf0, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33741 - { 0x0000abf4, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33742 - { 0x0000abf8, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33743 - { 0x0000abfc, 0x00000000, 0x00000000, 0x000eb7db, 0x000eb7db, 0x00000000 },
33744 - { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
33745 - { 0x0000a20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
33746 - { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f000, 0x0001f000, 0x0001f000 },
33747 - { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
33748 - { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
33749 - { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
33750 - { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
33751 -};
33752 -
33753 -static const u_int32_t ar9271Common_9271[][2] = {
33754 - { 0x0000000c, 0x00000000 },
33755 - { 0x00000030, 0x00020045 },
33756 - { 0x00000034, 0x00000005 },
33757 - { 0x00000040, 0x00000000 },
33758 - { 0x00000044, 0x00000008 },
33759 - { 0x00000048, 0x00000008 },
33760 - { 0x0000004c, 0x00000010 },
33761 - { 0x00000050, 0x00000000 },
33762 - { 0x00000054, 0x0000001f },
33763 - { 0x00000800, 0x00000000 },
33764 - { 0x00000804, 0x00000000 },
33765 - { 0x00000808, 0x00000000 },
33766 - { 0x0000080c, 0x00000000 },
33767 - { 0x00000810, 0x00000000 },
33768 - { 0x00000814, 0x00000000 },
33769 - { 0x00000818, 0x00000000 },
33770 - { 0x0000081c, 0x00000000 },
33771 - { 0x00000820, 0x00000000 },
33772 - { 0x00000824, 0x00000000 },
33773 - { 0x00001040, 0x002ffc0f },
33774 - { 0x00001044, 0x002ffc0f },
33775 - { 0x00001048, 0x002ffc0f },
33776 - { 0x0000104c, 0x002ffc0f },
33777 - { 0x00001050, 0x002ffc0f },
33778 - { 0x00001054, 0x002ffc0f },
33779 - { 0x00001058, 0x002ffc0f },
33780 - { 0x0000105c, 0x002ffc0f },
33781 - { 0x00001060, 0x002ffc0f },
33782 - { 0x00001064, 0x002ffc0f },
33783 - { 0x00001230, 0x00000000 },
33784 - { 0x00001270, 0x00000000 },
33785 - { 0x00001038, 0x00000000 },
33786 - { 0x00001078, 0x00000000 },
33787 - { 0x000010b8, 0x00000000 },
33788 - { 0x000010f8, 0x00000000 },
33789 - { 0x00001138, 0x00000000 },
33790 - { 0x00001178, 0x00000000 },
33791 - { 0x000011b8, 0x00000000 },
33792 - { 0x000011f8, 0x00000000 },
33793 - { 0x00001238, 0x00000000 },
33794 - { 0x00001278, 0x00000000 },
33795 - { 0x000012b8, 0x00000000 },
33796 - { 0x000012f8, 0x00000000 },
33797 - { 0x00001338, 0x00000000 },
33798 - { 0x00001378, 0x00000000 },
33799 - { 0x000013b8, 0x00000000 },
33800 - { 0x000013f8, 0x00000000 },
33801 - { 0x00001438, 0x00000000 },
33802 - { 0x00001478, 0x00000000 },
33803 - { 0x000014b8, 0x00000000 },
33804 - { 0x000014f8, 0x00000000 },
33805 - { 0x00001538, 0x00000000 },
33806 - { 0x00001578, 0x00000000 },
33807 - { 0x000015b8, 0x00000000 },
33808 - { 0x000015f8, 0x00000000 },
33809 - { 0x00001638, 0x00000000 },
33810 - { 0x00001678, 0x00000000 },
33811 - { 0x000016b8, 0x00000000 },
33812 - { 0x000016f8, 0x00000000 },
33813 - { 0x00001738, 0x00000000 },
33814 - { 0x00001778, 0x00000000 },
33815 - { 0x000017b8, 0x00000000 },
33816 - { 0x000017f8, 0x00000000 },
33817 - { 0x0000103c, 0x00000000 },
33818 - { 0x0000107c, 0x00000000 },
33819 - { 0x000010bc, 0x00000000 },
33820 - { 0x000010fc, 0x00000000 },
33821 - { 0x0000113c, 0x00000000 },
33822 - { 0x0000117c, 0x00000000 },
33823 - { 0x000011bc, 0x00000000 },
33824 - { 0x000011fc, 0x00000000 },
33825 - { 0x0000123c, 0x00000000 },
33826 - { 0x0000127c, 0x00000000 },
33827 - { 0x000012bc, 0x00000000 },
33828 - { 0x000012fc, 0x00000000 },
33829 - { 0x0000133c, 0x00000000 },
33830 - { 0x0000137c, 0x00000000 },
33831 - { 0x000013bc, 0x00000000 },
33832 - { 0x000013fc, 0x00000000 },
33833 - { 0x0000143c, 0x00000000 },
33834 - { 0x0000147c, 0x00000000 },
33835 - { 0x00004030, 0x00000002 },
33836 - { 0x0000403c, 0x00000002 },
33837 - { 0x00004024, 0x0000001f },
33838 - { 0x00004060, 0x00000000 },
33839 - { 0x00004064, 0x00000000 },
33840 - { 0x00008004, 0x00000000 },
33841 - { 0x00008008, 0x00000000 },
33842 - { 0x0000800c, 0x00000000 },
33843 - { 0x00008018, 0x00000700 },
33844 - { 0x00008020, 0x00000000 },
33845 - { 0x00008038, 0x00000000 },
33846 - { 0x0000803c, 0x00000000 },
33847 - { 0x00008048, 0x00000000 },
33848 - { 0x00008054, 0x00000000 },
33849 - { 0x00008058, 0x00000000 },
33850 - { 0x0000805c, 0x000fc78f },
33851 - { 0x00008060, 0x0000000f },
33852 - { 0x00008064, 0x00000000 },
33853 - { 0x00008070, 0x00000000 },
33854 - { 0x000080b0, 0x00000000 },
33855 - { 0x000080b4, 0x00000000 },
33856 - { 0x000080b8, 0x00000000 },
33857 - { 0x000080bc, 0x00000000 },
33858 - { 0x000080c0, 0x2a80001a },
33859 - { 0x000080c4, 0x05dc01e0 },
33860 - { 0x000080c8, 0x1f402710 },
33861 - { 0x000080cc, 0x01f40000 },
33862 - { 0x000080d0, 0x00001e00 },
33863 - { 0x000080d4, 0x00000000 },
33864 - { 0x000080d8, 0x00400000 },
33865 - { 0x000080e0, 0xffffffff },
33866 - { 0x000080e4, 0x0000ffff },
33867 - { 0x000080e8, 0x003f3f3f },
33868 - { 0x000080ec, 0x00000000 },
33869 - { 0x000080f0, 0x00000000 },
33870 - { 0x000080f4, 0x00000000 },
33871 - { 0x000080f8, 0x00000000 },
33872 - { 0x000080fc, 0x00020000 },
33873 - { 0x00008100, 0x00020000 },
33874 - { 0x00008104, 0x00000001 },
33875 - { 0x00008108, 0x00000052 },
33876 - { 0x0000810c, 0x00000000 },
33877 - { 0x00008110, 0x00000168 },
33878 - { 0x00008118, 0x000100aa },
33879 - { 0x0000811c, 0x00003210 },
33880 - { 0x00008120, 0x08f04810 },
33881 - { 0x00008124, 0x00000000 },
33882 - { 0x00008128, 0x00000000 },
33883 - { 0x0000812c, 0x00000000 },
33884 - { 0x00008130, 0x00000000 },
33885 - { 0x00008134, 0x00000000 },
33886 - { 0x00008138, 0x00000000 },
33887 - { 0x0000813c, 0x00000000 },
33888 - { 0x00008144, 0xffffffff },
33889 - { 0x00008168, 0x00000000 },
33890 - { 0x0000816c, 0x00000000 },
33891 - { 0x00008170, 0x32143320 },
33892 - { 0x00008174, 0xfaa4fa50 },
33893 - { 0x00008178, 0x00000100 },
33894 - { 0x0000817c, 0x00000000 },
33895 - { 0x000081c0, 0x00000000 },
33896 - { 0x000081d0, 0x0000320a },
33897 - { 0x000081ec, 0x00000000 },
33898 - { 0x000081f0, 0x00000000 },
33899 - { 0x000081f4, 0x00000000 },
33900 - { 0x000081f8, 0x00000000 },
33901 - { 0x000081fc, 0x00000000 },
33902 - { 0x00008200, 0x00000000 },
33903 - { 0x00008204, 0x00000000 },
33904 - { 0x00008208, 0x00000000 },
33905 - { 0x0000820c, 0x00000000 },
33906 - { 0x00008210, 0x00000000 },
33907 - { 0x00008214, 0x00000000 },
33908 - { 0x00008218, 0x00000000 },
33909 - { 0x0000821c, 0x00000000 },
33910 - { 0x00008220, 0x00000000 },
33911 - { 0x00008224, 0x00000000 },
33912 - { 0x00008228, 0x00000000 },
33913 - { 0x0000822c, 0x00000000 },
33914 - { 0x00008230, 0x00000000 },
33915 - { 0x00008234, 0x00000000 },
33916 - { 0x00008238, 0x00000000 },
33917 - { 0x0000823c, 0x00000000 },
33918 - { 0x00008240, 0x00100000 },
33919 - { 0x00008244, 0x0010f400 },
33920 - { 0x00008248, 0x00000100 },
33921 - { 0x0000824c, 0x0001e800 },
33922 - { 0x00008250, 0x00000000 },
33923 - { 0x00008254, 0x00000000 },
33924 - { 0x00008258, 0x00000000 },
33925 - { 0x0000825c, 0x400000ff },
33926 - { 0x00008260, 0x00080922 },
33927 - { 0x00008264, 0xa8a00010 },
33928 - { 0x00008270, 0x00000000 },
33929 - { 0x00008274, 0x40000000 },
33930 - { 0x00008278, 0x003e4180 },
33931 - { 0x0000827c, 0x00000000 },
33932 - { 0x00008284, 0x0000002c },
33933 - { 0x00008288, 0x0000002c },
33934 - { 0x0000828c, 0x00000000 },
33935 - { 0x00008294, 0x00000000 },
33936 - { 0x00008298, 0x00000000 },
33937 - { 0x0000829c, 0x00000000 },
33938 - { 0x00008300, 0x00000040 },
33939 - { 0x00008314, 0x00000000 },
33940 - { 0x00008328, 0x00000000 },
33941 - { 0x0000832c, 0x00000001 },
33942 - { 0x00008330, 0x00000302 },
33943 - { 0x00008334, 0x00000e00 },
33944 - { 0x00008338, 0x00ff0000 },
33945 - { 0x0000833c, 0x00000000 },
33946 - { 0x00008340, 0x00010380 },
33947 - { 0x00008344, 0x00581043 },
33948 - { 0x00007010, 0x00000030 },
33949 - { 0x00007034, 0x00000002 },
33950 - { 0x00007038, 0x000004c2 },
33951 - { 0x00007800, 0x00140000 },
33952 - { 0x00007804, 0x0e4548d8 },
33953 - { 0x00007808, 0x54214514 },
33954 - { 0x0000780c, 0x02025820 },
33955 - { 0x00007810, 0x71c0d388 },
33956 - { 0x00007814, 0x924934a8 },
33957 - { 0x0000781c, 0x00000000 },
33958 - { 0x00007828, 0x66964300 },
33959 - { 0x0000782c, 0x8db6d961 },
33960 - { 0x00007830, 0x8db6d96c },
33961 - { 0x00007834, 0x6140008b },
33962 - { 0x0000783c, 0x72ee0a72 },
33963 - { 0x00007840, 0xbbfffffc },
33964 - { 0x00007844, 0x000c0db6 },
33965 - { 0x00007848, 0x6db61b6f },
33966 - { 0x0000784c, 0x6d9b66db },
33967 - { 0x00007850, 0x6d8c6dba },
33968 - { 0x00007854, 0x00040000 },
33969 - { 0x00007858, 0xdb003012 },
33970 - { 0x0000785c, 0x04924914 },
33971 - { 0x00007860, 0x21084210 },
33972 - { 0x00007864, 0xf7d7ffde },
33973 - { 0x00007868, 0xc2034080 },
33974 - { 0x00007870, 0x10142c00 },
33975 - { 0x00009808, 0x00000000 },
33976 - { 0x0000980c, 0xafe68e30 },
33977 - { 0x00009810, 0xfd14e000 },
33978 - { 0x00009814, 0x9c0a9f6b },
33979 - { 0x0000981c, 0x00000000 },
33980 - { 0x0000982c, 0x0000a000 },
33981 - { 0x00009830, 0x00000000 },
33982 - { 0x0000983c, 0x00200400 },
33983 - { 0x0000984c, 0x0040233c },
33984 - { 0x00009854, 0x00000044 },
33985 - { 0x00009900, 0x00000000 },
33986 - { 0x00009904, 0x00000000 },
33987 - { 0x00009908, 0x00000000 },
33988 - { 0x0000990c, 0x00000000 },
33989 - { 0x0000991c, 0x10000fff },
33990 - { 0x00009920, 0x04900000 },
33991 - { 0x00009928, 0x00000001 },
33992 - { 0x0000992c, 0x00000004 },
33993 - { 0x00009934, 0x1e1f2022 },
33994 - { 0x00009938, 0x0a0b0c0d },
33995 - { 0x0000993c, 0x00000000 },
33996 - { 0x00009940, 0x14750604 },
33997 - { 0x00009948, 0x9280c00a },
33998 - { 0x0000994c, 0x00020028 },
33999 - { 0x00009954, 0x5f3ca3de },
34000 - { 0x00009958, 0x0108ecff },
34001 - { 0x00009968, 0x000003ce },
34002 - { 0x00009970, 0x192bb514 },
34003 - { 0x00009974, 0x00000000 },
34004 - { 0x00009978, 0x00000001 },
34005 - { 0x0000997c, 0x00000000 },
34006 - { 0x00009980, 0x00000000 },
34007 - { 0x00009984, 0x00000000 },
34008 - { 0x00009988, 0x00000000 },
34009 - { 0x0000998c, 0x00000000 },
34010 - { 0x00009990, 0x00000000 },
34011 - { 0x00009994, 0x00000000 },
34012 - { 0x00009998, 0x00000000 },
34013 - { 0x0000999c, 0x00000000 },
34014 - { 0x000099a0, 0x00000000 },
34015 - { 0x000099a4, 0x00000001 },
34016 - { 0x000099a8, 0x201fff00 },
34017 - { 0x000099ac, 0x2def0400 },
34018 - { 0x000099b0, 0x03051000 },
34019 - { 0x000099b4, 0x00000820 },
34020 - { 0x000099dc, 0x00000000 },
34021 - { 0x000099e0, 0x00000000 },
34022 - { 0x000099e4, 0xaaaaaaaa },
34023 - { 0x000099e8, 0x3c466478 },
34024 - { 0x000099ec, 0x0cc80caa },
34025 - { 0x000099f0, 0x00000000 },
34026 - { 0x0000a208, 0x803e68c8 },
34027 - { 0x0000a210, 0x4080a333 },
34028 - { 0x0000a214, 0x00206c10 },
34029 - { 0x0000a218, 0x009c4060 },
34030 - { 0x0000a220, 0x01834061 },
34031 - { 0x0000a224, 0x00000400 },
34032 - { 0x0000a228, 0x000003b5 },
34033 - { 0x0000a22c, 0x00000000 },
34034 - { 0x0000a234, 0x20202020 },
34035 - { 0x0000a238, 0x20202020 },
34036 - { 0x0000a244, 0x00000000 },
34037 - { 0x0000a248, 0xfffffffc },
34038 - { 0x0000a24c, 0x00000000 },
34039 - { 0x0000a254, 0x00000000 },
34040 - { 0x0000a258, 0x0ccb5380 },
34041 - { 0x0000a25c, 0x15151501 },
34042 - { 0x0000a260, 0xdfa90f01 },
34043 - { 0x0000a268, 0x00000000 },
34044 - { 0x0000a26c, 0x0ebae9e6 },
34045 - { 0x0000a388, 0x0c000000 },
34046 - { 0x0000a38c, 0x20202020 },
34047 - { 0x0000a390, 0x20202020 },
34048 - { 0x0000a39c, 0x00000001 },
34049 - { 0x0000a3a0, 0x00000000 },
34050 - { 0x0000a3a4, 0x00000000 },
34051 - { 0x0000a3a8, 0x00000000 },
34052 - { 0x0000a3ac, 0x00000000 },
34053 - { 0x0000a3b0, 0x00000000 },
34054 - { 0x0000a3b4, 0x00000000 },
34055 - { 0x0000a3b8, 0x00000000 },
34056 - { 0x0000a3bc, 0x00000000 },
34057 - { 0x0000a3c0, 0x00000000 },
34058 - { 0x0000a3c4, 0x00000000 },
34059 - { 0x0000a3cc, 0x20202020 },
34060 - { 0x0000a3d0, 0x20202020 },
34061 - { 0x0000a3d4, 0x20202020 },
34062 - { 0x0000a3e4, 0x00000000 },
34063 - { 0x0000a3e8, 0x18c43433 },
34064 - { 0x0000a3ec, 0x00f70081 },
34065 - { 0x0000a3f0, 0x01036a2f },
34066 - { 0x0000a3f4, 0x00000000 },
34067 - { 0x0000d270, 0x0d820820 },
34068 - { 0x0000d35c, 0x07ffffef },
34069 - { 0x0000d360, 0x0fffffe7 },
34070 - { 0x0000d364, 0x17ffffe5 },
34071 - { 0x0000d368, 0x1fffffe4 },
34072 - { 0x0000d36c, 0x37ffffe3 },
34073 - { 0x0000d370, 0x3fffffe3 },
34074 - { 0x0000d374, 0x57ffffe3 },
34075 - { 0x0000d378, 0x5fffffe2 },
34076 - { 0x0000d37c, 0x7fffffe2 },
34077 - { 0x0000d380, 0x7f3c7bba },
34078 - { 0x0000d384, 0xf3307ff0 },
34079 -};
34080 -
34081 -static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = {
34082 - { 0x0000a1f4, 0x00fffeff },
34083 - { 0x0000a1f8, 0x00f5f9ff },
34084 - { 0x0000a1fc, 0xb79f6427 },
34085 -};
34086 -
34087 -static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
34088 - { 0x0000a1f4, 0x00000000 },
34089 - { 0x0000a1f8, 0xefff0301 },
34090 - { 0x0000a1fc, 0xca9228ee },
34091 -};
34092 -
34093 -static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
34094 - { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
34095 - { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
34096 -};
34097 -
34098 -static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
34099 - { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
34100 - { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
34101 - { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
34102 - { 0x0000986c, 0x06903881, 0x06903881, 0x06903881, 0x06903881, 0x06903881 },
34103 - { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
34104 - { 0x0000a208, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8, 0x803e68c8 },
34105 - { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
34106 - { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
34107 -};
34108 -
34109 -static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
34110 - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
34111 - { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
34112 - { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
34113 - { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
34114 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001e610, 0x0001e610, 0x00000000 },
34115 - { 0x0000a314, 0x00000000, 0x00000000, 0x0002d6d0, 0x0002d6d0, 0x00000000 },
34116 - { 0x0000a318, 0x00000000, 0x00000000, 0x00039758, 0x00039758, 0x00000000 },
34117 - { 0x0000a31c, 0x00000000, 0x00000000, 0x0003b759, 0x0003b759, 0x00000000 },
34118 - { 0x0000a320, 0x00000000, 0x00000000, 0x0003d75a, 0x0003d75a, 0x00000000 },
34119 - { 0x0000a324, 0x00000000, 0x00000000, 0x0004175c, 0x0004175c, 0x00000000 },
34120 - { 0x0000a328, 0x00000000, 0x00000000, 0x0004575e, 0x0004575e, 0x00000000 },
34121 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0004979f, 0x0004979f, 0x00000000 },
34122 - { 0x0000a330, 0x00000000, 0x00000000, 0x0004d7df, 0x0004d7df, 0x00000000 },
34123 - { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
34124 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
34125 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
34126 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34127 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34128 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34129 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34130 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34131 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34132 - { 0x00007838, 0x00000029, 0x00000029, 0x00000029, 0x00000029, 0x00000029 },
34133 - { 0x00007824, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff, 0x00d8abff },
34134 - { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
34135 - { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
34136 - { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a218652, 0x0a218652, 0x0a22a652 },
34137 - { 0x0000a278, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
34138 - { 0x0000a27c, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd, 0x050e83bd },
34139 - { 0x0000a394, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
34140 - { 0x0000a398, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
34141 - { 0x0000a3dc, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd, 0x3bdef7bd },
34142 - { 0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
34143 -};
34144 -
34145 -static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
34146 - { 0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000 },
34147 - { 0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000 },
34148 - { 0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000 },
34149 - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001b240, 0x0001b240, 0x00000000 },
34150 - { 0x0000a310, 0x00000000, 0x00000000, 0x0001d241, 0x0001d241, 0x00000000 },
34151 - { 0x0000a314, 0x00000000, 0x00000000, 0x0001f600, 0x0001f600, 0x00000000 },
34152 - { 0x0000a318, 0x00000000, 0x00000000, 0x00022800, 0x00022800, 0x00000000 },
34153 - { 0x0000a31c, 0x00000000, 0x00000000, 0x00026802, 0x00026802, 0x00000000 },
34154 - { 0x0000a320, 0x00000000, 0x00000000, 0x0002b805, 0x0002b805, 0x00000000 },
34155 - { 0x0000a324, 0x00000000, 0x00000000, 0x0002ea41, 0x0002ea41, 0x00000000 },
34156 - { 0x0000a328, 0x00000000, 0x00000000, 0x00038b00, 0x00038b00, 0x00000000 },
34157 - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003ab40, 0x0003ab40, 0x00000000 },
34158 - { 0x0000a330, 0x00000000, 0x00000000, 0x0003cd80, 0x0003cd80, 0x00000000 },
34159 - { 0x0000a334, 0x000368de, 0x000368de, 0x000368de, 0x000368de, 0x00000000 },
34160 - { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
34161 - { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
34162 - { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34163 - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34164 - { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34165 - { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34166 - { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34167 - { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
34168 - { 0x00007838, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b },
34169 - { 0x00007824, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff, 0x00d8a7ff },
34170 - { 0x0000786c, 0x08609eb6, 0x08609eb6, 0x08609eba, 0x08609eba, 0x08609eb6 },
34171 - { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
34172 - { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a212652, 0x0a212652, 0x0a22a652 },
34173 - { 0x0000a278, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7, 0x0e739ce7 },
34174 - { 0x0000a27c, 0x05018063, 0x05038063, 0x05018063, 0x05018063, 0x05018063 },
34175 - { 0x0000a394, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
34176 - { 0x0000a398, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
34177 - { 0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
34178 - { 0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
34179 -};
34180 --- a/drivers/net/wireless/ath/ath9k/mac.c
34181 +++ b/drivers/net/wireless/ath/ath9k/mac.c
34182 @@ -207,281 +207,6 @@ bool ath9k_hw_stoptxdma(struct ath_hw *a
34183 }
34184 EXPORT_SYMBOL(ath9k_hw_stoptxdma);
34185
34186 -void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
34187 - u32 segLen, bool firstSeg,
34188 - bool lastSeg, const struct ath_desc *ds0)
34189 -{
34190 - struct ar5416_desc *ads = AR5416DESC(ds);
34191 -
34192 - if (firstSeg) {
34193 - ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
34194 - } else if (lastSeg) {
34195 - ads->ds_ctl0 = 0;
34196 - ads->ds_ctl1 = segLen;
34197 - ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
34198 - ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
34199 - } else {
34200 - ads->ds_ctl0 = 0;
34201 - ads->ds_ctl1 = segLen | AR_TxMore;
34202 - ads->ds_ctl2 = 0;
34203 - ads->ds_ctl3 = 0;
34204 - }
34205 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
34206 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
34207 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
34208 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
34209 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
34210 -}
34211 -EXPORT_SYMBOL(ath9k_hw_filltxdesc);
34212 -
34213 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
34214 -{
34215 - struct ar5416_desc *ads = AR5416DESC(ds);
34216 -
34217 - ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
34218 - ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
34219 - ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
34220 - ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
34221 - ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
34222 -}
34223 -EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
34224 -
34225 -int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
34226 - struct ath_tx_status *ts)
34227 -{
34228 - struct ar5416_desc *ads = AR5416DESC(ds);
34229 -
34230 - if ((ads->ds_txstatus9 & AR_TxDone) == 0)
34231 - return -EINPROGRESS;
34232 -
34233 - ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
34234 - ts->ts_tstamp = ads->AR_SendTimestamp;
34235 - ts->ts_status = 0;
34236 - ts->ts_flags = 0;
34237 -
34238 - if (ads->ds_txstatus1 & AR_FrmXmitOK)
34239 - ts->ts_status |= ATH9K_TX_ACKED;
34240 - if (ads->ds_txstatus1 & AR_ExcessiveRetries)
34241 - ts->ts_status |= ATH9K_TXERR_XRETRY;
34242 - if (ads->ds_txstatus1 & AR_Filtered)
34243 - ts->ts_status |= ATH9K_TXERR_FILT;
34244 - if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
34245 - ts->ts_status |= ATH9K_TXERR_FIFO;
34246 - ath9k_hw_updatetxtriglevel(ah, true);
34247 - }
34248 - if (ads->ds_txstatus9 & AR_TxOpExceeded)
34249 - ts->ts_status |= ATH9K_TXERR_XTXOP;
34250 - if (ads->ds_txstatus1 & AR_TxTimerExpired)
34251 - ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
34252 -
34253 - if (ads->ds_txstatus1 & AR_DescCfgErr)
34254 - ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
34255 - if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
34256 - ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
34257 - ath9k_hw_updatetxtriglevel(ah, true);
34258 - }
34259 - if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
34260 - ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
34261 - ath9k_hw_updatetxtriglevel(ah, true);
34262 - }
34263 - if (ads->ds_txstatus0 & AR_TxBaStatus) {
34264 - ts->ts_flags |= ATH9K_TX_BA;
34265 - ts->ba_low = ads->AR_BaBitmapLow;
34266 - ts->ba_high = ads->AR_BaBitmapHigh;
34267 - }
34268 -
34269 - ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
34270 - switch (ts->ts_rateindex) {
34271 - case 0:
34272 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
34273 - break;
34274 - case 1:
34275 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
34276 - break;
34277 - case 2:
34278 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
34279 - break;
34280 - case 3:
34281 - ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
34282 - break;
34283 - }
34284 -
34285 - ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
34286 - ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
34287 - ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
34288 - ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
34289 - ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
34290 - ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
34291 - ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
34292 - ts->evm0 = ads->AR_TxEVM0;
34293 - ts->evm1 = ads->AR_TxEVM1;
34294 - ts->evm2 = ads->AR_TxEVM2;
34295 - ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
34296 - ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
34297 - ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
34298 - ts->ts_antenna = 0;
34299 -
34300 - return 0;
34301 -}
34302 -EXPORT_SYMBOL(ath9k_hw_txprocdesc);
34303 -
34304 -void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
34305 - u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
34306 - u32 keyIx, enum ath9k_key_type keyType, u32 flags)
34307 -{
34308 - struct ar5416_desc *ads = AR5416DESC(ds);
34309 -
34310 - txPower += ah->txpower_indexoffset;
34311 - if (txPower > 63)
34312 - txPower = 63;
34313 -
34314 - ads->ds_ctl0 = (pktLen & AR_FrameLen)
34315 - | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
34316 - | SM(txPower, AR_XmitPower)
34317 - | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
34318 - | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
34319 - | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
34320 - | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
34321 -
34322 - ads->ds_ctl1 =
34323 - (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
34324 - | SM(type, AR_FrameType)
34325 - | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
34326 - | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
34327 - | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
34328 -
34329 - ads->ds_ctl6 = SM(keyType, AR_EncrType);
34330 -
34331 - if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
34332 - ads->ds_ctl8 = 0;
34333 - ads->ds_ctl9 = 0;
34334 - ads->ds_ctl10 = 0;
34335 - ads->ds_ctl11 = 0;
34336 - }
34337 -}
34338 -EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
34339 -
34340 -void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
34341 - struct ath_desc *lastds,
34342 - u32 durUpdateEn, u32 rtsctsRate,
34343 - u32 rtsctsDuration,
34344 - struct ath9k_11n_rate_series series[],
34345 - u32 nseries, u32 flags)
34346 -{
34347 - struct ar5416_desc *ads = AR5416DESC(ds);
34348 - struct ar5416_desc *last_ads = AR5416DESC(lastds);
34349 - u32 ds_ctl0;
34350 -
34351 - if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
34352 - ds_ctl0 = ads->ds_ctl0;
34353 -
34354 - if (flags & ATH9K_TXDESC_RTSENA) {
34355 - ds_ctl0 &= ~AR_CTSEnable;
34356 - ds_ctl0 |= AR_RTSEnable;
34357 - } else {
34358 - ds_ctl0 &= ~AR_RTSEnable;
34359 - ds_ctl0 |= AR_CTSEnable;
34360 - }
34361 -
34362 - ads->ds_ctl0 = ds_ctl0;
34363 - } else {
34364 - ads->ds_ctl0 =
34365 - (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
34366 - }
34367 -
34368 - ads->ds_ctl2 = set11nTries(series, 0)
34369 - | set11nTries(series, 1)
34370 - | set11nTries(series, 2)
34371 - | set11nTries(series, 3)
34372 - | (durUpdateEn ? AR_DurUpdateEna : 0)
34373 - | SM(0, AR_BurstDur);
34374 -
34375 - ads->ds_ctl3 = set11nRate(series, 0)
34376 - | set11nRate(series, 1)
34377 - | set11nRate(series, 2)
34378 - | set11nRate(series, 3);
34379 -
34380 - ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
34381 - | set11nPktDurRTSCTS(series, 1);
34382 -
34383 - ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
34384 - | set11nPktDurRTSCTS(series, 3);
34385 -
34386 - ads->ds_ctl7 = set11nRateFlags(series, 0)
34387 - | set11nRateFlags(series, 1)
34388 - | set11nRateFlags(series, 2)
34389 - | set11nRateFlags(series, 3)
34390 - | SM(rtsctsRate, AR_RTSCTSRate);
34391 - last_ads->ds_ctl2 = ads->ds_ctl2;
34392 - last_ads->ds_ctl3 = ads->ds_ctl3;
34393 -}
34394 -EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
34395 -
34396 -void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
34397 - u32 aggrLen)
34398 -{
34399 - struct ar5416_desc *ads = AR5416DESC(ds);
34400 -
34401 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
34402 - ads->ds_ctl6 &= ~AR_AggrLen;
34403 - ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
34404 -}
34405 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
34406 -
34407 -void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
34408 - u32 numDelims)
34409 -{
34410 - struct ar5416_desc *ads = AR5416DESC(ds);
34411 - unsigned int ctl6;
34412 -
34413 - ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
34414 -
34415 - ctl6 = ads->ds_ctl6;
34416 - ctl6 &= ~AR_PadDelim;
34417 - ctl6 |= SM(numDelims, AR_PadDelim);
34418 - ads->ds_ctl6 = ctl6;
34419 -}
34420 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
34421 -
34422 -void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
34423 -{
34424 - struct ar5416_desc *ads = AR5416DESC(ds);
34425 -
34426 - ads->ds_ctl1 |= AR_IsAggr;
34427 - ads->ds_ctl1 &= ~AR_MoreAggr;
34428 - ads->ds_ctl6 &= ~AR_PadDelim;
34429 -}
34430 -EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
34431 -
34432 -void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
34433 -{
34434 - struct ar5416_desc *ads = AR5416DESC(ds);
34435 -
34436 - ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
34437 -}
34438 -EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
34439 -
34440 -void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
34441 - u32 burstDuration)
34442 -{
34443 - struct ar5416_desc *ads = AR5416DESC(ds);
34444 -
34445 - ads->ds_ctl2 &= ~AR_BurstDur;
34446 - ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
34447 -}
34448 -EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
34449 -
34450 -void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
34451 - u32 vmf)
34452 -{
34453 - struct ar5416_desc *ads = AR5416DESC(ds);
34454 -
34455 - if (vmf)
34456 - ads->ds_ctl0 |= AR_VirtMoreFrag;
34457 - else
34458 - ads->ds_ctl0 &= ~AR_VirtMoreFrag;
34459 -}
34460 -
34461 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
34462 {
34463 *txqs &= ah->intr_txqs;
34464 @@ -796,6 +521,12 @@ bool ath9k_hw_resettxqueue(struct ath_hw
34465 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
34466 | AR_D_MISC_BEACON_USE
34467 | AR_D_MISC_POST_FR_BKOFF_DIS);
34468 + /* cwmin and cwmax should be 0 for beacon queue */
34469 + if (AR_SREV_9300_20_OR_LATER(ah)) {
34470 + REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
34471 + | SM(0, AR_D_LCL_IFS_CWMAX)
34472 + | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
34473 + }
34474 break;
34475 case ATH9K_TX_QUEUE_CAB:
34476 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
34477 @@ -832,6 +563,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw
34478 AR_D_MISC_POST_FR_BKOFF_DIS);
34479 }
34480
34481 + if (AR_SREV_9300_20_OR_LATER(ah))
34482 + REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
34483 +
34484 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
34485 ah->txok_interrupt_mask |= 1 << q;
34486 else
34487 @@ -999,12 +733,6 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah
34488 }
34489 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
34490
34491 -void ath9k_hw_rxena(struct ath_hw *ah)
34492 -{
34493 - REG_WRITE(ah, AR_CR, AR_CR_RXE);
34494 -}
34495 -EXPORT_SYMBOL(ath9k_hw_rxena);
34496 -
34497 void ath9k_hw_startpcureceive(struct ath_hw *ah)
34498 {
34499 ath9k_enable_mib_counters(ah);
34500 @@ -1023,6 +751,14 @@ void ath9k_hw_stoppcurecv(struct ath_hw
34501 }
34502 EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
34503
34504 +void ath9k_hw_abortpcurecv(struct ath_hw *ah)
34505 +{
34506 + REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
34507 +
34508 + ath9k_hw_disable_mib_counters(ah);
34509 +}
34510 +EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
34511 +
34512 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
34513 {
34514 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
34515 @@ -1068,3 +804,140 @@ int ath9k_hw_beaconq_setup(struct ath_hw
34516 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
34517 }
34518 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
34519 +
34520 +bool ath9k_hw_intrpend(struct ath_hw *ah)
34521 +{
34522 + u32 host_isr;
34523 +
34524 + if (AR_SREV_9100(ah))
34525 + return true;
34526 +
34527 + host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
34528 + if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
34529 + return true;
34530 +
34531 + host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
34532 + if ((host_isr & AR_INTR_SYNC_DEFAULT)
34533 + && (host_isr != AR_INTR_SPURIOUS))
34534 + return true;
34535 +
34536 + return false;
34537 +}
34538 +EXPORT_SYMBOL(ath9k_hw_intrpend);
34539 +
34540 +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
34541 + enum ath9k_int ints)
34542 +{
34543 + enum ath9k_int omask = ah->imask;
34544 + u32 mask, mask2;
34545 + struct ath9k_hw_capabilities *pCap = &ah->caps;
34546 + struct ath_common *common = ath9k_hw_common(ah);
34547 +
34548 + ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
34549 +
34550 + if (omask & ATH9K_INT_GLOBAL) {
34551 + ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
34552 + REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
34553 + (void) REG_READ(ah, AR_IER);
34554 + if (!AR_SREV_9100(ah)) {
34555 + REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
34556 + (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
34557 +
34558 + REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
34559 + (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
34560 + }
34561 + }
34562 +
34563 + /* TODO: global int Ref count */
34564 + mask = ints & ATH9K_INT_COMMON;
34565 + mask2 = 0;
34566 +
34567 + if (ints & ATH9K_INT_TX) {
34568 + if (ah->config.tx_intr_mitigation)
34569 + mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
34570 + if (ah->txok_interrupt_mask)
34571 + mask |= AR_IMR_TXOK;
34572 + if (ah->txdesc_interrupt_mask)
34573 + mask |= AR_IMR_TXDESC;
34574 + if (ah->txerr_interrupt_mask)
34575 + mask |= AR_IMR_TXERR;
34576 + if (ah->txeol_interrupt_mask)
34577 + mask |= AR_IMR_TXEOL;
34578 + }
34579 + if (ints & ATH9K_INT_RX) {
34580 + if (AR_SREV_9300_20_OR_LATER(ah)) {
34581 + mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
34582 + if (ah->config.rx_intr_mitigation) {
34583 + mask &= ~AR_IMR_RXOK_LP;
34584 + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
34585 + } else {
34586 + mask |= AR_IMR_RXOK_LP;
34587 + }
34588 + } else {
34589 + if (ah->config.rx_intr_mitigation)
34590 + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
34591 + else
34592 + mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
34593 + }
34594 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
34595 + mask |= AR_IMR_GENTMR;
34596 + }
34597 +
34598 + if (ints & (ATH9K_INT_BMISC)) {
34599 + mask |= AR_IMR_BCNMISC;
34600 + if (ints & ATH9K_INT_TIM)
34601 + mask2 |= AR_IMR_S2_TIM;
34602 + if (ints & ATH9K_INT_DTIM)
34603 + mask2 |= AR_IMR_S2_DTIM;
34604 + if (ints & ATH9K_INT_DTIMSYNC)
34605 + mask2 |= AR_IMR_S2_DTIMSYNC;
34606 + if (ints & ATH9K_INT_CABEND)
34607 + mask2 |= AR_IMR_S2_CABEND;
34608 + if (ints & ATH9K_INT_TSFOOR)
34609 + mask2 |= AR_IMR_S2_TSFOOR;
34610 + }
34611 +
34612 + if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
34613 + mask |= AR_IMR_BCNMISC;
34614 + if (ints & ATH9K_INT_GTT)
34615 + mask2 |= AR_IMR_S2_GTT;
34616 + if (ints & ATH9K_INT_CST)
34617 + mask2 |= AR_IMR_S2_CST;
34618 + }
34619 +
34620 + ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
34621 + REG_WRITE(ah, AR_IMR, mask);
34622 + ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
34623 + AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
34624 + AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
34625 + ah->imrs2_reg |= mask2;
34626 + REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
34627 +
34628 + if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
34629 + if (ints & ATH9K_INT_TIM_TIMER)
34630 + REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
34631 + else
34632 + REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
34633 + }
34634 +
34635 + if (ints & ATH9K_INT_GLOBAL) {
34636 + ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
34637 + REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
34638 + if (!AR_SREV_9100(ah)) {
34639 + REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
34640 + AR_INTR_MAC_IRQ);
34641 + REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
34642 +
34643 +
34644 + REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
34645 + AR_INTR_SYNC_DEFAULT);
34646 + REG_WRITE(ah, AR_INTR_SYNC_MASK,
34647 + AR_INTR_SYNC_DEFAULT);
34648 + }
34649 + ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
34650 + REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
34651 + }
34652 +
34653 + return omask;
34654 +}
34655 +EXPORT_SYMBOL(ath9k_hw_set_interrupts);
34656 --- a/drivers/net/wireless/ath/ath9k/mac.h
34657 +++ b/drivers/net/wireless/ath/ath9k/mac.h
34658 @@ -86,7 +86,6 @@
34659 #define ATH9K_TX_DESC_CFG_ERR 0x04
34660 #define ATH9K_TX_DATA_UNDERRUN 0x08
34661 #define ATH9K_TX_DELIM_UNDERRUN 0x10
34662 -#define ATH9K_TX_SW_ABORTED 0x40
34663 #define ATH9K_TX_SW_FILTERED 0x80
34664
34665 /* 64 bytes */
34666 @@ -117,7 +116,10 @@ struct ath_tx_status {
34667 int8_t ts_rssi_ext0;
34668 int8_t ts_rssi_ext1;
34669 int8_t ts_rssi_ext2;
34670 - u8 pad[3];
34671 + u8 qid;
34672 + u16 desc_id;
34673 + u8 tid;
34674 + u8 pad[2];
34675 u32 ba_low;
34676 u32 ba_high;
34677 u32 evm0;
34678 @@ -148,6 +150,8 @@ struct ath_rx_status {
34679 u32 evm0;
34680 u32 evm1;
34681 u32 evm2;
34682 + u32 evm3;
34683 + u32 evm4;
34684 };
34685
34686 struct ath_htc_rx_status {
34687 @@ -259,7 +263,8 @@ struct ath_desc {
34688 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
34689 #define ATH9K_TXDESC_VMF 0x0100
34690 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
34691 -#define ATH9K_TXDESC_CAB 0x0400
34692 +#define ATH9K_TXDESC_LOWRXCHAIN 0x0400
34693 +#define ATH9K_TXDESC_LDPC 0x00010000
34694
34695 #define ATH9K_RXDESC_INTREQ 0x0020
34696
34697 @@ -353,7 +358,8 @@ struct ar5416_desc {
34698 #define AR_DestIdxValid 0x40000000
34699 #define AR_CTSEnable 0x80000000
34700
34701 -#define AR_BufLen 0x00000fff
34702 +#define AR_BufLen AR_SREV_9300_20_OR_LATER(ah) ? 0x0fff0000 : \
34703 + 0x00000fff
34704 #define AR_TxMore 0x00001000
34705 #define AR_DestIdx 0x000fe000
34706 #define AR_DestIdx_S 13
34707 @@ -410,6 +416,7 @@ struct ar5416_desc {
34708 #define AR_EncrType 0x0c000000
34709 #define AR_EncrType_S 26
34710 #define AR_TxCtlRsvd61 0xf0000000
34711 +#define AR_LDPC 0x80000000
34712
34713 #define AR_2040_0 0x00000001
34714 #define AR_GI0 0x00000002
34715 @@ -493,7 +500,6 @@ struct ar5416_desc {
34716
34717 #define AR_RxCTLRsvd00 0xffffffff
34718
34719 -#define AR_BufLen 0x00000fff
34720 #define AR_RxCtlRsvd00 0x00001000
34721 #define AR_RxIntrReq 0x00002000
34722 #define AR_RxCtlRsvd01 0xffffc000
34723 @@ -689,31 +695,6 @@ void ath9k_hw_txstart(struct ath_hw *ah,
34724 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
34725 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
34726 bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
34727 -void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
34728 - u32 segLen, bool firstSeg,
34729 - bool lastSeg, const struct ath_desc *ds0);
34730 -void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
34731 -int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
34732 - struct ath_tx_status *ts);
34733 -void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
34734 - u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
34735 - u32 keyIx, enum ath9k_key_type keyType, u32 flags);
34736 -void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
34737 - struct ath_desc *lastds,
34738 - u32 durUpdateEn, u32 rtsctsRate,
34739 - u32 rtsctsDuration,
34740 - struct ath9k_11n_rate_series series[],
34741 - u32 nseries, u32 flags);
34742 -void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
34743 - u32 aggrLen);
34744 -void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
34745 - u32 numDelims);
34746 -void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
34747 -void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
34748 -void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
34749 - u32 burstDuration);
34750 -void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
34751 - u32 vmf);
34752 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
34753 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
34754 const struct ath9k_tx_queue_info *qinfo);
34755 @@ -729,10 +710,17 @@ void ath9k_hw_setuprxdesc(struct ath_hw
34756 u32 size, u32 flags);
34757 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
34758 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
34759 -void ath9k_hw_rxena(struct ath_hw *ah);
34760 void ath9k_hw_startpcureceive(struct ath_hw *ah);
34761 void ath9k_hw_stoppcurecv(struct ath_hw *ah);
34762 +void ath9k_hw_abortpcurecv(struct ath_hw *ah);
34763 bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
34764 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
34765
34766 +/* Interrupt Handling */
34767 +bool ath9k_hw_intrpend(struct ath_hw *ah);
34768 +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
34769 + enum ath9k_int ints);
34770 +
34771 +void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
34772 +
34773 #endif /* MAC_H */
34774 --- a/drivers/net/wireless/ath/ath9k/main.c
34775 +++ b/drivers/net/wireless/ath/ath9k/main.c
34776 @@ -401,6 +401,7 @@ void ath9k_tasklet(unsigned long data)
34777 struct ath_common *common = ath9k_hw_common(ah);
34778
34779 u32 status = sc->intrstatus;
34780 + u32 rxmask;
34781
34782 ath9k_ps_wakeup(sc);
34783
34784 @@ -410,14 +411,30 @@ void ath9k_tasklet(unsigned long data)
34785 return;
34786 }
34787
34788 - if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
34789 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34790 + rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
34791 + ATH9K_INT_RXORN);
34792 + else
34793 + rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
34794 +
34795 + if (status & rxmask) {
34796 spin_lock_bh(&sc->rx.rxflushlock);
34797 - ath_rx_tasklet(sc, 0);
34798 +
34799 + /* Check for high priority Rx first */
34800 + if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
34801 + (status & ATH9K_INT_RXHP))
34802 + ath_rx_tasklet(sc, 0, true);
34803 +
34804 + ath_rx_tasklet(sc, 0, false);
34805 spin_unlock_bh(&sc->rx.rxflushlock);
34806 }
34807
34808 - if (status & ATH9K_INT_TX)
34809 - ath_tx_tasklet(sc);
34810 + if (status & ATH9K_INT_TX) {
34811 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34812 + ath_tx_edma_tasklet(sc);
34813 + else
34814 + ath_tx_tasklet(sc);
34815 + }
34816
34817 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
34818 /*
34819 @@ -445,6 +462,8 @@ irqreturn_t ath_isr(int irq, void *dev)
34820 ATH9K_INT_RXORN | \
34821 ATH9K_INT_RXEOL | \
34822 ATH9K_INT_RX | \
34823 + ATH9K_INT_RXLP | \
34824 + ATH9K_INT_RXHP | \
34825 ATH9K_INT_TX | \
34826 ATH9K_INT_BMISS | \
34827 ATH9K_INT_CST | \
34828 @@ -496,7 +515,8 @@ irqreturn_t ath_isr(int irq, void *dev)
34829 * If a FATAL or RXORN interrupt is received, we have to reset the
34830 * chip immediately.
34831 */
34832 - if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
34833 + if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
34834 + !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
34835 goto chip_reset;
34836
34837 if (status & ATH9K_INT_SWBA)
34838 @@ -505,6 +525,13 @@ irqreturn_t ath_isr(int irq, void *dev)
34839 if (status & ATH9K_INT_TXURN)
34840 ath9k_hw_updatetxtriglevel(ah, true);
34841
34842 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
34843 + if (status & ATH9K_INT_RXEOL) {
34844 + ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
34845 + ath9k_hw_set_interrupts(ah, ah->imask);
34846 + }
34847 + }
34848 +
34849 if (status & ATH9K_INT_MIB) {
34850 /*
34851 * Disable interrupts until we service the MIB
34852 @@ -1162,9 +1189,14 @@ static int ath9k_start(struct ieee80211_
34853 }
34854
34855 /* Setup our intr mask. */
34856 - ah->imask = ATH9K_INT_RX | ATH9K_INT_TX
34857 - | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
34858 - | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
34859 + ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
34860 + ATH9K_INT_RXORN | ATH9K_INT_FATAL |
34861 + ATH9K_INT_GLOBAL;
34862 +
34863 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
34864 + ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
34865 + else
34866 + ah->imask |= ATH9K_INT_RX;
34867
34868 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
34869 ah->imask |= ATH9K_INT_GTT;
34870 --- a/drivers/net/wireless/ath/ath9k/pci.c
34871 +++ b/drivers/net/wireless/ath/ath9k/pci.c
34872 @@ -28,6 +28,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
34873 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
34874 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
34875 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
34876 + { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
34877 { 0 }
34878 };
34879
34880 --- a/drivers/net/wireless/ath/ath9k/phy.c
34881 +++ /dev/null
34882 @@ -1,976 +0,0 @@
34883 -/*
34884 - * Copyright (c) 2008-2009 Atheros Communications Inc.
34885 - *
34886 - * Permission to use, copy, modify, and/or distribute this software for any
34887 - * purpose with or without fee is hereby granted, provided that the above
34888 - * copyright notice and this permission notice appear in all copies.
34889 - *
34890 - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
34891 - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
34892 - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
34893 - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34894 - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
34895 - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
34896 - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
34897 - */
34898 -
34899 -/**
34900 - * DOC: Programming Atheros 802.11n analog front end radios
34901 - *
34902 - * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
34903 - * devices have either an external AR2133 analog front end radio for single
34904 - * band 2.4 GHz communication or an AR5133 analog front end radio for dual
34905 - * band 2.4 GHz / 5 GHz communication.
34906 - *
34907 - * All devices after the AR5416 and AR5418 family starting with the AR9280
34908 - * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
34909 - * into a single-chip and require less programming.
34910 - *
34911 - * The following single-chips exist with a respective embedded radio:
34912 - *
34913 - * AR9280 - 11n dual-band 2x2 MIMO for PCIe
34914 - * AR9281 - 11n single-band 1x2 MIMO for PCIe
34915 - * AR9285 - 11n single-band 1x1 for PCIe
34916 - * AR9287 - 11n single-band 2x2 MIMO for PCIe
34917 - *
34918 - * AR9220 - 11n dual-band 2x2 MIMO for PCI
34919 - * AR9223 - 11n single-band 2x2 MIMO for PCI
34920 - *
34921 - * AR9287 - 11n single-band 1x1 MIMO for USB
34922 - */
34923 -
34924 -#include "hw.h"
34925 -
34926 -/**
34927 - * ath9k_hw_write_regs - ??
34928 - *
34929 - * @ah: atheros hardware structure
34930 - * @freqIndex:
34931 - * @regWrites:
34932 - *
34933 - * Used for both the chipsets with an external AR2133/AR5133 radios and
34934 - * single-chip devices.
34935 - */
34936 -void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
34937 -{
34938 - REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
34939 -}
34940 -
34941 -/**
34942 - * ath9k_hw_ar9280_set_channel - set channel on single-chip device
34943 - * @ah: atheros hardware structure
34944 - * @chan:
34945 - *
34946 - * This is the function to change channel on single-chip devices, that is
34947 - * all devices after ar9280.
34948 - *
34949 - * This function takes the channel value in MHz and sets
34950 - * hardware channel value. Assumes writes have been enabled to analog bus.
34951 - *
34952 - * Actual Expression,
34953 - *
34954 - * For 2GHz channel,
34955 - * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
34956 - * (freq_ref = 40MHz)
34957 - *
34958 - * For 5GHz channel,
34959 - * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
34960 - * (freq_ref = 40MHz/(24>>amodeRefSel))
34961 - */
34962 -int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
34963 -{
34964 - u16 bMode, fracMode, aModeRefSel = 0;
34965 - u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
34966 - struct chan_centers centers;
34967 - u32 refDivA = 24;
34968 -
34969 - ath9k_hw_get_channel_centers(ah, chan, &centers);
34970 - freq = centers.synth_center;
34971 -
34972 - reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
34973 - reg32 &= 0xc0000000;
34974 -
34975 - if (freq < 4800) { /* 2 GHz, fractional mode */
34976 - u32 txctl;
34977 - int regWrites = 0;
34978 -
34979 - bMode = 1;
34980 - fracMode = 1;
34981 - aModeRefSel = 0;
34982 - channelSel = (freq * 0x10000) / 15;
34983 -
34984 - if (AR_SREV_9287_11_OR_LATER(ah)) {
34985 - if (freq == 2484) {
34986 - /* Enable channel spreading for channel 14 */
34987 - REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
34988 - 1, regWrites);
34989 - } else {
34990 - REG_WRITE_ARRAY(&ah->iniCckfirNormal,
34991 - 1, regWrites);
34992 - }
34993 - } else {
34994 - txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
34995 - if (freq == 2484) {
34996 - /* Enable channel spreading for channel 14 */
34997 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
34998 - txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
34999 - } else {
35000 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
35001 - txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
35002 - }
35003 - }
35004 - } else {
35005 - bMode = 0;
35006 - fracMode = 0;
35007 -
35008 - switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
35009 - case 0:
35010 - if ((freq % 20) == 0) {
35011 - aModeRefSel = 3;
35012 - } else if ((freq % 10) == 0) {
35013 - aModeRefSel = 2;
35014 - }
35015 - if (aModeRefSel)
35016 - break;
35017 - case 1:
35018 - default:
35019 - aModeRefSel = 0;
35020 - /*
35021 - * Enable 2G (fractional) mode for channels
35022 - * which are 5MHz spaced.
35023 - */
35024 - fracMode = 1;
35025 - refDivA = 1;
35026 - channelSel = (freq * 0x8000) / 15;
35027 -
35028 - /* RefDivA setting */
35029 - REG_RMW_FIELD(ah, AR_AN_SYNTH9,
35030 - AR_AN_SYNTH9_REFDIVA, refDivA);
35031 -
35032 - }
35033 -
35034 - if (!fracMode) {
35035 - ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
35036 - channelSel = ndiv & 0x1ff;
35037 - channelFrac = (ndiv & 0xfffffe00) * 2;
35038 - channelSel = (channelSel << 17) | channelFrac;
35039 - }
35040 - }
35041 -
35042 - reg32 = reg32 |
35043 - (bMode << 29) |
35044 - (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
35045 -
35046 - REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
35047 -
35048 - ah->curchan = chan;
35049 - ah->curchan_rad_index = -1;
35050 -
35051 - return 0;
35052 -}
35053 -
35054 -/**
35055 - * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
35056 - * @ah: atheros hardware structure
35057 - * @chan:
35058 - *
35059 - * For single-chip solutions. Converts to baseband spur frequency given the
35060 - * input channel frequency and compute register settings below.
35061 - */
35062 -void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
35063 -{
35064 - int bb_spur = AR_NO_SPUR;
35065 - int freq;
35066 - int bin, cur_bin;
35067 - int bb_spur_off, spur_subchannel_sd;
35068 - int spur_freq_sd;
35069 - int spur_delta_phase;
35070 - int denominator;
35071 - int upper, lower, cur_vit_mask;
35072 - int tmp, newVal;
35073 - int i;
35074 - int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
35075 - AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
35076 - };
35077 - int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
35078 - AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
35079 - };
35080 - int inc[4] = { 0, 100, 0, 0 };
35081 - struct chan_centers centers;
35082 -
35083 - int8_t mask_m[123];
35084 - int8_t mask_p[123];
35085 - int8_t mask_amt;
35086 - int tmp_mask;
35087 - int cur_bb_spur;
35088 - bool is2GHz = IS_CHAN_2GHZ(chan);
35089 -
35090 - memset(&mask_m, 0, sizeof(int8_t) * 123);
35091 - memset(&mask_p, 0, sizeof(int8_t) * 123);
35092 -
35093 - ath9k_hw_get_channel_centers(ah, chan, &centers);
35094 - freq = centers.synth_center;
35095 -
35096 - ah->config.spurmode = SPUR_ENABLE_EEPROM;
35097 - for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
35098 - cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
35099 -
35100 - if (is2GHz)
35101 - cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
35102 - else
35103 - cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
35104 -
35105 - if (AR_NO_SPUR == cur_bb_spur)
35106 - break;
35107 - cur_bb_spur = cur_bb_spur - freq;
35108 -
35109 - if (IS_CHAN_HT40(chan)) {
35110 - if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
35111 - (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
35112 - bb_spur = cur_bb_spur;
35113 - break;
35114 - }
35115 - } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
35116 - (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
35117 - bb_spur = cur_bb_spur;
35118 - break;
35119 - }
35120 - }
35121 -
35122 - if (AR_NO_SPUR == bb_spur) {
35123 - REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
35124 - AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
35125 - return;
35126 - } else {
35127 - REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
35128 - AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
35129 - }
35130 -
35131 - bin = bb_spur * 320;
35132 -
35133 - tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
35134 -
35135 - newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
35136 - AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
35137 - AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
35138 - AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
35139 - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
35140 -
35141 - newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
35142 - AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
35143 - AR_PHY_SPUR_REG_MASK_RATE_SELECT |
35144 - AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
35145 - SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
35146 - REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
35147 -
35148 - if (IS_CHAN_HT40(chan)) {
35149 - if (bb_spur < 0) {
35150 - spur_subchannel_sd = 1;
35151 - bb_spur_off = bb_spur + 10;
35152 - } else {
35153 - spur_subchannel_sd = 0;
35154 - bb_spur_off = bb_spur - 10;
35155 - }
35156 - } else {
35157 - spur_subchannel_sd = 0;
35158 - bb_spur_off = bb_spur;
35159 - }
35160 -
35161 - if (IS_CHAN_HT40(chan))
35162 - spur_delta_phase =
35163 - ((bb_spur * 262144) /
35164 - 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
35165 - else
35166 - spur_delta_phase =
35167 - ((bb_spur * 524288) /
35168 - 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
35169 -
35170 - denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
35171 - spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
35172 -
35173 - newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
35174 - SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
35175 - SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
35176 - REG_WRITE(ah, AR_PHY_TIMING11, newVal);
35177 -
35178 - newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
35179 - REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
35180 -
35181 - cur_bin = -6000;
35182 - upper = bin + 100;
35183 - lower = bin - 100;
35184 -
35185 - for (i = 0; i < 4; i++) {
35186 - int pilot_mask = 0;
35187 - int chan_mask = 0;
35188 - int bp = 0;
35189 - for (bp = 0; bp < 30; bp++) {
35190 - if ((cur_bin > lower) && (cur_bin < upper)) {
35191 - pilot_mask = pilot_mask | 0x1 << bp;
35192 - chan_mask = chan_mask | 0x1 << bp;
35193 - }
35194 - cur_bin += 100;
35195 - }
35196 - cur_bin += inc[i];
35197 - REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
35198 - REG_WRITE(ah, chan_mask_reg[i], chan_mask);
35199 - }
35200 -
35201 - cur_vit_mask = 6100;
35202 - upper = bin + 120;
35203 - lower = bin - 120;
35204 -
35205 - for (i = 0; i < 123; i++) {
35206 - if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
35207 -
35208 - /* workaround for gcc bug #37014 */
35209 - volatile int tmp_v = abs(cur_vit_mask - bin);
35210 -
35211 - if (tmp_v < 75)
35212 - mask_amt = 1;
35213 - else
35214 - mask_amt = 0;
35215 - if (cur_vit_mask < 0)
35216 - mask_m[abs(cur_vit_mask / 100)] = mask_amt;
35217 - else
35218 - mask_p[cur_vit_mask / 100] = mask_amt;
35219 - }
35220 - cur_vit_mask -= 100;
35221 - }
35222 -
35223 - tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
35224 - | (mask_m[48] << 26) | (mask_m[49] << 24)
35225 - | (mask_m[50] << 22) | (mask_m[51] << 20)
35226 - | (mask_m[52] << 18) | (mask_m[53] << 16)
35227 - | (mask_m[54] << 14) | (mask_m[55] << 12)
35228 - | (mask_m[56] << 10) | (mask_m[57] << 8)
35229 - | (mask_m[58] << 6) | (mask_m[59] << 4)
35230 - | (mask_m[60] << 2) | (mask_m[61] << 0);
35231 - REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
35232 - REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
35233 -
35234 - tmp_mask = (mask_m[31] << 28)
35235 - | (mask_m[32] << 26) | (mask_m[33] << 24)
35236 - | (mask_m[34] << 22) | (mask_m[35] << 20)
35237 - | (mask_m[36] << 18) | (mask_m[37] << 16)
35238 - | (mask_m[48] << 14) | (mask_m[39] << 12)
35239 - | (mask_m[40] << 10) | (mask_m[41] << 8)
35240 - | (mask_m[42] << 6) | (mask_m[43] << 4)
35241 - | (mask_m[44] << 2) | (mask_m[45] << 0);
35242 - REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
35243 - REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
35244 -
35245 - tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
35246 - | (mask_m[18] << 26) | (mask_m[18] << 24)
35247 - | (mask_m[20] << 22) | (mask_m[20] << 20)
35248 - | (mask_m[22] << 18) | (mask_m[22] << 16)
35249 - | (mask_m[24] << 14) | (mask_m[24] << 12)
35250 - | (mask_m[25] << 10) | (mask_m[26] << 8)
35251 - | (mask_m[27] << 6) | (mask_m[28] << 4)
35252 - | (mask_m[29] << 2) | (mask_m[30] << 0);
35253 - REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
35254 - REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
35255 -
35256 - tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
35257 - | (mask_m[2] << 26) | (mask_m[3] << 24)
35258 - | (mask_m[4] << 22) | (mask_m[5] << 20)
35259 - | (mask_m[6] << 18) | (mask_m[7] << 16)
35260 - | (mask_m[8] << 14) | (mask_m[9] << 12)
35261 - | (mask_m[10] << 10) | (mask_m[11] << 8)
35262 - | (mask_m[12] << 6) | (mask_m[13] << 4)
35263 - | (mask_m[14] << 2) | (mask_m[15] << 0);
35264 - REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
35265 - REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
35266 -
35267 - tmp_mask = (mask_p[15] << 28)
35268 - | (mask_p[14] << 26) | (mask_p[13] << 24)
35269 - | (mask_p[12] << 22) | (mask_p[11] << 20)
35270 - | (mask_p[10] << 18) | (mask_p[9] << 16)
35271 - | (mask_p[8] << 14) | (mask_p[7] << 12)
35272 - | (mask_p[6] << 10) | (mask_p[5] << 8)
35273 - | (mask_p[4] << 6) | (mask_p[3] << 4)
35274 - | (mask_p[2] << 2) | (mask_p[1] << 0);
35275 - REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
35276 - REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
35277 -
35278 - tmp_mask = (mask_p[30] << 28)
35279 - | (mask_p[29] << 26) | (mask_p[28] << 24)
35280 - | (mask_p[27] << 22) | (mask_p[26] << 20)
35281 - | (mask_p[25] << 18) | (mask_p[24] << 16)
35282 - | (mask_p[23] << 14) | (mask_p[22] << 12)
35283 - | (mask_p[21] << 10) | (mask_p[20] << 8)
35284 - | (mask_p[19] << 6) | (mask_p[18] << 4)
35285 - | (mask_p[17] << 2) | (mask_p[16] << 0);
35286 - REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
35287 - REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
35288 -
35289 - tmp_mask = (mask_p[45] << 28)
35290 - | (mask_p[44] << 26) | (mask_p[43] << 24)
35291 - | (mask_p[42] << 22) | (mask_p[41] << 20)
35292 - | (mask_p[40] << 18) | (mask_p[39] << 16)
35293 - | (mask_p[38] << 14) | (mask_p[37] << 12)
35294 - | (mask_p[36] << 10) | (mask_p[35] << 8)
35295 - | (mask_p[34] << 6) | (mask_p[33] << 4)
35296 - | (mask_p[32] << 2) | (mask_p[31] << 0);
35297 - REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
35298 - REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
35299 -
35300 - tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
35301 - | (mask_p[59] << 26) | (mask_p[58] << 24)
35302 - | (mask_p[57] << 22) | (mask_p[56] << 20)
35303 - | (mask_p[55] << 18) | (mask_p[54] << 16)
35304 - | (mask_p[53] << 14) | (mask_p[52] << 12)
35305 - | (mask_p[51] << 10) | (mask_p[50] << 8)
35306 - | (mask_p[49] << 6) | (mask_p[48] << 4)
35307 - | (mask_p[47] << 2) | (mask_p[46] << 0);
35308 - REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
35309 - REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
35310 -}
35311 -
35312 -/* All code below is for non single-chip solutions */
35313 -
35314 -/**
35315 - * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
35316 - * @rfbuf:
35317 - * @reg32:
35318 - * @numBits:
35319 - * @firstBit:
35320 - * @column:
35321 - *
35322 - * Performs analog "swizzling" of parameters into their location.
35323 - * Used on external AR2133/AR5133 radios.
35324 - */
35325 -static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
35326 - u32 numBits, u32 firstBit,
35327 - u32 column)
35328 -{
35329 - u32 tmp32, mask, arrayEntry, lastBit;
35330 - int32_t bitPosition, bitsLeft;
35331 -
35332 - tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
35333 - arrayEntry = (firstBit - 1) / 8;
35334 - bitPosition = (firstBit - 1) % 8;
35335 - bitsLeft = numBits;
35336 - while (bitsLeft > 0) {
35337 - lastBit = (bitPosition + bitsLeft > 8) ?
35338 - 8 : bitPosition + bitsLeft;
35339 - mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
35340 - (column * 8);
35341 - rfBuf[arrayEntry] &= ~mask;
35342 - rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
35343 - (column * 8)) & mask;
35344 - bitsLeft -= 8 - bitPosition;
35345 - tmp32 = tmp32 >> (8 - bitPosition);
35346 - bitPosition = 0;
35347 - arrayEntry++;
35348 - }
35349 -}
35350 -
35351 -/*
35352 - * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
35353 - * rf_pwd_icsyndiv.
35354 - *
35355 - * Theoretical Rules:
35356 - * if 2 GHz band
35357 - * if forceBiasAuto
35358 - * if synth_freq < 2412
35359 - * bias = 0
35360 - * else if 2412 <= synth_freq <= 2422
35361 - * bias = 1
35362 - * else // synth_freq > 2422
35363 - * bias = 2
35364 - * else if forceBias > 0
35365 - * bias = forceBias & 7
35366 - * else
35367 - * no change, use value from ini file
35368 - * else
35369 - * no change, invalid band
35370 - *
35371 - * 1st Mod:
35372 - * 2422 also uses value of 2
35373 - * <approved>
35374 - *
35375 - * 2nd Mod:
35376 - * Less than 2412 uses value of 0, 2412 and above uses value of 2
35377 - */
35378 -static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
35379 -{
35380 - struct ath_common *common = ath9k_hw_common(ah);
35381 - u32 tmp_reg;
35382 - int reg_writes = 0;
35383 - u32 new_bias = 0;
35384 -
35385 - if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
35386 - return;
35387 - }
35388 -
35389 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
35390 -
35391 - if (synth_freq < 2412)
35392 - new_bias = 0;
35393 - else if (synth_freq < 2422)
35394 - new_bias = 1;
35395 - else
35396 - new_bias = 2;
35397 -
35398 - /* pre-reverse this field */
35399 - tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
35400 -
35401 - ath_print(common, ATH_DBG_CONFIG,
35402 - "Force rf_pwd_icsyndiv to %1d on %4d\n",
35403 - new_bias, synth_freq);
35404 -
35405 - /* swizzle rf_pwd_icsyndiv */
35406 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
35407 -
35408 - /* write Bank 6 with new params */
35409 - REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
35410 -}
35411 -
35412 -/**
35413 - * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
35414 - * @ah: atheros hardware stucture
35415 - * @chan:
35416 - *
35417 - * For the external AR2133/AR5133 radios, takes the MHz channel value and set
35418 - * the channel value. Assumes writes enabled to analog bus and bank6 register
35419 - * cache in ah->analogBank6Data.
35420 - */
35421 -int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
35422 -{
35423 - struct ath_common *common = ath9k_hw_common(ah);
35424 - u32 channelSel = 0;
35425 - u32 bModeSynth = 0;
35426 - u32 aModeRefSel = 0;
35427 - u32 reg32 = 0;
35428 - u16 freq;
35429 - struct chan_centers centers;
35430 -
35431 - ath9k_hw_get_channel_centers(ah, chan, &centers);
35432 - freq = centers.synth_center;
35433 -
35434 - if (freq < 4800) {
35435 - u32 txctl;
35436 -
35437 - if (((freq - 2192) % 5) == 0) {
35438 - channelSel = ((freq - 672) * 2 - 3040) / 10;
35439 - bModeSynth = 0;
35440 - } else if (((freq - 2224) % 5) == 0) {
35441 - channelSel = ((freq - 704) * 2 - 3040) / 10;
35442 - bModeSynth = 1;
35443 - } else {
35444 - ath_print(common, ATH_DBG_FATAL,
35445 - "Invalid channel %u MHz\n", freq);
35446 - return -EINVAL;
35447 - }
35448 -
35449 - channelSel = (channelSel << 2) & 0xff;
35450 - channelSel = ath9k_hw_reverse_bits(channelSel, 8);
35451 -
35452 - txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
35453 - if (freq == 2484) {
35454 -
35455 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
35456 - txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
35457 - } else {
35458 - REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
35459 - txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
35460 - }
35461 -
35462 - } else if ((freq % 20) == 0 && freq >= 5120) {
35463 - channelSel =
35464 - ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
35465 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
35466 - } else if ((freq % 10) == 0) {
35467 - channelSel =
35468 - ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
35469 - if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
35470 - aModeRefSel = ath9k_hw_reverse_bits(2, 2);
35471 - else
35472 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
35473 - } else if ((freq % 5) == 0) {
35474 - channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
35475 - aModeRefSel = ath9k_hw_reverse_bits(1, 2);
35476 - } else {
35477 - ath_print(common, ATH_DBG_FATAL,
35478 - "Invalid channel %u MHz\n", freq);
35479 - return -EINVAL;
35480 - }
35481 -
35482 - ath9k_hw_force_bias(ah, freq);
35483 -
35484 - reg32 =
35485 - (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
35486 - (1 << 5) | 0x1;
35487 -
35488 - REG_WRITE(ah, AR_PHY(0x37), reg32);
35489 -
35490 - ah->curchan = chan;
35491 - ah->curchan_rad_index = -1;
35492 -
35493 - return 0;
35494 -}
35495 -
35496 -/**
35497 - * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
35498 - * @ah: atheros hardware structure
35499 - * @chan:
35500 - *
35501 - * For non single-chip solutions. Converts to baseband spur frequency given the
35502 - * input channel frequency and compute register settings below.
35503 - */
35504 -void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
35505 -{
35506 - int bb_spur = AR_NO_SPUR;
35507 - int bin, cur_bin;
35508 - int spur_freq_sd;
35509 - int spur_delta_phase;
35510 - int denominator;
35511 - int upper, lower, cur_vit_mask;
35512 - int tmp, new;
35513 - int i;
35514 - int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
35515 - AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
35516 - };
35517 - int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
35518 - AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
35519 - };
35520 - int inc[4] = { 0, 100, 0, 0 };
35521 -
35522 - int8_t mask_m[123];
35523 - int8_t mask_p[123];
35524 - int8_t mask_amt;
35525 - int tmp_mask;
35526 - int cur_bb_spur;
35527 - bool is2GHz = IS_CHAN_2GHZ(chan);
35528 -
35529 - memset(&mask_m, 0, sizeof(int8_t) * 123);
35530 - memset(&mask_p, 0, sizeof(int8_t) * 123);
35531 -
35532 - for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
35533 - cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
35534 - if (AR_NO_SPUR == cur_bb_spur)
35535 - break;
35536 - cur_bb_spur = cur_bb_spur - (chan->channel * 10);
35537 - if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
35538 - bb_spur = cur_bb_spur;
35539 - break;
35540 - }
35541 - }
35542 -
35543 - if (AR_NO_SPUR == bb_spur)
35544 - return;
35545 -
35546 - bin = bb_spur * 32;
35547 -
35548 - tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
35549 - new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
35550 - AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
35551 - AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
35552 - AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
35553 -
35554 - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
35555 -
35556 - new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
35557 - AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
35558 - AR_PHY_SPUR_REG_MASK_RATE_SELECT |
35559 - AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
35560 - SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
35561 - REG_WRITE(ah, AR_PHY_SPUR_REG, new);
35562 -
35563 - spur_delta_phase = ((bb_spur * 524288) / 100) &
35564 - AR_PHY_TIMING11_SPUR_DELTA_PHASE;
35565 -
35566 - denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
35567 - spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
35568 -
35569 - new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
35570 - SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
35571 - SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
35572 - REG_WRITE(ah, AR_PHY_TIMING11, new);
35573 -
35574 - cur_bin = -6000;
35575 - upper = bin + 100;
35576 - lower = bin - 100;
35577 -
35578 - for (i = 0; i < 4; i++) {
35579 - int pilot_mask = 0;
35580 - int chan_mask = 0;
35581 - int bp = 0;
35582 - for (bp = 0; bp < 30; bp++) {
35583 - if ((cur_bin > lower) && (cur_bin < upper)) {
35584 - pilot_mask = pilot_mask | 0x1 << bp;
35585 - chan_mask = chan_mask | 0x1 << bp;
35586 - }
35587 - cur_bin += 100;
35588 - }
35589 - cur_bin += inc[i];
35590 - REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
35591 - REG_WRITE(ah, chan_mask_reg[i], chan_mask);
35592 - }
35593 -
35594 - cur_vit_mask = 6100;
35595 - upper = bin + 120;
35596 - lower = bin - 120;
35597 -
35598 - for (i = 0; i < 123; i++) {
35599 - if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
35600 -
35601 - /* workaround for gcc bug #37014 */
35602 - volatile int tmp_v = abs(cur_vit_mask - bin);
35603 -
35604 - if (tmp_v < 75)
35605 - mask_amt = 1;
35606 - else
35607 - mask_amt = 0;
35608 - if (cur_vit_mask < 0)
35609 - mask_m[abs(cur_vit_mask / 100)] = mask_amt;
35610 - else
35611 - mask_p[cur_vit_mask / 100] = mask_amt;
35612 - }
35613 - cur_vit_mask -= 100;
35614 - }
35615 -
35616 - tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
35617 - | (mask_m[48] << 26) | (mask_m[49] << 24)
35618 - | (mask_m[50] << 22) | (mask_m[51] << 20)
35619 - | (mask_m[52] << 18) | (mask_m[53] << 16)
35620 - | (mask_m[54] << 14) | (mask_m[55] << 12)
35621 - | (mask_m[56] << 10) | (mask_m[57] << 8)
35622 - | (mask_m[58] << 6) | (mask_m[59] << 4)
35623 - | (mask_m[60] << 2) | (mask_m[61] << 0);
35624 - REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
35625 - REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
35626 -
35627 - tmp_mask = (mask_m[31] << 28)
35628 - | (mask_m[32] << 26) | (mask_m[33] << 24)
35629 - | (mask_m[34] << 22) | (mask_m[35] << 20)
35630 - | (mask_m[36] << 18) | (mask_m[37] << 16)
35631 - | (mask_m[48] << 14) | (mask_m[39] << 12)
35632 - | (mask_m[40] << 10) | (mask_m[41] << 8)
35633 - | (mask_m[42] << 6) | (mask_m[43] << 4)
35634 - | (mask_m[44] << 2) | (mask_m[45] << 0);
35635 - REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
35636 - REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
35637 -
35638 - tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
35639 - | (mask_m[18] << 26) | (mask_m[18] << 24)
35640 - | (mask_m[20] << 22) | (mask_m[20] << 20)
35641 - | (mask_m[22] << 18) | (mask_m[22] << 16)
35642 - | (mask_m[24] << 14) | (mask_m[24] << 12)
35643 - | (mask_m[25] << 10) | (mask_m[26] << 8)
35644 - | (mask_m[27] << 6) | (mask_m[28] << 4)
35645 - | (mask_m[29] << 2) | (mask_m[30] << 0);
35646 - REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
35647 - REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
35648 -
35649 - tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
35650 - | (mask_m[2] << 26) | (mask_m[3] << 24)
35651 - | (mask_m[4] << 22) | (mask_m[5] << 20)
35652 - | (mask_m[6] << 18) | (mask_m[7] << 16)
35653 - | (mask_m[8] << 14) | (mask_m[9] << 12)
35654 - | (mask_m[10] << 10) | (mask_m[11] << 8)
35655 - | (mask_m[12] << 6) | (mask_m[13] << 4)
35656 - | (mask_m[14] << 2) | (mask_m[15] << 0);
35657 - REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
35658 - REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
35659 -
35660 - tmp_mask = (mask_p[15] << 28)
35661 - | (mask_p[14] << 26) | (mask_p[13] << 24)
35662 - | (mask_p[12] << 22) | (mask_p[11] << 20)
35663 - | (mask_p[10] << 18) | (mask_p[9] << 16)
35664 - | (mask_p[8] << 14) | (mask_p[7] << 12)
35665 - | (mask_p[6] << 10) | (mask_p[5] << 8)
35666 - | (mask_p[4] << 6) | (mask_p[3] << 4)
35667 - | (mask_p[2] << 2) | (mask_p[1] << 0);
35668 - REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
35669 - REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
35670 -
35671 - tmp_mask = (mask_p[30] << 28)
35672 - | (mask_p[29] << 26) | (mask_p[28] << 24)
35673 - | (mask_p[27] << 22) | (mask_p[26] << 20)
35674 - | (mask_p[25] << 18) | (mask_p[24] << 16)
35675 - | (mask_p[23] << 14) | (mask_p[22] << 12)
35676 - | (mask_p[21] << 10) | (mask_p[20] << 8)
35677 - | (mask_p[19] << 6) | (mask_p[18] << 4)
35678 - | (mask_p[17] << 2) | (mask_p[16] << 0);
35679 - REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
35680 - REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
35681 -
35682 - tmp_mask = (mask_p[45] << 28)
35683 - | (mask_p[44] << 26) | (mask_p[43] << 24)
35684 - | (mask_p[42] << 22) | (mask_p[41] << 20)
35685 - | (mask_p[40] << 18) | (mask_p[39] << 16)
35686 - | (mask_p[38] << 14) | (mask_p[37] << 12)
35687 - | (mask_p[36] << 10) | (mask_p[35] << 8)
35688 - | (mask_p[34] << 6) | (mask_p[33] << 4)
35689 - | (mask_p[32] << 2) | (mask_p[31] << 0);
35690 - REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
35691 - REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
35692 -
35693 - tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
35694 - | (mask_p[59] << 26) | (mask_p[58] << 24)
35695 - | (mask_p[57] << 22) | (mask_p[56] << 20)
35696 - | (mask_p[55] << 18) | (mask_p[54] << 16)
35697 - | (mask_p[53] << 14) | (mask_p[52] << 12)
35698 - | (mask_p[51] << 10) | (mask_p[50] << 8)
35699 - | (mask_p[49] << 6) | (mask_p[48] << 4)
35700 - | (mask_p[47] << 2) | (mask_p[46] << 0);
35701 - REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
35702 - REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
35703 -}
35704 -
35705 -/**
35706 - * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
35707 - * @ah: atheros hardware structure
35708 - *
35709 - * Only required for older devices with external AR2133/AR5133 radios.
35710 - */
35711 -int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
35712 -{
35713 -#define ATH_ALLOC_BANK(bank, size) do { \
35714 - bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
35715 - if (!bank) { \
35716 - ath_print(common, ATH_DBG_FATAL, \
35717 - "Cannot allocate RF banks\n"); \
35718 - return -ENOMEM; \
35719 - } \
35720 - } while (0);
35721 -
35722 - struct ath_common *common = ath9k_hw_common(ah);
35723 -
35724 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
35725 -
35726 - ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
35727 - ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
35728 - ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
35729 - ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
35730 - ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
35731 - ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
35732 - ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
35733 - ATH_ALLOC_BANK(ah->addac5416_21,
35734 - ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
35735 - ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
35736 -
35737 - return 0;
35738 -#undef ATH_ALLOC_BANK
35739 -}
35740 -
35741 -
35742 -/**
35743 - * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
35744 - * @ah: atheros hardware struture
35745 - * For the external AR2133/AR5133 radios banks.
35746 - */
35747 -void
35748 -ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
35749 -{
35750 -#define ATH_FREE_BANK(bank) do { \
35751 - kfree(bank); \
35752 - bank = NULL; \
35753 - } while (0);
35754 -
35755 - BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
35756 -
35757 - ATH_FREE_BANK(ah->analogBank0Data);
35758 - ATH_FREE_BANK(ah->analogBank1Data);
35759 - ATH_FREE_BANK(ah->analogBank2Data);
35760 - ATH_FREE_BANK(ah->analogBank3Data);
35761 - ATH_FREE_BANK(ah->analogBank6Data);
35762 - ATH_FREE_BANK(ah->analogBank6TPCData);
35763 - ATH_FREE_BANK(ah->analogBank7Data);
35764 - ATH_FREE_BANK(ah->addac5416_21);
35765 - ATH_FREE_BANK(ah->bank6Temp);
35766 -
35767 -#undef ATH_FREE_BANK
35768 -}
35769 -
35770 -/* *
35771 - * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
35772 - * @ah: atheros hardware structure
35773 - * @chan:
35774 - * @modesIndex:
35775 - *
35776 - * Used for the external AR2133/AR5133 radios.
35777 - *
35778 - * Reads the EEPROM header info from the device structure and programs
35779 - * all rf registers. This routine requires access to the analog
35780 - * rf device. This is not required for single-chip devices.
35781 - */
35782 -bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
35783 - u16 modesIndex)
35784 -{
35785 - u32 eepMinorRev;
35786 - u32 ob5GHz = 0, db5GHz = 0;
35787 - u32 ob2GHz = 0, db2GHz = 0;
35788 - int regWrites = 0;
35789 -
35790 - /*
35791 - * Software does not need to program bank data
35792 - * for single chip devices, that is AR9280 or anything
35793 - * after that.
35794 - */
35795 - if (AR_SREV_9280_10_OR_LATER(ah))
35796 - return true;
35797 -
35798 - /* Setup rf parameters */
35799 - eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
35800 -
35801 - /* Setup Bank 0 Write */
35802 - RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
35803 -
35804 - /* Setup Bank 1 Write */
35805 - RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
35806 -
35807 - /* Setup Bank 2 Write */
35808 - RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
35809 -
35810 - /* Setup Bank 6 Write */
35811 - RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
35812 - modesIndex);
35813 - {
35814 - int i;
35815 - for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
35816 - ah->analogBank6Data[i] =
35817 - INI_RA(&ah->iniBank6TPC, i, modesIndex);
35818 - }
35819 - }
35820 -
35821 - /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
35822 - if (eepMinorRev >= 2) {
35823 - if (IS_CHAN_2GHZ(chan)) {
35824 - ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
35825 - db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
35826 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
35827 - ob2GHz, 3, 197, 0);
35828 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
35829 - db2GHz, 3, 194, 0);
35830 - } else {
35831 - ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
35832 - db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
35833 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
35834 - ob5GHz, 3, 203, 0);
35835 - ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
35836 - db5GHz, 3, 200, 0);
35837 - }
35838 - }
35839 -
35840 - /* Setup Bank 7 Setup */
35841 - RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
35842 -
35843 - /* Write Analog registers */
35844 - REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
35845 - regWrites);
35846 - REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
35847 - regWrites);
35848 - REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
35849 - regWrites);
35850 - REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
35851 - regWrites);
35852 - REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
35853 - regWrites);
35854 - REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
35855 - regWrites);
35856 -
35857 - return true;
35858 -}
35859 --- a/drivers/net/wireless/ath/ath9k/phy.h
35860 +++ b/drivers/net/wireless/ath/ath9k/phy.h
35861 @@ -17,504 +17,15 @@
35862 #ifndef PHY_H
35863 #define PHY_H
35864
35865 -/* Common between single chip and non single-chip solutions */
35866 -void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
35867 -
35868 -/* Single chip radio settings */
35869 -int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
35870 -void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35871 -
35872 -/* Routines below are for non single-chip solutions */
35873 -int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
35874 -void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35875 -
35876 -int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
35877 -void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
35878 -
35879 -bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
35880 - struct ath9k_channel *chan,
35881 - u16 modesIndex);
35882 +#define CHANSEL_DIV 15
35883 +#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
35884 +#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
35885
35886 #define AR_PHY_BASE 0x9800
35887 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
35888
35889 -#define AR_PHY_TEST 0x9800
35890 -#define PHY_AGC_CLR 0x10000000
35891 -#define RFSILENT_BB 0x00002000
35892 -
35893 -#define AR_PHY_TURBO 0x9804
35894 -#define AR_PHY_FC_TURBO_MODE 0x00000001
35895 -#define AR_PHY_FC_TURBO_SHORT 0x00000002
35896 -#define AR_PHY_FC_DYN2040_EN 0x00000004
35897 -#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
35898 -#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
35899 -/* For 25 MHz channel spacing -- not used but supported by hw */
35900 -#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
35901 -#define AR_PHY_FC_HT_EN 0x00000040
35902 -#define AR_PHY_FC_SHORT_GI_40 0x00000080
35903 -#define AR_PHY_FC_WALSH 0x00000100
35904 -#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
35905 -#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
35906 -
35907 -#define AR_PHY_TEST2 0x9808
35908 -
35909 -#define AR_PHY_TIMING2 0x9810
35910 -#define AR_PHY_TIMING3 0x9814
35911 -#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
35912 -#define AR_PHY_TIMING3_DSC_MAN_S 17
35913 -#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
35914 -#define AR_PHY_TIMING3_DSC_EXP_S 13
35915 -
35916 -#define AR_PHY_CHIP_ID 0x9818
35917 -#define AR_PHY_CHIP_ID_REV_0 0x80
35918 -#define AR_PHY_CHIP_ID_REV_1 0x81
35919 -#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
35920 -
35921 -#define AR_PHY_ACTIVE 0x981C
35922 -#define AR_PHY_ACTIVE_EN 0x00000001
35923 -#define AR_PHY_ACTIVE_DIS 0x00000000
35924 -
35925 -#define AR_PHY_RF_CTL2 0x9824
35926 -#define AR_PHY_TX_END_DATA_START 0x000000FF
35927 -#define AR_PHY_TX_END_DATA_START_S 0
35928 -#define AR_PHY_TX_END_PA_ON 0x0000FF00
35929 -#define AR_PHY_TX_END_PA_ON_S 8
35930 -
35931 -#define AR_PHY_RF_CTL3 0x9828
35932 -#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
35933 -#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
35934 -
35935 -#define AR_PHY_ADC_CTL 0x982C
35936 -#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
35937 -#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
35938 -#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
35939 -#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
35940 -#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
35941 -#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
35942 -#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
35943 -
35944 -#define AR_PHY_ADC_SERIAL_CTL 0x9830
35945 -#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
35946 -#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
35947 -
35948 -#define AR_PHY_RF_CTL4 0x9834
35949 -#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
35950 -#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
35951 -#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
35952 -#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
35953 -#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
35954 -#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
35955 -#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
35956 -#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
35957 -
35958 -#define AR_PHY_TSTDAC_CONST 0x983c
35959 -
35960 -#define AR_PHY_SETTLING 0x9844
35961 -#define AR_PHY_SETTLING_SWITCH 0x00003F80
35962 -#define AR_PHY_SETTLING_SWITCH_S 7
35963 -
35964 -#define AR_PHY_RXGAIN 0x9848
35965 -#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
35966 -#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
35967 -#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
35968 -#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
35969 -#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
35970 -#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
35971 -#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
35972 -#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
35973 -
35974 -#define AR_PHY_DESIRED_SZ 0x9850
35975 -#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
35976 -#define AR_PHY_DESIRED_SZ_ADC_S 0
35977 -#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
35978 -#define AR_PHY_DESIRED_SZ_PGA_S 8
35979 -#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
35980 -#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
35981 -
35982 -#define AR_PHY_FIND_SIG 0x9858
35983 -#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
35984 -#define AR_PHY_FIND_SIG_FIRSTEP_S 12
35985 -#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
35986 -#define AR_PHY_FIND_SIG_FIRPWR_S 18
35987 -
35988 -#define AR_PHY_AGC_CTL1 0x985C
35989 -#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
35990 -#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
35991 -#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
35992 -#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
35993 -
35994 -#define AR_PHY_AGC_CONTROL 0x9860
35995 -#define AR_PHY_AGC_CONTROL_CAL 0x00000001
35996 -#define AR_PHY_AGC_CONTROL_NF 0x00000002
35997 -#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
35998 -#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
35999 -#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
36000 -
36001 -#define AR_PHY_CCA 0x9864
36002 -#define AR_PHY_MINCCA_PWR 0x0FF80000
36003 -#define AR_PHY_MINCCA_PWR_S 19
36004 -#define AR_PHY_CCA_THRESH62 0x0007F000
36005 -#define AR_PHY_CCA_THRESH62_S 12
36006 -#define AR9280_PHY_MINCCA_PWR 0x1FF00000
36007 -#define AR9280_PHY_MINCCA_PWR_S 20
36008 -#define AR9280_PHY_CCA_THRESH62 0x000FF000
36009 -#define AR9280_PHY_CCA_THRESH62_S 12
36010 -
36011 -#define AR_PHY_SFCORR_LOW 0x986C
36012 -#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
36013 -#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
36014 -#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
36015 -#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
36016 -#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
36017 -#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
36018 -#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
36019 -
36020 -#define AR_PHY_SFCORR 0x9868
36021 -#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
36022 -#define AR_PHY_SFCORR_M2COUNT_THR_S 0
36023 -#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
36024 -#define AR_PHY_SFCORR_M1_THRESH_S 17
36025 -#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
36026 -#define AR_PHY_SFCORR_M2_THRESH_S 24
36027 -
36028 -#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
36029 -#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
36030 -#define AR_PHY_SYNTH_CONTROL 0x9874
36031 -#define AR_PHY_SLEEP_SCAL 0x9878
36032 -
36033 -#define AR_PHY_PLL_CTL 0x987c
36034 -#define AR_PHY_PLL_CTL_40 0xaa
36035 -#define AR_PHY_PLL_CTL_40_5413 0x04
36036 -#define AR_PHY_PLL_CTL_44 0xab
36037 -#define AR_PHY_PLL_CTL_44_2133 0xeb
36038 -#define AR_PHY_PLL_CTL_40_2133 0xea
36039 -
36040 -#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
36041 -#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
36042 -#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
36043 -#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
36044 -#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
36045 -#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
36046 -#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
36047 -#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
36048 -#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
36049 -#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
36050 -#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
36051 -#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
36052 -#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
36053 -#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
36054 -
36055 -#define AR_PHY_RX_DELAY 0x9914
36056 -#define AR_PHY_SEARCH_START_DELAY 0x9918
36057 -#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
36058 -
36059 -#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
36060 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
36061 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
36062 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
36063 -#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
36064 -#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
36065 -#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
36066 -#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
36067 -#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
36068 -
36069 -#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
36070 -#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
36071 -#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
36072 -#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
36073 -
36074 -#define AR_PHY_TIMING5 0x9924
36075 -#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
36076 -#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
36077 -
36078 -#define AR_PHY_POWER_TX_RATE1 0x9934
36079 -#define AR_PHY_POWER_TX_RATE2 0x9938
36080 -#define AR_PHY_POWER_TX_RATE_MAX 0x993c
36081 -#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
36082 -
36083 -#define AR_PHY_FRAME_CTL 0x9944
36084 -#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
36085 -#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
36086 -
36087 -#define AR_PHY_TXPWRADJ 0x994C
36088 -#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
36089 -#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
36090 -#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
36091 -#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
36092 -
36093 -#define AR_PHY_RADAR_EXT 0x9940
36094 -#define AR_PHY_RADAR_EXT_ENA 0x00004000
36095 -
36096 -#define AR_PHY_RADAR_0 0x9954
36097 -#define AR_PHY_RADAR_0_ENA 0x00000001
36098 -#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
36099 -#define AR_PHY_RADAR_0_INBAND 0x0000003e
36100 -#define AR_PHY_RADAR_0_INBAND_S 1
36101 -#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
36102 -#define AR_PHY_RADAR_0_PRSSI_S 6
36103 -#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
36104 -#define AR_PHY_RADAR_0_HEIGHT_S 12
36105 -#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
36106 -#define AR_PHY_RADAR_0_RRSSI_S 18
36107 -#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
36108 -#define AR_PHY_RADAR_0_FIRPWR_S 24
36109 -
36110 -#define AR_PHY_RADAR_1 0x9958
36111 -#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
36112 -#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
36113 -#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
36114 -#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
36115 -#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
36116 -#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
36117 -#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
36118 -#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
36119 -#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
36120 -#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
36121 -#define AR_PHY_RADAR_1_MAXLEN_S 0
36122 -
36123 -#define AR_PHY_SWITCH_CHAIN_0 0x9960
36124 -#define AR_PHY_SWITCH_COM 0x9964
36125 -
36126 -#define AR_PHY_SIGMA_DELTA 0x996C
36127 -#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
36128 -#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
36129 -#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
36130 -#define AR_PHY_SIGMA_DELTA_FILT2_S 3
36131 -#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
36132 -#define AR_PHY_SIGMA_DELTA_FILT1_S 8
36133 -#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
36134 -#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
36135 -
36136 -#define AR_PHY_RESTART 0x9970
36137 -#define AR_PHY_RESTART_DIV_GC 0x001C0000
36138 -#define AR_PHY_RESTART_DIV_GC_S 18
36139 -
36140 -#define AR_PHY_RFBUS_REQ 0x997C
36141 -#define AR_PHY_RFBUS_REQ_EN 0x00000001
36142 -
36143 -#define AR_PHY_TIMING7 0x9980
36144 -#define AR_PHY_TIMING8 0x9984
36145 -#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
36146 -#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
36147 -
36148 -#define AR_PHY_BIN_MASK2_1 0x9988
36149 -#define AR_PHY_BIN_MASK2_2 0x998c
36150 -#define AR_PHY_BIN_MASK2_3 0x9990
36151 -#define AR_PHY_BIN_MASK2_4 0x9994
36152 -
36153 -#define AR_PHY_BIN_MASK_1 0x9900
36154 -#define AR_PHY_BIN_MASK_2 0x9904
36155 -#define AR_PHY_BIN_MASK_3 0x9908
36156 -
36157 -#define AR_PHY_MASK_CTL 0x990c
36158 -
36159 -#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
36160 -#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
36161 -
36162 -#define AR_PHY_TIMING9 0x9998
36163 -#define AR_PHY_TIMING10 0x999c
36164 -#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
36165 -#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
36166 -
36167 -#define AR_PHY_TIMING11 0x99a0
36168 -#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
36169 -#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
36170 -#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
36171 -#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
36172 -#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
36173 -#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
36174 -
36175 -#define AR_PHY_RX_CHAINMASK 0x99a4
36176 -#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
36177 -#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
36178 -#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
36179 -
36180 -#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
36181 -#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
36182 -#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
36183 -#define AR_PHY_9285_ANT_DIV_CTL_S 24
36184 -#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
36185 -#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
36186 -#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
36187 -#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
36188 -#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
36189 -#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
36190 -#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
36191 -#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
36192 -#define AR_PHY_9285_ANT_DIV_LNA1 2
36193 -#define AR_PHY_9285_ANT_DIV_LNA2 1
36194 -#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
36195 -#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
36196 -#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
36197 -#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
36198 -
36199 -#define AR_PHY_EXT_CCA0 0x99b8
36200 -#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
36201 -#define AR_PHY_EXT_CCA0_THRESH62_S 0
36202 -
36203 -#define AR_PHY_EXT_CCA 0x99bc
36204 -#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
36205 -#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
36206 -#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
36207 -#define AR_PHY_EXT_CCA_THRESH62_S 16
36208 -#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
36209 -#define AR_PHY_EXT_MINCCA_PWR_S 23
36210 -#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
36211 -#define AR9280_PHY_EXT_MINCCA_PWR_S 16
36212 -
36213 -#define AR_PHY_SFCORR_EXT 0x99c0
36214 -#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
36215 -#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
36216 -#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
36217 -#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
36218 -#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
36219 -#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
36220 -#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
36221 -#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
36222 -#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
36223 -
36224 -#define AR_PHY_HALFGI 0x99D0
36225 -#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
36226 -#define AR_PHY_HALFGI_DSC_MAN_S 4
36227 -#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
36228 -#define AR_PHY_HALFGI_DSC_EXP_S 0
36229 -
36230 -#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
36231 -#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
36232 -
36233 -#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
36234 -
36235 -#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
36236 -#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
36237 -
36238 -#define AR_PHY_M_SLEEP 0x99f0
36239 -#define AR_PHY_REFCLKDLY 0x99f4
36240 -#define AR_PHY_REFCLKPD 0x99f8
36241 -
36242 -#define AR_PHY_CALMODE 0x99f0
36243 -
36244 -#define AR_PHY_CALMODE_IQ 0x00000000
36245 -#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
36246 -#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
36247 -#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
36248 -
36249 -#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
36250 -#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
36251 -#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
36252 -#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
36253 -
36254 -#define AR_PHY_CURRENT_RSSI 0x9c1c
36255 -#define AR9280_PHY_CURRENT_RSSI 0x9c3c
36256 -
36257 -#define AR_PHY_RFBUS_GRANT 0x9C20
36258 -#define AR_PHY_RFBUS_GRANT_EN 0x00000001
36259 -
36260 -#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
36261 -#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
36262 -
36263 -#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
36264 -
36265 -#define AR_PHY_MODE 0xA200
36266 -#define AR_PHY_MODE_ASYNCFIFO 0x80
36267 -#define AR_PHY_MODE_AR2133 0x08
36268 -#define AR_PHY_MODE_AR5111 0x00
36269 -#define AR_PHY_MODE_AR5112 0x08
36270 -#define AR_PHY_MODE_DYNAMIC 0x04
36271 -#define AR_PHY_MODE_RF2GHZ 0x02
36272 -#define AR_PHY_MODE_RF5GHZ 0x00
36273 -#define AR_PHY_MODE_CCK 0x01
36274 -#define AR_PHY_MODE_OFDM 0x00
36275 -#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
36276 -
36277 -#define AR_PHY_CCK_TX_CTRL 0xA204
36278 -#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
36279 -#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
36280 -#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
36281 -
36282 -#define AR_PHY_CCK_DETECT 0xA208
36283 -#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
36284 -#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
36285 -/* [12:6] settling time for antenna switch */
36286 -#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
36287 -#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
36288 -#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
36289 -#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
36290 -
36291 -#define AR_PHY_GAIN_2GHZ 0xA20C
36292 -#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
36293 -#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
36294 -#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
36295 -#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
36296 -#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
36297 -#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
36298 -
36299 -#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
36300 -#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
36301 -#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
36302 -#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
36303 -#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
36304 -#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
36305 -#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
36306 -#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
36307 -
36308 -#define AR_PHY_CCK_RXCTRL4 0xA21C
36309 -#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
36310 -#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
36311 -
36312 -#define AR_PHY_DAG_CTRLCCK 0xA228
36313 -#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
36314 -#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
36315 -#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
36316 -
36317 -#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
36318 -#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
36319 -
36320 -#define AR_PHY_POWER_TX_RATE3 0xA234
36321 -#define AR_PHY_POWER_TX_RATE4 0xA238
36322 -
36323 -#define AR_PHY_SCRM_SEQ_XR 0xA23C
36324 -#define AR_PHY_HEADER_DETECT_XR 0xA240
36325 -#define AR_PHY_CHIRP_DETECTED_XR 0xA244
36326 -#define AR_PHY_BLUETOOTH 0xA254
36327 -
36328 -#define AR_PHY_TPCRG1 0xA258
36329 -#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
36330 -#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
36331 -
36332 -#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
36333 -#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
36334 -#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
36335 -#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
36336 -#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
36337 -#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
36338 -
36339 -#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
36340 -#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
36341 -
36342 -#define AR_PHY_TX_PWRCTRL4 0xa264
36343 -#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
36344 -#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
36345 -#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
36346 -#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
36347 -
36348 -#define AR_PHY_TX_PWRCTRL6_0 0xa270
36349 -#define AR_PHY_TX_PWRCTRL6_1 0xb270
36350 -#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
36351 -#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
36352 -
36353 -#define AR_PHY_TX_PWRCTRL7 0xa274
36354 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
36355 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
36356 -#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
36357 -#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
36358 -
36359 -#define AR_PHY_TX_PWRCTRL9 0xa27C
36360 -#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
36361 -#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
36362 -#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
36363 -#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
36364 -
36365 -#define AR_PHY_TX_GAIN_TBL1 0xa300
36366 #define AR_PHY_TX_GAIN_CLC 0x0000001E
36367 #define AR_PHY_TX_GAIN_CLC_S 1
36368 #define AR_PHY_TX_GAIN 0x0007F000
36369 @@ -526,91 +37,6 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
36370 #define AR_PHY_CLC_Q0 0x0000ffd0
36371 #define AR_PHY_CLC_Q0_S 5
36372
36373 -#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
36374 -#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
36375 -#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
36376 -#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
36377 -
36378 -#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
36379 -#define AR_PHY_MASK2_M_31_45 0xa3a4
36380 -#define AR_PHY_MASK2_M_16_30 0xa3a8
36381 -#define AR_PHY_MASK2_M_00_15 0xa3ac
36382 -#define AR_PHY_MASK2_P_15_01 0xa3b8
36383 -#define AR_PHY_MASK2_P_30_16 0xa3bc
36384 -#define AR_PHY_MASK2_P_45_31 0xa3c0
36385 -#define AR_PHY_MASK2_P_61_45 0xa3c4
36386 -#define AR_PHY_SPUR_REG 0x994c
36387 -
36388 -#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
36389 -#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
36390 -
36391 -#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
36392 -#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
36393 -#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
36394 -#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
36395 -#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
36396 -#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
36397 -
36398 -#define AR_PHY_PILOT_MASK_01_30 0xa3b0
36399 -#define AR_PHY_PILOT_MASK_31_60 0xa3b4
36400 -
36401 -#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
36402 -#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
36403 -
36404 -#define AR_PHY_ANALOG_SWAP 0xa268
36405 -#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
36406 -
36407 -#define AR_PHY_TPCRG5 0xA26C
36408 -#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
36409 -#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
36410 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
36411 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
36412 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
36413 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
36414 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
36415 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
36416 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
36417 -#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
36418 -
36419 -/* Carrier leak calibration control, do it after AGC calibration */
36420 -#define AR_PHY_CL_CAL_CTL 0xA358
36421 -#define AR_PHY_CL_CAL_ENABLE 0x00000002
36422 -#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
36423 -
36424 -#define AR_PHY_POWER_TX_RATE5 0xA38C
36425 -#define AR_PHY_POWER_TX_RATE6 0xA390
36426 -
36427 -#define AR_PHY_CAL_CHAINMASK 0xA39C
36428 -
36429 -#define AR_PHY_POWER_TX_SUB 0xA3C8
36430 -#define AR_PHY_POWER_TX_RATE7 0xA3CC
36431 -#define AR_PHY_POWER_TX_RATE8 0xA3D0
36432 -#define AR_PHY_POWER_TX_RATE9 0xA3D4
36433 -
36434 -#define AR_PHY_XPA_CFG 0xA3D8
36435 -#define AR_PHY_FORCE_XPA_CFG 0x000000001
36436 -#define AR_PHY_FORCE_XPA_CFG_S 0
36437 -
36438 -#define AR_PHY_CH1_CCA 0xa864
36439 -#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
36440 -#define AR_PHY_CH1_MINCCA_PWR_S 19
36441 -#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
36442 -#define AR9280_PHY_CH1_MINCCA_PWR_S 20
36443 -
36444 -#define AR_PHY_CH2_CCA 0xb864
36445 -#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
36446 -#define AR_PHY_CH2_MINCCA_PWR_S 19
36447 -
36448 -#define AR_PHY_CH1_EXT_CCA 0xa9bc
36449 -#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
36450 -#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
36451 -#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
36452 -#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
36453 -
36454 -#define AR_PHY_CH2_EXT_CCA 0xb9bc
36455 -#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
36456 -#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
36457 -
36458 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
36459 int r; \
36460 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
36461 @@ -625,6 +51,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
36462 #define ANTSWAP_AB 0x0001
36463 #define REDUCE_CHAIN_0 0x00000050
36464 #define REDUCE_CHAIN_1 0x00000051
36465 +#define AR_PHY_CHIP_ID 0x9818
36466
36467 #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
36468 int i; \
36469 @@ -632,4 +59,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw
36470 (_bank)[i] = INI_RA((_iniarray), i, _col);; \
36471 } while (0)
36472
36473 +#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
36474 +#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
36475 +
36476 #endif
36477 --- a/drivers/net/wireless/ath/ath9k/rc.c
36478 +++ b/drivers/net/wireless/ath/ath9k/rc.c
36479 @@ -689,6 +689,15 @@ static void ath_get_rate(void *priv, str
36480 rate_table = sc->cur_rate_table;
36481 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe);
36482
36483 + /*
36484 + * If we're in HT mode and both us and our peer supports LDPC.
36485 + * We don't need to check our own device's capabilities as our own
36486 + * ht capabilities would have already been intersected with our peer's.
36487 + */
36488 + if (conf_is_ht(&sc->hw->conf) &&
36489 + (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
36490 + tx_info->flags |= IEEE80211_TX_CTL_LDPC;
36491 +
36492 if (is_probe) {
36493 /* set one try for probe rates. For the
36494 * probes don't enable rts */
36495 --- a/drivers/net/wireless/ath/ath9k/recv.c
36496 +++ b/drivers/net/wireless/ath/ath9k/recv.c
36497 @@ -16,6 +16,8 @@
36498
36499 #include "ath9k.h"
36500
36501 +#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
36502 +
36503 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
36504 struct ieee80211_hdr *hdr)
36505 {
36506 @@ -115,56 +117,246 @@ static void ath_opmode_init(struct ath_s
36507 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
36508 }
36509
36510 -int ath_rx_init(struct ath_softc *sc, int nbufs)
36511 +static bool ath_rx_edma_buf_link(struct ath_softc *sc,
36512 + enum ath9k_rx_qtype qtype)
36513 {
36514 - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
36515 + struct ath_hw *ah = sc->sc_ah;
36516 + struct ath_rx_edma *rx_edma;
36517 struct sk_buff *skb;
36518 struct ath_buf *bf;
36519 - int error = 0;
36520
36521 - spin_lock_init(&sc->rx.rxflushlock);
36522 - sc->sc_flags &= ~SC_OP_RXFLUSH;
36523 - spin_lock_init(&sc->rx.rxbuflock);
36524 + rx_edma = &sc->rx.rx_edma[qtype];
36525 + if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
36526 + return false;
36527
36528 - common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
36529 - min(common->cachelsz, (u16)64));
36530 + bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
36531 + list_del_init(&bf->list);
36532 +
36533 + skb = bf->bf_mpdu;
36534
36535 - ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
36536 - common->cachelsz, common->rx_bufsize);
36537 + ATH_RXBUF_RESET(bf);
36538 + memset(skb->data, 0, ah->caps.rx_status_len);
36539 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
36540 + ah->caps.rx_status_len, DMA_TO_DEVICE);
36541 +
36542 + SKB_CB_ATHBUF(skb) = bf;
36543 + ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
36544 + skb_queue_tail(&rx_edma->rx_fifo, skb);
36545 +
36546 + return true;
36547 +}
36548
36549 - /* Initialize rx descriptors */
36550 +static void ath_rx_addbuffer_edma(struct ath_softc *sc,
36551 + enum ath9k_rx_qtype qtype, int size)
36552 +{
36553 + struct ath_rx_edma *rx_edma;
36554 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
36555 + u32 nbuf = 0;
36556
36557 - error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
36558 - "rx", nbufs, 1);
36559 - if (error != 0) {
36560 - ath_print(common, ATH_DBG_FATAL,
36561 - "failed to allocate rx descriptors: %d\n", error);
36562 - goto err;
36563 + rx_edma = &sc->rx.rx_edma[qtype];
36564 + if (list_empty(&sc->rx.rxbuf)) {
36565 + ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
36566 + return;
36567 }
36568
36569 + while (!list_empty(&sc->rx.rxbuf)) {
36570 + nbuf++;
36571 +
36572 + if (!ath_rx_edma_buf_link(sc, qtype))
36573 + break;
36574 +
36575 + if (nbuf >= size)
36576 + break;
36577 + }
36578 +}
36579 +
36580 +static void ath_rx_remove_buffer(struct ath_softc *sc,
36581 + enum ath9k_rx_qtype qtype)
36582 +{
36583 + struct ath_buf *bf;
36584 + struct ath_rx_edma *rx_edma;
36585 + struct sk_buff *skb;
36586 +
36587 + rx_edma = &sc->rx.rx_edma[qtype];
36588 +
36589 + while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
36590 + bf = SKB_CB_ATHBUF(skb);
36591 + BUG_ON(!bf);
36592 + list_add_tail(&bf->list, &sc->rx.rxbuf);
36593 + }
36594 +}
36595 +
36596 +static void ath_rx_edma_cleanup(struct ath_softc *sc)
36597 +{
36598 + struct ath_buf *bf;
36599 +
36600 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
36601 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
36602 +
36603 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
36604 + if (bf->bf_mpdu)
36605 + dev_kfree_skb_any(bf->bf_mpdu);
36606 + }
36607 +
36608 + INIT_LIST_HEAD(&sc->rx.rxbuf);
36609 +
36610 + kfree(sc->rx.rx_bufptr);
36611 + sc->rx.rx_bufptr = NULL;
36612 +}
36613 +
36614 +static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
36615 +{
36616 + skb_queue_head_init(&rx_edma->rx_fifo);
36617 + skb_queue_head_init(&rx_edma->rx_buffers);
36618 + rx_edma->rx_fifo_hwsize = size;
36619 +}
36620 +
36621 +static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
36622 +{
36623 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
36624 + struct ath_hw *ah = sc->sc_ah;
36625 + struct sk_buff *skb;
36626 + struct ath_buf *bf;
36627 + int error = 0, i;
36628 + u32 size;
36629 +
36630 +
36631 + common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
36632 + ah->caps.rx_status_len,
36633 + min(common->cachelsz, (u16)64));
36634 +
36635 + ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
36636 + ah->caps.rx_status_len);
36637 +
36638 + ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
36639 + ah->caps.rx_lp_qdepth);
36640 + ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
36641 + ah->caps.rx_hp_qdepth);
36642 +
36643 + size = sizeof(struct ath_buf) * nbufs;
36644 + bf = kzalloc(size, GFP_KERNEL);
36645 + if (!bf)
36646 + return -ENOMEM;
36647 +
36648 + INIT_LIST_HEAD(&sc->rx.rxbuf);
36649 + sc->rx.rx_bufptr = bf;
36650 +
36651 + for (i = 0; i < nbufs; i++, bf++) {
36652 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
36653 - if (skb == NULL) {
36654 + if (!skb) {
36655 error = -ENOMEM;
36656 - goto err;
36657 + goto rx_init_fail;
36658 }
36659
36660 + memset(skb->data, 0, common->rx_bufsize);
36661 bf->bf_mpdu = skb;
36662 +
36663 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
36664 common->rx_bufsize,
36665 - DMA_FROM_DEVICE);
36666 + DMA_BIDIRECTIONAL);
36667 if (unlikely(dma_mapping_error(sc->dev,
36668 - bf->bf_buf_addr))) {
36669 - dev_kfree_skb_any(skb);
36670 - bf->bf_mpdu = NULL;
36671 + bf->bf_buf_addr))) {
36672 + dev_kfree_skb_any(skb);
36673 + bf->bf_mpdu = NULL;
36674 + ath_print(common, ATH_DBG_FATAL,
36675 + "dma_mapping_error() on RX init\n");
36676 + error = -ENOMEM;
36677 + goto rx_init_fail;
36678 + }
36679 +
36680 + list_add_tail(&bf->list, &sc->rx.rxbuf);
36681 + }
36682 +
36683 + return 0;
36684 +
36685 +rx_init_fail:
36686 + ath_rx_edma_cleanup(sc);
36687 + return error;
36688 +}
36689 +
36690 +static void ath_edma_start_recv(struct ath_softc *sc)
36691 +{
36692 + spin_lock_bh(&sc->rx.rxbuflock);
36693 +
36694 + ath9k_hw_rxena(sc->sc_ah);
36695 +
36696 + ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
36697 + sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
36698 +
36699 + ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
36700 + sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
36701 +
36702 + spin_unlock_bh(&sc->rx.rxbuflock);
36703 +
36704 + ath_opmode_init(sc);
36705 +
36706 + ath9k_hw_startpcureceive(sc->sc_ah);
36707 +}
36708 +
36709 +static void ath_edma_stop_recv(struct ath_softc *sc)
36710 +{
36711 + spin_lock_bh(&sc->rx.rxbuflock);
36712 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
36713 + ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
36714 + spin_unlock_bh(&sc->rx.rxbuflock);
36715 +}
36716 +
36717 +int ath_rx_init(struct ath_softc *sc, int nbufs)
36718 +{
36719 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
36720 + struct sk_buff *skb;
36721 + struct ath_buf *bf;
36722 + int error = 0;
36723 +
36724 + spin_lock_init(&sc->rx.rxflushlock);
36725 + sc->sc_flags &= ~SC_OP_RXFLUSH;
36726 + spin_lock_init(&sc->rx.rxbuflock);
36727 +
36728 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
36729 + return ath_rx_edma_init(sc, nbufs);
36730 + } else {
36731 + common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
36732 + min(common->cachelsz, (u16)64));
36733 +
36734 + ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
36735 + common->cachelsz, common->rx_bufsize);
36736 +
36737 + /* Initialize rx descriptors */
36738 +
36739 + error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
36740 + "rx", nbufs, 1, 0);
36741 + if (error != 0) {
36742 ath_print(common, ATH_DBG_FATAL,
36743 - "dma_mapping_error() on RX init\n");
36744 - error = -ENOMEM;
36745 + "failed to allocate rx descriptors: %d\n",
36746 + error);
36747 goto err;
36748 }
36749 - bf->bf_dmacontext = bf->bf_buf_addr;
36750 +
36751 + list_for_each_entry(bf, &sc->rx.rxbuf, list) {
36752 + skb = ath_rxbuf_alloc(common, common->rx_bufsize,
36753 + GFP_KERNEL);
36754 + if (skb == NULL) {
36755 + error = -ENOMEM;
36756 + goto err;
36757 + }
36758 +
36759 + bf->bf_mpdu = skb;
36760 + bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
36761 + common->rx_bufsize,
36762 + DMA_FROM_DEVICE);
36763 + if (unlikely(dma_mapping_error(sc->dev,
36764 + bf->bf_buf_addr))) {
36765 + dev_kfree_skb_any(skb);
36766 + bf->bf_mpdu = NULL;
36767 + ath_print(common, ATH_DBG_FATAL,
36768 + "dma_mapping_error() on RX init\n");
36769 + error = -ENOMEM;
36770 + goto err;
36771 + }
36772 + bf->bf_dmacontext = bf->bf_buf_addr;
36773 + }
36774 + sc->rx.rxlink = NULL;
36775 }
36776 - sc->rx.rxlink = NULL;
36777
36778 err:
36779 if (error)
36780 @@ -180,17 +372,23 @@ void ath_rx_cleanup(struct ath_softc *sc
36781 struct sk_buff *skb;
36782 struct ath_buf *bf;
36783
36784 - list_for_each_entry(bf, &sc->rx.rxbuf, list) {
36785 - skb = bf->bf_mpdu;
36786 - if (skb) {
36787 - dma_unmap_single(sc->dev, bf->bf_buf_addr,
36788 - common->rx_bufsize, DMA_FROM_DEVICE);
36789 - dev_kfree_skb(skb);
36790 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
36791 + ath_rx_edma_cleanup(sc);
36792 + return;
36793 + } else {
36794 + list_for_each_entry(bf, &sc->rx.rxbuf, list) {
36795 + skb = bf->bf_mpdu;
36796 + if (skb) {
36797 + dma_unmap_single(sc->dev, bf->bf_buf_addr,
36798 + common->rx_bufsize,
36799 + DMA_FROM_DEVICE);
36800 + dev_kfree_skb(skb);
36801 + }
36802 }
36803 - }
36804
36805 - if (sc->rx.rxdma.dd_desc_len != 0)
36806 - ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
36807 + if (sc->rx.rxdma.dd_desc_len != 0)
36808 + ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
36809 + }
36810 }
36811
36812 /*
36813 @@ -273,6 +471,11 @@ int ath_startrecv(struct ath_softc *sc)
36814 struct ath_hw *ah = sc->sc_ah;
36815 struct ath_buf *bf, *tbf;
36816
36817 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
36818 + ath_edma_start_recv(sc);
36819 + return 0;
36820 + }
36821 +
36822 spin_lock_bh(&sc->rx.rxbuflock);
36823 if (list_empty(&sc->rx.rxbuf))
36824 goto start_recv;
36825 @@ -306,7 +509,12 @@ bool ath_stoprecv(struct ath_softc *sc)
36826 ath9k_hw_stoppcurecv(ah);
36827 ath9k_hw_setrxfilter(ah, 0);
36828 stopped = ath9k_hw_stopdmarecv(ah);
36829 - sc->rx.rxlink = NULL;
36830 +
36831 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
36832 + ath_edma_stop_recv(sc);
36833 + } else {
36834 + sc->rx.rxlink = NULL;
36835 + }
36836
36837 return stopped;
36838 }
36839 @@ -315,7 +523,9 @@ void ath_flushrecv(struct ath_softc *sc)
36840 {
36841 spin_lock_bh(&sc->rx.rxflushlock);
36842 sc->sc_flags |= SC_OP_RXFLUSH;
36843 - ath_rx_tasklet(sc, 1);
36844 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
36845 + ath_rx_tasklet(sc, 1, true);
36846 + ath_rx_tasklet(sc, 1, false);
36847 sc->sc_flags &= ~SC_OP_RXFLUSH;
36848 spin_unlock_bh(&sc->rx.rxflushlock);
36849 }
36850 @@ -469,14 +679,147 @@ static void ath_rx_send_to_mac80211(stru
36851 ieee80211_rx(hw, skb);
36852 }
36853
36854 -int ath_rx_tasklet(struct ath_softc *sc, int flush)
36855 +static bool ath_edma_get_buffers(struct ath_softc *sc,
36856 + enum ath9k_rx_qtype qtype)
36857 {
36858 -#define PA2DESC(_sc, _pa) \
36859 - ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
36860 - ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
36861 + struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
36862 + struct ath_hw *ah = sc->sc_ah;
36863 + struct ath_common *common = ath9k_hw_common(ah);
36864 + struct sk_buff *skb;
36865 + struct ath_buf *bf;
36866 + int ret;
36867 +
36868 + skb = skb_peek(&rx_edma->rx_fifo);
36869 + if (!skb)
36870 + return false;
36871 +
36872 + bf = SKB_CB_ATHBUF(skb);
36873 + BUG_ON(!bf);
36874 +
36875 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
36876 + common->rx_bufsize, DMA_FROM_DEVICE);
36877 +
36878 + ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
36879 + if (ret == -EINPROGRESS)
36880 + return false;
36881 +
36882 + __skb_unlink(skb, &rx_edma->rx_fifo);
36883 + if (ret == -EINVAL) {
36884 + /* corrupt descriptor, skip this one and the following one */
36885 + list_add_tail(&bf->list, &sc->rx.rxbuf);
36886 + ath_rx_edma_buf_link(sc, qtype);
36887 + skb = skb_peek(&rx_edma->rx_fifo);
36888 + if (!skb)
36889 + return true;
36890
36891 + bf = SKB_CB_ATHBUF(skb);
36892 + BUG_ON(!bf);
36893 +
36894 + __skb_unlink(skb, &rx_edma->rx_fifo);
36895 + list_add_tail(&bf->list, &sc->rx.rxbuf);
36896 + ath_rx_edma_buf_link(sc, qtype);
36897 + }
36898 + skb_queue_tail(&rx_edma->rx_buffers, skb);
36899 +
36900 + return true;
36901 +}
36902 +
36903 +static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
36904 + struct ath_rx_status *rs,
36905 + enum ath9k_rx_qtype qtype)
36906 +{
36907 + struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
36908 + struct sk_buff *skb;
36909 struct ath_buf *bf;
36910 +
36911 + while (ath_edma_get_buffers(sc, qtype));
36912 + skb = __skb_dequeue(&rx_edma->rx_buffers);
36913 + if (!skb)
36914 + return NULL;
36915 +
36916 + bf = SKB_CB_ATHBUF(skb);
36917 + ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
36918 + return bf;
36919 +}
36920 +
36921 +static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
36922 + struct ath_rx_status *rs)
36923 +{
36924 + struct ath_hw *ah = sc->sc_ah;
36925 + struct ath_common *common = ath9k_hw_common(ah);
36926 struct ath_desc *ds;
36927 + struct ath_buf *bf;
36928 + int ret;
36929 +
36930 + if (list_empty(&sc->rx.rxbuf)) {
36931 + sc->rx.rxlink = NULL;
36932 + return NULL;
36933 + }
36934 +
36935 + bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
36936 + ds = bf->bf_desc;
36937 +
36938 + /*
36939 + * Must provide the virtual address of the current
36940 + * descriptor, the physical address, and the virtual
36941 + * address of the next descriptor in the h/w chain.
36942 + * This allows the HAL to look ahead to see if the
36943 + * hardware is done with a descriptor by checking the
36944 + * done bit in the following descriptor and the address
36945 + * of the current descriptor the DMA engine is working
36946 + * on. All this is necessary because of our use of
36947 + * a self-linked list to avoid rx overruns.
36948 + */
36949 + ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
36950 + if (ret == -EINPROGRESS) {
36951 + struct ath_rx_status trs;
36952 + struct ath_buf *tbf;
36953 + struct ath_desc *tds;
36954 +
36955 + memset(&trs, 0, sizeof(trs));
36956 + if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
36957 + sc->rx.rxlink = NULL;
36958 + return NULL;
36959 + }
36960 +
36961 + tbf = list_entry(bf->list.next, struct ath_buf, list);
36962 +
36963 + /*
36964 + * On some hardware the descriptor status words could
36965 + * get corrupted, including the done bit. Because of
36966 + * this, check if the next descriptor's done bit is
36967 + * set or not.
36968 + *
36969 + * If the next descriptor's done bit is set, the current
36970 + * descriptor has been corrupted. Force s/w to discard
36971 + * this descriptor and continue...
36972 + */
36973 +
36974 + tds = tbf->bf_desc;
36975 + ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
36976 + if (ret == -EINPROGRESS)
36977 + return NULL;
36978 + }
36979 +
36980 + if (!bf->bf_mpdu)
36981 + return bf;
36982 +
36983 + /*
36984 + * Synchronize the DMA transfer with CPU before
36985 + * 1. accessing the frame
36986 + * 2. requeueing the same buffer to h/w
36987 + */
36988 + dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
36989 + common->rx_bufsize,
36990 + DMA_FROM_DEVICE);
36991 +
36992 + return bf;
36993 +}
36994 +
36995 +
36996 +int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
36997 +{
36998 + struct ath_buf *bf;
36999 struct sk_buff *skb = NULL, *requeue_skb;
37000 struct ieee80211_rx_status *rxs;
37001 struct ath_hw *ah = sc->sc_ah;
37002 @@ -491,7 +834,16 @@ int ath_rx_tasklet(struct ath_softc *sc,
37003 int retval;
37004 bool decrypt_error = false;
37005 struct ath_rx_status rs;
37006 + enum ath9k_rx_qtype qtype;
37007 + bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
37008 + int dma_type;
37009 +
37010 + if (edma)
37011 + dma_type = DMA_FROM_DEVICE;
37012 + else
37013 + dma_type = DMA_BIDIRECTIONAL;
37014
37015 + qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
37016 spin_lock_bh(&sc->rx.rxbuflock);
37017
37018 do {
37019 @@ -499,71 +851,19 @@ int ath_rx_tasklet(struct ath_softc *sc,
37020 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
37021 break;
37022
37023 - if (list_empty(&sc->rx.rxbuf)) {
37024 - sc->rx.rxlink = NULL;
37025 - break;
37026 - }
37027 -
37028 - bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
37029 - ds = bf->bf_desc;
37030 -
37031 - /*
37032 - * Must provide the virtual address of the current
37033 - * descriptor, the physical address, and the virtual
37034 - * address of the next descriptor in the h/w chain.
37035 - * This allows the HAL to look ahead to see if the
37036 - * hardware is done with a descriptor by checking the
37037 - * done bit in the following descriptor and the address
37038 - * of the current descriptor the DMA engine is working
37039 - * on. All this is necessary because of our use of
37040 - * a self-linked list to avoid rx overruns.
37041 - */
37042 memset(&rs, 0, sizeof(rs));
37043 - retval = ath9k_hw_rxprocdesc(ah, ds, &rs, 0);
37044 - if (retval == -EINPROGRESS) {
37045 - struct ath_rx_status trs;
37046 - struct ath_buf *tbf;
37047 - struct ath_desc *tds;
37048 -
37049 - memset(&trs, 0, sizeof(trs));
37050 - if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
37051 - sc->rx.rxlink = NULL;
37052 - break;
37053 - }
37054 + if (edma)
37055 + bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
37056 + else
37057 + bf = ath_get_next_rx_buf(sc, &rs);
37058
37059 - tbf = list_entry(bf->list.next, struct ath_buf, list);
37060 -
37061 - /*
37062 - * On some hardware the descriptor status words could
37063 - * get corrupted, including the done bit. Because of
37064 - * this, check if the next descriptor's done bit is
37065 - * set or not.
37066 - *
37067 - * If the next descriptor's done bit is set, the current
37068 - * descriptor has been corrupted. Force s/w to discard
37069 - * this descriptor and continue...
37070 - */
37071 -
37072 - tds = tbf->bf_desc;
37073 - retval = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
37074 - if (retval == -EINPROGRESS) {
37075 - break;
37076 - }
37077 - }
37078 + if (!bf)
37079 + break;
37080
37081 skb = bf->bf_mpdu;
37082 if (!skb)
37083 continue;
37084
37085 - /*
37086 - * Synchronize the DMA transfer with CPU before
37087 - * 1. accessing the frame
37088 - * 2. requeueing the same buffer to h/w
37089 - */
37090 - dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
37091 - common->rx_bufsize,
37092 - DMA_FROM_DEVICE);
37093 -
37094 hdr = (struct ieee80211_hdr *) skb->data;
37095 rxs = IEEE80211_SKB_RXCB(skb);
37096
37097 @@ -597,9 +897,11 @@ int ath_rx_tasklet(struct ath_softc *sc,
37098 /* Unmap the frame */
37099 dma_unmap_single(sc->dev, bf->bf_buf_addr,
37100 common->rx_bufsize,
37101 - DMA_FROM_DEVICE);
37102 + dma_type);
37103
37104 - skb_put(skb, rs.rs_datalen);
37105 + skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
37106 + if (ah->caps.rx_status_len)
37107 + skb_pull(skb, ah->caps.rx_status_len);
37108
37109 ath9k_cmn_rx_skb_postprocess(common, skb, &rs,
37110 rxs, decrypt_error);
37111 @@ -608,7 +910,7 @@ int ath_rx_tasklet(struct ath_softc *sc,
37112 bf->bf_mpdu = requeue_skb;
37113 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
37114 common->rx_bufsize,
37115 - DMA_FROM_DEVICE);
37116 + dma_type);
37117 if (unlikely(dma_mapping_error(sc->dev,
37118 bf->bf_buf_addr))) {
37119 dev_kfree_skb_any(requeue_skb);
37120 @@ -639,12 +941,16 @@ int ath_rx_tasklet(struct ath_softc *sc,
37121 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
37122
37123 requeue:
37124 - list_move_tail(&bf->list, &sc->rx.rxbuf);
37125 - ath_rx_buf_link(sc, bf);
37126 + if (edma) {
37127 + list_add_tail(&bf->list, &sc->rx.rxbuf);
37128 + ath_rx_edma_buf_link(sc, qtype);
37129 + } else {
37130 + list_move_tail(&bf->list, &sc->rx.rxbuf);
37131 + ath_rx_buf_link(sc, bf);
37132 + }
37133 } while (1);
37134
37135 spin_unlock_bh(&sc->rx.rxbuflock);
37136
37137 return 0;
37138 -#undef PA2DESC
37139 }
37140 --- a/drivers/net/wireless/ath/ath9k/reg.h
37141 +++ b/drivers/net/wireless/ath/ath9k/reg.h
37142 @@ -20,7 +20,7 @@
37143 #include "../reg.h"
37144
37145 #define AR_CR 0x0008
37146 -#define AR_CR_RXE 0x00000004
37147 +#define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
37148 #define AR_CR_RXD 0x00000020
37149 #define AR_CR_SWI 0x00000040
37150
37151 @@ -39,6 +39,12 @@
37152 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
37153 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
37154
37155 +#define AR_RXBP_THRESH 0x0018
37156 +#define AR_RXBP_THRESH_HP 0x0000000f
37157 +#define AR_RXBP_THRESH_HP_S 0
37158 +#define AR_RXBP_THRESH_LP 0x00003f00
37159 +#define AR_RXBP_THRESH_LP_S 8
37160 +
37161 #define AR_MIRT 0x0020
37162 #define AR_MIRT_VAL 0x0000ffff
37163 #define AR_MIRT_VAL_S 16
37164 @@ -144,6 +150,9 @@
37165 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15
37166 #define AR_MACMISC_MISC_OBS_BUS_1 1
37167
37168 +#define AR_DATABUF_SIZE 0x0060
37169 +#define AR_DATABUF_SIZE_MASK 0x00000FFF
37170 +
37171 #define AR_GTXTO 0x0064
37172 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF
37173 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000
37174 @@ -160,9 +169,14 @@
37175 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000
37176 #define AR_CST_TIMEOUT_LIMIT_S 16
37177
37178 +#define AR_HP_RXDP 0x0074
37179 +#define AR_LP_RXDP 0x0078
37180 +
37181 #define AR_ISR 0x0080
37182 #define AR_ISR_RXOK 0x00000001
37183 #define AR_ISR_RXDESC 0x00000002
37184 +#define AR_ISR_HP_RXOK 0x00000001
37185 +#define AR_ISR_LP_RXOK 0x00000002
37186 #define AR_ISR_RXERR 0x00000004
37187 #define AR_ISR_RXNOPKT 0x00000008
37188 #define AR_ISR_RXEOL 0x00000010
37189 @@ -232,7 +246,6 @@
37190 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00
37191 #define AR_ISR_S5_TIM_TIMER 0x00000010
37192 #define AR_ISR_S5_DTIM_TIMER 0x00000020
37193 -#define AR_ISR_S5_S 0x00d8
37194 #define AR_IMR_S5 0x00b8
37195 #define AR_IMR_S5_TIM_TIMER 0x00000010
37196 #define AR_IMR_S5_DTIM_TIMER 0x00000020
37197 @@ -240,7 +253,6 @@
37198 #define AR_ISR_S5_GENTIMER_TRIG_S 0
37199 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000
37200 #define AR_ISR_S5_GENTIMER_THRESH_S 16
37201 -#define AR_ISR_S5_S 0x00d8
37202 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80
37203 #define AR_IMR_S5_GENTIMER_TRIG_S 0
37204 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000
37205 @@ -249,6 +261,8 @@
37206 #define AR_IMR 0x00a0
37207 #define AR_IMR_RXOK 0x00000001
37208 #define AR_IMR_RXDESC 0x00000002
37209 +#define AR_IMR_RXOK_HP 0x00000001
37210 +#define AR_IMR_RXOK_LP 0x00000002
37211 #define AR_IMR_RXERR 0x00000004
37212 #define AR_IMR_RXNOPKT 0x00000008
37213 #define AR_IMR_RXEOL 0x00000010
37214 @@ -332,10 +346,10 @@
37215 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000
37216 #define AR_ISR_S1_QCU_TXEOL_S 16
37217
37218 -#define AR_ISR_S2_S 0x00cc
37219 -#define AR_ISR_S3_S 0x00d0
37220 -#define AR_ISR_S4_S 0x00d4
37221 -#define AR_ISR_S5_S 0x00d8
37222 +#define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
37223 +#define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
37224 +#define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
37225 +#define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
37226 #define AR_DMADBG_0 0x00e0
37227 #define AR_DMADBG_1 0x00e4
37228 #define AR_DMADBG_2 0x00e8
37229 @@ -369,6 +383,9 @@
37230 #define AR_Q9_TXDP 0x0824
37231 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
37232
37233 +#define AR_Q_STATUS_RING_START 0x830
37234 +#define AR_Q_STATUS_RING_END 0x834
37235 +
37236 #define AR_Q_TXE 0x0840
37237 #define AR_Q_TXE_M 0x000003FF
37238
37239 @@ -461,6 +478,9 @@
37240 #define AR_Q_RDYTIMESHDN 0x0a40
37241 #define AR_Q_RDYTIMESHDN_M 0x000003FF
37242
37243 +/* MAC Descriptor CRC check */
37244 +#define AR_Q_DESC_CRCCHK 0xa44
37245 +#define AR_Q_DESC_CRCCHK_EN 1 /* Enable CRC check on the descriptor fetched from host */
37246
37247 #define AR_NUM_DCU 10
37248 #define AR_DCU_0 0x0001
37249 @@ -759,6 +779,8 @@
37250 #define AR_SREV_VERSION_9271 0x140
37251 #define AR_SREV_REVISION_9271_10 0
37252 #define AR_SREV_REVISION_9271_11 1
37253 +#define AR_SREV_VERSION_9300 0x1c0
37254 +#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
37255
37256 #define AR_SREV_5416(_ah) \
37257 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
37258 @@ -844,6 +866,15 @@
37259 #define AR_SREV_9271_11(_ah) \
37260 (AR_SREV_9271(_ah) && \
37261 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))
37262 +#define AR_SREV_9300(_ah) \
37263 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
37264 +#define AR_SREV_9300_20(_ah) \
37265 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
37266 + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20))
37267 +#define AR_SREV_9300_20_OR_LATER(_ah) \
37268 + (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \
37269 + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
37270 + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
37271
37272 #define AR_SREV_9285E_20(_ah) \
37273 (AR_SREV_9285_12_OR_LATER(_ah) && \
37274 @@ -945,6 +976,7 @@ enum {
37275 #define AR9285_NUM_GPIO 12
37276 #define AR9287_NUM_GPIO 11
37277 #define AR9271_NUM_GPIO 16
37278 +#define AR9300_NUM_GPIO 17
37279
37280 #define AR_GPIO_IN_OUT 0x4048
37281 #define AR_GPIO_IN_VAL 0x0FFFC000
37282 @@ -957,19 +989,21 @@ enum {
37283 #define AR9287_GPIO_IN_VAL_S 11
37284 #define AR9271_GPIO_IN_VAL 0xFFFF0000
37285 #define AR9271_GPIO_IN_VAL_S 16
37286 +#define AR9300_GPIO_IN_VAL 0x0001FFFF
37287 +#define AR9300_GPIO_IN_VAL_S 0
37288
37289 -#define AR_GPIO_OE_OUT 0x404c
37290 +#define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)
37291 #define AR_GPIO_OE_OUT_DRV 0x3
37292 #define AR_GPIO_OE_OUT_DRV_NO 0x0
37293 #define AR_GPIO_OE_OUT_DRV_LOW 0x1
37294 #define AR_GPIO_OE_OUT_DRV_HI 0x2
37295 #define AR_GPIO_OE_OUT_DRV_ALL 0x3
37296
37297 -#define AR_GPIO_INTR_POL 0x4050
37298 -#define AR_GPIO_INTR_POL_VAL 0x00001FFF
37299 +#define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050)
37300 +#define AR_GPIO_INTR_POL_VAL 0x0001FFFF
37301 #define AR_GPIO_INTR_POL_VAL_S 0
37302
37303 -#define AR_GPIO_INPUT_EN_VAL 0x4054
37304 +#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054)
37305 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
37306 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
37307 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
37308 @@ -987,13 +1021,13 @@ enum {
37309 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
37310 #define AR_GPIO_JTAG_DISABLE 0x00020000
37311
37312 -#define AR_GPIO_INPUT_MUX1 0x4058
37313 +#define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058)
37314 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
37315 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
37316 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
37317 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
37318
37319 -#define AR_GPIO_INPUT_MUX2 0x405c
37320 +#define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c)
37321 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
37322 #define AR_GPIO_INPUT_MUX2_CLK25_S 0
37323 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
37324 @@ -1001,13 +1035,13 @@ enum {
37325 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
37326 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
37327
37328 -#define AR_GPIO_OUTPUT_MUX1 0x4060
37329 -#define AR_GPIO_OUTPUT_MUX2 0x4064
37330 -#define AR_GPIO_OUTPUT_MUX3 0x4068
37331 +#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060)
37332 +#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064)
37333 +#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068)
37334
37335 -#define AR_INPUT_STATE 0x406c
37336 +#define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c)
37337
37338 -#define AR_EEPROM_STATUS_DATA 0x407c
37339 +#define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c)
37340 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
37341 #define AR_EEPROM_STATUS_DATA_VAL_S 0
37342 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
37343 @@ -1015,13 +1049,24 @@ enum {
37344 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
37345 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
37346
37347 -#define AR_OBS 0x4080
37348 +#define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080)
37349
37350 -#define AR_GPIO_PDPU 0x4088
37351 +#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
37352
37353 -#define AR_PCIE_MSI 0x4094
37354 +#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
37355 #define AR_PCIE_MSI_ENABLE 0x00000001
37356
37357 +#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
37358 +#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
37359 +#define AR_INTR_PRIO_SYNC_MASK 0x40cc
37360 +#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
37361 +
37362 +#define AR_RTC_9300_PLL_DIV 0x000003ff
37363 +#define AR_RTC_9300_PLL_DIV_S 0
37364 +#define AR_RTC_9300_PLL_REFDIV 0x00003C00
37365 +#define AR_RTC_9300_PLL_REFDIV_S 10
37366 +#define AR_RTC_9300_PLL_CLKSEL 0x0000C000
37367 +#define AR_RTC_9300_PLL_CLKSEL_S 14
37368
37369 #define AR_RTC_9160_PLL_DIV 0x000003ff
37370 #define AR_RTC_9160_PLL_DIV_S 0
37371 @@ -1039,6 +1084,16 @@ enum {
37372 #define AR_RTC_RC_COLD_RESET 0x00000004
37373 #define AR_RTC_RC_WARM_RESET 0x00000008
37374
37375 +/* Crystal Control */
37376 +#define AR_RTC_XTAL_CONTROL 0x7004
37377 +
37378 +/* Reg Control 0 */
37379 +#define AR_RTC_REG_CONTROL0 0x7008
37380 +
37381 +/* Reg Control 1 */
37382 +#define AR_RTC_REG_CONTROL1 0x700c
37383 +#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
37384 +
37385 #define AR_RTC_PLL_CONTROL \
37386 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
37387
37388 @@ -1069,6 +1124,7 @@ enum {
37389 #define AR_RTC_SLEEP_CLK \
37390 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
37391 #define AR_RTC_FORCE_DERIVED_CLK 0x2
37392 +#define AR_RTC_FORCE_SWREG_PRD 0x00000004
37393
37394 #define AR_RTC_FORCE_WAKE \
37395 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
37396 @@ -1533,7 +1589,7 @@ enum {
37397 #define AR_TSFOOR_THRESHOLD 0x813c
37398 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
37399
37400 -#define AR_PHY_ERR_EIFS_MASK 8144
37401 +#define AR_PHY_ERR_EIFS_MASK 0x8144
37402
37403 #define AR_PHY_ERR_3 0x8168
37404 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF
37405 @@ -1599,24 +1655,26 @@ enum {
37406 #define AR_FIRST_NDP_TIMER 7
37407 #define AR_NDP2_PERIOD 0x81a0
37408 #define AR_NDP2_TIMER_MODE 0x81c0
37409 -#define AR_NEXT_TBTT_TIMER 0x8200
37410 -#define AR_NEXT_DMA_BEACON_ALERT 0x8204
37411 -#define AR_NEXT_SWBA 0x8208
37412 -#define AR_NEXT_CFP 0x8208
37413 -#define AR_NEXT_HCF 0x820C
37414 -#define AR_NEXT_TIM 0x8210
37415 -#define AR_NEXT_DTIM 0x8214
37416 -#define AR_NEXT_QUIET_TIMER 0x8218
37417 -#define AR_NEXT_NDP_TIMER 0x821C
37418 -
37419 -#define AR_BEACON_PERIOD 0x8220
37420 -#define AR_DMA_BEACON_PERIOD 0x8224
37421 -#define AR_SWBA_PERIOD 0x8228
37422 -#define AR_HCF_PERIOD 0x822C
37423 -#define AR_TIM_PERIOD 0x8230
37424 -#define AR_DTIM_PERIOD 0x8234
37425 -#define AR_QUIET_PERIOD 0x8238
37426 -#define AR_NDP_PERIOD 0x823C
37427 +
37428 +#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))
37429 +#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
37430 +#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1)
37431 +#define AR_NEXT_SWBA AR_GEN_TIMERS(2)
37432 +#define AR_NEXT_CFP AR_GEN_TIMERS(2)
37433 +#define AR_NEXT_HCF AR_GEN_TIMERS(3)
37434 +#define AR_NEXT_TIM AR_GEN_TIMERS(4)
37435 +#define AR_NEXT_DTIM AR_GEN_TIMERS(5)
37436 +#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6)
37437 +#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7)
37438 +
37439 +#define AR_BEACON_PERIOD AR_GEN_TIMERS(8)
37440 +#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9)
37441 +#define AR_SWBA_PERIOD AR_GEN_TIMERS(10)
37442 +#define AR_HCF_PERIOD AR_GEN_TIMERS(11)
37443 +#define AR_TIM_PERIOD AR_GEN_TIMERS(12)
37444 +#define AR_DTIM_PERIOD AR_GEN_TIMERS(13)
37445 +#define AR_QUIET_PERIOD AR_GEN_TIMERS(14)
37446 +#define AR_NDP_PERIOD AR_GEN_TIMERS(15)
37447
37448 #define AR_TIMER_MODE 0x8240
37449 #define AR_TBTT_TIMER_EN 0x00000001
37450 @@ -1730,4 +1788,32 @@ enum {
37451 #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
37452 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
37453
37454 +#define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */
37455 +#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search
37456 + * based on both MAC Address and Key ID.
37457 + * If bit is 0, then Multicast search is
37458 + * based on MAC address only.
37459 + * For Merlin and above only.
37460 + */
37461 +#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature,
37462 + * when it is enable, AGG_WEP would takes
37463 + * charge of the encryption interface of
37464 + * pcu_txsm.
37465 + */
37466 +
37467 +#define AR9300_SM_BASE 0xa200
37468 +#define AR9002_PHY_AGC_CONTROL 0x9860
37469 +#define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4
37470 +#define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
37471 +#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
37472 +#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */
37473 +#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */
37474 +#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */
37475 +#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */
37476 +#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
37477 +#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
37478 +#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
37479 +#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
37480 +#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
37481 +
37482 #endif
37483 --- a/drivers/net/wireless/ath/ath9k/xmit.c
37484 +++ b/drivers/net/wireless/ath/ath9k/xmit.c
37485 @@ -91,7 +91,6 @@ static int ath_max_4ms_framelen[3][16] =
37486 }
37487 };
37488
37489 -
37490 /*********************/
37491 /* Aggregation logic */
37492 /*********************/
37493 @@ -279,7 +278,7 @@ static struct ath_buf* ath_clone_txbuf(s
37494 tbf->aphy = bf->aphy;
37495 tbf->bf_mpdu = bf->bf_mpdu;
37496 tbf->bf_buf_addr = bf->bf_buf_addr;
37497 - *(tbf->bf_desc) = *(bf->bf_desc);
37498 + memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
37499 tbf->bf_state = bf->bf_state;
37500 tbf->bf_dmacontext = bf->bf_dmacontext;
37501
37502 @@ -358,8 +357,7 @@ static void ath_tx_complete_aggr(struct
37503 /* transmit completion */
37504 acked_cnt++;
37505 } else {
37506 - if (!(tid->state & AGGR_CLEANUP) &&
37507 - ts->ts_flags != ATH9K_TX_SW_ABORTED) {
37508 + if (!(tid->state & AGGR_CLEANUP) && !bf_last->bf_tx_aborted) {
37509 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
37510 ath_tx_set_retry(sc, txq, bf);
37511 txpending = 1;
37512 @@ -378,7 +376,8 @@ static void ath_tx_complete_aggr(struct
37513 }
37514 }
37515
37516 - if (bf_next == NULL) {
37517 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
37518 + bf_next == NULL) {
37519 /*
37520 * Make sure the last desc is reclaimed if it
37521 * not a holding desc.
37522 @@ -412,7 +411,8 @@ static void ath_tx_complete_aggr(struct
37523 !txfail, sendbar);
37524 } else {
37525 /* retry the un-acked ones */
37526 - if (bf->bf_next == NULL && bf_last->bf_stale) {
37527 + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
37528 + bf->bf_next == NULL && bf_last->bf_stale) {
37529 struct ath_buf *tbf;
37530
37531 tbf = ath_clone_txbuf(sc, bf_last);
37532 @@ -665,7 +665,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_
37533 bpad = PADBYTES(al_delta) + (ndelim << 2);
37534
37535 bf->bf_next = NULL;
37536 - bf->bf_desc->ds_link = 0;
37537 + ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
37538
37539 /* link buffers of this frame to the aggregate */
37540 ath_tx_addto_baw(sc, tid, bf);
37541 @@ -673,7 +673,8 @@ static enum ATH_AGGR_STATUS ath_tx_form_
37542 list_move_tail(&bf->list, bf_q);
37543 if (bf_prev) {
37544 bf_prev->bf_next = bf;
37545 - bf_prev->bf_desc->ds_link = bf->bf_daddr;
37546 + ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
37547 + bf->bf_daddr);
37548 }
37549 bf_prev = bf;
37550
37551 @@ -853,7 +854,7 @@ struct ath_txq *ath_txq_setup(struct ath
37552 struct ath_hw *ah = sc->sc_ah;
37553 struct ath_common *common = ath9k_hw_common(ah);
37554 struct ath9k_tx_queue_info qi;
37555 - int qnum;
37556 + int qnum, i;
37557
37558 memset(&qi, 0, sizeof(qi));
37559 qi.tqi_subtype = subtype;
37560 @@ -877,11 +878,16 @@ struct ath_txq *ath_txq_setup(struct ath
37561 * The UAPSD queue is an exception, since we take a desc-
37562 * based intr on the EOSP frames.
37563 */
37564 - if (qtype == ATH9K_TX_QUEUE_UAPSD)
37565 - qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
37566 - else
37567 - qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
37568 - TXQ_FLAG_TXDESCINT_ENABLE;
37569 + if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37570 + qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
37571 + TXQ_FLAG_TXERRINT_ENABLE;
37572 + } else {
37573 + if (qtype == ATH9K_TX_QUEUE_UAPSD)
37574 + qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
37575 + else
37576 + qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
37577 + TXQ_FLAG_TXDESCINT_ENABLE;
37578 + }
37579 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
37580 if (qnum == -1) {
37581 /*
37582 @@ -908,6 +914,11 @@ struct ath_txq *ath_txq_setup(struct ath
37583 txq->axq_depth = 0;
37584 txq->axq_tx_inprogress = false;
37585 sc->tx.txqsetup |= 1<<qnum;
37586 +
37587 + txq->txq_headidx = txq->txq_tailidx = 0;
37588 + for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
37589 + INIT_LIST_HEAD(&txq->txq_fifo[i]);
37590 + INIT_LIST_HEAD(&txq->txq_fifo_pending);
37591 }
37592 return &sc->tx.txq[qnum];
37593 }
37594 @@ -1035,36 +1046,64 @@ void ath_draintxq(struct ath_softc *sc,
37595 struct ath_tx_status ts;
37596
37597 memset(&ts, 0, sizeof(ts));
37598 - if (!retry_tx)
37599 - ts.ts_flags = ATH9K_TX_SW_ABORTED;
37600 -
37601 INIT_LIST_HEAD(&bf_head);
37602
37603 for (;;) {
37604 spin_lock_bh(&txq->axq_lock);
37605
37606 - if (list_empty(&txq->axq_q)) {
37607 - txq->axq_link = NULL;
37608 - spin_unlock_bh(&txq->axq_lock);
37609 - break;
37610 - }
37611 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37612 + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
37613 + if (list_empty(&txq->txq_fifo_pending)) {
37614 + txq->txq_headidx = txq->txq_tailidx = 0;
37615 + spin_unlock_bh(&txq->axq_lock);
37616 + break;
37617 + }
37618
37619 - bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
37620 + bf = list_first_entry(&txq->txq_fifo_pending,
37621 + struct ath_buf, list);
37622
37623 - if (bf->bf_stale) {
37624 - list_del(&bf->list);
37625 - spin_unlock_bh(&txq->axq_lock);
37626 + list_cut_position(
37627 + &txq->txq_fifo[txq->txq_tailidx],
37628 + &txq->txq_fifo_pending,
37629 + &bf->bf_lastbf->list);
37630 + } else {
37631 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
37632 + struct ath_buf, list);
37633 + }
37634 + } else {
37635 + if (list_empty(&txq->axq_q)) {
37636 + txq->axq_link = NULL;
37637 + spin_unlock_bh(&txq->axq_lock);
37638 + break;
37639 + }
37640 + bf = list_first_entry(&txq->axq_q, struct ath_buf,
37641 + list);
37642
37643 - spin_lock_bh(&sc->tx.txbuflock);
37644 - list_add_tail(&bf->list, &sc->tx.txbuf);
37645 - spin_unlock_bh(&sc->tx.txbuflock);
37646 - continue;
37647 + if (bf->bf_stale) {
37648 + list_del(&bf->list);
37649 + spin_unlock_bh(&txq->axq_lock);
37650 +
37651 + spin_lock_bh(&sc->tx.txbuflock);
37652 + list_add_tail(&bf->list, &sc->tx.txbuf);
37653 + spin_unlock_bh(&sc->tx.txbuflock);
37654 + continue;
37655 + }
37656 }
37657
37658 lastbf = bf->bf_lastbf;
37659 + if (!retry_tx)
37660 + lastbf->bf_tx_aborted = true;
37661 +
37662 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37663 + list_cut_position(&bf_head,
37664 + &txq->txq_fifo[txq->txq_tailidx],
37665 + &lastbf->list);
37666 + INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
37667 + } else {
37668 + /* remove ath_buf's of the same mpdu from txq */
37669 + list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
37670 + }
37671
37672 - /* remove ath_buf's of the same mpdu from txq */
37673 - list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
37674 txq->axq_depth--;
37675
37676 spin_unlock_bh(&txq->axq_lock);
37677 @@ -1224,25 +1263,46 @@ static void ath_tx_txqaddbuf(struct ath_
37678
37679 bf = list_first_entry(head, struct ath_buf, list);
37680
37681 - list_splice_tail_init(head, &txq->axq_q);
37682 - txq->axq_depth++;
37683 -
37684 ath_print(common, ATH_DBG_QUEUE,
37685 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
37686
37687 - if (txq->axq_link == NULL) {
37688 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37689 + if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
37690 + list_splice_tail_init(head, &txq->txq_fifo_pending);
37691 + return;
37692 + }
37693 + if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
37694 + ath_print(common, ATH_DBG_XMIT,
37695 + "Initializing tx fifo %d which is non-empty\n",
37696 + txq->txq_headidx);
37697 + INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
37698 + list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
37699 + INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
37700 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
37701 ath_print(common, ATH_DBG_XMIT,
37702 "TXDP[%u] = %llx (%p)\n",
37703 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
37704 } else {
37705 - *txq->axq_link = bf->bf_daddr;
37706 - ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
37707 - txq->axq_qnum, txq->axq_link,
37708 - ito64(bf->bf_daddr), bf->bf_desc);
37709 + list_splice_tail_init(head, &txq->axq_q);
37710 +
37711 + if (txq->axq_link == NULL) {
37712 + ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
37713 + ath_print(common, ATH_DBG_XMIT,
37714 + "TXDP[%u] = %llx (%p)\n",
37715 + txq->axq_qnum, ito64(bf->bf_daddr),
37716 + bf->bf_desc);
37717 + } else {
37718 + *txq->axq_link = bf->bf_daddr;
37719 + ath_print(common, ATH_DBG_XMIT,
37720 + "link[%u] (%p)=%llx (%p)\n",
37721 + txq->axq_qnum, txq->axq_link,
37722 + ito64(bf->bf_daddr), bf->bf_desc);
37723 + }
37724 + ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
37725 + &txq->axq_link);
37726 + ath9k_hw_txstart(ah, txq->axq_qnum);
37727 }
37728 - txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
37729 - ath9k_hw_txstart(ah, txq->axq_qnum);
37730 + txq->axq_depth++;
37731 }
37732
37733 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
37734 @@ -1408,8 +1468,7 @@ static void assign_aggr_tid_seqno(struct
37735 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
37736 }
37737
37738 -static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
37739 - struct ath_txq *txq)
37740 +static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
37741 {
37742 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
37743 int flags = 0;
37744 @@ -1420,6 +1479,9 @@ static int setup_tx_flags(struct ath_sof
37745 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
37746 flags |= ATH9K_TXDESC_NOACK;
37747
37748 + if (use_ldpc)
37749 + flags |= ATH9K_TXDESC_LDPC;
37750 +
37751 return flags;
37752 }
37753
37754 @@ -1571,6 +1633,7 @@ static int ath_tx_setup_buffer(struct ie
37755 int hdrlen;
37756 __le16 fc;
37757 int padpos, padsize;
37758 + bool use_ldpc = false;
37759
37760 tx_info->pad[0] = 0;
37761 switch (txctl->frame_type) {
37762 @@ -1597,10 +1660,13 @@ static int ath_tx_setup_buffer(struct ie
37763 bf->bf_frmlen -= padsize;
37764 }
37765
37766 - if (conf_is_ht(&hw->conf))
37767 + if (conf_is_ht(&hw->conf)) {
37768 bf->bf_state.bf_type |= BUF_HT;
37769 + if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
37770 + use_ldpc = true;
37771 + }
37772
37773 - bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
37774 + bf->bf_flags = setup_tx_flags(skb, use_ldpc);
37775
37776 bf->bf_keytype = get_hw_crypto_keytype(skb);
37777 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
37778 @@ -1659,8 +1725,7 @@ static void ath_tx_start_dma(struct ath_
37779 list_add_tail(&bf->list, &bf_head);
37780
37781 ds = bf->bf_desc;
37782 - ds->ds_link = 0;
37783 - ds->ds_data = bf->bf_buf_addr;
37784 + ath9k_hw_set_desc_link(ah, ds, 0);
37785
37786 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
37787 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
37788 @@ -1669,7 +1734,9 @@ static void ath_tx_start_dma(struct ath_
37789 skb->len, /* segment length */
37790 true, /* first segment */
37791 true, /* last segment */
37792 - ds); /* first descriptor */
37793 + ds, /* first descriptor */
37794 + bf->bf_buf_addr,
37795 + txctl->txq->axq_qnum);
37796
37797 spin_lock_bh(&txctl->txq->axq_lock);
37798
37799 @@ -1896,7 +1963,7 @@ static int ath_tx_num_badfrms(struct ath
37800 int nbad = 0;
37801 int isaggr = 0;
37802
37803 - if (ts->ts_flags == ATH9K_TX_SW_ABORTED)
37804 + if (bf->bf_tx_aborted)
37805 return 0;
37806
37807 isaggr = bf_isaggr(bf);
37808 @@ -2138,10 +2205,119 @@ void ath_tx_tasklet(struct ath_softc *sc
37809 }
37810 }
37811
37812 +void ath_tx_edma_tasklet(struct ath_softc *sc)
37813 +{
37814 + struct ath_tx_status txs;
37815 + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
37816 + struct ath_hw *ah = sc->sc_ah;
37817 + struct ath_txq *txq;
37818 + struct ath_buf *bf, *lastbf;
37819 + struct list_head bf_head;
37820 + int status;
37821 + int txok;
37822 +
37823 + for (;;) {
37824 + status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
37825 + if (status == -EINPROGRESS)
37826 + break;
37827 + if (status == -EIO) {
37828 + ath_print(common, ATH_DBG_XMIT,
37829 + "Error processing tx status\n");
37830 + break;
37831 + }
37832 +
37833 + /* Skip beacon completions */
37834 + if (txs.qid == sc->beacon.beaconq)
37835 + continue;
37836 +
37837 + txq = &sc->tx.txq[txs.qid];
37838 +
37839 + spin_lock_bh(&txq->axq_lock);
37840 + if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
37841 + spin_unlock_bh(&txq->axq_lock);
37842 + return;
37843 + }
37844 +
37845 + bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
37846 + struct ath_buf, list);
37847 + lastbf = bf->bf_lastbf;
37848 +
37849 + INIT_LIST_HEAD(&bf_head);
37850 + list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
37851 + &lastbf->list);
37852 + INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
37853 + txq->axq_depth--;
37854 + txq->axq_tx_inprogress = false;
37855 + spin_unlock_bh(&txq->axq_lock);
37856 +
37857 + txok = !(txs.ts_status & ATH9K_TXERR_MASK);
37858 +
37859 + if (!bf_isampdu(bf)) {
37860 + bf->bf_retries = txs.ts_longretry;
37861 + if (txs.ts_status & ATH9K_TXERR_XRETRY)
37862 + bf->bf_state.bf_type |= BUF_XRETRY;
37863 + ath_tx_rc_status(bf, &txs, 0, txok, true);
37864 + }
37865 +
37866 + if (bf_isampdu(bf))
37867 + ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
37868 + else
37869 + ath_tx_complete_buf(sc, bf, txq, &bf_head,
37870 + &txs, txok, 0);
37871 +
37872 + spin_lock_bh(&txq->axq_lock);
37873 + if (!list_empty(&txq->txq_fifo_pending)) {
37874 + INIT_LIST_HEAD(&bf_head);
37875 + bf = list_first_entry(&txq->txq_fifo_pending,
37876 + struct ath_buf, list);
37877 + list_cut_position(&bf_head, &txq->txq_fifo_pending,
37878 + &bf->bf_lastbf->list);
37879 + ath_tx_txqaddbuf(sc, txq, &bf_head);
37880 + } else if (sc->sc_flags & SC_OP_TXAGGR)
37881 + ath_txq_schedule(sc, txq);
37882 + spin_unlock_bh(&txq->axq_lock);
37883 + }
37884 +}
37885 +
37886 /*****************/
37887 /* Init, Cleanup */
37888 /*****************/
37889
37890 +static int ath_txstatus_setup(struct ath_softc *sc, int size)
37891 +{
37892 + struct ath_descdma *dd = &sc->txsdma;
37893 + u8 txs_len = sc->sc_ah->caps.txs_len;
37894 +
37895 + dd->dd_desc_len = size * txs_len;
37896 + dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
37897 + &dd->dd_desc_paddr, GFP_KERNEL);
37898 + if (!dd->dd_desc)
37899 + return -ENOMEM;
37900 +
37901 + return 0;
37902 +}
37903 +
37904 +static int ath_tx_edma_init(struct ath_softc *sc)
37905 +{
37906 + int err;
37907 +
37908 + err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
37909 + if (!err)
37910 + ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
37911 + sc->txsdma.dd_desc_paddr,
37912 + ATH_TXSTATUS_RING_SIZE);
37913 +
37914 + return err;
37915 +}
37916 +
37917 +static void ath_tx_edma_cleanup(struct ath_softc *sc)
37918 +{
37919 + struct ath_descdma *dd = &sc->txsdma;
37920 +
37921 + dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
37922 + dd->dd_desc_paddr);
37923 +}
37924 +
37925 int ath_tx_init(struct ath_softc *sc, int nbufs)
37926 {
37927 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
37928 @@ -2150,7 +2326,7 @@ int ath_tx_init(struct ath_softc *sc, in
37929 spin_lock_init(&sc->tx.txbuflock);
37930
37931 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
37932 - "tx", nbufs, 1);
37933 + "tx", nbufs, 1, 1);
37934 if (error != 0) {
37935 ath_print(common, ATH_DBG_FATAL,
37936 "Failed to allocate tx descriptors: %d\n", error);
37937 @@ -2158,7 +2334,7 @@ int ath_tx_init(struct ath_softc *sc, in
37938 }
37939
37940 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
37941 - "beacon", ATH_BCBUF, 1);
37942 + "beacon", ATH_BCBUF, 1, 1);
37943 if (error != 0) {
37944 ath_print(common, ATH_DBG_FATAL,
37945 "Failed to allocate beacon descriptors: %d\n", error);
37946 @@ -2167,6 +2343,12 @@ int ath_tx_init(struct ath_softc *sc, in
37947
37948 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
37949
37950 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
37951 + error = ath_tx_edma_init(sc);
37952 + if (error)
37953 + goto err;
37954 + }
37955 +
37956 err:
37957 if (error != 0)
37958 ath_tx_cleanup(sc);
37959 @@ -2181,6 +2363,9 @@ void ath_tx_cleanup(struct ath_softc *sc
37960
37961 if (sc->tx.txdma.dd_desc_len != 0)
37962 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
37963 +
37964 + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
37965 + ath_tx_edma_cleanup(sc);
37966 }
37967
37968 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
37969 --- a/include/net/mac80211.h
37970 +++ b/include/net/mac80211.h
37971 @@ -274,6 +274,7 @@ struct ieee80211_bss_conf {
37972 * @IEEE80211_TX_INTFL_NL80211_FRAME_TX: Frame was requested through nl80211
37973 * MLME command (internal to mac80211 to figure out whether to send TX
37974 * status to user space)
37975 + * @IEEE80211_TX_CTL_LDPC: tells the driver to use LDPC for this frame
37976 */
37977 enum mac80211_tx_control_flags {
37978 IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0),
37979 @@ -297,6 +298,7 @@ enum mac80211_tx_control_flags {
37980 IEEE80211_TX_INTFL_RETRANSMISSION = BIT(19),
37981 IEEE80211_TX_INTFL_HAS_RADIOTAP = BIT(20),
37982 IEEE80211_TX_INTFL_NL80211_FRAME_TX = BIT(21),
37983 + IEEE80211_TX_CTL_LDPC = BIT(22),
37984 };
37985
37986 /**
Staging tree of Stijn Tintel