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Fix prism54 firmware indentation and malformed comments
[openwrt/svn-archive/archive.git] / package / mac80211 / patches / 312-rt2x00_implement_support_for_rt2800usb.patch
1 From: Ivo van Doorn <IvDoorn@gmail.com>
2 Date: Sun, 28 Dec 2008 12:48:56 +0000 (+0100)
3 Subject: rt2x00: Implement support for rt2800usb
4 X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fivd%2Frt2x00.git;a=commitdiff_plain;h=e0af839d714d1d04af044d00858ce4113ebd602b
5
6 rt2x00: Implement support for rt2800usb
7
8 Add support for the rt2800usb chipset.
9
10 Includes various patches from Mattias and Felix.
11
12 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
13 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
15 ---
16
17 --- a/drivers/net/wireless/rt2x00/Makefile
18 +++ b/drivers/net/wireless/rt2x00/Makefile
19 @@ -19,3 +19,4 @@ obj-$(CONFIG_RT61PCI) += rt61pci.o
20 obj-$(CONFIG_RT2800PCI) += rt2800pci.o
21 obj-$(CONFIG_RT2500USB) += rt2500usb.o
22 obj-$(CONFIG_RT73USB) += rt73usb.o
23 +obj-$(CONFIG_RT2800USB) += rt2800usb.o
24 --- /dev/null
25 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
26 @@ -0,0 +1,2548 @@
27 +/*
28 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
29 + <http://rt2x00.serialmonkey.com>
30 +
31 + This program is free software; you can redistribute it and/or modify
32 + it under the terms of the GNU General Public License as published by
33 + the Free Software Foundation; either version 2 of the License, or
34 + (at your option) any later version.
35 +
36 + This program is distributed in the hope that it will be useful,
37 + but WITHOUT ANY WARRANTY; without even the implied warranty of
38 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
39 + GNU General Public License for more details.
40 +
41 + You should have received a copy of the GNU General Public License
42 + along with this program; if not, write to the
43 + Free Software Foundation, Inc.,
44 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
45 + */
46 +
47 +/*
48 + Module: rt2800usb
49 + Abstract: rt2800usb device specific routines.
50 + Supported chipsets: RT2800U.
51 + */
52 +
53 +#include <linux/crc-ccitt.h>
54 +#include <linux/delay.h>
55 +#include <linux/etherdevice.h>
56 +#include <linux/init.h>
57 +#include <linux/kernel.h>
58 +#include <linux/module.h>
59 +#include <linux/usb.h>
60 +
61 +#include "rt2x00.h"
62 +#include "rt2x00usb.h"
63 +#include "rt2800usb.h"
64 +
65 +/*
66 + * Allow hardware encryption to be disabled.
67 + */
68 +static int modparam_nohwcrypt = 0;
69 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
70 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
71 +
72 +/*
73 + * Register access.
74 + * All access to the CSR registers will go through the methods
75 + * rt2x00usb_register_read and rt2x00usb_register_write.
76 + * BBP and RF register require indirect register access,
77 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
78 + * These indirect registers work with busy bits,
79 + * and we will try maximal REGISTER_BUSY_COUNT times to access
80 + * the register while taking a REGISTER_BUSY_DELAY us delay
81 + * between each attampt. When the busy bit is still set at that time,
82 + * the access attempt is considered to have failed,
83 + * and we will print an error.
84 + * The _lock versions must be used if you already hold the csr_mutex
85 + */
86 +#define WAIT_FOR_BBP(__dev, __reg) \
87 + rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
88 +#define WAIT_FOR_RF(__dev, __reg) \
89 + rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
90 +#define WAIT_FOR_MCU(__dev, __reg) \
91 + rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
92 + H2M_MAILBOX_CSR_OWNER, (__reg))
93 +
94 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95 + const unsigned int word, const u8 value)
96 +{
97 + u32 reg;
98 +
99 + mutex_lock(&rt2x00dev->csr_mutex);
100 +
101 + /*
102 + * Wait until the BBP becomes available, afterwards we
103 + * can safely write the new data into the register.
104 + */
105 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106 + reg = 0;
107 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
108 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
109 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
110 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
111 +
112 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
113 + }
114 +
115 + mutex_unlock(&rt2x00dev->csr_mutex);
116 +}
117 +
118 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
119 + const unsigned int word, u8 *value)
120 +{
121 + u32 reg;
122 +
123 + mutex_lock(&rt2x00dev->csr_mutex);
124 +
125 + /*
126 + * Wait until the BBP becomes available, afterwards we
127 + * can safely write the read request into the register.
128 + * After the data has been written, we wait until hardware
129 + * returns the correct value, if at any time the register
130 + * doesn't become available in time, reg will be 0xffffffff
131 + * which means we return 0xff to the caller.
132 + */
133 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
134 + reg = 0;
135 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
136 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
137 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
138 +
139 + rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
140 +
141 + WAIT_FOR_BBP(rt2x00dev, &reg);
142 + }
143 +
144 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
145 +
146 + mutex_unlock(&rt2x00dev->csr_mutex);
147 +}
148 +
149 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
150 + const unsigned int word, const u32 value)
151 +{
152 + u32 reg;
153 +
154 + if (!word)
155 + return;
156 +
157 + mutex_lock(&rt2x00dev->csr_mutex);
158 +
159 + /*
160 + * Wait until the RF becomes available, afterwards we
161 + * can safely write the new data into the register.
162 + */
163 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
164 + reg = 0;
165 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
166 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
167 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
168 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
169 +
170 + rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
171 + rt2x00_rf_write(rt2x00dev, word, value);
172 + }
173 +
174 + mutex_unlock(&rt2x00dev->csr_mutex);
175 +}
176 +
177 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
178 + const u8 command, const u8 token,
179 + const u8 arg0, const u8 arg1)
180 +{
181 + u32 reg;
182 +
183 + mutex_lock(&rt2x00dev->csr_mutex);
184 +
185 + /*
186 + * Wait until the MCU becomes available, afterwards we
187 + * can safely write the new data into the register.
188 + */
189 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
190 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
191 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
192 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
193 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
194 + rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
195 +
196 + reg = 0;
197 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
198 + rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
199 + }
200 +
201 + mutex_unlock(&rt2x00dev->csr_mutex);
202 +}
203 +
204 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
205 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
206 + .owner = THIS_MODULE,
207 + .csr = {
208 + .read = rt2x00usb_register_read,
209 + .write = rt2x00usb_register_write,
210 + .flags = RT2X00DEBUGFS_OFFSET,
211 + .word_base = CSR_REG_BASE,
212 + .word_size = sizeof(u32),
213 + .word_count = CSR_REG_SIZE / sizeof(u32),
214 + },
215 + .eeprom = {
216 + .read = rt2x00_eeprom_read,
217 + .write = rt2x00_eeprom_write,
218 + .word_base = EEPROM_BASE,
219 + .word_size = sizeof(u16),
220 + .word_count = EEPROM_SIZE / sizeof(u16),
221 + },
222 + .bbp = {
223 + .read = rt2800usb_bbp_read,
224 + .write = rt2800usb_bbp_write,
225 + .word_base = BBP_BASE,
226 + .word_size = sizeof(u8),
227 + .word_count = BBP_SIZE / sizeof(u8),
228 + },
229 + .rf = {
230 + .read = rt2x00_rf_read,
231 + .write = rt2800usb_rf_write,
232 + .word_base = RF_BASE,
233 + .word_size = sizeof(u32),
234 + .word_count = RF_SIZE / sizeof(u32),
235 + },
236 +};
237 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238 +
239 +#ifdef CONFIG_RT2X00_LIB_RFKILL
240 +static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241 +{
242 + u32 reg;
243 +
244 + rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
245 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
246 +}
247 +#else
248 +#define rt2800usb_rfkill_poll NULL
249 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
250 +
251 +#ifdef CONFIG_RT2X00_LIB_LEDS
252 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
253 + enum led_brightness brightness)
254 +{
255 + struct rt2x00_led *led =
256 + container_of(led_cdev, struct rt2x00_led, led_dev);
257 + unsigned int enabled = brightness != LED_OFF;
258 + unsigned int bg_mode =
259 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
260 + unsigned int polarity =
261 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
262 + EEPROM_FREQ_LED_POLARITY);
263 + unsigned int ledmode =
264 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
265 + EEPROM_FREQ_LED_MODE);
266 +
267 + if (led->type == LED_TYPE_RADIO) {
268 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
269 + enabled ? 0x20 : 0);
270 + } else if (led->type == LED_TYPE_ASSOC) {
271 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
272 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
273 + } else if (led->type == LED_TYPE_QUALITY) {
274 + /*
275 + * The brightness is divided into 6 levels (0 - 5),
276 + * The specs tell us the following levels:
277 + * 0, 1 ,3, 7, 15, 31
278 + * to determine the level in a simple way we can simply
279 + * work with bitshifting:
280 + * (1 << level) - 1
281 + */
282 + rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
283 + (1 << brightness / (LED_FULL / 6)) - 1,
284 + polarity);
285 + }
286 +}
287 +
288 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
289 + unsigned long *delay_on,
290 + unsigned long *delay_off)
291 +{
292 + struct rt2x00_led *led =
293 + container_of(led_cdev, struct rt2x00_led, led_dev);
294 + u32 reg;
295 +
296 + rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
297 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
298 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
299 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
300 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
301 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
302 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
303 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
304 + rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
305 +
306 + return 0;
307 +}
308 +
309 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
310 + struct rt2x00_led *led,
311 + enum led_type type)
312 +{
313 + led->rt2x00dev = rt2x00dev;
314 + led->type = type;
315 + led->led_dev.brightness_set = rt2800usb_brightness_set;
316 + led->led_dev.blink_set = rt2800usb_blink_set;
317 + led->flags = LED_INITIALIZED;
318 +}
319 +#endif /* CONFIG_RT2X00_LIB_LEDS */
320 +
321 +/*
322 + * Configuration handlers.
323 + */
324 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
325 + struct rt2x00lib_crypto *crypto,
326 + struct ieee80211_key_conf *key)
327 +{
328 + u32 offset;
329 + u32 reg;
330 +
331 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
332 +
333 + reg = 0;
334 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
335 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
336 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
337 + crypto->cipher);
338 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
339 + (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
340 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
341 + rt2x00usb_register_write(rt2x00dev, offset, reg);
342 +}
343 +
344 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
345 + struct rt2x00lib_crypto *crypto,
346 + struct ieee80211_key_conf *key)
347 +{
348 + struct hw_key_entry key_entry;
349 + struct rt2x00_field32 field;
350 + int timeout;
351 + u32 offset;
352 + u32 mask;
353 + u32 reg;
354 +
355 + if (crypto->cmd == SET_KEY) {
356 + memcpy(key_entry.key, crypto->key,
357 + sizeof(key_entry.key));
358 + memcpy(key_entry.tx_mic, crypto->tx_mic,
359 + sizeof(key_entry.tx_mic));
360 + memcpy(key_entry.rx_mic, crypto->rx_mic,
361 + sizeof(key_entry.rx_mic));
362 +
363 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
364 + timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
365 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
366 + USB_VENDOR_REQUEST_OUT,
367 + offset, &key_entry,
368 + sizeof(key_entry),
369 + timeout);
370 +
371 + /*
372 + * The driver does not support the IV/EIV generation
373 + * in hardware. However it doesn't support the IV/EIV
374 + * inside the ieee80211 frame either, but requires it
375 + * to be provided seperately for the descriptor.
376 + * rt2x00lib will cut the IV/EIV data out of all frames
377 + * given to us by mac80211, but we must tell mac80211
378 + * to generate the IV/EIV data.
379 + */
380 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
381 + }
382 +
383 + /*
384 + * The cipher types are stored over multiple registers
385 + * starting with SHARED_KEY_MODE_BASE each word will have
386 + * 32 bits and contains the cipher types for 2 modes each.
387 + * Using the correct defines correctly will cause overhead,
388 + * so just calculate the correct offset.
389 + */
390 + mask = key->hw_key_idx % 8;
391 + field.bit_offset = (3 * mask);
392 + field.bit_mask = 0x7 << field.bit_offset;
393 +
394 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
395 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
396 + rt2x00_set_field32(&reg, field,
397 + (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
398 + rt2x00usb_register_write(rt2x00dev, offset, reg);
399 +
400 + /*
401 + * Update WCID information
402 + */
403 + rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
404 +
405 + return 0;
406 +}
407 +
408 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
409 + struct rt2x00lib_crypto *crypto,
410 + struct ieee80211_key_conf *key)
411 +{
412 + struct hw_key_entry key_entry;
413 + int timeout;
414 + u32 offset;
415 +
416 + /*
417 + * 1 pairwise key is possible per AID, this means that the AID
418 + * equals our hw_key_idx.
419 + */
420 + key->hw_key_idx = crypto->aid;
421 +
422 + if (crypto->cmd == SET_KEY) {
423 + memcpy(key_entry.key, crypto->key,
424 + sizeof(key_entry.key));
425 + memcpy(key_entry.tx_mic, crypto->tx_mic,
426 + sizeof(key_entry.tx_mic));
427 + memcpy(key_entry.rx_mic, crypto->rx_mic,
428 + sizeof(key_entry.rx_mic));
429 +
430 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
431 + timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
432 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
433 + USB_VENDOR_REQUEST_OUT,
434 + offset, &key_entry,
435 + sizeof(key_entry),
436 + timeout);
437 +
438 + /*
439 + * The driver does not support the IV/EIV generation
440 + * in hardware. However it doesn't support the IV/EIV
441 + * inside the ieee80211 frame either, but requires it
442 + * to be provided seperately for the descriptor.
443 + * rt2x00lib will cut the IV/EIV data out of all frames
444 + * given to us by mac80211, but we must tell mac80211
445 + * to generate the IV/EIV data.
446 + */
447 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
448 + }
449 +
450 + /*
451 + * Update WCID information
452 + */
453 + rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
454 +
455 + return 0;
456 +}
457 +
458 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
459 + const unsigned int filter_flags)
460 +{
461 + u32 reg;
462 +
463 + /*
464 + * Start configuration steps.
465 + * Note that the version error will always be dropped
466 + * and broadcast frames will always be accepted since
467 + * there is no filter for it at this time.
468 + */
469 + rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
470 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
471 + !(filter_flags & FIF_FCSFAIL));
472 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
473 + !(filter_flags & FIF_PLCPFAIL));
474 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
475 + !(filter_flags & FIF_PROMISC_IN_BSS));
476 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD,
477 + !(filter_flags & FIF_OTHER_BSS));
478 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
479 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
480 + !(filter_flags & FIF_ALLMULTI));
481 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
482 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
483 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
484 + !(filter_flags & FIF_CONTROL));
485 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
486 + !(filter_flags & FIF_CONTROL));
487 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
488 + !(filter_flags & FIF_CONTROL));
489 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
490 + !(filter_flags & FIF_CONTROL));
491 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
492 + !(filter_flags & FIF_CONTROL));
493 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
494 + !(filter_flags & FIF_CONTROL));
495 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
496 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
497 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
498 + !(filter_flags & FIF_CONTROL));
499 + rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
500 +}
501 +
502 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
503 + struct rt2x00_intf *intf,
504 + struct rt2x00intf_conf *conf,
505 + const unsigned int flags)
506 +{
507 + unsigned int beacon_base;
508 + u32 reg;
509 +
510 + if (flags & CONFIG_UPDATE_TYPE) {
511 + /*
512 + * Clear current synchronisation setup.
513 + * For the Beacon base registers we only need to clear
514 + * the first byte since that byte contains the VALID and OWNER
515 + * bits which (when set to 0) will invalidate the entire beacon.
516 + */
517 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
518 + rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
519 +
520 + /*
521 + * Enable synchronisation.
522 + */
523 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
524 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
525 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
526 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
527 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
528 + }
529 +
530 + if (flags & CONFIG_UPDATE_MAC) {
531 + reg = le32_to_cpu(conf->mac[1]);
532 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
533 + conf->mac[1] = cpu_to_le32(reg);
534 +
535 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
536 + conf->mac, sizeof(conf->mac));
537 + }
538 +
539 + if (flags & CONFIG_UPDATE_BSSID) {
540 + reg = le32_to_cpu(conf->bssid[1]);
541 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
542 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
543 + conf->bssid[1] = cpu_to_le32(reg);
544 +
545 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
546 + conf->bssid, sizeof(conf->bssid));
547 + }
548 +}
549 +
550 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
551 + struct rt2x00lib_erp *erp)
552 +{
553 + u32 reg;
554 +
555 + rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
556 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
557 + erp->ack_timeout);
558 + rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
559 +
560 + rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
561 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
562 + !!erp->short_preamble);
563 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
564 + !!erp->short_preamble);
565 + rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
566 +
567 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
568 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
569 + erp->cts_protection ? 2 : 0);
570 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
571 +
572 + rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
573 + erp->basic_rates);
574 + rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE,
575 + erp->basic_rates >> 32);
576 +
577 + rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
578 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
579 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
580 + rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
581 +
582 + rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
583 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
584 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
585 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
586 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
587 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
588 + rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
589 +}
590 +
591 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
592 + struct antenna_setup *ant)
593 +{
594 + u16 eeprom;
595 + u8 r1;
596 + u8 r3;
597 +
598 + /*
599 + * FIXME: Use requested antenna configuration.
600 + */
601 +
602 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
603 +
604 + rt2800usb_bbp_read(rt2x00dev, 1, &r1);
605 + rt2800usb_bbp_read(rt2x00dev, 3, &r3);
606 +
607 + /*
608 + * Configure the TX antenna.
609 + */
610 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
611 + case 1:
612 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
613 + break;
614 + case 2:
615 + case 3:
616 + /* Do nothing */
617 + break;
618 + }
619 +
620 + /*
621 + * Configure the RX antenna.
622 + */
623 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
624 + case 1:
625 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
626 + break;
627 + case 2:
628 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
629 + break;
630 + case 3:
631 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
632 + break;
633 + }
634 +
635 + rt2800usb_bbp_write(rt2x00dev, 3, r3);
636 + rt2800usb_bbp_write(rt2x00dev, 1, r1);
637 +}
638 +
639 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
640 + struct rt2x00lib_conf *libconf)
641 +{
642 + u16 eeprom;
643 + short lna_gain;
644 +
645 + if (libconf->rf.channel <= 14) {
646 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
647 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
648 + } else if (libconf->rf.channel <= 64) {
649 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
650 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
651 + } else if (libconf->rf.channel <= 128) {
652 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
653 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
654 + } else {
655 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
656 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
657 + }
658 +
659 + rt2x00dev->lna_gain = lna_gain;
660 +}
661 +
662 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
663 + struct rf_channel *rf,
664 + struct channel_info *info)
665 +{
666 + u32 reg;
667 + unsigned int tx_pin;
668 + u16 eeprom;
669 +
670 + tx_pin = 0;
671 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
672 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
673 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
674 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
675 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
676 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
677 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
678 +
679 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
680 +
681 + /*
682 + * Determine antenna settings from EEPROM
683 + */
684 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
685 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
686 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
687 + /* Turn off unused PA or LNA when only 1T or 1R */
688 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
689 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
690 + }
691 +
692 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
693 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
694 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
695 + /* Turn off unused PA or LNA when only 1T or 1R */
696 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
697 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
698 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
699 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
700 +
701 + if (rf->channel > 14) {
702 + /*
703 + * When TX power is below 0, we should increase it by 7 to
704 + * make it a positive value (Minumum value is -7).
705 + * However this means that values between 0 and 7 have
706 + * double meaning, and we should set a 7DBm boost flag.
707 + */
708 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
709 + (info->tx_power1 >= 0));
710 +
711 + if (info->tx_power1 < 0)
712 + info->tx_power1 += 7;
713 +
714 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
715 + TXPOWER_A_TO_DEV(info->tx_power1));
716 +
717 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
718 + (info->tx_power2 >= 0));
719 +
720 + if (info->tx_power2 < 0)
721 + info->tx_power2 += 7;
722 +
723 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
724 + TXPOWER_A_TO_DEV(info->tx_power2));
725 +
726 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
727 + } else {
728 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
729 + TXPOWER_G_TO_DEV(info->tx_power1));
730 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
731 + TXPOWER_G_TO_DEV(info->tx_power2));
732 +
733 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
734 + }
735 +
736 + rt2x00_set_field32(&rf->rf4, RF4_BW40,
737 + test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
738 +
739 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
740 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
741 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
742 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
743 +
744 + udelay(200);
745 +
746 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
747 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
748 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
749 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
750 +
751 + udelay(200);
752 +
753 + rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
754 + rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
755 + rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
756 + rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
757 +
758 + /*
759 + * Change BBP settings
760 + */
761 + rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
762 + rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
763 + rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
764 + rt2800usb_bbp_write(rt2x00dev, 86, 0);
765 +
766 + if (rf->channel <= 14) {
767 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
768 + rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
769 + rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
770 + } else {
771 + rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
772 + rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
773 + }
774 +
775 + rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
776 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
777 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
778 + rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
779 + } else {
780 + rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
781 +
782 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
783 + rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
784 + else
785 + rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
786 +
787 + rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
788 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
789 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
790 + rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
791 + }
792 +
793 + rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
794 +
795 + msleep(1);
796 +}
797 +
798 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
799 + const int txpower)
800 +{
801 + u32 reg;
802 + u32 value = TXPOWER_G_TO_DEV(txpower);
803 + u8 r1;
804 +
805 + rt2800usb_bbp_read(rt2x00dev, 1, &r1);
806 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
807 + rt2800usb_bbp_write(rt2x00dev, 1, r1);
808 +
809 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
810 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
811 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
812 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
813 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
814 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
815 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
816 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
817 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
818 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
819 +
820 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
821 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
822 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
823 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
824 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
825 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
826 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
827 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
828 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
829 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
830 +
831 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
832 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
833 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
834 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
835 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
836 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
837 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
838 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
839 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
840 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
841 +
842 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
843 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
844 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
845 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
846 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
847 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
848 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
849 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
850 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
851 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
852 +
853 + rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
854 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
855 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
856 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
857 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
858 + rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
859 +}
860 +
861 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
862 + struct rt2x00lib_conf *libconf)
863 +{
864 + u32 reg;
865 +
866 + rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
867 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
868 + libconf->conf->short_frame_max_tx_count);
869 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
870 + libconf->conf->long_frame_max_tx_count);
871 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
872 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
873 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
874 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
875 + rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
876 +}
877 +
878 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
879 + struct rt2x00lib_conf *libconf)
880 +{
881 + u32 reg;
882 +
883 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
884 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
885 + libconf->conf->beacon_int * 16);
886 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
887 +}
888 +
889 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
890 + struct rt2x00lib_conf *libconf,
891 + const unsigned int flags)
892 +{
893 + /* Always recalculate LNA gain before changing configuration */
894 + rt2800usb_config_lna_gain(rt2x00dev, libconf);
895 +
896 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
897 + rt2800usb_config_channel(rt2x00dev, &libconf->rf,
898 + &libconf->channel);
899 + if (flags & IEEE80211_CONF_CHANGE_POWER)
900 + rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
901 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
902 + rt2800usb_config_retry_limit(rt2x00dev, libconf);
903 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
904 + rt2800usb_config_duration(rt2x00dev, libconf);
905 +}
906 +
907 +/*
908 + * Link tuning
909 + */
910 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
911 + struct link_qual *qual)
912 +{
913 + u32 reg;
914 +
915 + /*
916 + * Update FCS error count from register.
917 + */
918 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
919 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
920 +
921 + /*
922 + * Update False CCA count from register.
923 + */
924 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
925 + qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
926 +}
927 +
928 +static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
929 +{
930 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
931 + return 0x2e + rt2x00dev->lna_gain;
932 +
933 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
934 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
935 + else
936 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
937 +}
938 +
939 +static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
940 + struct link_qual *qual, u8 vgc_level)
941 +{
942 + if (qual->vgc_level != vgc_level) {
943 + rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
944 + qual->vgc_level = vgc_level;
945 + qual->vgc_level_reg = vgc_level;
946 + }
947 +}
948 +
949 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
950 + struct link_qual *qual)
951 +{
952 + rt2800usb_set_vgc(rt2x00dev, qual,
953 + rt2800usb_get_default_vgc(rt2x00dev));
954 +}
955 +
956 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
957 + struct link_qual *qual, const u32 count)
958 +{
959 + if (rt2x00_rev(&rt2x00dev->chip) == RT2870_VERSION_C)
960 + return;
961 +
962 + /*
963 + * When RSSI is better then -80 increase VGC level with 0x10
964 + */
965 + rt2800usb_set_vgc(rt2x00dev, qual,
966 + rt2800usb_get_default_vgc(rt2x00dev) +
967 + ((qual->rssi > -80) * 0x10));
968 +}
969 +
970 +/*
971 + * Firmware functions
972 + */
973 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
974 +{
975 + return FIRMWARE_RT2870;
976 +}
977 +
978 +static u16 rt2800usb_get_firmware_crc(const void *data, const size_t len)
979 +{
980 + u16 crc;
981 +
982 + /*
983 + * Use the crc ccitt algorithm.
984 + * This will return the same value as the legacy driver which
985 + * used bit ordering reversion on the both the firmware bytes
986 + * before input input as well as on the final output.
987 + * Obviously using crc ccitt directly is much more efficient.
988 + * The last 2 bytes in the firmware array are the crc checksum itself,
989 + * this means that we should never pass those 2 bytes to the crc
990 + * algorithm.
991 + */
992 + crc = crc_ccitt(~0, data, len - 2);
993 +
994 + /*
995 + * There is a small difference between the crc-itu-t + bitrev and
996 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
997 + * will be swapped, use swab16 to convert the crc to the correct
998 + * value.
999 + */
1000 + return swab16(crc);
1001 +}
1002 +
1003 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1004 + const void *data, const size_t len)
1005 +{
1006 + unsigned int i;
1007 + int status;
1008 + u32 reg;
1009 +
1010 + /*
1011 + * Wait for stable hardware.
1012 + */
1013 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1014 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1015 + if (reg && reg != ~0)
1016 + break;
1017 + msleep(1);
1018 + }
1019 +
1020 + if (i == REGISTER_BUSY_COUNT) {
1021 + ERROR(rt2x00dev, "Unstable hardware.\n");
1022 + return -EBUSY;
1023 + }
1024 +
1025 + /*
1026 + * Write firmware to device.
1027 + */
1028 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1029 + USB_VENDOR_REQUEST_OUT,
1030 + FIRMWARE_IMAGE_BASE,
1031 + data, len,
1032 + REGISTER_TIMEOUT32(len));
1033 +
1034 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1035 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1036 +
1037 + /*
1038 + * Send firmware request to device to load firmware,
1039 + * we need to specify a long timeout time.
1040 + */
1041 + status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1042 + 0, USB_MODE_FIRMWARE,
1043 + REGISTER_TIMEOUT_FIRMWARE);
1044 + if (status < 0) {
1045 + ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1046 + return status;
1047 + }
1048 +
1049 + /*
1050 + * Wait for device to stabilize.
1051 + */
1052 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1053 + rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1054 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1055 + break;
1056 + msleep(1);
1057 + }
1058 +
1059 + if (i == REGISTER_BUSY_COUNT) {
1060 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1061 + return -EBUSY;
1062 + }
1063 +
1064 + /*
1065 + * Initialize firmware.
1066 + */
1067 + rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1068 + rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1069 + msleep(1);
1070 +
1071 + return 0;
1072 +}
1073 +
1074 +/*
1075 + * Initialization functions.
1076 + */
1077 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1078 +{
1079 + u32 reg;
1080 + unsigned int i;
1081 +
1082 + /*
1083 + * Wait untill BBP and RF are ready.
1084 + */
1085 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1086 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1087 + if (reg && reg != ~0)
1088 + break;
1089 + msleep(1);
1090 + }
1091 +
1092 + if (i == REGISTER_BUSY_COUNT) {
1093 + ERROR(rt2x00dev, "Unstable hardware.\n");
1094 + return -EBUSY;
1095 + }
1096 +
1097 + rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1098 + rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1099 +
1100 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1101 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1102 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1103 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1104 +
1105 + rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1106 +
1107 + rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1108 + USB_MODE_RESET, REGISTER_TIMEOUT);
1109 +
1110 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1111 +
1112 + rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1113 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1114 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1115 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1116 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1117 + rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1118 +
1119 + rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1120 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1121 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1122 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1123 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1124 + rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1125 +
1126 + rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1127 + rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1128 +
1129 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1130 +
1131 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1132 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1133 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1134 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1135 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1136 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1137 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1138 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1139 +
1140 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1141 + rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1142 +
1143 + rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1144 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1145 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1146 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1147 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1148 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1149 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1150 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1151 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1152 + rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1153 +
1154 + rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1155 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1156 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1157 + rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1158 +
1159 + rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1160 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1161 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1162 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1163 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1164 + rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1165 +
1166 + rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1167 +
1168 + rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1169 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1170 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1171 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1172 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1173 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1174 + rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1175 +
1176 + rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1177 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1178 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1179 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1180 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1181 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1182 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1183 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1184 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1185 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1186 + rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1187 +
1188 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1189 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1190 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1191 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1192 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1193 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1194 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1195 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1196 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1197 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1198 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1199 +
1200 + rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1201 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1202 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1203 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1204 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1205 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1206 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1207 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1208 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1209 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1210 + rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1211 +
1212 + rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1213 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1214 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1215 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1216 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1217 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1218 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1219 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1220 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1221 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1222 + rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1223 +
1224 + rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1225 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1226 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1227 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1228 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1229 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1230 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1231 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1232 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1233 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1234 + rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1235 +
1236 + rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1237 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1238 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1239 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1240 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1241 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1242 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1243 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1244 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1245 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1246 + rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1247 +
1248 + rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1249 +
1250 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1251 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1252 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1253 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1254 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1255 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1256 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1257 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1258 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1259 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1260 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1261 +
1262 + rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1263 + rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1264 +
1265 + rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1266 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1267 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1268 + rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1269 +
1270 + rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1271 + rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1272 +
1273 + /*
1274 + * ASIC will keep garbage value after boot, clear encryption keys.
1275 + */
1276 + for (i = 0; i < 254; i++) {
1277 + u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1278 + rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1279 + wcid, sizeof(wcid));
1280 + }
1281 +
1282 + for (i = 0; i < 4; i++)
1283 + rt2x00usb_register_write(rt2x00dev,
1284 + SHARED_KEY_MODE_ENTRY(i), 0);
1285 +
1286 + for (i = 0; i < 256; i++)
1287 + rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1288 +
1289 + /*
1290 + * Clear all beacons
1291 + * For the Beacon base registers we only need to clear
1292 + * the first byte since that byte contains the VALID and OWNER
1293 + * bits which (when set to 0) will invalidate the entire beacon.
1294 + */
1295 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1296 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1297 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1298 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1299 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1300 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1301 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1302 + rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1303 +
1304 + rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1305 + rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1306 + rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1307 +
1308 + rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1309 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1310 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1311 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1312 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1313 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1314 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1315 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1316 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1317 + rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1318 +
1319 + rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1320 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1321 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1322 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1323 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1324 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1325 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1326 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1327 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1328 + rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1329 +
1330 + rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1331 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1332 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1333 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1334 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1335 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1336 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1337 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1338 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1339 + rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1340 +
1341 + rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1342 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1343 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1344 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1345 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1346 + rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1347 +
1348 + /*
1349 + * We must clear the error counters.
1350 + * These registers are cleared on read,
1351 + * so we may pass a useless variable to store the value.
1352 + */
1353 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1354 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1355 + rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1356 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1357 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1358 + rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1359 +
1360 + return 0;
1361 +}
1362 +
1363 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1364 +{
1365 + unsigned int i;
1366 + u32 reg;
1367 +
1368 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1369 + rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1370 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1371 + return 0;
1372 +
1373 + udelay(REGISTER_BUSY_DELAY);
1374 + }
1375 +
1376 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1377 + return -EACCES;
1378 +}
1379 +
1380 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1381 +{
1382 + unsigned int i;
1383 + u8 value;
1384 +
1385 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1386 + rt2800usb_bbp_read(rt2x00dev, 0, &value);
1387 + if ((value != 0xff) && (value != 0x00))
1388 + return 0;
1389 + udelay(REGISTER_BUSY_DELAY);
1390 + }
1391 +
1392 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1393 + return -EACCES;
1394 +}
1395 +
1396 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1397 +{
1398 + unsigned int i;
1399 + u16 eeprom;
1400 + u8 reg_id;
1401 + u8 value;
1402 +
1403 + if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1404 + rt2800usb_wait_bbp_ready(rt2x00dev)))
1405 + return -EACCES;
1406 +
1407 + rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1408 + rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1409 + rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1410 + rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1411 + rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1412 + rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1413 + rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1414 + rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1415 + rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1416 + rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1417 + rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1418 + rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1419 + rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1420 +
1421 + if (rt2x00_rev(&rt2x00dev->chip) == RT2870_VERSION_C) {
1422 + rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1423 + rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1424 + }
1425 +
1426 + if (rt2x00_rev(&rt2x00dev->chip) != RT2870_VERSION_D)
1427 + rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1428 +
1429 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1430 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1431 +
1432 + if (eeprom != 0xffff && eeprom != 0x0000) {
1433 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1434 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1435 + rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1436 + }
1437 + }
1438 +
1439 + return 0;
1440 +}
1441 +
1442 +/*
1443 + * Device state switch handlers.
1444 + */
1445 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1446 + enum dev_state state)
1447 +{
1448 + u32 reg;
1449 +
1450 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1451 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1452 + (state == STATE_RADIO_RX_ON) ||
1453 + (state == STATE_RADIO_RX_ON_LINK));
1454 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1455 +}
1456 +
1457 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1458 +{
1459 + unsigned int i;
1460 + u32 reg;
1461 +
1462 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1463 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1464 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1465 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1466 + return 0;
1467 +
1468 + msleep(1);
1469 + }
1470 +
1471 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1472 + return -EACCES;
1473 +}
1474 +
1475 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1476 +{
1477 + u32 reg;
1478 + u16 word;
1479 +
1480 + /*
1481 + * Initialize all registers.
1482 + */
1483 + if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1484 + rt2800usb_init_registers(rt2x00dev) ||
1485 + rt2800usb_init_bbp(rt2x00dev)))
1486 + return -EIO;
1487 +
1488 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1489 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1490 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1491 +
1492 + udelay(50);
1493 +
1494 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1495 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1496 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1497 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1498 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1499 +
1500 +
1501 + rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1502 + rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1503 + /* Don't use bulk in aggregation when working with USB 1.1 */
1504 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1505 + (rt2x00dev->rx->usb_maxpacket == 512));
1506 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1507 + /* FIXME: Calculate this value based on Aggregation defines */
1508 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1509 + rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1510 + rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1511 + rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1512 +
1513 + rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1514 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1515 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1516 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1517 +
1518 + /*
1519 + * Initialize LED control
1520 + */
1521 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1522 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1523 + word & 0xff, (word >> 8) & 0xff);
1524 +
1525 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1526 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1527 + word & 0xff, (word >> 8) & 0xff);
1528 +
1529 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1530 + rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1531 + word & 0xff, (word >> 8) & 0xff);
1532 +
1533 + /*
1534 + * Send signal to firmware during boot time.
1535 + */
1536 + rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1537 +
1538 + return 0;
1539 +}
1540 +
1541 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1542 +{
1543 + u32 reg;
1544 +
1545 + rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1546 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1547 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1548 + rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1549 +
1550 + rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1551 + rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1552 + rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1553 +
1554 + /* Wait for DMA, ignore error */
1555 + rt2800usb_wait_wpdma_ready(rt2x00dev);
1556 +
1557 + rt2x00usb_disable_radio(rt2x00dev);
1558 +}
1559 +
1560 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1561 + enum dev_state state)
1562 +{
1563 + rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1564 +
1565 + if (state == STATE_AWAKE)
1566 + rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1567 + else
1568 + rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1569 +
1570 + return 0;
1571 +}
1572 +
1573 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1574 + enum dev_state state)
1575 +{
1576 + int retval = 0;
1577 +
1578 + switch (state) {
1579 + case STATE_RADIO_ON:
1580 + /*
1581 + * Before the radio can be enabled, the device first has
1582 + * to be woken up. After that it needs a bit of time
1583 + * to be fully awake and the radio can be enabled.
1584 + */
1585 + rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1586 + msleep(1);
1587 + retval = rt2800usb_enable_radio(rt2x00dev);
1588 + break;
1589 + case STATE_RADIO_OFF:
1590 + /*
1591 + * After the radio has been disablee, the device should
1592 + * be put to sleep for powersaving.
1593 + */
1594 + rt2800usb_disable_radio(rt2x00dev);
1595 + rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1596 + break;
1597 + case STATE_RADIO_RX_ON:
1598 + case STATE_RADIO_RX_ON_LINK:
1599 + case STATE_RADIO_RX_OFF:
1600 + case STATE_RADIO_RX_OFF_LINK:
1601 + rt2800usb_toggle_rx(rt2x00dev, state);
1602 + break;
1603 + case STATE_RADIO_IRQ_ON:
1604 + case STATE_RADIO_IRQ_OFF:
1605 + /* No support, but no error either */
1606 + break;
1607 + case STATE_DEEP_SLEEP:
1608 + case STATE_SLEEP:
1609 + case STATE_STANDBY:
1610 + case STATE_AWAKE:
1611 + retval = rt2800usb_set_state(rt2x00dev, state);
1612 + break;
1613 + default:
1614 + retval = -ENOTSUPP;
1615 + break;
1616 + }
1617 +
1618 + if (unlikely(retval))
1619 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1620 + state, retval);
1621 +
1622 + return retval;
1623 +}
1624 +
1625 +/*
1626 + * TX descriptor initialization
1627 + */
1628 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1629 + struct sk_buff *skb,
1630 + struct txentry_desc *txdesc)
1631 +{
1632 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1633 + __le32 *txd = skbdesc->desc;
1634 + __le32 *txwi = txd + TXD_DESC_SIZE;
1635 + u32 word;
1636 +
1637 + /*
1638 + * Initialize TX Info descriptor
1639 + */
1640 + rt2x00_desc_read(txwi, 0, &word);
1641 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1642 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1643 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1644 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1645 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1646 + rt2x00_set_field32(&word, TXWI_W0_TS,
1647 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1648 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1649 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1650 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1651 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1652 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1653 + rt2x00_set_field32(&word, TXWI_W0_BW,
1654 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1655 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1656 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1657 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1658 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1659 + rt2x00_desc_write(txwi, 0, word);
1660 +
1661 + rt2x00_desc_read(txwi, 1, &word);
1662 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1663 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1664 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1665 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1666 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1667 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 0xff);
1668 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1669 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1670 + skbdesc->entry->entry_idx);
1671 + rt2x00_desc_write(txwi, 1, word);
1672 +
1673 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1674 + _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
1675 + _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
1676 + }
1677 +
1678 + /*
1679 + * Initialize TX descriptor
1680 + */
1681 + rt2x00_desc_read(txd, 0, &word);
1682 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1683 + rt2x00_desc_write(txd, 0, word);
1684 +
1685 + rt2x00_desc_read(txd, 1, &word);
1686 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1687 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1688 + rt2x00_set_field32(&word, TXD_W1_BURST,
1689 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1690 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1691 + rt2x00dev->hw->extra_tx_headroom);
1692 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1693 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1694 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1695 + rt2x00_desc_write(txd, 1, word);
1696 +
1697 + rt2x00_desc_read(txd, 2, &word);
1698 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1699 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1700 + rt2x00_desc_write(txd, 2, word);
1701 +
1702 + rt2x00_desc_read(txd, 3, &word);
1703 + rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1704 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1705 + rt2x00_desc_write(txd, 3, word);
1706 +}
1707 +
1708 +/*
1709 + * TX data initialization
1710 + */
1711 +static void rt2800usb_write_beacon(struct queue_entry *entry)
1712 +{
1713 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1714 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1715 + unsigned int beacon_base;
1716 + u32 reg;
1717 +
1718 + /*
1719 + * Add the descriptor in front of the skb.
1720 + */
1721 + skb_push(entry->skb, entry->queue->desc_size);
1722 + memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1723 + skbdesc->desc = entry->skb->data;
1724 +
1725 + /*
1726 + * Disable beaconing while we are reloading the beacon data,
1727 + * otherwise we might be sending out invalid data.
1728 + */
1729 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1730 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1731 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1732 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1733 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1734 +
1735 + /*
1736 + * Write entire beacon with descriptor to register.
1737 + */
1738 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1739 + rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1740 + USB_VENDOR_REQUEST_OUT, beacon_base,
1741 + entry->skb->data, entry->skb->len,
1742 + REGISTER_TIMEOUT32(entry->skb->len));
1743 +
1744 + /*
1745 + * Clean up the beacon skb.
1746 + */
1747 + dev_kfree_skb(entry->skb);
1748 + entry->skb = NULL;
1749 +}
1750 +
1751 +static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
1752 +{
1753 + int length;
1754 +
1755 + /*
1756 + * The length _must_ be a multiple of 4,
1757 + * but it must _not_ be a multiple of the USB packet size.
1758 + */
1759 + length = roundup(entry->skb->len, 4);
1760 + length += (4 * !(length % entry->queue->usb_maxpacket));
1761 +
1762 + return length;
1763 +}
1764 +
1765 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1766 + const enum data_queue_qid queue)
1767 +{
1768 + u32 reg;
1769 +
1770 + if (queue != QID_BEACON) {
1771 + rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1772 + return;
1773 + }
1774 +
1775 + rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1776 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1777 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1778 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1779 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1780 + rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1781 + }
1782 +}
1783 +
1784 +/*
1785 + * RX control handlers
1786 + */
1787 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
1788 + struct rxdone_entry_desc *rxdesc)
1789 +{
1790 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1791 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1792 + __le32 *rxd = (__le32 *)entry->skb->data;
1793 + __le32 *rxwi = (__le32 *)(entry->skb->data + skbdesc->desc_len);
1794 + u32 rxd0;
1795 + u32 rxwi0;
1796 + u32 rxwi1;
1797 + u32 rxwi2;
1798 + u32 rxwi3;
1799 +
1800 + /*
1801 + * Copy descriptor to the skbdesc->desc buffer, making it safe from
1802 + * moving of frame data in rt2x00usb.
1803 + */
1804 + memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1805 + rxd = (__le32 *)skbdesc->desc;
1806 +
1807 + /*
1808 + * It is now safe to read the descriptor on all architectures.
1809 + */
1810 + rt2x00_desc_read(rxd, 0, &rxd0);
1811 + rt2x00_desc_read(rxwi, 0, &rxwi0);
1812 + rt2x00_desc_read(rxwi, 1, &rxwi1);
1813 + rt2x00_desc_read(rxwi, 2, &rxwi2);
1814 + rt2x00_desc_read(rxwi, 3, &rxwi3);
1815 +
1816 + if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
1817 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1818 +
1819 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1820 + /*
1821 + * Unfortunately we don't know the cipher type used during
1822 + * decryption. This prevents us from correct providing
1823 + * correct statistics through debugfs.
1824 + */
1825 + rxdesc->cipher = CIPHER_NONE;
1826 + rxdesc->cipher_status =
1827 + rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
1828 + }
1829 +
1830 + if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
1831 + /*
1832 + * Hardware has stripped IV/EIV data from 802.11 frame during
1833 + * decryption. Unfortunately the descriptor doesn't contain
1834 + * any fields with the EIV/IV data either, so they can't
1835 + * be restored by rt2x00lib.
1836 + */
1837 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1838 +
1839 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1840 + rxdesc->flags |= RX_FLAG_DECRYPTED;
1841 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1842 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1843 + }
1844 +
1845 + if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
1846 + rxdesc->dev_flags |= RXDONE_MY_BSS;
1847 +
1848 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
1849 + rxdesc->flags |= RX_FLAG_SHORT_GI;
1850 +
1851 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
1852 + rxdesc->flags |= RX_FLAG_40MHZ;
1853 +
1854 + switch (rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE)) {
1855 + case RATE_MODE_CCK:
1856 + /*
1857 + * Mask of 0x8 bit to remove the short preamble flag.
1858 + */
1859 + rxdesc->signal =
1860 + (RATE_MODE_CCK << 8) |
1861 + (rt2x00_get_field32(rxwi1, RXWI_W1_MCS) & ~0x8);
1862 + break;
1863 + case RATE_MODE_OFDM:
1864 + rxdesc->signal =
1865 + (RATE_MODE_OFDM << 8) |
1866 + rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1867 + break;
1868 + case RATE_MODE_HT_MIX:
1869 + case RATE_MODE_HT_GREENFIELD:
1870 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1871 + rxdesc->flags |= RX_FLAG_HT;
1872 + break;
1873 + }
1874 +
1875 + rxdesc->rssi =
1876 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
1877 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
1878 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
1879 +
1880 + rxdesc->noise =
1881 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
1882 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
1883 +
1884 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
1885 +
1886 + /*
1887 + * Remove TXWI descriptor from start of buffer.
1888 + */
1889 + skb_pull(entry->skb, TXWI_DESC_SIZE + skbdesc->desc_len);
1890 + skb_trim(entry->skb, rxdesc->size);
1891 +}
1892 +
1893 +/*
1894 + * Device probe functions.
1895 + */
1896 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1897 +{
1898 + u16 word;
1899 + u8 *mac;
1900 + u8 default_lna_gain;
1901 +
1902 + rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1903 +
1904 + /*
1905 + * Start validation of the data that has been read.
1906 + */
1907 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1908 + if (!is_valid_ether_addr(mac)) {
1909 + DECLARE_MAC_BUF(macbuf);
1910 +
1911 + random_ether_addr(mac);
1912 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1913 + }
1914 +
1915 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1916 + if (word == 0xffff) {
1917 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1918 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1919 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1920 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1921 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1922 + }
1923 +
1924 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1925 + if (word != 0) {
1926 + /* NIC configuration must always be 0. */
1927 + word = 0;
1928 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1929 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1930 + }
1931 +
1932 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1933 + if ((word & 0x00ff) == 0x00ff) {
1934 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1935 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1936 + LED_MODE_TXRX_ACTIVITY);
1937 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1938 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1939 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1940 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1941 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1942 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1943 + }
1944 +
1945 + /*
1946 + * During the LNA validation we are going to use
1947 + * lna0 as correct value. Note that EEPROM_LNA
1948 + * is never validated.
1949 + */
1950 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1951 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1952 +
1953 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1954 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1955 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1956 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1957 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1958 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1959 +
1960 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1961 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1962 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1963 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1964 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1965 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1966 + default_lna_gain);
1967 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1968 +
1969 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1970 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1971 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1972 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1973 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1974 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1975 +
1976 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1977 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1978 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1979 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1980 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1981 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1982 + default_lna_gain);
1983 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1984 +
1985 + return 0;
1986 +}
1987 +
1988 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1989 +{
1990 + u32 reg;
1991 + u16 rev;
1992 + u16 value;
1993 + u16 eeprom;
1994 +
1995 + /*
1996 + * Read EEPROM word for configuration.
1997 + */
1998 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1999 +
2000 + /*
2001 + * Identify RF chipset.
2002 + */
2003 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2004 + rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2005 + rev = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2006 + rt2x00_set_chip(rt2x00dev, RT2870, value, rev);
2007 +
2008 + /*
2009 + * The check for rt2860 is not a typo, some rt2870 hardware
2010 + * identifies itself as rt2860 in the CSR register.
2011 + */
2012 + if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2013 + (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870)) {
2014 + ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2015 + return -ENODEV;
2016 + }
2017 +
2018 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2019 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2020 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2021 + !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2022 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2023 + return -ENODEV;
2024 + }
2025 +
2026 + /*
2027 + * Read frequency offset and RF programming sequence.
2028 + */
2029 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2030 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2031 +
2032 + /*
2033 + * Read external LNA informations.
2034 + */
2035 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2036 +
2037 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2038 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2039 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2040 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2041 +
2042 + /*
2043 + * Detect if this device has an hardware controlled radio.
2044 + */
2045 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2046 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2047 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2048 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2049 +
2050 + /*
2051 + * Store led settings, for correct led behaviour.
2052 + */
2053 +#ifdef CONFIG_RT2X00_LIB_LEDS
2054 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2055 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2056 + rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2057 +
2058 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2059 + &rt2x00dev->led_mcu_reg);
2060 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2061 +
2062 + return 0;
2063 +}
2064 +
2065 +/*
2066 + * RF value list for rt2870
2067 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2068 + */
2069 +static const struct rf_channel rf_vals[] = {
2070 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2071 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2072 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2073 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2074 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2075 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2076 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2077 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2078 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2079 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2080 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2081 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2082 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2083 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2084 +
2085 + /* 802.11 UNI / HyperLan 2 */
2086 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2087 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2088 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2089 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2090 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2091 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2092 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2093 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2094 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2095 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2096 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2097 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2098 +
2099 + /* 802.11 HyperLan 2 */
2100 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2101 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2102 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2103 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2104 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2105 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2106 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2107 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2108 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2109 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2110 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2111 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2112 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2113 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2114 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2115 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2116 +
2117 + /* 802.11 UNII */
2118 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2119 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2120 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2121 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2122 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2123 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2124 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2125 +
2126 + /* 802.11 Japan */
2127 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2128 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2129 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2130 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2131 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2132 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2133 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2134 +};
2135 +
2136 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2137 +{
2138 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2139 + struct channel_info *info;
2140 + char *tx_power1;
2141 + char *tx_power2;
2142 + unsigned int i;
2143 +
2144 + /*
2145 + * Initialize all hw fields.
2146 + */
2147 + rt2x00dev->hw->flags =
2148 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2149 + IEEE80211_HW_SIGNAL_DBM;
2150 + rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE + TXINFO_DESC_SIZE;
2151 +
2152 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2153 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2154 + rt2x00_eeprom_addr(rt2x00dev,
2155 + EEPROM_MAC_ADDR_0));
2156 +
2157 + /*
2158 + * Initialize HT information.
2159 + */
2160 + spec->ht.ht_supported = true;
2161 + spec->ht.cap =
2162 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2163 + IEEE80211_HT_CAP_GRN_FLD |
2164 + IEEE80211_HT_CAP_SGI_20 |
2165 + IEEE80211_HT_CAP_SGI_40 |
2166 + IEEE80211_HT_CAP_TX_STBC |
2167 + IEEE80211_HT_CAP_RX_STBC |
2168 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2169 + spec->ht.ampdu_factor = 3;
2170 + spec->ht.ampdu_density = 4;
2171 + spec->ht.mcs.rx_mask[0] = 0xff;
2172 + spec->ht.mcs.rx_mask[1] = 0xff;
2173 + spec->ht.mcs.tx_params =
2174 + IEEE80211_HT_MCS_TX_DEFINED;
2175 +
2176 + /*
2177 + * Initialize hw_mode information.
2178 + */
2179 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2180 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2181 +
2182 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2183 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2184 + spec->num_channels = 14;
2185 + spec->channels = rf_vals;
2186 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2187 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2188 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2189 + spec->num_channels = ARRAY_SIZE(rf_vals);
2190 + spec->channels = rf_vals;
2191 + }
2192 +
2193 + /*
2194 + * Create channel information array
2195 + */
2196 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2197 + if (!info)
2198 + return -ENOMEM;
2199 +
2200 + spec->channels_info = info;
2201 +
2202 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2203 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2204 +
2205 + for (i = 0; i < 14; i++) {
2206 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2207 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2208 + }
2209 +
2210 + if (spec->num_channels > 14) {
2211 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2212 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2213 +
2214 + for (i = 14; i < spec->num_channels; i++) {
2215 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2216 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2217 + }
2218 + }
2219 +
2220 + return 0;
2221 +}
2222 +
2223 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2224 +{
2225 + int retval;
2226 +
2227 + /*
2228 + * Allocate eeprom data.
2229 + */
2230 + retval = rt2800usb_validate_eeprom(rt2x00dev);
2231 + if (retval)
2232 + return retval;
2233 +
2234 + retval = rt2800usb_init_eeprom(rt2x00dev);
2235 + if (retval)
2236 + return retval;
2237 +
2238 + /*
2239 + * Initialize hw specifications.
2240 + */
2241 + retval = rt2800usb_probe_hw_mode(rt2x00dev);
2242 + if (retval)
2243 + return retval;
2244 +
2245 + /*
2246 + * This device requires firmware.
2247 + */
2248 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2249 + __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2250 + if (!modparam_nohwcrypt)
2251 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2252 +
2253 + /*
2254 + * Set the rssi offset.
2255 + */
2256 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2257 +
2258 + return 0;
2259 +}
2260 +
2261 +/*
2262 + * IEEE80211 stack callback functions.
2263 + */
2264 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2265 +{
2266 + struct rt2x00_dev *rt2x00dev = hw->priv;
2267 + u32 reg;
2268 +
2269 + rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2270 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2271 + rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2272 +
2273 + rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2274 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2275 + rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2276 +
2277 + rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2278 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2279 + rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2280 +
2281 + rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2282 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2283 + rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2284 +
2285 + rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2286 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2287 + rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2288 +
2289 + rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2290 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2291 + rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2292 +
2293 + rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2294 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2295 + rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2296 +
2297 + return 0;
2298 +}
2299 +
2300 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2301 + const struct ieee80211_tx_queue_params *params)
2302 +{
2303 + struct rt2x00_dev *rt2x00dev = hw->priv;
2304 + struct data_queue *queue;
2305 + struct rt2x00_field32 field;
2306 + int retval;
2307 + u32 reg;
2308 + u32 offset;
2309 +
2310 + /*
2311 + * First pass the configuration through rt2x00lib, that will
2312 + * update the queue settings and validate the input. After that
2313 + * we are free to update the registers based on the value
2314 + * in the queue parameter.
2315 + */
2316 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2317 + if (retval)
2318 + return retval;
2319 +
2320 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2321 +
2322 + /* Update WMM TXOP register */
2323 + if (queue_idx < 2) {
2324 + field.bit_offset = queue_idx * 16;
2325 + field.bit_mask = 0xffff << field.bit_offset;
2326 +
2327 + rt2x00usb_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2328 + rt2x00_set_field32(&reg, field, queue->txop);
2329 + rt2x00usb_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2330 + } else if (queue_idx < 4) {
2331 + field.bit_offset = (queue_idx - 2) * 16;
2332 + field.bit_mask = 0xffff << field.bit_offset;
2333 +
2334 + rt2x00usb_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2335 + rt2x00_set_field32(&reg, field, queue->txop);
2336 + rt2x00usb_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2337 + }
2338 +
2339 + /* Update WMM registers */
2340 + field.bit_offset = queue_idx * 4;
2341 + field.bit_mask = 0xf << field.bit_offset;
2342 +
2343 + rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2344 + rt2x00_set_field32(&reg, field, queue->aifs);
2345 + rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2346 +
2347 + rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2348 + rt2x00_set_field32(&reg, field, queue->cw_min);
2349 + rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2350 +
2351 + rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2352 + rt2x00_set_field32(&reg, field, queue->cw_max);
2353 + rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2354 +
2355 + /* Update EDCA registers */
2356 + if (queue_idx < 4) {
2357 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2358 +
2359 + rt2x00usb_register_read(rt2x00dev, offset, &reg);
2360 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2361 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2362 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2363 + rt2x00usb_register_write(rt2x00dev, offset, reg);
2364 + }
2365 +
2366 + return 0;
2367 +}
2368 +
2369 +#if 0
2370 +/*
2371 + * Mac80211 demands get_tsf must be atomic.
2372 + * This is not possible for rt2800usb since all register access
2373 + * functions require sleeping. Untill mac80211 no longer needs
2374 + * get_tsf to be atomic, this function should be disabled.
2375 + */
2376 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2377 +{
2378 + struct rt2x00_dev *rt2x00dev = hw->priv;
2379 + u64 tsf;
2380 + u32 reg;
2381 +
2382 + rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2383 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2384 + rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2385 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2386 +
2387 + return tsf;
2388 +}
2389 +#else
2390 +#define rt2800usb_get_tsf NULL
2391 +#endif
2392 +
2393 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2394 + .tx = rt2x00mac_tx,
2395 + .start = rt2x00mac_start,
2396 + .stop = rt2x00mac_stop,
2397 + .add_interface = rt2x00mac_add_interface,
2398 + .remove_interface = rt2x00mac_remove_interface,
2399 + .config = rt2x00mac_config,
2400 + .config_interface = rt2x00mac_config_interface,
2401 + .configure_filter = rt2x00mac_configure_filter,
2402 + .set_key = rt2x00mac_set_key,
2403 + .get_stats = rt2x00mac_get_stats,
2404 + .set_rts_threshold = rt2800usb_set_rts_threshold,
2405 + .bss_info_changed = rt2x00mac_bss_info_changed,
2406 + .conf_tx = rt2800usb_conf_tx,
2407 + .get_tx_stats = rt2x00mac_get_tx_stats,
2408 + .get_tsf = rt2800usb_get_tsf,
2409 +};
2410 +
2411 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2412 + .probe_hw = rt2800usb_probe_hw,
2413 + .get_firmware_name = rt2800usb_get_firmware_name,
2414 + .get_firmware_crc = rt2800usb_get_firmware_crc,
2415 + .load_firmware = rt2800usb_load_firmware,
2416 + .initialize = rt2x00usb_initialize,
2417 + .uninitialize = rt2x00usb_uninitialize,
2418 + .clear_entry = rt2x00usb_clear_entry,
2419 + .set_device_state = rt2800usb_set_device_state,
2420 + .rfkill_poll = rt2800usb_rfkill_poll,
2421 + .link_stats = rt2800usb_link_stats,
2422 + .reset_tuner = rt2800usb_reset_tuner,
2423 + .link_tuner = rt2800usb_link_tuner,
2424 + .write_tx_desc = rt2800usb_write_tx_desc,
2425 + .write_tx_data = rt2x00usb_write_tx_data,
2426 + .write_beacon = rt2800usb_write_beacon,
2427 + .get_tx_data_len = rt2800usb_get_tx_data_len,
2428 + .kick_tx_queue = rt2800usb_kick_tx_queue,
2429 + .fill_rxdone = rt2800usb_fill_rxdone,
2430 + .config_shared_key = rt2800usb_config_shared_key,
2431 + .config_pairwise_key = rt2800usb_config_pairwise_key,
2432 + .config_filter = rt2800usb_config_filter,
2433 + .config_intf = rt2800usb_config_intf,
2434 + .config_erp = rt2800usb_config_erp,
2435 + .config_ant = rt2800usb_config_ant,
2436 + .config = rt2800usb_config,
2437 +};
2438 +
2439 +static const struct data_queue_desc rt2800usb_queue_rx = {
2440 + .entry_num = RX_ENTRIES,
2441 + .data_size = DATA_FRAME_SIZE,
2442 + .desc_size = RXD_DESC_SIZE,
2443 + .priv_size = sizeof(struct queue_entry_priv_usb),
2444 +};
2445 +
2446 +static const struct data_queue_desc rt2800usb_queue_tx = {
2447 + .entry_num = TX_ENTRIES,
2448 + .data_size = DATA_FRAME_SIZE,
2449 + .desc_size = TXD_DESC_SIZE,
2450 + .priv_size = sizeof(struct queue_entry_priv_usb),
2451 +};
2452 +
2453 +static const struct data_queue_desc rt2800usb_queue_bcn = {
2454 + .entry_num = 8 * BEACON_ENTRIES,
2455 + .data_size = MGMT_FRAME_SIZE,
2456 + .desc_size = TXWI_DESC_SIZE,
2457 + .priv_size = sizeof(struct queue_entry_priv_usb),
2458 +};
2459 +
2460 +static const struct rt2x00_ops rt2800usb_ops = {
2461 + .name = KBUILD_MODNAME,
2462 + .max_sta_intf = 1,
2463 + .max_ap_intf = 8,
2464 + .eeprom_size = EEPROM_SIZE,
2465 + .rf_size = RF_SIZE,
2466 + .tx_queues = NUM_TX_QUEUES,
2467 + .rx = &rt2800usb_queue_rx,
2468 + .tx = &rt2800usb_queue_tx,
2469 + .bcn = &rt2800usb_queue_bcn,
2470 + .lib = &rt2800usb_rt2x00_ops,
2471 + .hw = &rt2800usb_mac80211_ops,
2472 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2473 + .debugfs = &rt2800usb_rt2x00debug,
2474 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2475 +};
2476 +
2477 +/*
2478 + * rt2800usb module information.
2479 + */
2480 +static struct usb_device_id rt2800usb_device_table[] = {
2481 + /* Amit */
2482 + { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2483 + /* ASUS */
2484 + { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2485 + { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2486 + { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2487 + /* AzureWave */
2488 + { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2489 + /* Belkin */
2490 + { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2491 + /* Conceptronic */
2492 + { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2493 + { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2494 + { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2495 + { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2496 + { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2497 + { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2498 + /* Corega */
2499 + { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2500 + { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2501 + { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2502 + /* D-Link */
2503 + { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2504 + { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2505 + /* EnGenius */
2506 + { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2507 + { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2508 + /* Gigabyte */
2509 + { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2510 + /* Hawking */
2511 + { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2512 + { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2513 + /* Linksys */
2514 + { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2515 + /* Philips */
2516 + { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2517 + /* Planex */
2518 + { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2519 + /* Ralink */
2520 + { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2521 + { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2522 + /* Siemens */
2523 + { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
2524 + /* Sitecom */
2525 + { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
2526 + { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
2527 + { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
2528 + { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
2529 + /* SMC */
2530 + { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
2531 + { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
2532 + { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
2533 + { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
2534 + /* Sparklan */
2535 + { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
2536 + /* U-Media*/
2537 + { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
2538 + /* ZCOM */
2539 + { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
2540 + { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
2541 + /* Zyxel */
2542 + { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
2543 + { 0, }
2544 +};
2545 +
2546 +MODULE_AUTHOR(DRV_PROJECT);
2547 +MODULE_VERSION(DRV_VERSION);
2548 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
2549 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
2550 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
2551 +MODULE_FIRMWARE(FIRMWARE_RT2870);
2552 +MODULE_LICENSE("GPL");
2553 +
2554 +static struct usb_driver rt2800usb_driver = {
2555 + .name = KBUILD_MODNAME,
2556 + .id_table = rt2800usb_device_table,
2557 + .probe = rt2x00usb_probe,
2558 + .disconnect = rt2x00usb_disconnect,
2559 + .suspend = rt2x00usb_suspend,
2560 + .resume = rt2x00usb_resume,
2561 +};
2562 +
2563 +static int __init rt2800usb_init(void)
2564 +{
2565 + return usb_register(&rt2800usb_driver);
2566 +}
2567 +
2568 +static void __exit rt2800usb_exit(void)
2569 +{
2570 + usb_deregister(&rt2800usb_driver);
2571 +}
2572 +
2573 +module_init(rt2800usb_init);
2574 +module_exit(rt2800usb_exit);
2575 --- /dev/null
2576 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
2577 @@ -0,0 +1,1886 @@
2578 +/*
2579 + Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2580 + <http://rt2x00.serialmonkey.com>
2581 +
2582 + This program is free software; you can redistribute it and/or modify
2583 + it under the terms of the GNU General Public License as published by
2584 + the Free Software Foundation; either version 2 of the License, or
2585 + (at your option) any later version.
2586 +
2587 + This program is distributed in the hope that it will be useful,
2588 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2589 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2590 + GNU General Public License for more details.
2591 +
2592 + You should have received a copy of the GNU General Public License
2593 + along with this program; if not, write to the
2594 + Free Software Foundation, Inc.,
2595 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2596 + */
2597 +
2598 +/*
2599 + Module: rt2800usb
2600 + Abstract: Data structures and registers for the rt2800usb module.
2601 + Supported chipsets: RT2800U.
2602 + */
2603 +
2604 +#ifndef RT2800USB_H
2605 +#define RT2800USB_H
2606 +
2607 +/*
2608 + * RF chip defines.
2609 + *
2610 + * RF2820 2.4G 2T3R
2611 + * RF2850 2.4G/5G 2T3R
2612 + * RF2720 2.4G 1T2R
2613 + * RF2750 2.4G/5G 1T2R
2614 + * RF3020 2.4G 1T1R
2615 + * RF2020 2.4G B/G
2616 + */
2617 +#define RF2820 0x0001
2618 +#define RF2850 0x0002
2619 +#define RF2720 0x0003
2620 +#define RF2750 0x0004
2621 +#define RF3020 0x0005
2622 +#define RF2020 0x0006
2623 +
2624 +/*
2625 + * RT2870 version
2626 + */
2627 +#define RT2870_VERSION_C 0x0100
2628 +#define RT2870_VERSION_D 0x0101
2629 +#define RT2870_VERSION_E 0x0200
2630 +
2631 +/*
2632 + * Signal information.
2633 + * Defaul offset is required for RSSI <-> dBm conversion.
2634 + */
2635 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2636 +
2637 +/*
2638 + * Register layout information.
2639 + */
2640 +#define CSR_REG_BASE 0x1000
2641 +#define CSR_REG_SIZE 0x0800
2642 +#define EEPROM_BASE 0x0000
2643 +#define EEPROM_SIZE 0x0110
2644 +#define BBP_BASE 0x0000
2645 +#define BBP_SIZE 0x0080
2646 +#define RF_BASE 0x0000
2647 +#define RF_SIZE 0x0014
2648 +
2649 +/*
2650 + * Number of TX queues.
2651 + */
2652 +#define NUM_TX_QUEUES 4
2653 +
2654 +/*
2655 + * USB registers.
2656 + */
2657 +
2658 +/*
2659 + * HOST-MCU shared memory
2660 + */
2661 +#define HOST_CMD_CSR 0x0404
2662 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2663 +
2664 +/*
2665 + * INT_SOURCE_CSR: Interrupt source register.
2666 + * Write one to clear corresponding bit.
2667 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2668 + */
2669 +#define INT_SOURCE_CSR 0x0200
2670 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2671 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2672 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2673 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2674 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2675 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2676 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2677 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2678 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2679 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2680 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2681 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2682 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2683 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2684 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2685 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
2686 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
2687 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
2688 +
2689 +/*
2690 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2691 + */
2692 +#define INT_MASK_CSR 0x0204
2693 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
2694 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
2695 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
2696 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2697 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2698 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2699 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2700 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2701 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2702 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
2703 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x40000000)
2704 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x80000000)
2705 +
2706 +/*
2707 + * WPDMA_GLO_CFG
2708 + */
2709 +#define WPDMA_GLO_CFG 0x0208
2710 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
2711 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
2712 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
2713 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
2714 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
2715 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
2716 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
2717 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
2718 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
2719 +
2720 +/*
2721 + * WPDMA_RST_IDX
2722 + */
2723 +#define WPDMA_RST_IDX 0x020c
2724 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
2725 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
2726 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
2727 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
2728 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
2729 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
2730 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
2731 +
2732 +/*
2733 + * DELAY_INT_CFG
2734 + */
2735 +#define DELAY_INT_CFG 0x0210
2736 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
2737 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
2738 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
2739 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
2740 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
2741 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
2742 +
2743 +/*
2744 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2745 + * AIFSN0: AC_BE
2746 + * AIFSN1: AC_BK
2747 + * AIFSN1: AC_VI
2748 + * AIFSN1: AC_VO
2749 + */
2750 +#define WMM_AIFSN_CFG 0x0214
2751 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
2752 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
2753 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
2754 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
2755 +
2756 +/*
2757 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
2758 + * CWMIN0: AC_BE
2759 + * CWMIN1: AC_BK
2760 + * CWMIN1: AC_VI
2761 + * CWMIN1: AC_VO
2762 + */
2763 +#define WMM_CWMIN_CFG 0x0218
2764 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
2765 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
2766 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
2767 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
2768 +
2769 +/*
2770 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
2771 + * CWMAX0: AC_BE
2772 + * CWMAX1: AC_BK
2773 + * CWMAX1: AC_VI
2774 + * CWMAX1: AC_VO
2775 + */
2776 +#define WMM_CWMAX_CFG 0x021c
2777 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
2778 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
2779 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
2780 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
2781 +
2782 +/*
2783 + * AC_TXOP0: AC_BK/AC_BE TXOP register
2784 + * AC0TXOP: AC_BK in unit of 32us
2785 + * AC1TXOP: AC_BE in unit of 32us
2786 + */
2787 +#define WMM_TXOP0_CFG 0x0220
2788 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
2789 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
2790 +
2791 +/*
2792 + * AC_TXOP1: AC_VO/AC_VI TXOP register
2793 + * AC2TXOP: AC_VI in unit of 32us
2794 + * AC3TXOP: AC_VO in unit of 32us
2795 + */
2796 +#define WMM_TXOP1_CFG 0x0224
2797 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
2798 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
2799 +
2800 +/*
2801 + * RINGREG_DIFF
2802 + */
2803 +#define RINGREG_DIFF 0x0010
2804 +
2805 +/*
2806 + * GPIO_CTRL_CFG:
2807 + */
2808 +#define GPIO_CTRL_CFG 0x0228
2809 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
2810 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
2811 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
2812 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
2813 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
2814 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
2815 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
2816 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
2817 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
2818 +
2819 +/*
2820 + * MCU_CMD_CFG
2821 + */
2822 +#define MCU_CMD_CFG 0x022c
2823 +
2824 +/*
2825 + * AC_BK register offsets
2826 + */
2827 +#define TX_BASE_PTR0 0x0230
2828 +#define TX_MAX_CNT0 0x0234
2829 +#define TX_CTX_IDX0 0x0238
2830 +#define TX_DTX_IDX0 0x023c
2831 +
2832 +/*
2833 + * AC_BE register offsets
2834 + */
2835 +#define TX_BASE_PTR1 0x0240
2836 +#define TX_MAX_CNT1 0x0244
2837 +#define TX_CTX_IDX1 0x0248
2838 +#define TX_DTX_IDX1 0x024c
2839 +
2840 +/*
2841 + * AC_VI register offsets
2842 + */
2843 +#define TX_BASE_PTR2 0x0250
2844 +#define TX_MAX_CNT2 0x0254
2845 +#define TX_CTX_IDX2 0x0258
2846 +#define TX_DTX_IDX2 0x025c
2847 +
2848 +/*
2849 + * AC_VO register offsets
2850 + */
2851 +#define TX_BASE_PTR3 0x0260
2852 +#define TX_MAX_CNT3 0x0264
2853 +#define TX_CTX_IDX3 0x0268
2854 +#define TX_DTX_IDX3 0x026c
2855 +
2856 +/*
2857 + * HCCA register offsets
2858 + */
2859 +#define TX_BASE_PTR4 0x0270
2860 +#define TX_MAX_CNT4 0x0274
2861 +#define TX_CTX_IDX4 0x0278
2862 +#define TX_DTX_IDX4 0x027c
2863 +
2864 +/*
2865 + * MGMT register offsets
2866 + */
2867 +#define TX_BASE_PTR5 0x0280
2868 +#define TX_MAX_CNT5 0x0284
2869 +#define TX_CTX_IDX5 0x0288
2870 +#define TX_DTX_IDX5 0x028c
2871 +
2872 +/*
2873 + * RX register offsets
2874 + */
2875 +#define RX_BASE_PTR 0x0290
2876 +#define RX_MAX_CNT 0x0294
2877 +#define RX_CRX_IDX 0x0298
2878 +#define RX_DRX_IDX 0x029c
2879 +
2880 +/*
2881 + * USB_DMA_CFG
2882 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
2883 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
2884 + * PHY_CLEAR: phy watch dog enable.
2885 + * TX_CLEAR: Clear USB DMA TX path.
2886 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
2887 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
2888 + * RX_BULK_EN: Enable USB DMA Rx.
2889 + * TX_BULK_EN: Enable USB DMA Tx.
2890 + * EP_OUT_VALID: OUT endpoint data valid.
2891 + * RX_BUSY: USB DMA RX FSM busy.
2892 + * TX_BUSY: USB DMA TX FSM busy.
2893 + */
2894 +#define USB_DMA_CFG 0x02a0
2895 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
2896 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
2897 +#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
2898 +#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
2899 +#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
2900 +#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
2901 +#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
2902 +#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
2903 +#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
2904 +#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
2905 +#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
2906 +
2907 +/*
2908 + * USB_CYC_CFG
2909 + */
2910 +#define USB_CYC_CFG 0x02a4
2911 +#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
2912 +
2913 +/*
2914 + * PBF_SYS_CTRL
2915 + * HOST_RAM_WRITE: enable Host program ram write selection
2916 + */
2917 +#define PBF_SYS_CTRL 0x0400
2918 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
2919 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
2920 +
2921 +/*
2922 + * PBF registers
2923 + * Most are for debug. Driver doesn't touch PBF register.
2924 + */
2925 +#define PBF_CFG 0x0408
2926 +#define PBF_MAX_PCNT 0x040c
2927 +#define PBF_CTRL 0x0410
2928 +#define PBF_INT_STA 0x0414
2929 +#define PBF_INT_ENA 0x0418
2930 +
2931 +/*
2932 + * BCN_OFFSET0:
2933 + */
2934 +#define BCN_OFFSET0 0x042c
2935 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
2936 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
2937 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
2938 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
2939 +
2940 +/*
2941 + * BCN_OFFSET1:
2942 + */
2943 +#define BCN_OFFSET1 0x0430
2944 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
2945 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
2946 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
2947 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
2948 +
2949 +/*
2950 + * PBF registers
2951 + * Most are for debug. Driver doesn't touch PBF register.
2952 + */
2953 +#define TXRXQ_PCNT 0x0438
2954 +#define PBF_DBG 0x043c
2955 +
2956 +/*
2957 + * MAC Control/Status Registers(CSR).
2958 + * Some values are set in TU, whereas 1 TU == 1024 us.
2959 + */
2960 +
2961 +/*
2962 + * MAC_CSR0: ASIC revision number.
2963 + * ASIC_REV: 0
2964 + * ASIC_VER: 2870
2965 + */
2966 +#define MAC_CSR0 0x1000
2967 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
2968 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
2969 +
2970 +/*
2971 + * MAC_SYS_CTRL:
2972 + */
2973 +#define MAC_SYS_CTRL 0x1004
2974 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
2975 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
2976 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
2977 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
2978 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
2979 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
2980 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
2981 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
2982 +
2983 +/*
2984 + * MAC_ADDR_DW0: STA MAC register 0
2985 + */
2986 +#define MAC_ADDR_DW0 0x1008
2987 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
2988 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
2989 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
2990 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
2991 +
2992 +/*
2993 + * MAC_ADDR_DW1: STA MAC register 1
2994 + * UNICAST_TO_ME_MASK:
2995 + * Used to mask off bits from byte 5 of the MAC address
2996 + * to determine the UNICAST_TO_ME bit for RX frames.
2997 + * The full mask is complemented by BSS_ID_MASK:
2998 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
2999 + */
3000 +#define MAC_ADDR_DW1 0x100c
3001 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3002 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3003 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3004 +
3005 +/*
3006 + * MAC_BSSID_DW0: BSSID register 0
3007 + */
3008 +#define MAC_BSSID_DW0 0x1010
3009 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3010 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3011 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3012 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3013 +
3014 +/*
3015 + * MAC_BSSID_DW1: BSSID register 1
3016 + * BSS_ID_MASK:
3017 + * 0: 1-BSSID mode (BSS index = 0)
3018 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3019 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3020 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3021 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3022 + * BSSID. This will make sure that those bits will be ignored
3023 + * when determining the MY_BSS of RX frames.
3024 + */
3025 +#define MAC_BSSID_DW1 0x1014
3026 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3027 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3028 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3029 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3030 +
3031 +/*
3032 + * MAX_LEN_CFG: Maximum frame length register.
3033 + * MAX_MPDU: rt2860b max 16k bytes
3034 + * MAX_PSDU: Maximum PSDU length
3035 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3036 + */
3037 +#define MAX_LEN_CFG 0x1018
3038 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3039 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3040 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3041 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3042 +
3043 +/*
3044 + * BBP_CSR_CFG: BBP serial control register
3045 + * VALUE: Register value to program into BBP
3046 + * REG_NUM: Selected BBP register
3047 + * READ_CONTROL: 0 write BBP, 1 read BBP
3048 + * BUSY: ASIC is busy executing BBP commands
3049 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3050 + * BBP_RW_MODE: 0 serial, 1 paralell
3051 + */
3052 +#define BBP_CSR_CFG 0x101c
3053 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3054 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3055 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3056 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3057 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3058 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3059 +
3060 +/*
3061 + * RF_CSR_CFG0: RF control register
3062 + * REGID_AND_VALUE: Register value to program into RF
3063 + * BITWIDTH: Selected RF register
3064 + * STANDBYMODE: 0 high when standby, 1 low when standby
3065 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3066 + * BUSY: ASIC is busy executing RF commands
3067 + */
3068 +#define RF_CSR_CFG0 0x1020
3069 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3070 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3071 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3072 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3073 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3074 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3075 +
3076 +/*
3077 + * RF_CSR_CFG1: RF control register
3078 + * REGID_AND_VALUE: Register value to program into RF
3079 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3080 + * 0: 3 system clock cycle (37.5usec)
3081 + * 1: 5 system clock cycle (62.5usec)
3082 + */
3083 +#define RF_CSR_CFG1 0x1024
3084 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3085 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3086 +
3087 +/*
3088 + * RF_CSR_CFG2: RF control register
3089 + * VALUE: Register value to program into RF
3090 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3091 + * 0: 3 system clock cycle (37.5usec)
3092 + * 1: 5 system clock cycle (62.5usec)
3093 + */
3094 +#define RF_CSR_CFG2 0x1028
3095 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3096 +
3097 +/*
3098 + * LED_CFG: LED control
3099 + * color LED's:
3100 + * 0: off
3101 + * 1: blinking upon TX2
3102 + * 2: periodic slow blinking
3103 + * 3: always on
3104 + * LED polarity:
3105 + * 0: active low
3106 + * 1: active high
3107 + */
3108 +#define LED_CFG 0x102c
3109 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3110 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3111 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3112 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3113 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3114 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3115 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3116 +
3117 +/*
3118 + * XIFS_TIME_CFG: MAC timing
3119 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3120 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3121 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3122 + * when MAC doesn't reference BBP signal BBRXEND
3123 + * EIFS: unit 1us
3124 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3125 + *
3126 + */
3127 +#define XIFS_TIME_CFG 0x1100
3128 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3129 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3130 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3131 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3132 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3133 +
3134 +/*
3135 + * BKOFF_SLOT_CFG:
3136 + */
3137 +#define BKOFF_SLOT_CFG 0x1104
3138 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3139 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3140 +
3141 +/*
3142 + * NAV_TIME_CFG:
3143 + */
3144 +#define NAV_TIME_CFG 0x1108
3145 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3146 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3147 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3148 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3149 +
3150 +/*
3151 + * CH_TIME_CFG: count as channel busy
3152 + */
3153 +#define CH_TIME_CFG 0x110c
3154 +
3155 +/*
3156 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3157 + */
3158 +#define PBF_LIFE_TIMER 0x1110
3159 +
3160 +/*
3161 + * BCN_TIME_CFG:
3162 + * BEACON_INTERVAL: in unit of 1/16 TU
3163 + * TSF_TICKING: Enable TSF auto counting
3164 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3165 + * BEACON_GEN: Enable beacon generator
3166 + */
3167 +#define BCN_TIME_CFG 0x1114
3168 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3169 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3170 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3171 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3172 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3173 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3174 +
3175 +/*
3176 + * TBTT_SYNC_CFG:
3177 + */
3178 +#define TBTT_SYNC_CFG 0x1118
3179 +
3180 +/*
3181 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3182 + */
3183 +#define TSF_TIMER_DW0 0x111c
3184 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3185 +
3186 +/*
3187 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3188 + */
3189 +#define TSF_TIMER_DW1 0x1120
3190 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3191 +
3192 +/*
3193 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3194 + */
3195 +#define TBTT_TIMER 0x1124
3196 +
3197 +/*
3198 + * INT_TIMER_CFG:
3199 + */
3200 +#define INT_TIMER_CFG 0x1128
3201 +
3202 +/*
3203 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3204 + */
3205 +#define INT_TIMER_EN 0x112c
3206 +
3207 +/*
3208 + * CH_IDLE_STA: channel idle time
3209 + */
3210 +#define CH_IDLE_STA 0x1130
3211 +
3212 +/*
3213 + * CH_BUSY_STA: channel busy time
3214 + */
3215 +#define CH_BUSY_STA 0x1134
3216 +
3217 +/*
3218 + * MAC_STATUS_CFG:
3219 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3220 + * if 1 or higher one of the 2 registers is busy.
3221 + */
3222 +#define MAC_STATUS_CFG 0x1200
3223 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3224 +
3225 +/*
3226 + * PWR_PIN_CFG:
3227 + */
3228 +#define PWR_PIN_CFG 0x1204
3229 +
3230 +/*
3231 + * AUTOWAKEUP_CFG: Manual power control / status register
3232 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3233 + * AUTOWAKE: 0:sleep, 1:awake
3234 + */
3235 +#define AUTOWAKEUP_CFG 0x1208
3236 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3237 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3238 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3239 +
3240 +/*
3241 + * EDCA_AC0_CFG:
3242 + */
3243 +#define EDCA_AC0_CFG 0x1300
3244 +#define EDCA_AC0_CFG_AC_TX_OP FIELD32(0x000000ff)
3245 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3246 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3247 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3248 +
3249 +/*
3250 + * EDCA_AC1_CFG:
3251 + */
3252 +#define EDCA_AC1_CFG 0x1304
3253 +#define EDCA_AC1_CFG_AC_TX_OP FIELD32(0x000000ff)
3254 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3255 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3256 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3257 +
3258 +/*
3259 + * EDCA_AC2_CFG:
3260 + */
3261 +#define EDCA_AC2_CFG 0x1308
3262 +#define EDCA_AC2_CFG_AC_TX_OP FIELD32(0x000000ff)
3263 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3264 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3265 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3266 +
3267 +/*
3268 + * EDCA_AC3_CFG:
3269 + */
3270 +#define EDCA_AC3_CFG 0x130c
3271 +#define EDCA_AC3_CFG_AC_TX_OP FIELD32(0x000000ff)
3272 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3273 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3274 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3275 +
3276 +/*
3277 + * EDCA_TID_AC_MAP:
3278 + */
3279 +#define EDCA_TID_AC_MAP 0x1310
3280 +
3281 +/*
3282 + * TX_PWR_CFG_0:
3283 + */
3284 +#define TX_PWR_CFG_0 0x1314
3285 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3286 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3287 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3288 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3289 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3290 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3291 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3292 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3293 +
3294 +/*
3295 + * TX_PWR_CFG_1:
3296 + */
3297 +#define TX_PWR_CFG_1 0x1318
3298 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3299 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3300 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3301 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3302 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3303 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3304 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3305 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3306 +
3307 +/*
3308 + * TX_PWR_CFG_2:
3309 + */
3310 +#define TX_PWR_CFG_2 0x131c
3311 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3312 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3313 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3314 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3315 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3316 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3317 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3318 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3319 +
3320 +/*
3321 + * TX_PWR_CFG_3:
3322 + */
3323 +#define TX_PWR_CFG_3 0x1320
3324 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3325 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3326 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3327 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3328 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3329 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3330 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3331 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3332 +
3333 +/*
3334 + * TX_PWR_CFG_4:
3335 + */
3336 +#define TX_PWR_CFG_4 0x1324
3337 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3338 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3339 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3340 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3341 +
3342 +/*
3343 + * TX_PIN_CFG:
3344 + */
3345 +#define TX_PIN_CFG 0x1328
3346 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3347 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3348 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3349 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3350 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3351 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3352 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3353 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3354 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3355 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3356 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3357 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3358 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3359 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3360 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3361 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3362 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3363 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3364 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3365 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3366 +
3367 +/*
3368 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3369 + */
3370 +#define TX_BAND_CFG 0x132c
3371 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3372 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3373 +
3374 +/*
3375 + * TX_SW_CFG0:
3376 + */
3377 +#define TX_SW_CFG0 0x1330
3378 +
3379 +/*
3380 + * TX_SW_CFG1:
3381 + */
3382 +#define TX_SW_CFG1 0x1334
3383 +
3384 +/*
3385 + * TX_SW_CFG2:
3386 + */
3387 +#define TX_SW_CFG2 0x1338
3388 +
3389 +/*
3390 + * TXOP_THRES_CFG:
3391 + */
3392 +#define TXOP_THRES_CFG 0x133c
3393 +
3394 +/*
3395 + * TXOP_CTRL_CFG:
3396 + */
3397 +#define TXOP_CTRL_CFG 0x1340
3398 +
3399 +/*
3400 + * TX_RTS_CFG:
3401 + * RTS_THRES: unit:byte
3402 + * RTS_FBK_EN: enable rts rate fallback
3403 + */
3404 +#define TX_RTS_CFG 0x1344
3405 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3406 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3407 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3408 +
3409 +/*
3410 + * TX_TIMEOUT_CFG:
3411 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3412 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3413 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3414 + * it is recommended that:
3415 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3416 + */
3417 +#define TX_TIMEOUT_CFG 0x1348
3418 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3419 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3420 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3421 +
3422 +/*
3423 + * TX_RTY_CFG:
3424 + * SHORT_RTY_LIMIT: short retry limit
3425 + * LONG_RTY_LIMIT: long retry limit
3426 + * LONG_RTY_THRE: Long retry threshoold
3427 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3428 + * 0:expired by retry limit, 1: expired by mpdu life timer
3429 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3430 + * 0:expired by retry limit, 1: expired by mpdu life timer
3431 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3432 + */
3433 +#define TX_RTY_CFG 0x134c
3434 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3435 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3436 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3437 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3438 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3439 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3440 +
3441 +/*
3442 + * TX_LINK_CFG:
3443 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3444 + * MFB_ENABLE: TX apply remote MFB 1:enable
3445 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3446 + * 0: not apply remote remote unsolicit (MFS=7)
3447 + * TX_MRQ_EN: MCS request TX enable
3448 + * TX_RDG_EN: RDG TX enable
3449 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3450 + * REMOTE_MFB: remote MCS feedback
3451 + * REMOTE_MFS: remote MCS feedback sequence number
3452 + */
3453 +#define TX_LINK_CFG 0x1350
3454 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3455 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3456 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3457 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3458 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3459 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3460 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3461 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3462 +
3463 +/*
3464 + * HT_FBK_CFG0:
3465 + */
3466 +#define HT_FBK_CFG0 0x1354
3467 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3468 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3469 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3470 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3471 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3472 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3473 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3474 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3475 +
3476 +/*
3477 + * HT_FBK_CFG1:
3478 + */
3479 +#define HT_FBK_CFG1 0x1358
3480 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3481 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3482 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3483 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3484 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3485 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3486 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3487 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3488 +
3489 +/*
3490 + * LG_FBK_CFG0:
3491 + */
3492 +#define LG_FBK_CFG0 0x135c
3493 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3494 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3495 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3496 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3497 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3498 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3499 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3500 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3501 +
3502 +/*
3503 + * LG_FBK_CFG1:
3504 + */
3505 +#define LG_FBK_CFG1 0x1360
3506 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3507 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3508 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3509 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3510 +
3511 +/*
3512 + * CCK_PROT_CFG: CCK Protection
3513 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3514 + * PROTECT_CTRL: Protection control frame type for CCK TX
3515 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3516 + * PROTECT_NAV: TXOP protection type for CCK TX
3517 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3518 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3519 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3520 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3521 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3522 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3523 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3524 + * RTS_TH_EN: RTS threshold enable on CCK TX
3525 + */
3526 +#define CCK_PROT_CFG 0x1364
3527 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3528 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3529 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3530 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3531 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3532 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3533 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3534 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3535 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3536 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3537 +
3538 +/*
3539 + * OFDM_PROT_CFG: OFDM Protection
3540 + */
3541 +#define OFDM_PROT_CFG 0x1368
3542 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3543 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3544 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3545 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3546 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3547 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3548 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3549 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3550 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3551 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3552 +
3553 +/*
3554 + * MM20_PROT_CFG: MM20 Protection
3555 + */
3556 +#define MM20_PROT_CFG 0x136c
3557 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3558 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3559 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3560 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3561 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3562 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3563 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3564 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3565 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3566 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3567 +
3568 +/*
3569 + * MM40_PROT_CFG: MM40 Protection
3570 + */
3571 +#define MM40_PROT_CFG 0x1370
3572 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3573 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3574 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3575 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3576 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3577 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3578 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3579 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3580 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3581 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3582 +
3583 +/*
3584 + * GF20_PROT_CFG: GF20 Protection
3585 + */
3586 +#define GF20_PROT_CFG 0x1374
3587 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3588 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3589 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3590 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3591 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3592 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3593 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3594 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3595 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3596 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3597 +
3598 +/*
3599 + * GF40_PROT_CFG: GF40 Protection
3600 + */
3601 +#define GF40_PROT_CFG 0x1378
3602 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3603 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3604 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3605 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3606 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3607 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3608 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3609 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3610 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3611 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3612 +
3613 +/*
3614 + * EXP_CTS_TIME:
3615 + */
3616 +#define EXP_CTS_TIME 0x137c
3617 +
3618 +/*
3619 + * EXP_ACK_TIME:
3620 + */
3621 +#define EXP_ACK_TIME 0x1380
3622 +
3623 +/*
3624 + * RX_FILTER_CFG: RX configuration register.
3625 + */
3626 +#define RX_FILTER_CFG 0x1400
3627 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
3628 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
3629 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
3630 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3631 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
3632 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
3633 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
3634 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
3635 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
3636 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
3637 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
3638 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
3639 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
3640 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
3641 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
3642 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
3643 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
3644 +
3645 +/*
3646 + * AUTO_RSP_CFG:
3647 + * AUTORESPONDER: 0: disable, 1: enable
3648 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3649 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3650 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3651 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3652 + * DUAL_CTS_EN: Power bit value in control frame
3653 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3654 + */
3655 +#define AUTO_RSP_CFG 0x1404
3656 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
3657 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
3658 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
3659 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
3660 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
3661 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
3662 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
3663 +
3664 +/*
3665 + * LEGACY_BASIC_RATE:
3666 + */
3667 +#define LEGACY_BASIC_RATE 0x1408
3668 +
3669 +/*
3670 + * HT_BASIC_RATE:
3671 + */
3672 +#define HT_BASIC_RATE 0x140c
3673 +
3674 +/*
3675 + * HT_CTRL_CFG:
3676 + */
3677 +#define HT_CTRL_CFG 0x1410
3678 +
3679 +/*
3680 + * SIFS_COST_CFG:
3681 + */
3682 +#define SIFS_COST_CFG 0x1414
3683 +
3684 +/*
3685 + * RX_PARSER_CFG:
3686 + * Set NAV for all received frames
3687 + */
3688 +#define RX_PARSER_CFG 0x1418
3689 +
3690 +/*
3691 + * TX_SEC_CNT0:
3692 + */
3693 +#define TX_SEC_CNT0 0x1500
3694 +
3695 +/*
3696 + * RX_SEC_CNT0:
3697 + */
3698 +#define RX_SEC_CNT0 0x1504
3699 +
3700 +/*
3701 + * CCMP_FC_MUTE:
3702 + */
3703 +#define CCMP_FC_MUTE 0x1508
3704 +
3705 +/*
3706 + * TXOP_HLDR_ADDR0:
3707 + */
3708 +#define TXOP_HLDR_ADDR0 0x1600
3709 +
3710 +/*
3711 + * TXOP_HLDR_ADDR1:
3712 + */
3713 +#define TXOP_HLDR_ADDR1 0x1604
3714 +
3715 +/*
3716 + * TXOP_HLDR_ET:
3717 + */
3718 +#define TXOP_HLDR_ET 0x1608
3719 +
3720 +/*
3721 + * QOS_CFPOLL_RA_DW0:
3722 + */
3723 +#define QOS_CFPOLL_RA_DW0 0x160c
3724 +
3725 +/*
3726 + * QOS_CFPOLL_RA_DW1:
3727 + */
3728 +#define QOS_CFPOLL_RA_DW1 0x1610
3729 +
3730 +/*
3731 + * QOS_CFPOLL_QC:
3732 + */
3733 +#define QOS_CFPOLL_QC 0x1614
3734 +
3735 +/*
3736 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3737 + */
3738 +#define RX_STA_CNT0 0x1700
3739 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
3740 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
3741 +
3742 +/*
3743 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3744 + */
3745 +#define RX_STA_CNT1 0x1704
3746 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
3747 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
3748 +
3749 +/*
3750 + * RX_STA_CNT2:
3751 + */
3752 +#define RX_STA_CNT2 0x1708
3753 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
3754 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
3755 +
3756 +/*
3757 + * TX_STA_CNT0: TX Beacon count
3758 + */
3759 +#define TX_STA_CNT0 0x170c
3760 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
3761 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
3762 +
3763 +/*
3764 + * TX_STA_CNT1: TX tx count
3765 + */
3766 +#define TX_STA_CNT1 0x1710
3767 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
3768 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
3769 +
3770 +/*
3771 + * TX_STA_CNT2: TX tx count
3772 + */
3773 +#define TX_STA_CNT2 0x1714
3774 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
3775 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
3776 +
3777 +/*
3778 + * TX_STA_FIFO: TX Result for specific PID status fifo register
3779 + */
3780 +#define TX_STA_FIFO 0x1718
3781 +#define TX_STA_FIFO_B_VALID FIELD32(0x00000001)
3782 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
3783 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
3784 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
3785 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
3786 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
3787 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
3788 +
3789 +/*
3790 + * TX_AGG_CNT: Debug counter
3791 + */
3792 +#define TX_AGG_CNT 0x171c
3793 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
3794 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
3795 +
3796 +/*
3797 + * TX_AGG_CNT0:
3798 + */
3799 +#define TX_AGG_CNT0 0x1720
3800 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
3801 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
3802 +
3803 +/*
3804 + * TX_AGG_CNT1:
3805 + */
3806 +#define TX_AGG_CNT1 0x1724
3807 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
3808 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
3809 +
3810 +/*
3811 + * TX_AGG_CNT2:
3812 + */
3813 +#define TX_AGG_CNT2 0x1728
3814 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
3815 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
3816 +
3817 +/*
3818 + * TX_AGG_CNT3:
3819 + */
3820 +#define TX_AGG_CNT3 0x172c
3821 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
3822 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
3823 +
3824 +/*
3825 + * TX_AGG_CNT4:
3826 + */
3827 +#define TX_AGG_CNT4 0x1730
3828 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
3829 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
3830 +
3831 +/*
3832 + * TX_AGG_CNT5:
3833 + */
3834 +#define TX_AGG_CNT5 0x1734
3835 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
3836 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
3837 +
3838 +/*
3839 + * TX_AGG_CNT6:
3840 + */
3841 +#define TX_AGG_CNT6 0x1738
3842 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
3843 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
3844 +
3845 +/*
3846 + * TX_AGG_CNT7:
3847 + */
3848 +#define TX_AGG_CNT7 0x173c
3849 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
3850 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
3851 +
3852 +/*
3853 + * MPDU_DENSITY_CNT:
3854 + * TX_ZERO_DEL: TX zero length delimiter count
3855 + * RX_ZERO_DEL: RX zero length delimiter count
3856 + */
3857 +#define MPDU_DENSITY_CNT 0x1740
3858 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
3859 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
3860 +
3861 +/*
3862 + * Security key table memory, base address = 0x1800
3863 + */
3864 +struct hw_pairwise_ta_entry {
3865 + u8 address[6];
3866 + u8 reserved[2];
3867 +} __attribute__ ((packed));
3868 +
3869 +struct wcid_entry {
3870 + u8 rx_ba_bitmat7;
3871 + u8 rx_ba_bitmat0;
3872 + u8 mac[6];
3873 +} __attribute__ ((packed));
3874 +
3875 +struct hw_key_entry {
3876 + u8 key[16];
3877 + u8 tx_mic[8];
3878 + u8 rx_mic[8];
3879 +} __attribute__ ((packed));
3880 +
3881 +/*
3882 + * Security key table memory.
3883 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
3884 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
3885 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
3886 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
3887 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
3888 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
3889 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
3890 + */
3891 +#define MAC_WCID_BASE 0x1800
3892 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
3893 +#define PAIRWISE_IVEIV_TABLE_BASE 0x6000
3894 +#define MAC_IVEIV_TABLE_BASE 0x6000
3895 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
3896 +#define SHARED_KEY_TABLE_BASE 0x6c00
3897 +#define SHARED_KEY_MODE_BASE 0x7000
3898 +
3899 +#define SHARED_KEY_ENTRY(__idx) \
3900 + ( SHARED_KEY_TABLE_BASE + \
3901 + ((__idx) * sizeof(struct hw_key_entry)) )
3902 +#define SHARED_KEY_MODE_ENTRY(__idx) \
3903 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
3904 +#define PAIRWISE_KEY_ENTRY(__idx) \
3905 + ( PAIRWISE_KEY_TABLE_BASE + \
3906 + ((__idx) * sizeof(struct hw_key_entry)) )
3907 +
3908 +#define MAC_WCID_ENTRY(__idx) \
3909 + ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
3910 +#define MAC_WCID_ATTR_ENTRY(__idx) \
3911 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
3912 +
3913 +/*
3914 + * MAC_WCID_ATTRIBUTE:
3915 + * KEYTAB: 0: shared key table, 1: pairwise key table
3916 + * BSS_IDX: multipleBSS index for the WCID
3917 + */
3918 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
3919 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE FIELD32(0x0000000e)
3920 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
3921 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
3922 +
3923 +/*
3924 + * SHARED_KEY_MODE:
3925 + */
3926 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
3927 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
3928 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
3929 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
3930 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
3931 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
3932 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
3933 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
3934 +
3935 +/*
3936 + * HOST-MCU communication
3937 + */
3938 +
3939 +/*
3940 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
3941 + */
3942 +#define H2M_MAILBOX_CSR 0x7010
3943 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
3944 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
3945 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
3946 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
3947 +
3948 +/*
3949 + * H2M_MAILBOX_CID:
3950 + */
3951 +#define H2M_MAILBOX_CID 0x7014
3952 +
3953 +/*
3954 + * H2M_MAILBOX_STATUS:
3955 + */
3956 +#define H2M_MAILBOX_STATUS 0x701c
3957 +
3958 +/*
3959 + * H2M_INT_SRC:
3960 + */
3961 +#define H2M_INT_SRC 0x7024
3962 +
3963 +/*
3964 + * H2M_BBP_AGENT:
3965 + */
3966 +#define H2M_BBP_AGENT 0x7028
3967 +
3968 +/*
3969 + * MCU_LEDCS: LED control for MCU Mailbox.
3970 + */
3971 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
3972 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
3973 +
3974 +/*
3975 + * HW_CS_CTS_BASE:
3976 + * Carrier-sense CTS frame base address.
3977 + * It's where mac stores carrier-sense frame for carrier-sense function.
3978 + */
3979 +#define HW_CS_CTS_BASE 0x7700
3980 +
3981 +/*
3982 + * HW_DFS_CTS_BASE:
3983 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
3984 + */
3985 +#define HW_DFS_CTS_BASE 0x7780
3986 +
3987 +/*
3988 + * TXRX control registers - base address 0x3000
3989 + */
3990 +
3991 +/*
3992 + * TXRX_CSR1:
3993 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
3994 + */
3995 +#define TXRX_CSR1 0x77d0
3996 +
3997 +/*
3998 + * HW_DEBUG_SETTING_BASE:
3999 + * since NULL frame won't be that long (256 byte)
4000 + * We steal 16 tail bytes to save debugging settings
4001 + */
4002 +#define HW_DEBUG_SETTING_BASE 0x77f0
4003 +#define HW_DEBUG_SETTING_BASE2 0x7770
4004 +
4005 +/*
4006 + * HW_BEACON_BASE
4007 + * In order to support maximum 8 MBSS and its maximum length
4008 + * is 512 bytes for each beacon
4009 + * Three section discontinue memory segments will be used.
4010 + * 1. The original region for BCN 0~3
4011 + * 2. Extract memory from FCE table for BCN 4~5
4012 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4013 + * It occupied those memory of wcid 238~253 for BCN 6
4014 + * and wcid 222~237 for BCN 7
4015 + *
4016 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4017 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4018 + */
4019 +#define HW_BEACON_BASE0 0x7800
4020 +#define HW_BEACON_BASE1 0x7a00
4021 +#define HW_BEACON_BASE2 0x7c00
4022 +#define HW_BEACON_BASE3 0x7e00
4023 +#define HW_BEACON_BASE4 0x7200
4024 +#define HW_BEACON_BASE5 0x7400
4025 +#define HW_BEACON_BASE6 0x5dc0
4026 +#define HW_BEACON_BASE7 0x5bc0
4027 +
4028 +#define HW_BEACON_OFFSET(__index) \
4029 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4030 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4031 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4032 +
4033 +/*
4034 + * 8051 firmware image.
4035 + */
4036 +#define FIRMWARE_RT2870 "rt2870.bin"
4037 +#define FIRMWARE_IMAGE_BASE 0x3000
4038 +
4039 +/*
4040 + * BBP registers.
4041 + * The wordsize of the BBP is 8 bits.
4042 + */
4043 +
4044 +/*
4045 + * BBP 1: TX Antenna
4046 + */
4047 +#define BBP1_TX_POWER FIELD8(0x07)
4048 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4049 +
4050 +/*
4051 + * BBP 3: RX Antenna
4052 + */
4053 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4054 +
4055 +/*
4056 + * RF registers
4057 + */
4058 +
4059 +/*
4060 + * RF 2
4061 + */
4062 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4063 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4064 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4065 +
4066 +/*
4067 + * RF 3
4068 + */
4069 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4070 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4071 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4072 +
4073 +/*
4074 + * RF 4
4075 + */
4076 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4077 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4078 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4079 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4080 +#define RF4_BW40 FIELD32(0x00200000)
4081 +
4082 +/*
4083 + * EEPROM content.
4084 + * The wordsize of the EEPROM is 16 bits.
4085 + */
4086 +
4087 +/*
4088 + * EEPROM Version
4089 + */
4090 +#define EEPROM_VERSION 0x0001
4091 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4092 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4093 +
4094 +/*
4095 + * HW MAC address.
4096 + */
4097 +#define EEPROM_MAC_ADDR_0 0x0002
4098 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4099 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4100 +#define EEPROM_MAC_ADDR1 0x0003
4101 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4102 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4103 +#define EEPROM_MAC_ADDR_2 0x0004
4104 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4105 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4106 +
4107 +/*
4108 + * EEPROM ANTENNA config
4109 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4110 + * TXPATH: 1: 1T, 2: 2T
4111 + */
4112 +#define EEPROM_ANTENNA 0x001a
4113 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4114 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4115 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4116 +
4117 +/*
4118 + * EEPROM NIC config
4119 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4120 + */
4121 +#define EEPROM_NIC 0x001b
4122 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4123 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4124 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4125 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4126 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4127 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4128 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4129 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4130 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4131 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4132 +
4133 +/*
4134 + * EEPROM frequency
4135 + */
4136 +#define EEPROM_FREQ 0x001d
4137 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4138 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4139 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4140 +
4141 +/*
4142 + * EEPROM LED
4143 + * POLARITY_RDY_G: Polarity RDY_G setting.
4144 + * POLARITY_RDY_A: Polarity RDY_A setting.
4145 + * POLARITY_ACT: Polarity ACT setting.
4146 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4147 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4148 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4149 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4150 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4151 + * LED_MODE: Led mode.
4152 + */
4153 +#define EEPROM_LED1 0x001e
4154 +#define EEPROM_LED2 0x001f
4155 +#define EEPROM_LED3 0x0020
4156 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4157 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4158 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4159 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4160 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4161 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4162 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4163 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4164 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4165 +
4166 +/*
4167 + * EEPROM LNA
4168 + */
4169 +#define EEPROM_LNA 0x0022
4170 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4171 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4172 +
4173 +/*
4174 + * EEPROM RSSI BG offset
4175 + */
4176 +#define EEPROM_RSSI_BG 0x0023
4177 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4178 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4179 +
4180 +/*
4181 + * EEPROM RSSI BG2 offset
4182 + */
4183 +#define EEPROM_RSSI_BG2 0x0024
4184 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4185 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4186 +
4187 +/*
4188 + * EEPROM RSSI A offset
4189 + */
4190 +#define EEPROM_RSSI_A 0x0025
4191 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4192 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4193 +
4194 +/*
4195 + * EEPROM RSSI A2 offset
4196 + */
4197 +#define EEPROM_RSSI_A2 0x0026
4198 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4199 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4200 +
4201 +/*
4202 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4203 + * This is delta in 40MHZ.
4204 + * VALUE: Tx Power dalta value (MAX=4)
4205 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4206 + * TXPOWER: Enable:
4207 + */
4208 +#define EEPROM_TXPOWER_DELTA 0x0028
4209 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4210 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4211 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4212 +
4213 +/*
4214 + * EEPROM TXPOWER 802.11BG
4215 + */
4216 +#define EEPROM_TXPOWER_BG1 0x0029
4217 +#define EEPROM_TXPOWER_BG2 0x0030
4218 +#define EEPROM_TXPOWER_BG_SIZE 7
4219 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4220 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4221 +
4222 +/*
4223 + * EEPROM TXPOWER 802.11A
4224 + */
4225 +#define EEPROM_TXPOWER_A1 0x003c
4226 +#define EEPROM_TXPOWER_A2 0x0053
4227 +#define EEPROM_TXPOWER_A_SIZE 6
4228 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4229 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4230 +
4231 +/*
4232 + * EEPROM TXpower byrate: 20MHZ power
4233 + */
4234 +#define EEPROM_TXPOWER_BYRATE 0x006f
4235 +
4236 +/*
4237 + * EEPROM BBP.
4238 + */
4239 +#define EEPROM_BBP_START 0x0078
4240 +#define EEPROM_BBP_SIZE 16
4241 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4242 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4243 +
4244 +/*
4245 + * MCU mailbox commands.
4246 + */
4247 +#define MCU_SLEEP 0x30
4248 +#define MCU_WAKEUP 0x31
4249 +#define MCU_LED 0x50
4250 +#define MCU_LED_STRENGTH 0x51
4251 +#define MCU_LED_1 0x52
4252 +#define MCU_LED_2 0x53
4253 +#define MCU_LED_3 0x54
4254 +#define MCU_RADAR 0x60
4255 +#define MCU_BOOT_SIGNAL 0x72
4256 +
4257 +/*
4258 + * DMA descriptor defines.
4259 + */
4260 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4261 +#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
4262 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4263 +#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
4264 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4265 +
4266 +/*
4267 + * TX descriptor format for TX, PRIO and Beacon Ring.
4268 + */
4269 +
4270 +/*
4271 + * Word0
4272 + */
4273 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4274 +
4275 +/*
4276 + * Word1
4277 + */
4278 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4279 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4280 +#define TXD_W1_BURST FIELD32(0x00008000)
4281 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4282 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4283 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4284 +
4285 +/*
4286 + * Word2
4287 + */
4288 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4289 +
4290 +/*
4291 + * Word3
4292 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4293 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4294 + * 0:MGMT, 1:HCCA 2:EDCA
4295 + */
4296 +#define TXD_W3_WIV FIELD32(0x01000000)
4297 +#define TXD_W3_QSEL FIELD32(0x06000000)
4298 +#define TXD_W3_TCO FIELD32(0x20000000)
4299 +#define TXD_W3_UCO FIELD32(0x40000000)
4300 +#define TXD_W3_ICO FIELD32(0x80000000)
4301 +
4302 +/*
4303 + * TX Info structure
4304 + */
4305 +
4306 +/*
4307 + * Word0
4308 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4309 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4310 + * 0:MGMT, 1:HCCA 2:EDCA
4311 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
4312 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
4313 + * Force USB DMA transmit frame from current selected endpoint
4314 + */
4315 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
4316 +#define TXINFO_W0_WIV FIELD32(0x01000000)
4317 +#define TXINFO_W0_QSEL FIELD32(0x06000000)
4318 +#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
4319 +#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
4320 +
4321 +/*
4322 + * TX WI structure
4323 + */
4324 +
4325 +/*
4326 + * Word0
4327 + * FRAG: 1 To inform TKIP engine this is a fragment.
4328 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4329 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4330 + * BW: Channel bandwidth 20MHz or 40 MHz
4331 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4332 + */
4333 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4334 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4335 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4336 +#define TXWI_W0_TS FIELD32(0x00000008)
4337 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4338 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4339 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4340 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4341 +#define TXWI_W0_BW FIELD32(0x00800000)
4342 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4343 +#define TXWI_W0_STBC FIELD32(0x06000000)
4344 +#define TXWI_W0_IFS FIELD32(0x08000000)
4345 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4346 +
4347 +/*
4348 + * Word1
4349 + */
4350 +#define TXWI_W1_ACK FIELD32(0x00000001)
4351 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4352 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4353 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4354 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4355 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4356 +
4357 +/*
4358 + * Word2
4359 + */
4360 +#define TXWI_W2_IV FIELD32(0xffffffff)
4361 +
4362 +/*
4363 + * Word3
4364 + */
4365 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4366 +
4367 +/*
4368 + * RX descriptor format for RX Ring.
4369 + */
4370 +
4371 +/*
4372 + * Word0
4373 + * UNICAST_TO_ME: This RX frame is unicast to me.
4374 + * MULTICAST: This is a multicast frame.
4375 + * BROADCAST: This is a broadcast frame.
4376 + * MY_BSS: this frame belongs to the same BSSID.
4377 + * CRC_ERROR: CRC error.
4378 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
4379 + * AMSDU: rx with 802.3 header, not 802.11 header.
4380 + */
4381 +
4382 +#define RXD_W0_BA FIELD32(0x00000001)
4383 +#define RXD_W0_DATA FIELD32(0x00000002)
4384 +#define RXD_W0_NULLDATA FIELD32(0x00000004)
4385 +#define RXD_W0_FRAG FIELD32(0x00000008)
4386 +#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
4387 +#define RXD_W0_MULTICAST FIELD32(0x00000020)
4388 +#define RXD_W0_BROADCAST FIELD32(0x00000040)
4389 +#define RXD_W0_MY_BSS FIELD32(0x00000080)
4390 +#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
4391 +#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
4392 +#define RXD_W0_AMSDU FIELD32(0x00000800)
4393 +#define RXD_W0_HTC FIELD32(0x00001000)
4394 +#define RXD_W0_RSSI FIELD32(0x00002000)
4395 +#define RXD_W0_L2PAD FIELD32(0x00004000)
4396 +#define RXD_W0_AMPDU FIELD32(0x00008000)
4397 +#define RXD_W0_DECRYPTED FIELD32(0x00010000)
4398 +#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
4399 +#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
4400 +#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
4401 +#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
4402 +
4403 +/*
4404 + * RX WI structure
4405 + */
4406 +
4407 +/*
4408 + * Word0
4409 + */
4410 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4411 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4412 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4413 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4414 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4415 +#define RXWI_W0_TID FIELD32(0xf0000000)
4416 +
4417 +/*
4418 + * Word1
4419 + */
4420 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4421 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4422 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4423 +#define RXWI_W1_BW FIELD32(0x00800000)
4424 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4425 +#define RXWI_W1_STBC FIELD32(0x06000000)
4426 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4427 +
4428 +/*
4429 + * Word2
4430 + */
4431 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4432 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4433 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4434 +
4435 +/*
4436 + * Word3
4437 + */
4438 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4439 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4440 +
4441 +/*
4442 + * Macro's for converting txpower from EEPROM to mac80211 value
4443 + * and from mac80211 value to register value.
4444 + */
4445 +#define MIN_G_TXPOWER 0
4446 +#define MIN_A_TXPOWER -7
4447 +#define MAX_G_TXPOWER 31
4448 +#define MAX_A_TXPOWER 15
4449 +#define DEFAULT_TXPOWER 5
4450 +
4451 +#define TXPOWER_G_FROM_DEV(__txpower) \
4452 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4453 +
4454 +#define TXPOWER_G_TO_DEV(__txpower) \
4455 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4456 +
4457 +#define TXPOWER_A_FROM_DEV(__txpower) \
4458 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4459 +
4460 +#define TXPOWER_A_TO_DEV(__txpower) \
4461 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4462 +
4463 +#endif /* RT2800USB_H */
4464 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4465 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4466 @@ -142,6 +142,7 @@ struct rt2x00_chip {
4467 #define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
4468 #define RT2890 0x0701 /* 2.4GHz PCIe */
4469 #define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
4470 +#define RT2870 0x1600
4471
4472 u16 rf;
4473 u32 rev;
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