1 From 39c2811d18b39991f49c16dcd9ed1a81200371ad Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Mon, 5 Jan 2009 11:01:09 +0100
4 Subject: [PATCH v2 05/11] ath9k: move PCI code into separate file
6 Now that we have converted all bus specific routines to replaceable, we
7 can move the PCI specific codes into a separate file.
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
12 drivers/net/wireless/ath9k/Makefile | 1 +
13 drivers/net/wireless/ath9k/core.h | 19 ++-
14 drivers/net/wireless/ath9k/main.c | 300 +++--------------------------------
15 drivers/net/wireless/ath9k/pci.c | 287 +++++++++++++++++++++++++++++++++
16 4 files changed, 328 insertions(+), 279 deletions(-)
18 --- a/drivers/net/wireless/ath9k/Makefile
19 +++ b/drivers/net/wireless/ath9k/Makefile
20 @@ -11,6 +11,7 @@ ath9k-y += hw.o \
24 +ath9k-$(CONFIG_PCI) += pci.o
25 ath9k-$(CONFIG_ATH9K_DEBUG) += debug.o
27 obj-$(CONFIG_ATH9K) += ath9k.o
28 --- a/drivers/net/wireless/ath9k/core.h
29 +++ b/drivers/net/wireless/ath9k/core.h
33 #include <linux/etherdevice.h>
34 -#include <linux/pci.h>
35 +#include <linux/device.h>
36 #include <net/mac80211.h>
37 #include <linux/leds.h>
38 #include <linux/rfkill.h>
39 @@ -767,4 +767,21 @@ static inline void ath_bus_cleanup(struc
40 sc->bus_ops->cleanup(sc);
43 +extern struct ieee80211_ops ath9k_ops;
45 +irqreturn_t ath_isr(int irq, void *dev);
46 +void ath_cleanup(struct ath_softc *sc);
47 +int ath_attach(u16 devid, struct ath_softc *sc);
48 +void ath_detach(struct ath_softc *sc);
49 +const char *ath_mac_bb_name(u32 mac_bb_version);
50 +const char *ath_rf_name(u16 rf_version);
53 +int ath_pci_init(void);
54 +void ath_pci_exit(void);
56 +static inline int ath_pci_init(void) { return 0; };
57 +static inline void ath_pci_exit(void) {};
61 --- a/drivers/net/wireless/ath9k/main.c
62 +++ b/drivers/net/wireless/ath9k/main.c
63 @@ -28,39 +28,6 @@ MODULE_DESCRIPTION("Support for Atheros
64 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
65 MODULE_LICENSE("Dual BSD/GPL");
67 -static struct pci_device_id ath_pci_id_table[] __devinitdata = {
68 - { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
69 - { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
70 - { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
71 - { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
72 - { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
73 - { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
77 -static void ath_detach(struct ath_softc *sc);
78 -static void ath_cleanup(struct ath_softc *sc);
80 -/* return bus cachesize in 4B word units */
82 -static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
86 - pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
91 - * This check was put in to avoid "unplesant" consequences if
92 - * the bootrom has not fully initialized all PCI devices.
93 - * Sometimes the cache line size register is not set
97 - *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
100 static void ath_cache_conf_rate(struct ath_softc *sc,
101 struct ieee80211_conf *conf)
103 @@ -498,7 +465,7 @@ static void ath9k_tasklet(unsigned long
104 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
107 -static irqreturn_t ath_isr(int irq, void *dev)
108 +irqreturn_t ath_isr(int irq, void *dev)
110 struct ath_softc *sc = dev;
111 struct ath_hal *ah = sc->sc_ah;
112 @@ -1279,7 +1246,7 @@ static int ath_start_rfkill_poll(struct
114 #endif /* CONFIG_RFKILL */
116 -static void ath_cleanup(struct ath_softc *sc)
117 +void ath_cleanup(struct ath_softc *sc)
120 free_irq(sc->irq, sc);
121 @@ -1287,7 +1254,7 @@ static void ath_cleanup(struct ath_softc
122 ieee80211_free_hw(sc->hw);
125 -static void ath_detach(struct ath_softc *sc)
126 +void ath_detach(struct ath_softc *sc)
128 struct ieee80211_hw *hw = sc->hw;
130 @@ -1538,7 +1505,7 @@ bad:
134 -static int ath_attach(u16 devid, struct ath_softc *sc)
135 +int ath_attach(u16 devid, struct ath_softc *sc)
137 struct ieee80211_hw *hw = sc->hw;
139 @@ -2457,7 +2424,7 @@ static int ath9k_ampdu_action(struct iee
143 -static struct ieee80211_ops ath9k_ops = {
144 +struct ieee80211_ops ath9k_ops = {
146 .start = ath9k_start,
148 @@ -2501,7 +2468,7 @@ static struct {
150 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
154 ath_mac_bb_name(u32 mac_bb_version)
157 @@ -2518,7 +2485,7 @@ ath_mac_bb_name(u32 mac_bb_version)
159 * Return the RF name. "????" is returned if the RF is unknown.
163 ath_rf_name(u16 rf_version)
166 @@ -2532,234 +2499,7 @@ ath_rf_name(u16 rf_version)
170 -static void ath_pci_cleanup(struct ath_softc *sc)
172 - struct pci_dev *pdev = to_pci_dev(sc->dev);
174 - pci_iounmap(pdev, sc->mem);
175 - pci_release_region(pdev, 0);
176 - pci_disable_device(pdev);
179 -static struct ath_bus_ops ath_pci_bus_ops = {
180 - .read_cachesize = ath_pci_read_cachesize,
181 - .cleanup = ath_pci_cleanup,
184 -static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
187 - struct ath_softc *sc;
188 - struct ieee80211_hw *hw;
192 - struct ath_hal *ah;
194 - if (pci_enable_device(pdev))
197 - ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
200 - printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
204 - ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
207 - printk(KERN_ERR "ath9k: 32-bit DMA consistent "
208 - "DMA enable failed\n");
213 - * Cache line size is used to size and align various
214 - * structures used to communicate with the hardware.
216 - pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
219 - * Linux 2.4.18 (at least) writes the cache line size
220 - * register as a 16-bit wide register which is wrong.
221 - * We must have this setup properly for rx buffer
222 - * DMA to work so force a reasonable value here if it
225 - csz = L1_CACHE_BYTES / sizeof(u32);
226 - pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
229 - * The default setting of latency timer yields poor results,
230 - * set it to the value used by other systems. It may be worth
231 - * tweaking this setting more.
233 - pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
235 - pci_set_master(pdev);
238 - * Disable the RETRY_TIMEOUT register (0x41) to keep
239 - * PCI Tx retries from interfering with C3 CPU state.
241 - pci_read_config_dword(pdev, 0x40, &val);
242 - if ((val & 0x0000ff00) != 0)
243 - pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
245 - ret = pci_request_region(pdev, 0, "ath9k");
247 - dev_err(&pdev->dev, "PCI memory region reserve error\n");
252 - mem = pci_iomap(pdev, 0, 0);
254 - printk(KERN_ERR "PCI memory map error\n") ;
259 - hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
261 - printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
265 - SET_IEEE80211_DEV(hw, &pdev->dev);
266 - pci_set_drvdata(pdev, hw);
270 - sc->dev = &pdev->dev;
272 - sc->bus_ops = &ath_pci_bus_ops;
274 - if (ath_attach(id->device, sc) != 0) {
279 - /* setup interrupt service routine */
281 - if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
282 - printk(KERN_ERR "%s: request_irq failed\n",
283 - wiphy_name(hw->wiphy));
288 - sc->irq = pdev->irq;
292 - "%s: Atheros AR%s MAC/BB Rev:%x "
293 - "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
294 - wiphy_name(hw->wiphy),
295 - ath_mac_bb_name(ah->ah_macVersion),
297 - ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
299 - (unsigned long)mem, pdev->irq);
305 - ieee80211_free_hw(hw);
307 - pci_iounmap(pdev, mem);
309 - pci_release_region(pdev, 0);
311 - pci_disable_device(pdev);
315 -static void ath_pci_remove(struct pci_dev *pdev)
317 - struct ieee80211_hw *hw = pci_get_drvdata(pdev);
318 - struct ath_softc *sc = hw->priv;
325 -static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
327 - struct ieee80211_hw *hw = pci_get_drvdata(pdev);
328 - struct ath_softc *sc = hw->priv;
330 - ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
332 -#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
333 - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
334 - cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
337 - pci_save_state(pdev);
338 - pci_disable_device(pdev);
339 - pci_set_power_state(pdev, 3);
344 -static int ath_pci_resume(struct pci_dev *pdev)
346 - struct ieee80211_hw *hw = pci_get_drvdata(pdev);
347 - struct ath_softc *sc = hw->priv;
351 - err = pci_enable_device(pdev);
354 - pci_restore_state(pdev);
356 - * Suspend/Resume resets the PCI configuration space, so we have to
357 - * re-disable the RETRY_TIMEOUT register (0x41) to keep
358 - * PCI Tx retries from interfering with C3 CPU state
360 - pci_read_config_dword(pdev, 0x40, &val);
361 - if ((val & 0x0000ff00) != 0)
362 - pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
365 - ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
366 - AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
367 - ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
369 -#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
371 - * check the h/w rfkill state on resume
372 - * and start the rfkill poll timer
374 - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
375 - queue_delayed_work(sc->hw->workqueue,
376 - &sc->rf_kill.rfkill_poll, 0);
382 -#endif /* CONFIG_PM */
384 -MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
386 -static struct pci_driver ath_pci_driver = {
388 - .id_table = ath_pci_id_table,
389 - .probe = ath_pci_probe,
390 - .remove = ath_pci_remove,
392 - .suspend = ath_pci_suspend,
393 - .resume = ath_pci_resume,
394 -#endif /* CONFIG_PM */
397 -static int __init init_ath_pci(void)
398 +static int __init ath9k_init(void)
402 @@ -2771,26 +2511,30 @@ static int __init init_ath_pci(void)
404 "Unable to register rate control algorithm: %d\n",
406 - ath_rate_control_unregister();
411 - if (pci_register_driver(&ath_pci_driver) < 0) {
412 + error = ath_pci_init();
415 "ath_pci: No devices found, driver not installed.\n");
416 - ath_rate_control_unregister();
417 - pci_unregister_driver(&ath_pci_driver);
420 + goto err_rate_unregister;
425 + err_rate_unregister:
426 + ath_rate_control_unregister();
430 -module_init(init_ath_pci);
431 +module_init(ath9k_init);
433 -static void __exit exit_ath_pci(void)
434 +static void __exit ath9k_exit(void)
437 ath_rate_control_unregister();
438 - pci_unregister_driver(&ath_pci_driver);
439 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
441 -module_exit(exit_ath_pci);
442 +module_exit(ath9k_exit);
444 +++ b/drivers/net/wireless/ath9k/pci.c
447 + * Copyright (c) 2008 Atheros Communications Inc.
449 + * Permission to use, copy, modify, and/or distribute this software for any
450 + * purpose with or without fee is hereby granted, provided that the above
451 + * copyright notice and this permission notice appear in all copies.
453 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
454 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
455 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
456 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
457 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
458 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
459 + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
462 +#include <linux/nl80211.h>
463 +#include <linux/pci.h>
468 +static struct pci_device_id ath_pci_id_table[] __devinitdata = {
469 + { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
470 + { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
471 + { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
472 + { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
473 + { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
474 + { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
478 +/* return bus cachesize in 4B word units */
479 +static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
483 + pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
488 + * This check was put in to avoid "unplesant" consequences if
489 + * the bootrom has not fully initialized all PCI devices.
490 + * Sometimes the cache line size register is not set
494 + *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
497 +static void ath_pci_cleanup(struct ath_softc *sc)
499 + struct pci_dev *pdev = to_pci_dev(sc->dev);
501 + pci_iounmap(pdev, sc->mem);
502 + pci_release_region(pdev, 0);
503 + pci_disable_device(pdev);
506 +static struct ath_bus_ops ath_pci_bus_ops = {
507 + .read_cachesize = ath_pci_read_cachesize,
508 + .cleanup = ath_pci_cleanup,
511 +static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
514 + struct ath_softc *sc;
515 + struct ieee80211_hw *hw;
519 + struct ath_hal *ah;
521 + if (pci_enable_device(pdev))
524 + ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
527 + printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
531 + ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
534 + printk(KERN_ERR "ath9k: 32-bit DMA consistent "
535 + "DMA enable failed\n");
540 + * Cache line size is used to size and align various
541 + * structures used to communicate with the hardware.
543 + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
546 + * Linux 2.4.18 (at least) writes the cache line size
547 + * register as a 16-bit wide register which is wrong.
548 + * We must have this setup properly for rx buffer
549 + * DMA to work so force a reasonable value here if it
552 + csz = L1_CACHE_BYTES / sizeof(u32);
553 + pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
556 + * The default setting of latency timer yields poor results,
557 + * set it to the value used by other systems. It may be worth
558 + * tweaking this setting more.
560 + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
562 + pci_set_master(pdev);
565 + * Disable the RETRY_TIMEOUT register (0x41) to keep
566 + * PCI Tx retries from interfering with C3 CPU state.
568 + pci_read_config_dword(pdev, 0x40, &val);
569 + if ((val & 0x0000ff00) != 0)
570 + pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
572 + ret = pci_request_region(pdev, 0, "ath9k");
574 + dev_err(&pdev->dev, "PCI memory region reserve error\n");
579 + mem = pci_iomap(pdev, 0, 0);
581 + printk(KERN_ERR "PCI memory map error\n") ;
586 + hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
588 + printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
592 + SET_IEEE80211_DEV(hw, &pdev->dev);
593 + pci_set_drvdata(pdev, hw);
597 + sc->dev = &pdev->dev;
599 + sc->bus_ops = &ath_pci_bus_ops;
601 + if (ath_attach(id->device, sc) != 0) {
606 + /* setup interrupt service routine */
608 + if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
609 + printk(KERN_ERR "%s: request_irq failed\n",
610 + wiphy_name(hw->wiphy));
615 + sc->irq = pdev->irq;
619 + "%s: Atheros AR%s MAC/BB Rev:%x "
620 + "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
621 + wiphy_name(hw->wiphy),
622 + ath_mac_bb_name(ah->ah_macVersion),
624 + ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
626 + (unsigned long)mem, pdev->irq);
632 + ieee80211_free_hw(hw);
634 + pci_iounmap(pdev, mem);
636 + pci_release_region(pdev, 0);
638 + pci_disable_device(pdev);
642 +static void ath_pci_remove(struct pci_dev *pdev)
644 + struct ieee80211_hw *hw = pci_get_drvdata(pdev);
645 + struct ath_softc *sc = hw->priv;
652 +static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
654 + struct ieee80211_hw *hw = pci_get_drvdata(pdev);
655 + struct ath_softc *sc = hw->priv;
657 + ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
659 +#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
660 + if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
661 + cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
664 + pci_save_state(pdev);
665 + pci_disable_device(pdev);
666 + pci_set_power_state(pdev, 3);
671 +static int ath_pci_resume(struct pci_dev *pdev)
673 + struct ieee80211_hw *hw = pci_get_drvdata(pdev);
674 + struct ath_softc *sc = hw->priv;
678 + err = pci_enable_device(pdev);
681 + pci_restore_state(pdev);
683 + * Suspend/Resume resets the PCI configuration space, so we have to
684 + * re-disable the RETRY_TIMEOUT register (0x41) to keep
685 + * PCI Tx retries from interfering with C3 CPU state
687 + pci_read_config_dword(pdev, 0x40, &val);
688 + if ((val & 0x0000ff00) != 0)
689 + pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
692 + ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
693 + AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
694 + ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
696 +#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
698 + * check the h/w rfkill state on resume
699 + * and start the rfkill poll timer
701 + if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
702 + queue_delayed_work(sc->hw->workqueue,
703 + &sc->rf_kill.rfkill_poll, 0);
709 +#endif /* CONFIG_PM */
711 +MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
713 +static struct pci_driver ath_pci_driver = {
715 + .id_table = ath_pci_id_table,
716 + .probe = ath_pci_probe,
717 + .remove = ath_pci_remove,
719 + .suspend = ath_pci_suspend,
720 + .resume = ath_pci_resume,
721 +#endif /* CONFIG_PM */
724 +int __init ath_pci_init(void)
726 + return pci_register_driver(&ath_pci_driver);
729 +void ath_pci_exit(void)
731 + pci_unregister_driver(&ath_pci_driver);