1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_core.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
24 #define IFX_ATM_VER_MAJOR 1
25 #define IFX_ATM_VER_MID 0
26 #define IFX_ATM_VER_MINOR 26
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/version.h>
31 #include <linux/types.h>
32 #include <linux/errno.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/ioctl.h>
36 #include <linux/atmdev.h>
37 #include <linux/platform_device.h>
38 #include <linux/of_device.h>
39 #include <linux/atm.h>
40 #include <linux/clk.h>
41 #include <linux/interrupt.h>
46 #include <lantiq_soc.h>
48 #include "ifxmips_atm_core.h"
50 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
51 #define MODULE_PARM(a, b) module_param(a, int, 0)
54 \brief QSB cell delay variation due to concurrency
56 static int qsb_tau
= 1; /* QSB cell delay variation due to concurrency */
58 \brief QSB scheduler burst length
60 static int qsb_srvm
= 0x0F; /* QSB scheduler burst length */
62 \brief QSB time step, all legal values are 1, 2, 4
64 static int qsb_tstep
= 4 ; /* QSB time step, all legal values are 1, 2, 4 */
67 \brief Write descriptor delay
69 static int write_descriptor_delay
= 0x20; /* Write descriptor delay */
72 \brief AAL5 padding byte ('~')
74 static int aal5_fill_pattern
= 0x007E; /* AAL5 padding byte ('~') */
76 \brief Max frame size for RX
78 static int aal5r_max_packet_size
= 0x0700; /* Max frame size for RX */
80 \brief Min frame size for RX
82 static int aal5r_min_packet_size
= 0x0000; /* Min frame size for RX */
84 \brief Max frame size for TX
86 static int aal5s_max_packet_size
= 0x0700; /* Max frame size for TX */
88 \brief Min frame size for TX
90 static int aal5s_min_packet_size
= 0x0000; /* Min frame size for TX */
92 \brief Drop error packet in RX path
94 static int aal5r_drop_error_packet
= 1; /* Drop error packet in RX path */
97 \brief Number of descriptors per DMA RX channel
99 static int dma_rx_descriptor_length
= 128; /* Number of descriptors per DMA RX channel */
101 \brief Number of descriptors per DMA TX channel
103 static int dma_tx_descriptor_length
= 64; /* Number of descriptors per DMA TX channel */
105 \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
107 static int dma_rx_clp1_descriptor_threshold
= 38;
110 MODULE_PARM(qsb_tau
, "i");
111 MODULE_PARM_DESC(qsb_tau
, "Cell delay variation. Value must be > 0");
112 MODULE_PARM(qsb_srvm
, "i");
113 MODULE_PARM_DESC(qsb_srvm
, "Maximum burst size");
114 MODULE_PARM(qsb_tstep
, "i");
115 MODULE_PARM_DESC(qsb_tstep
, "n*32 cycles per sbs cycles n=1,2,4");
117 MODULE_PARM(write_descriptor_delay
, "i");
118 MODULE_PARM_DESC(write_descriptor_delay
, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
120 MODULE_PARM(aal5_fill_pattern
, "i");
121 MODULE_PARM_DESC(aal5_fill_pattern
, "Filling pattern (PAD) for AAL5 frames");
122 MODULE_PARM(aal5r_max_packet_size
, "i");
123 MODULE_PARM_DESC(aal5r_max_packet_size
, "Max packet size in byte for downstream AAL5 frames");
124 MODULE_PARM(aal5r_min_packet_size
, "i");
125 MODULE_PARM_DESC(aal5r_min_packet_size
, "Min packet size in byte for downstream AAL5 frames");
126 MODULE_PARM(aal5s_max_packet_size
, "i");
127 MODULE_PARM_DESC(aal5s_max_packet_size
, "Max packet size in byte for upstream AAL5 frames");
128 MODULE_PARM(aal5s_min_packet_size
, "i");
129 MODULE_PARM_DESC(aal5s_min_packet_size
, "Min packet size in byte for upstream AAL5 frames");
130 MODULE_PARM(aal5r_drop_error_packet
, "i");
131 MODULE_PARM_DESC(aal5r_drop_error_packet
, "Non-zero value to drop error packet for downstream");
133 MODULE_PARM(dma_rx_descriptor_length
, "i");
134 MODULE_PARM_DESC(dma_rx_descriptor_length
, "Number of descriptor assigned to DMA RX channel (>16)");
135 MODULE_PARM(dma_tx_descriptor_length
, "i");
136 MODULE_PARM_DESC(dma_tx_descriptor_length
, "Number of descriptor assigned to DMA TX channel (>16)");
137 MODULE_PARM(dma_rx_clp1_descriptor_threshold
, "i");
138 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold
, "Descriptor threshold for cells with cell loss priority 1");
143 * ####################################
145 * ####################################
148 #ifdef CONFIG_AMAZON_SE
149 #define ENABLE_LESS_CACHE_INV 1
150 #define LESS_CACHE_INV_LEN 96
153 #define DUMP_SKB_LEN ~0
158 * ####################################
160 * ####################################
166 static int ppe_ioctl(struct atm_dev
*, unsigned int, void *);
167 static int ppe_open(struct atm_vcc
*);
168 static void ppe_close(struct atm_vcc
*);
169 static int ppe_send(struct atm_vcc
*, struct sk_buff
*);
170 static int ppe_send_oam(struct atm_vcc
*, void *, int);
171 static int ppe_change_qos(struct atm_vcc
*, struct atm_qos
*, int);
176 static inline void adsl_led_flash(void);
179 * 64-bit operation used by MIB calculation
181 static inline void u64_add_u32(ppe_u64_t
, unsigned int, ppe_u64_t
*);
184 * buffer manage functions
186 static inline struct sk_buff
* alloc_skb_rx(void);
187 static inline struct sk_buff
* alloc_skb_tx(unsigned int);
188 struct sk_buff
* atm_alloc_tx(struct atm_vcc
*, unsigned int);
189 static inline void atm_free_tx_skb_vcc(struct sk_buff
*, struct atm_vcc
*);
190 static inline struct sk_buff
*get_skb_rx_pointer(unsigned int);
191 static inline int get_tx_desc(unsigned int);
192 static struct sk_buff
* skb_duplicate(struct sk_buff
*);
193 static struct sk_buff
* skb_break_away_from_protocol(struct sk_buff
*);
196 * mailbox handler and signal function
198 static inline void mailbox_oam_rx_handler(void);
199 static inline void mailbox_aal_rx_handler(void);
200 static irqreturn_t
mailbox_irq_handler(int, void *);
201 static inline void mailbox_signal(unsigned int, int);
202 static void do_ppe_tasklet(unsigned long);
203 DECLARE_TASKLET(g_dma_tasklet
, do_ppe_tasklet
, 0);
206 * QSB & HTU setting functions
208 static void set_qsb(struct atm_vcc
*, struct atm_qos
*, unsigned int);
209 static void qsb_global_set(void);
210 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
211 static inline void clear_htu_entry(unsigned int);
212 static void validate_oam_htu_entry(void);
213 static void invalidate_oam_htu_entry(void);
216 * look up for connection ID
218 static inline int find_vpi(unsigned int);
219 static inline int find_vpivci(unsigned int, unsigned int);
220 static inline int find_vcc(struct atm_vcc
*);
222 static inline int ifx_atm_version(const struct ltq_atm_ops
*ops
, char *);
225 * Init & clean-up functions
227 static inline void check_parameters(void);
228 static inline int init_priv_data(void);
229 static inline void clear_priv_data(void);
230 static inline void init_rx_tables(void);
231 static inline void init_tx_tables(void);
236 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
237 extern void ifx_push_oam(unsigned char *);
239 static inline void ifx_push_oam(unsigned char *dummy
) {}
242 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
243 extern int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
);
244 extern int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *);
246 extern int (*ifx_mei_atm_showtime_exit
)(void);
247 extern int ifx_mei_atm_led_blink(void);
249 static inline int ifx_mei_atm_led_blink(void) { return 0; }
250 static inline int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
)
252 if ( is_showtime
!= NULL
)
256 int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *) = NULL
;
257 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter
);
259 int (*ifx_mei_atm_showtime_exit
)(void) = NULL
;
260 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit
);
264 static struct sk_buff
* (*ifx_atm_alloc_tx
)(struct atm_vcc
*, unsigned int) = NULL
;
266 static struct atm_priv_data g_atm_priv_data
;
268 static struct atmdev_ops g_ifx_atm_ops
= {
273 .send_oam
= ppe_send_oam
,
274 .change_qos
= ppe_change_qos
,
275 .owner
= THIS_MODULE
,
278 static int g_showtime
= 0;
279 static void *g_xdata_addr
= NULL
;
281 static int ppe_ioctl(struct atm_dev
*dev
, unsigned int cmd
, void *arg
)
284 atm_cell_ifEntry_t mib_cell
;
285 atm_aal5_ifEntry_t mib_aal5
;
286 atm_aal5_vcc_x_t mib_vcc
;
290 if ( _IOC_TYPE(cmd
) != PPE_ATM_IOC_MAGIC
291 || _IOC_NR(cmd
) >= PPE_ATM_IOC_MAXNR
)
294 if ( _IOC_DIR(cmd
) & _IOC_READ
)
295 ret
= !access_ok(VERIFY_WRITE
, arg
, _IOC_SIZE(cmd
));
296 else if ( _IOC_DIR(cmd
) & _IOC_WRITE
)
297 ret
= !access_ok(VERIFY_READ
, arg
, _IOC_SIZE(cmd
));
302 case PPE_ATM_MIB_CELL
: /* cell level MIB */
303 /* These MIB should be read at ARC side, now put zero only. */
304 mib_cell
.ifHCInOctets_h
= 0;
305 mib_cell
.ifHCInOctets_l
= 0;
306 mib_cell
.ifHCOutOctets_h
= 0;
307 mib_cell
.ifHCOutOctets_l
= 0;
308 mib_cell
.ifInErrors
= 0;
309 mib_cell
.ifInUnknownProtos
= WAN_MIB_TABLE
->wrx_drophtu_cell
;
310 mib_cell
.ifOutErrors
= 0;
312 ret
= sizeof(mib_cell
) - copy_to_user(arg
, &mib_cell
, sizeof(mib_cell
));
315 case PPE_ATM_MIB_AAL5
: /* AAL5 MIB */
316 value
= WAN_MIB_TABLE
->wrx_total_byte
;
317 u64_add_u32(g_atm_priv_data
.wrx_total_byte
, value
- g_atm_priv_data
.prev_wrx_total_byte
, &g_atm_priv_data
.wrx_total_byte
);
318 g_atm_priv_data
.prev_wrx_total_byte
= value
;
319 mib_aal5
.ifHCInOctets_h
= g_atm_priv_data
.wrx_total_byte
.h
;
320 mib_aal5
.ifHCInOctets_l
= g_atm_priv_data
.wrx_total_byte
.l
;
322 value
= WAN_MIB_TABLE
->wtx_total_byte
;
323 u64_add_u32(g_atm_priv_data
.wtx_total_byte
, value
- g_atm_priv_data
.prev_wtx_total_byte
, &g_atm_priv_data
.wtx_total_byte
);
324 g_atm_priv_data
.prev_wtx_total_byte
= value
;
325 mib_aal5
.ifHCOutOctets_h
= g_atm_priv_data
.wtx_total_byte
.h
;
326 mib_aal5
.ifHCOutOctets_l
= g_atm_priv_data
.wtx_total_byte
.l
;
328 mib_aal5
.ifInUcastPkts
= g_atm_priv_data
.wrx_pdu
;
329 mib_aal5
.ifOutUcastPkts
= WAN_MIB_TABLE
->wtx_total_pdu
;
330 mib_aal5
.ifInErrors
= WAN_MIB_TABLE
->wrx_err_pdu
;
331 mib_aal5
.ifInDiscards
= WAN_MIB_TABLE
->wrx_dropdes_pdu
+ g_atm_priv_data
.wrx_drop_pdu
;
332 mib_aal5
.ifOutErros
= g_atm_priv_data
.wtx_err_pdu
;
333 mib_aal5
.ifOutDiscards
= g_atm_priv_data
.wtx_drop_pdu
;
335 ret
= sizeof(mib_aal5
) - copy_to_user(arg
, &mib_aal5
, sizeof(mib_aal5
));
338 case PPE_ATM_MIB_VCC
: /* VCC related MIB */
339 copy_from_user(&mib_vcc
, arg
, sizeof(mib_vcc
));
340 conn
= find_vpivci(mib_vcc
.vpi
, mib_vcc
.vci
);
342 mib_vcc
.mib_vcc
.aal5VccCrcErrors
= g_atm_priv_data
.conn
[conn
].aal5_vcc_crc_err
;
343 mib_vcc
.mib_vcc
.aal5VccOverSizedSDUs
= g_atm_priv_data
.conn
[conn
].aal5_vcc_oversize_sdu
;
344 mib_vcc
.mib_vcc
.aal5VccSarTimeOuts
= 0; /* no timer support */
345 ret
= sizeof(mib_vcc
) - copy_to_user(arg
, &mib_vcc
, sizeof(mib_vcc
));
357 static int ppe_open(struct atm_vcc
*vcc
)
360 short vpi
= vcc
->vpi
;
362 struct port
*port
= &g_atm_priv_data
.port
[(int)vcc
->dev
->dev_data
];
364 int f_enable_irq
= 0;
366 if ( vcc
->qos
.aal
!= ATM_AAL5
&& vcc
->qos
.aal
!= ATM_AAL0
)
367 return -EPROTONOSUPPORT
;
369 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
370 /* check bandwidth */
371 if ( (vcc
->qos
.txtp
.traffic_class
== ATM_CBR
&& vcc
->qos
.txtp
.max_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
372 || (vcc
->qos
.txtp
.traffic_class
== ATM_VBR_RT
&& vcc
->qos
.txtp
.max_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
373 || (vcc
->qos
.txtp
.traffic_class
== ATM_VBR_NRT
&& vcc
->qos
.txtp
.scr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
))
374 || (vcc
->qos
.txtp
.traffic_class
== ATM_UBR_PLUS
&& vcc
->qos
.txtp
.min_pcr
> (port
->tx_max_cell_rate
- port
->tx_current_cell_rate
)) )
381 /* check existing vpi,vci */
382 conn
= find_vpivci(vpi
, vci
);
388 /* check whether it need to enable irq */
389 if ( g_atm_priv_data
.conn_table
== 0 )
392 /* allocate connection */
393 for ( conn
= 0; conn
< MAX_PVC_NUMBER
; conn
++ ) {
394 if ( test_and_set_bit(conn
, &g_atm_priv_data
.conn_table
) == 0 ) {
395 g_atm_priv_data
.conn
[conn
].vcc
= vcc
;
399 if ( conn
== MAX_PVC_NUMBER
) {
404 /* reserve bandwidth */
405 switch ( vcc
->qos
.txtp
.traffic_class
) {
408 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.max_pcr
;
411 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.scr
;
414 port
->tx_current_cell_rate
+= vcc
->qos
.txtp
.min_pcr
;
419 set_qsb(vcc
, &vcc
->qos
, conn
);
421 /* update atm_vcc structure */
422 vcc
->itf
= (int)vcc
->dev
->dev_data
;
425 set_bit(ATM_VF_READY
, &vcc
->flags
);
428 if ( f_enable_irq
) {
429 ifx_atm_alloc_tx
= atm_alloc_tx
;
431 *MBOX_IGU1_ISRC
= (1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
);
432 *MBOX_IGU1_IER
= (1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
);
434 enable_irq(PPE_MAILBOX_IGU1_INT
);
438 WTX_QUEUE_CONFIG(conn
+ FIRST_QSB_QID
)->sbid
= (int)vcc
->dev
->dev_data
;
441 set_htu_entry(vpi
, vci
, conn
, vcc
->qos
.aal
== ATM_AAL5
? 1 : 0, 0);
449 static void ppe_close(struct atm_vcc
*vcc
)
453 struct connection
*connection
;
457 /* get connection id */
458 conn
= find_vcc(vcc
);
460 pr_err("can't find vcc\n");
463 connection
= &g_atm_priv_data
.conn
[conn
];
464 port
= &g_atm_priv_data
.port
[connection
->port
];
467 clear_htu_entry(conn
);
469 /* release connection */
470 connection
->vcc
= NULL
;
471 connection
->aal5_vcc_crc_err
= 0;
472 connection
->aal5_vcc_oversize_sdu
= 0;
473 clear_bit(conn
, &g_atm_priv_data
.conn_table
);
476 if ( g_atm_priv_data
.conn_table
== 0 ) {
477 disable_irq(PPE_MAILBOX_IGU1_INT
);
478 ifx_atm_alloc_tx
= NULL
;
481 /* release bandwidth */
482 switch ( vcc
->qos
.txtp
.traffic_class
)
486 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.max_pcr
;
489 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.scr
;
492 port
->tx_current_cell_rate
-= vcc
->qos
.txtp
.min_pcr
;
496 /* wait for incoming packets to be processed by upper layers */
497 tasklet_unlock_wait(&g_dma_tasklet
);
503 static int ppe_send(struct atm_vcc
*vcc
, struct sk_buff
*skb
)
508 struct tx_descriptor reg_desc
= {0};
509 struct sk_buff
*new_skb
;
511 if ( vcc
== NULL
|| skb
== NULL
)
515 atm_free_tx_skb_vcc(skb
, vcc
);
517 conn
= find_vcc(vcc
);
524 pr_debug("not in showtime\n");
529 if ( vcc
->qos
.aal
== ATM_AAL5
) {
532 struct tx_inband_header
*header
;
534 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
535 if ( skb_headroom(skb
) < byteoff
+ TX_INBAND_HEADER_LENGTH
)
536 new_skb
= skb_duplicate(skb
);
538 new_skb
= skb_break_away_from_protocol(skb
);
539 if ( new_skb
== NULL
) {
540 pr_err("either skb_duplicate or skb_break_away_from_protocol fail\n");
544 dev_kfree_skb_any(skb
);
548 byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
550 skb_push(skb
, byteoff
+ TX_INBAND_HEADER_LENGTH
);
552 header
= (struct tx_inband_header
*)skb
->data
;
554 /* setup inband trailer */
557 header
->pad
= aal5_fill_pattern
;
560 /* setup cell header */
561 header
->clp
= (vcc
->atm_options
& ATM_ATMOPT_CLP
) ? 1 : 0;
562 header
->pti
= ATM_PTI_US0
;
563 header
->vci
= vcc
->vci
;
564 header
->vpi
= vcc
->vpi
;
567 /* setup descriptor */
568 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
569 reg_desc
.datalen
= datalen
;
570 reg_desc
.byteoff
= byteoff
;
573 /* if data pointer is not aligned, allocate new sk_buff */
574 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 ) {
575 pr_err("skb->data not aligned\n");
576 new_skb
= skb_duplicate(skb
);
578 new_skb
= skb_break_away_from_protocol(skb
);
579 if ( new_skb
== NULL
) {
580 pr_err("either skb_duplicate or skb_break_away_from_protocol fail\n");
584 dev_kfree_skb_any(skb
);
587 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
588 reg_desc
.datalen
= skb
->len
;
589 reg_desc
.byteoff
= 0;
595 reg_desc
.sop
= reg_desc
.eop
= 1;
597 desc_base
= get_tx_desc(conn
);
598 if ( desc_base
< 0 ) {
599 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
605 atomic_inc(&vcc
->stats
->tx
);
606 if ( vcc
->qos
.aal
== ATM_AAL5
)
607 g_atm_priv_data
.wtx_pdu
++;
609 /* update descriptor send pointer */
610 if ( g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] != NULL
)
611 dev_kfree_skb_any(g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
]);
612 g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] = skb
;
614 /* write discriptor to memory and write back cache */
615 g_atm_priv_data
.conn
[conn
].tx_desc
[desc_base
] = reg_desc
;
616 dma_cache_wback((unsigned long)skb
->data
, skb
->len
);
618 mailbox_signal(conn
, 1);
625 pr_err("FIND_VCC_FAIL\n");
626 g_atm_priv_data
.wtx_err_pdu
++;
627 dev_kfree_skb_any(skb
);
631 if ( vcc
->qos
.aal
== ATM_AAL5
)
632 g_atm_priv_data
.wtx_drop_pdu
++;
634 atomic_inc(&vcc
->stats
->tx_err
);
635 dev_kfree_skb_any(skb
);
639 /* operation and maintainance */
640 static int ppe_send_oam(struct atm_vcc
*vcc
, void *cell
, int flags
)
643 struct uni_cell_header
*uni_cell_header
= (struct uni_cell_header
*)cell
;
646 struct tx_descriptor reg_desc
= {0};
648 if ( ((uni_cell_header
->pti
== ATM_PTI_SEGF5
|| uni_cell_header
->pti
== ATM_PTI_E2EF5
)
649 && find_vpivci(uni_cell_header
->vpi
, uni_cell_header
->vci
) < 0)
650 || ((uni_cell_header
->vci
== 0x03 || uni_cell_header
->vci
== 0x04)
651 && find_vpi(uni_cell_header
->vpi
) < 0) )
653 g_atm_priv_data
.wtx_err_oam
++;
658 pr_err("not in showtime\n");
659 g_atm_priv_data
.wtx_drop_oam
++;
663 conn
= find_vcc(vcc
);
665 pr_err("FIND_VCC_FAIL\n");
666 g_atm_priv_data
.wtx_drop_oam
++;
670 skb
= alloc_skb_tx(CELL_SIZE
);
672 pr_err("ALLOC_SKB_TX_FAIL\n");
673 g_atm_priv_data
.wtx_drop_oam
++;
676 skb_put(skb
, CELL_SIZE
);
677 memcpy(skb
->data
, cell
, CELL_SIZE
);
679 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
680 reg_desc
.datalen
= CELL_SIZE
;
681 reg_desc
.byteoff
= 0;
686 reg_desc
.sop
= reg_desc
.eop
= 1;
688 desc_base
= get_tx_desc(conn
);
689 if ( desc_base
< 0 ) {
690 dev_kfree_skb_any(skb
);
691 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
692 g_atm_priv_data
.wtx_drop_oam
++;
697 atomic_inc(&vcc
->stats
->tx
);
699 /* update descriptor send pointer */
700 if ( g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] != NULL
)
701 dev_kfree_skb_any(g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
]);
702 g_atm_priv_data
.conn
[conn
].tx_skb
[desc_base
] = skb
;
704 /* write discriptor to memory and write back cache */
705 g_atm_priv_data
.conn
[conn
].tx_desc
[desc_base
] = reg_desc
;
706 dma_cache_wback((unsigned long)skb
->data
, CELL_SIZE
);
708 mailbox_signal(conn
, 1);
710 g_atm_priv_data
.wtx_oam
++;
716 static int ppe_change_qos(struct atm_vcc
*vcc
, struct atm_qos
*qos
, int flags
)
720 if ( vcc
== NULL
|| qos
== NULL
)
723 conn
= find_vcc(vcc
);
727 set_qsb(vcc
, qos
, conn
);
732 static inline void adsl_led_flash(void)
734 ifx_mei_atm_led_blink();
739 * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
741 * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
742 * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
743 * ret --- ppe_u64_t, pointer to a variable to hold result
747 static inline void u64_add_u32(ppe_u64_t opt1
, unsigned int opt2
, ppe_u64_t
*ret
)
749 ret
->l
= opt1
.l
+ opt2
;
750 if ( ret
->l
< opt1
.l
|| ret
->l
< opt2
)
754 static inline struct sk_buff
* alloc_skb_rx(void)
758 skb
= dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
);
760 /* must be burst length alignment */
761 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 )
762 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
763 /* pub skb in reserved area "skb->data - 4" */
764 *((struct sk_buff
**)skb
->data
- 1) = skb
;
765 /* write back and invalidate cache */
766 dma_cache_wback_inv((unsigned long)skb
->data
- sizeof(skb
), sizeof(skb
));
767 /* invalidate cache */
768 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
769 dma_cache_inv((unsigned long)skb
->data
, LESS_CACHE_INV_LEN
);
771 dma_cache_inv((unsigned long)skb
->data
, RX_DMA_CH_AAL_BUF_SIZE
);
777 static inline struct sk_buff
* alloc_skb_tx(unsigned int size
)
781 /* allocate memory including header and padding */
782 size
+= TX_INBAND_HEADER_LENGTH
+ MAX_TX_PACKET_ALIGN_BYTES
+ MAX_TX_PACKET_PADDING_BYTES
;
783 size
&= ~(DATA_BUFFER_ALIGNMENT
- 1);
784 skb
= dev_alloc_skb(size
+ DATA_BUFFER_ALIGNMENT
);
785 /* must be burst length alignment */
787 skb_reserve(skb
, (~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1)) + TX_INBAND_HEADER_LENGTH
);
791 struct sk_buff
* atm_alloc_tx(struct atm_vcc
*vcc
, unsigned int size
)
796 /* oversize packet */
797 if ( size
> aal5s_max_packet_size
) {
798 pr_err("atm_alloc_tx: oversize packet\n");
801 /* send buffer overflow */
802 if ( sk_wmem_alloc_get(sk_atm(vcc
)) && !atm_may_send(vcc
, size
) ) {
803 pr_err("atm_alloc_tx: send buffer overflow\n");
806 conn
= find_vcc(vcc
);
808 pr_err("atm_alloc_tx: unknown VCC\n");
812 skb
= dev_alloc_skb(size
);
814 pr_err("atm_alloc_tx: sk buffer is used up\n");
818 atomic_add(skb
->truesize
, &sk_atm(vcc
)->sk_wmem_alloc
);
823 static inline void atm_free_tx_skb_vcc(struct sk_buff
*skb
, struct atm_vcc
*vcc
)
825 if ( vcc
->pop
!= NULL
)
828 dev_kfree_skb_any(skb
);
831 static inline struct sk_buff
*get_skb_rx_pointer(unsigned int dataptr
)
833 unsigned int skb_dataptr
;
836 skb_dataptr
= ((dataptr
- 1) << 2) | KSEG1
;
837 skb
= *(struct sk_buff
**)skb_dataptr
;
839 ASSERT((unsigned int)skb
>= KSEG0
, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb
, dataptr
);
840 ASSERT(((unsigned int)skb
->data
| KSEG1
) == ((dataptr
<< 2) | KSEG1
), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb
, (unsigned int)skb
->data
, dataptr
);
845 static inline int get_tx_desc(unsigned int conn
)
848 struct connection
*p_conn
= &g_atm_priv_data
.conn
[conn
];
850 if ( p_conn
->tx_desc
[p_conn
->tx_desc_pos
].own
== 0 ) {
851 desc_base
= p_conn
->tx_desc_pos
;
852 if ( ++(p_conn
->tx_desc_pos
) == dma_tx_descriptor_length
)
853 p_conn
->tx_desc_pos
= 0;
859 static struct sk_buff
* skb_duplicate(struct sk_buff
*skb
)
861 struct sk_buff
*new_skb
;
863 new_skb
= alloc_skb_tx(skb
->len
);
864 if ( new_skb
== NULL
)
867 skb_put(new_skb
, skb
->len
);
868 memcpy(new_skb
->data
, skb
->data
, skb
->len
);
873 static struct sk_buff
* skb_break_away_from_protocol(struct sk_buff
*skb
)
875 struct sk_buff
*new_skb
;
877 if ( skb_shared(skb
) ) {
878 new_skb
= skb_clone(skb
, GFP_ATOMIC
);
879 if ( new_skb
== NULL
)
882 new_skb
= skb_get(skb
);
884 skb_dst_drop(new_skb
);
885 #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
886 nf_conntrack_put(new_skb
->nfct
);
887 new_skb
->nfct
= NULL
;
888 nf_conntrack_put_reasm(new_skb
->nfct_reasm
);
889 new_skb
->nfct_reasm
= NULL
;
890 #ifdef CONFIG_BRIDGE_NETFILTER
891 nf_bridge_put(new_skb
->nf_bridge
);
892 new_skb
->nf_bridge
= NULL
;
899 static inline void mailbox_oam_rx_handler(void)
901 unsigned int vlddes
= WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM
)->vlddes
;
902 struct rx_descriptor reg_desc
;
903 struct uni_cell_header
*header
;
908 for ( i
= 0; i
< vlddes
; i
++ ) {
909 unsigned int loop_count
= 0;
912 reg_desc
= g_atm_priv_data
.oam_desc
[g_atm_priv_data
.oam_desc_pos
];
913 if ( ++loop_count
== 1000 )
915 } while ( reg_desc
.own
|| !reg_desc
.c
); // keep test OWN and C bit until data is ready
916 ASSERT(loop_count
== 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count
, (int)reg_desc
.own
, (int)reg_desc
.c
, g_atm_priv_data
.oam_desc_pos
);
918 header
= (struct uni_cell_header
*)&g_atm_priv_data
.oam_buf
[g_atm_priv_data
.oam_desc_pos
* RX_DMA_CH_OAM_BUF_SIZE
];
920 if ( header
->pti
== ATM_PTI_SEGF5
|| header
->pti
== ATM_PTI_E2EF5
)
921 conn
= find_vpivci(header
->vpi
, header
->vci
);
922 else if ( header
->vci
== 0x03 || header
->vci
== 0x04 )
923 conn
= find_vpi(header
->vpi
);
927 if ( conn
>= 0 && g_atm_priv_data
.conn
[conn
].vcc
!= NULL
) {
928 vcc
= g_atm_priv_data
.conn
[conn
].vcc
;
930 if ( vcc
->push_oam
!= NULL
)
931 vcc
->push_oam(vcc
, header
);
933 ifx_push_oam((unsigned char *)header
);
935 g_atm_priv_data
.wrx_oam
++;
939 g_atm_priv_data
.wrx_drop_oam
++;
941 reg_desc
.byteoff
= 0;
942 reg_desc
.datalen
= RX_DMA_CH_OAM_BUF_SIZE
;
946 g_atm_priv_data
.oam_desc
[g_atm_priv_data
.oam_desc_pos
] = reg_desc
;
947 if ( ++g_atm_priv_data
.oam_desc_pos
== RX_DMA_CH_OAM_DESC_LEN
)
948 g_atm_priv_data
.oam_desc_pos
= 0;
950 dma_cache_inv((unsigned long)header
, CELL_SIZE
);
951 mailbox_signal(RX_DMA_CH_OAM
, 0);
955 static inline void mailbox_aal_rx_handler(void)
957 unsigned int vlddes
= WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL
)->vlddes
;
958 struct rx_descriptor reg_desc
;
961 struct sk_buff
*skb
, *new_skb
;
962 struct rx_inband_trailer
*trailer
;
965 for ( i
= 0; i
< vlddes
; i
++ ) {
966 unsigned int loop_count
= 0;
969 reg_desc
= g_atm_priv_data
.aal_desc
[g_atm_priv_data
.aal_desc_pos
];
970 if ( ++loop_count
== 1000 )
972 } while ( reg_desc
.own
|| !reg_desc
.c
); // keep test OWN and C bit until data is ready
973 ASSERT(loop_count
== 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count
, (int)reg_desc
.own
, (int)reg_desc
.c
, g_atm_priv_data
.aal_desc_pos
);
977 if ( g_atm_priv_data
.conn
[conn
].vcc
!= NULL
) {
978 vcc
= g_atm_priv_data
.conn
[conn
].vcc
;
980 skb
= get_skb_rx_pointer(reg_desc
.dataptr
);
982 if ( reg_desc
.err
) {
983 if ( vcc
->qos
.aal
== ATM_AAL5
) {
984 trailer
= (struct rx_inband_trailer
*)((unsigned int)skb
->data
+ ((reg_desc
.byteoff
+ reg_desc
.datalen
+ MAX_RX_PACKET_PADDING_BYTES
) & ~MAX_RX_PACKET_PADDING_BYTES
));
985 if ( trailer
->stw_crc
)
986 g_atm_priv_data
.conn
[conn
].aal5_vcc_crc_err
++;
987 if ( trailer
->stw_ovz
)
988 g_atm_priv_data
.conn
[conn
].aal5_vcc_oversize_sdu
++;
989 g_atm_priv_data
.wrx_drop_pdu
++;
992 atomic_inc(&vcc
->stats
->rx_drop
);
993 atomic_inc(&vcc
->stats
->rx_err
);
996 } else if ( atm_charge(vcc
, skb
->truesize
) ) {
997 new_skb
= alloc_skb_rx();
998 if ( new_skb
!= NULL
) {
999 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
1000 if ( reg_desc
.byteoff
+ reg_desc
.datalen
> LESS_CACHE_INV_LEN
)
1001 dma_cache_inv((unsigned long)skb
->data
+ LESS_CACHE_INV_LEN
, reg_desc
.byteoff
+ reg_desc
.datalen
- LESS_CACHE_INV_LEN
);
1004 skb_reserve(skb
, reg_desc
.byteoff
);
1005 skb_put(skb
, reg_desc
.datalen
);
1006 ATM_SKB(skb
)->vcc
= vcc
;
1008 vcc
->push(vcc
, skb
);
1010 if ( vcc
->qos
.aal
== ATM_AAL5
)
1011 g_atm_priv_data
.wrx_pdu
++;
1013 atomic_inc(&vcc
->stats
->rx
);
1016 reg_desc
.dataptr
= (unsigned int)new_skb
->data
>> 2;
1018 atm_return(vcc
, skb
->truesize
);
1019 if ( vcc
->qos
.aal
== ATM_AAL5
)
1020 g_atm_priv_data
.wrx_drop_pdu
++;
1022 atomic_inc(&vcc
->stats
->rx_drop
);
1025 if ( vcc
->qos
.aal
== ATM_AAL5
)
1026 g_atm_priv_data
.wrx_drop_pdu
++;
1028 atomic_inc(&vcc
->stats
->rx_drop
);
1031 g_atm_priv_data
.wrx_drop_pdu
++;
1034 reg_desc
.byteoff
= 0;
1035 reg_desc
.datalen
= RX_DMA_CH_AAL_BUF_SIZE
;
1039 g_atm_priv_data
.aal_desc
[g_atm_priv_data
.aal_desc_pos
] = reg_desc
;
1040 if ( ++g_atm_priv_data
.aal_desc_pos
== dma_rx_descriptor_length
)
1041 g_atm_priv_data
.aal_desc_pos
= 0;
1043 mailbox_signal(RX_DMA_CH_AAL
, 0);
1047 static void do_ppe_tasklet(unsigned long data
)
1049 *MBOX_IGU1_ISRC
= *MBOX_IGU1_ISR
;
1050 mailbox_oam_rx_handler();
1051 mailbox_aal_rx_handler();
1053 if ((*MBOX_IGU1_ISR
& ((1 << RX_DMA_CH_AAL
) | (1 << RX_DMA_CH_OAM
))) != 0)
1054 tasklet_schedule(&g_dma_tasklet
);
1056 enable_irq(PPE_MAILBOX_IGU1_INT
);
1059 static irqreturn_t
mailbox_irq_handler(int irq
, void *dev_id
)
1061 if ( !*MBOX_IGU1_ISR
)
1064 disable_irq_nosync(PPE_MAILBOX_IGU1_INT
);
1065 tasklet_schedule(&g_dma_tasklet
);
1070 static inline void mailbox_signal(unsigned int queue
, int is_tx
)
1075 while ( MBOX_IGU3_ISR_ISR(queue
+ FIRST_QSB_QID
+ 16) && count
> 0 )
1077 *MBOX_IGU3_ISRS
= MBOX_IGU3_ISRS_SET(queue
+ FIRST_QSB_QID
+ 16);
1079 while ( MBOX_IGU3_ISR_ISR(queue
) && count
> 0 )
1081 *MBOX_IGU3_ISRS
= MBOX_IGU3_ISRS_SET(queue
);
1084 ASSERT(count
> 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue
, is_tx
, IFX_REG_R32(MBOX_IGU3_ISR
));
1087 static void set_qsb(struct atm_vcc
*vcc
, struct atm_qos
*qos
, unsigned int queue
)
1089 struct clk
*fpi_clk
= clk_get_fpi();
1090 unsigned int qsb_clk
= clk_get_rate(fpi_clk
);
1091 unsigned int qsb_qid
= queue
+ FIRST_QSB_QID
;
1092 union qsb_queue_parameter_table qsb_queue_parameter_table
= {{0}};
1093 union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table
= {{0}};
1098 * Peak Cell Rate (PCR) Limiter
1100 if ( qos
->txtp
.max_pcr
== 0 )
1101 qsb_queue_parameter_table
.bit
.tp
= 0; /* disable PCR limiter */
1103 /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1104 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / qos
->txtp
.max_pcr
+ 1;
1105 /* check if overflow takes place */
1106 qsb_queue_parameter_table
.bit
.tp
= tmp
> QSB_TP_TS_MAX
? QSB_TP_TS_MAX
: tmp
;
1109 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1110 // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1111 // Send packets to these two PVCs at same time, it trigger strange behavior.
1112 // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1113 // In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1114 // To work around, create UBR always with max_pcr.
1115 // If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1116 if ( qos
->txtp
.traffic_class
== ATM_UBR
&& qsb_queue_parameter_table
.bit
.tp
== 0 ) {
1117 int port
= g_atm_priv_data
.conn
[queue
].port
;
1118 unsigned int max_pcr
= g_atm_priv_data
.port
[port
].tx_max_cell_rate
+ 1000;
1120 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / max_pcr
+ 1;
1121 if ( tmp
> QSB_TP_TS_MAX
)
1122 tmp
= QSB_TP_TS_MAX
;
1125 qsb_queue_parameter_table
.bit
.tp
= tmp
;
1130 * Weighted Fair Queueing Factor (WFQF)
1132 switch ( qos
->txtp
.traffic_class
) {
1135 /* real time queue gets weighted fair queueing bypass */
1136 qsb_queue_parameter_table
.bit
.wfqf
= 0;
1140 /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */
1141 /* WFQF is maximum cell rate / garenteed cell rate */
1142 /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */
1143 if ( qos
->txtp
.min_pcr
== 0 )
1144 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_NONUBR_MAX
;
1146 tmp
= QSB_GCR_MIN
* QSB_WFQ_NONUBR_MAX
/ qos
->txtp
.min_pcr
;
1148 qsb_queue_parameter_table
.bit
.wfqf
= 1;
1149 else if ( tmp
> QSB_WFQ_NONUBR_MAX
)
1150 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_NONUBR_MAX
;
1152 qsb_queue_parameter_table
.bit
.wfqf
= tmp
;
1157 qsb_queue_parameter_table
.bit
.wfqf
= QSB_WFQ_UBR_BYPASS
;
1161 * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1163 if ( qos
->txtp
.traffic_class
== ATM_VBR_RT
|| qos
->txtp
.traffic_class
== ATM_VBR_NRT
) {
1164 if ( qos
->txtp
.scr
== 0 ) {
1165 /* disable shaper */
1166 qsb_queue_vbr_parameter_table
.bit
.taus
= 0;
1167 qsb_queue_vbr_parameter_table
.bit
.ts
= 0;
1169 /* Cell Loss Priority (CLP) */
1170 if ( (vcc
->atm_options
& ATM_ATMOPT_CLP
) )
1172 qsb_queue_parameter_table
.bit
.vbr
= 1;
1175 qsb_queue_parameter_table
.bit
.vbr
= 0;
1176 /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1177 tmp
= ((qsb_clk
* qsb_tstep
) >> 5) / qos
->txtp
.scr
+ 1;
1178 qsb_queue_vbr_parameter_table
.bit
.ts
= tmp
> QSB_TP_TS_MAX
? QSB_TP_TS_MAX
: tmp
;
1179 tmp
= (qos
->txtp
.mbs
- 1) * (qsb_queue_vbr_parameter_table
.bit
.ts
- qsb_queue_parameter_table
.bit
.tp
) / 64;
1181 qsb_queue_vbr_parameter_table
.bit
.taus
= 1;
1182 else if ( tmp
> QSB_TAUS_MAX
)
1183 qsb_queue_vbr_parameter_table
.bit
.taus
= QSB_TAUS_MAX
;
1185 qsb_queue_vbr_parameter_table
.bit
.taus
= tmp
;
1188 qsb_queue_vbr_parameter_table
.bit
.taus
= 0;
1189 qsb_queue_vbr_parameter_table
.bit
.ts
= 0;
1192 /* Queue Parameter Table (QPT) */
1193 *QSB_RTM
= QSB_RTM_DM_SET(QSB_QPT_SET_MASK
);
1194 *QSB_RTD
= QSB_RTD_TTV_SET(qsb_queue_parameter_table
.dword
);
1195 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT
) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) | QSB_RAMAC_TESEL_SET(qsb_qid
);
1196 /* Queue VBR Paramter Table (QVPT) */
1197 *QSB_RTM
= QSB_RTM_DM_SET(QSB_QVPT_SET_MASK
);
1198 *QSB_RTD
= QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table
.dword
);
1199 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR
) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) | QSB_RAMAC_TESEL_SET(qsb_qid
);
1203 static void qsb_global_set(void)
1205 struct clk
*fpi_clk
= clk_get_fpi();
1206 unsigned int qsb_clk
= clk_get_rate(fpi_clk
);
1208 unsigned int tmp1
, tmp2
, tmp3
;
1210 *QSB_ICDV
= QSB_ICDV_TAU_SET(qsb_tau
);
1211 *QSB_SBL
= QSB_SBL_SBL_SET(qsb_srvm
);
1212 *QSB_CFG
= QSB_CFG_TSTEPC_SET(qsb_tstep
>> 1);
1215 * set SCT and SPT per port
1217 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ ) {
1218 if ( g_atm_priv_data
.port
[i
].tx_max_cell_rate
!= 0 ) {
1219 tmp1
= ((qsb_clk
* qsb_tstep
) >> 1) / g_atm_priv_data
.port
[i
].tx_max_cell_rate
;
1220 tmp2
= tmp1
>> 6; /* integer value of Tsb */
1221 tmp3
= (tmp1
& ((1 << 6) - 1)) + 1; /* fractional part of Tsb */
1222 /* carry over to integer part (?) */
1223 if ( tmp3
== (1 << 6) ) {
1230 /* 2. write value to data transfer register */
1231 /* 3. start the tranfer */
1232 /* SCT (FracRate) */
1233 *QSB_RTM
= QSB_RTM_DM_SET(QSB_SET_SCT_MASK
);
1234 *QSB_RTD
= QSB_RTD_TTV_SET(tmp3
);
1235 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) |
1236 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT
) |
1237 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) |
1238 QSB_RAMAC_TESEL_SET(i
& 0x01);
1239 /* SPT (SBV + PN + IntRage) */
1240 *QSB_RTM
= QSB_RTM_DM_SET(QSB_SET_SPT_MASK
);
1241 *QSB_RTD
= QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID
| QSB_SPT_PN_SET(i
& 0x01) | QSB_SPT_INTRATE_SET(tmp2
));
1242 *QSB_RAMAC
= QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE
) |
1243 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT
) |
1244 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW
) |
1245 QSB_RAMAC_TESEL_SET(i
& 0x01);
1250 static inline void set_htu_entry(unsigned int vpi
, unsigned int vci
, unsigned int queue
, int aal5
, int is_retx
)
1252 struct htu_entry htu_entry
= {
1254 clp
: is_retx
? 0x01 : 0x00,
1255 pid
: g_atm_priv_data
.conn
[queue
].port
& 0x01,
1261 struct htu_mask htu_mask
= {
1267 pti_mask
: 0x03, // 0xx, user data
1270 struct htu_result htu_result
= {
1274 type
: aal5
? 0x00 : 0x01,
1279 *HTU_RESULT(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_result
;
1280 *HTU_MASK(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_mask
;
1281 *HTU_ENTRY(queue
+ OAM_HTU_ENTRY_NUMBER
) = htu_entry
;
1284 static inline void clear_htu_entry(unsigned int queue
)
1286 HTU_ENTRY(queue
+ OAM_HTU_ENTRY_NUMBER
)->vld
= 0;
1289 static void validate_oam_htu_entry(void)
1291 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
)->vld
= 1;
1292 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
)->vld
= 1;
1293 HTU_ENTRY(OAM_F5_HTU_ENTRY
)->vld
= 1;
1296 static void invalidate_oam_htu_entry(void)
1298 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
)->vld
= 0;
1299 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
)->vld
= 0;
1300 HTU_ENTRY(OAM_F5_HTU_ENTRY
)->vld
= 0;
1303 static inline int find_vpi(unsigned int vpi
)
1308 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1309 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1310 && g_atm_priv_data
.conn
[i
].vcc
!= NULL
1311 && vpi
== g_atm_priv_data
.conn
[i
].vcc
->vpi
)
1318 static inline int find_vpivci(unsigned int vpi
, unsigned int vci
)
1323 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1324 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1325 && g_atm_priv_data
.conn
[i
].vcc
!= NULL
1326 && vpi
== g_atm_priv_data
.conn
[i
].vcc
->vpi
1327 && vci
== g_atm_priv_data
.conn
[i
].vcc
->vci
)
1334 static inline int find_vcc(struct atm_vcc
*vcc
)
1339 for ( i
= 0, bit
= 1; i
< MAX_PVC_NUMBER
; i
++, bit
<<= 1 ) {
1340 if ( (g_atm_priv_data
.conn_table
& bit
) != 0
1341 && g_atm_priv_data
.conn
[i
].vcc
== vcc
)
1348 static inline int ifx_atm_version(const struct ltq_atm_ops
*ops
, char *buf
)
1351 unsigned int major
, minor
;
1353 ops
->fw_ver(&major
, &minor
);
1355 len
+= sprintf(buf
+ len
, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR
, IFX_ATM_VER_MID
, IFX_ATM_VER_MINOR
);
1356 len
+= sprintf(buf
+ len
, " ATM (A1) firmware version %d.%d\n", major
, minor
);
1361 static inline void check_parameters(void)
1363 /* Please refer to Amazon spec 15.4 for setting these values. */
1366 if ( qsb_tstep
< 1 )
1368 else if ( qsb_tstep
> 4 )
1370 else if ( qsb_tstep
== 3 )
1373 /* There is a delay between PPE write descriptor and descriptor is */
1374 /* really stored in memory. Host also has this delay when writing */
1375 /* descriptor. So PPE will use this value to determine if the write */
1376 /* operation makes effect. */
1377 if ( write_descriptor_delay
< 0 )
1378 write_descriptor_delay
= 0;
1380 if ( aal5_fill_pattern
< 0 )
1381 aal5_fill_pattern
= 0;
1383 aal5_fill_pattern
&= 0xFF;
1385 /* Because of the limitation of length field in descriptors, the packet */
1386 /* size could not be larger than 64K minus overhead size. */
1387 if ( aal5r_max_packet_size
< 0 )
1388 aal5r_max_packet_size
= 0;
1389 else if ( aal5r_max_packet_size
>= 65535 - MAX_RX_FRAME_EXTRA_BYTES
)
1390 aal5r_max_packet_size
= 65535 - MAX_RX_FRAME_EXTRA_BYTES
;
1391 if ( aal5r_min_packet_size
< 0 )
1392 aal5r_min_packet_size
= 0;
1393 else if ( aal5r_min_packet_size
> aal5r_max_packet_size
)
1394 aal5r_min_packet_size
= aal5r_max_packet_size
;
1395 if ( aal5s_max_packet_size
< 0 )
1396 aal5s_max_packet_size
= 0;
1397 else if ( aal5s_max_packet_size
>= 65535 - MAX_TX_FRAME_EXTRA_BYTES
)
1398 aal5s_max_packet_size
= 65535 - MAX_TX_FRAME_EXTRA_BYTES
;
1399 if ( aal5s_min_packet_size
< 0 )
1400 aal5s_min_packet_size
= 0;
1401 else if ( aal5s_min_packet_size
> aal5s_max_packet_size
)
1402 aal5s_min_packet_size
= aal5s_max_packet_size
;
1404 if ( dma_rx_descriptor_length
< 2 )
1405 dma_rx_descriptor_length
= 2;
1406 if ( dma_tx_descriptor_length
< 2 )
1407 dma_tx_descriptor_length
= 2;
1408 if ( dma_rx_clp1_descriptor_threshold
< 0 )
1409 dma_rx_clp1_descriptor_threshold
= 0;
1410 else if ( dma_rx_clp1_descriptor_threshold
> dma_rx_descriptor_length
)
1411 dma_rx_clp1_descriptor_threshold
= dma_rx_descriptor_length
;
1413 if ( dma_tx_descriptor_length
< 2 )
1414 dma_tx_descriptor_length
= 2;
1417 static inline int init_priv_data(void)
1421 struct rx_descriptor rx_desc
= {0};
1422 struct sk_buff
*skb
;
1423 volatile struct tx_descriptor
*p_tx_desc
;
1424 struct sk_buff
**ppskb
;
1426 // clear atm private data structure
1427 memset(&g_atm_priv_data
, 0, sizeof(g_atm_priv_data
));
1429 // allocate memory for RX (AAL) descriptors
1430 p
= kzalloc(dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1433 dma_cache_wback_inv((unsigned long)p
, dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1434 g_atm_priv_data
.aal_desc_base
= p
;
1435 p
= (void *)((((unsigned int)p
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1436 g_atm_priv_data
.aal_desc
= (volatile struct rx_descriptor
*)p
;
1438 // allocate memory for RX (OAM) descriptors
1439 p
= kzalloc(RX_DMA_CH_OAM_DESC_LEN
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1442 dma_cache_wback_inv((unsigned long)p
, RX_DMA_CH_OAM_DESC_LEN
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1443 g_atm_priv_data
.oam_desc_base
= p
;
1444 p
= (void *)((((unsigned int)p
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1445 g_atm_priv_data
.oam_desc
= (volatile struct rx_descriptor
*)p
;
1447 // allocate memory for RX (OAM) buffer
1448 p
= kzalloc(RX_DMA_CH_OAM_DESC_LEN
* RX_DMA_CH_OAM_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
, GFP_KERNEL
);
1451 dma_cache_wback_inv((unsigned long)p
, RX_DMA_CH_OAM_DESC_LEN
* RX_DMA_CH_OAM_BUF_SIZE
+ DATA_BUFFER_ALIGNMENT
);
1452 g_atm_priv_data
.oam_buf_base
= p
;
1453 p
= (void *)(((unsigned int)p
+ DATA_BUFFER_ALIGNMENT
- 1) & ~(DATA_BUFFER_ALIGNMENT
- 1));
1454 g_atm_priv_data
.oam_buf
= p
;
1456 // allocate memory for TX descriptors
1457 p
= kzalloc(MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1460 dma_cache_wback_inv((unsigned long)p
, MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
);
1461 g_atm_priv_data
.tx_desc_base
= p
;
1463 // allocate memory for TX skb pointers
1464 p
= kzalloc(MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4, GFP_KERNEL
);
1467 dma_cache_wback_inv((unsigned long)p
, MAX_PVC_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4);
1468 g_atm_priv_data
.tx_skb_base
= p
;
1470 // setup RX (AAL) descriptors
1475 rx_desc
.byteoff
= 0;
1478 rx_desc
.datalen
= RX_DMA_CH_AAL_BUF_SIZE
;
1479 for ( i
= 0; i
< dma_rx_descriptor_length
; i
++ ) {
1480 skb
= alloc_skb_rx();
1483 rx_desc
.dataptr
= ((unsigned int)skb
->data
>> 2) & 0x0FFFFFFF;
1484 g_atm_priv_data
.aal_desc
[i
] = rx_desc
;
1487 // setup RX (OAM) descriptors
1488 p
= (void *)((unsigned int)g_atm_priv_data
.oam_buf
| KSEG1
);
1493 rx_desc
.byteoff
= 0;
1496 rx_desc
.datalen
= RX_DMA_CH_OAM_BUF_SIZE
;
1497 for ( i
= 0; i
< RX_DMA_CH_OAM_DESC_LEN
; i
++ ) {
1498 rx_desc
.dataptr
= ((unsigned int)p
>> 2) & 0x0FFFFFFF;
1499 g_atm_priv_data
.oam_desc
[i
] = rx_desc
;
1500 p
= (void *)((unsigned int)p
+ RX_DMA_CH_OAM_BUF_SIZE
);
1503 // setup TX descriptors and skb pointers
1504 p_tx_desc
= (volatile struct tx_descriptor
*)((((unsigned int)g_atm_priv_data
.tx_desc_base
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1505 ppskb
= (struct sk_buff
**)(((unsigned int)g_atm_priv_data
.tx_skb_base
+ 3) & ~3);
1506 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ ) {
1507 g_atm_priv_data
.conn
[i
].tx_desc
= &p_tx_desc
[i
* dma_tx_descriptor_length
];
1508 g_atm_priv_data
.conn
[i
].tx_skb
= &ppskb
[i
* dma_tx_descriptor_length
];
1511 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1512 g_atm_priv_data
.port
[i
].tx_max_cell_rate
= DEFAULT_TX_LINK_RATE
;
1517 static inline void clear_priv_data(void)
1520 struct sk_buff
*skb
;
1522 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ ) {
1523 if ( g_atm_priv_data
.conn
[i
].tx_skb
!= NULL
) {
1524 for ( j
= 0; j
< dma_tx_descriptor_length
; j
++ )
1525 if ( g_atm_priv_data
.conn
[i
].tx_skb
[j
] != NULL
)
1526 dev_kfree_skb_any(g_atm_priv_data
.conn
[i
].tx_skb
[j
]);
1530 if ( g_atm_priv_data
.tx_skb_base
!= NULL
)
1531 kfree(g_atm_priv_data
.tx_skb_base
);
1533 if ( g_atm_priv_data
.tx_desc_base
!= NULL
)
1534 kfree(g_atm_priv_data
.tx_desc_base
);
1536 if ( g_atm_priv_data
.oam_buf_base
!= NULL
)
1537 kfree(g_atm_priv_data
.oam_buf_base
);
1539 if ( g_atm_priv_data
.oam_desc_base
!= NULL
)
1540 kfree(g_atm_priv_data
.oam_desc_base
);
1542 if ( g_atm_priv_data
.aal_desc_base
!= NULL
) {
1543 for ( i
= 0; i
< dma_rx_descriptor_length
; i
++ ) {
1544 if ( g_atm_priv_data
.aal_desc
[i
].sop
|| g_atm_priv_data
.aal_desc
[i
].eop
) { // descriptor initialized
1545 skb
= get_skb_rx_pointer(g_atm_priv_data
.aal_desc
[i
].dataptr
);
1546 dev_kfree_skb_any(skb
);
1549 kfree(g_atm_priv_data
.aal_desc_base
);
1553 static inline void init_rx_tables(void)
1556 struct wrx_queue_config wrx_queue_config
= {0};
1557 struct wrx_dma_channel_config wrx_dma_channel_config
= {0};
1558 struct htu_entry htu_entry
= {0};
1559 struct htu_result htu_result
= {0};
1560 struct htu_mask htu_mask
= {
1573 *CFG_WRX_HTUTS
= MAX_PVC_NUMBER
+ OAM_HTU_ENTRY_NUMBER
;
1574 #ifndef CONFIG_AMAZON_SE
1575 *CFG_WRX_QNUM
= MAX_QUEUE_NUMBER
;
1577 *CFG_WRX_DCHNUM
= RX_DMA_CH_TOTAL
;
1578 *WRX_DMACH_ON
= (1 << RX_DMA_CH_TOTAL
) - 1;
1579 *WRX_HUNT_BITTH
= DEFAULT_RX_HUNT_BITTH
;
1582 * WRX Queue Configuration Table
1584 wrx_queue_config
.uumask
= 0xFF;
1585 wrx_queue_config
.cpimask
= 0xFF;
1586 wrx_queue_config
.uuexp
= 0;
1587 wrx_queue_config
.cpiexp
= 0;
1588 wrx_queue_config
.mfs
= aal5r_max_packet_size
;
1589 wrx_queue_config
.oversize
= aal5r_max_packet_size
;
1590 wrx_queue_config
.undersize
= aal5r_min_packet_size
;
1591 wrx_queue_config
.errdp
= aal5r_drop_error_packet
;
1592 wrx_queue_config
.dmach
= RX_DMA_CH_AAL
;
1593 for ( i
= 0; i
< MAX_QUEUE_NUMBER
; i
++ )
1594 *WRX_QUEUE_CONFIG(i
) = wrx_queue_config
;
1595 WRX_QUEUE_CONFIG(OAM_RX_QUEUE
)->dmach
= RX_DMA_CH_OAM
;
1598 * WRX DMA Channel Configuration Table
1600 wrx_dma_channel_config
.chrl
= 0;
1601 wrx_dma_channel_config
.clp1th
= dma_rx_clp1_descriptor_threshold
;
1602 wrx_dma_channel_config
.mode
= 0;
1603 wrx_dma_channel_config
.rlcfg
= 0;
1605 wrx_dma_channel_config
.deslen
= RX_DMA_CH_OAM_DESC_LEN
;
1606 wrx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.oam_desc
>> 2) & 0x0FFFFFFF;
1607 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM
) = wrx_dma_channel_config
;
1609 wrx_dma_channel_config
.deslen
= dma_rx_descriptor_length
;
1610 wrx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.aal_desc
>> 2) & 0x0FFFFFFF;
1611 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL
) = wrx_dma_channel_config
;
1616 for (i
= 0; i
< MAX_PVC_NUMBER
; i
++) {
1617 htu_result
.qid
= (unsigned int)i
;
1619 *HTU_ENTRY(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_entry
;
1620 *HTU_MASK(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_mask
;
1621 *HTU_RESULT(i
+ OAM_HTU_ENTRY_NUMBER
) = htu_result
;
1625 htu_entry
.vci
= 0x03;
1626 htu_mask
.pid_mask
= 0x03;
1627 htu_mask
.vpi_mask
= 0xFF;
1628 htu_mask
.vci_mask
= 0x0000;
1629 htu_mask
.pti_mask
= 0x07;
1630 htu_result
.cellid
= OAM_RX_QUEUE
;
1631 htu_result
.type
= 1;
1633 htu_result
.qid
= OAM_RX_QUEUE
;
1634 *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY
) = htu_result
;
1635 *HTU_MASK(OAM_F4_SEG_HTU_ENTRY
) = htu_mask
;
1636 *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY
) = htu_entry
;
1637 htu_entry
.vci
= 0x04;
1638 htu_result
.cellid
= OAM_RX_QUEUE
;
1639 htu_result
.type
= 1;
1641 htu_result
.qid
= OAM_RX_QUEUE
;
1642 *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY
) = htu_result
;
1643 *HTU_MASK(OAM_F4_TOT_HTU_ENTRY
) = htu_mask
;
1644 *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY
) = htu_entry
;
1645 htu_entry
.vci
= 0x00;
1646 htu_entry
.pti
= 0x04;
1647 htu_mask
.vci_mask
= 0xFFFF;
1648 htu_mask
.pti_mask
= 0x01;
1649 htu_result
.cellid
= OAM_RX_QUEUE
;
1650 htu_result
.type
= 1;
1652 htu_result
.qid
= OAM_RX_QUEUE
;
1653 *HTU_RESULT(OAM_F5_HTU_ENTRY
) = htu_result
;
1654 *HTU_MASK(OAM_F5_HTU_ENTRY
) = htu_mask
;
1655 *HTU_ENTRY(OAM_F5_HTU_ENTRY
) = htu_entry
;
1658 static inline void init_tx_tables(void)
1661 struct wtx_queue_config wtx_queue_config
= {0};
1662 struct wtx_dma_channel_config wtx_dma_channel_config
= {0};
1663 struct wtx_port_config wtx_port_config
= {
1672 *CFG_WTX_DCHNUM
= MAX_TX_DMA_CHANNEL_NUMBER
;
1673 *WTX_DMACH_ON
= ((1 << MAX_TX_DMA_CHANNEL_NUMBER
) - 1) ^ ((1 << FIRST_QSB_QID
) - 1);
1674 *CFG_WRDES_DELAY
= write_descriptor_delay
;
1677 * WTX Port Configuration Table
1679 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1680 *WTX_PORT_CONFIG(i
) = wtx_port_config
;
1683 * WTX Queue Configuration Table
1685 wtx_queue_config
.qsben
= 1;
1686 wtx_queue_config
.sbid
= 0;
1687 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1688 wtx_queue_config
.qsb_vcid
= i
;
1689 *WTX_QUEUE_CONFIG(i
) = wtx_queue_config
;
1693 * WTX DMA Channel Configuration Table
1695 wtx_dma_channel_config
.mode
= 0;
1696 wtx_dma_channel_config
.deslen
= 0;
1697 wtx_dma_channel_config
.desba
= 0;
1698 for ( i
= 0; i
< FIRST_QSB_QID
; i
++ )
1699 *WTX_DMA_CHANNEL_CONFIG(i
) = wtx_dma_channel_config
;
1700 /* normal connection */
1701 wtx_dma_channel_config
.deslen
= dma_tx_descriptor_length
;
1702 for ( ; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1703 wtx_dma_channel_config
.desba
= ((unsigned int)g_atm_priv_data
.conn
[i
- FIRST_QSB_QID
].tx_desc
>> 2) & 0x0FFFFFFF;
1704 *WTX_DMA_CHANNEL_CONFIG(i
) = wtx_dma_channel_config
;
1708 static int atm_showtime_enter(struct port_cell_info
*port_cell
, void *xdata_addr
)
1712 ASSERT(port_cell
!= NULL
, "port_cell is NULL");
1713 ASSERT(xdata_addr
!= NULL
, "xdata_addr is NULL");
1715 for ( j
= 0; j
< ATM_PORT_NUMBER
&& j
< port_cell
->port_num
; j
++ )
1716 if ( port_cell
->tx_link_rate
[j
] > 0 )
1718 for ( i
= 0; i
< ATM_PORT_NUMBER
&& i
< port_cell
->port_num
; i
++ )
1719 g_atm_priv_data
.port
[i
].tx_max_cell_rate
=
1720 port_cell
->tx_link_rate
[i
] > 0 ? port_cell
->tx_link_rate
[i
] : port_cell
->tx_link_rate
[j
];
1724 for ( i
= 0; i
< MAX_PVC_NUMBER
; i
++ )
1725 if ( g_atm_priv_data
.conn
[i
].vcc
!= NULL
)
1726 set_qsb(g_atm_priv_data
.conn
[i
].vcc
, &g_atm_priv_data
.conn
[i
].vcc
->qos
, i
);
1728 // TODO: ReTX set xdata_addr
1729 g_xdata_addr
= xdata_addr
;
1733 #if defined(CONFIG_VR9)
1734 IFX_REG_W32(0x0F, UTP_CFG
);
1737 printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1738 g_atm_priv_data
.port
[0].tx_max_cell_rate
,
1739 g_atm_priv_data
.port
[1].tx_max_cell_rate
,
1740 (unsigned int)g_xdata_addr
);
1745 static int atm_showtime_exit(void)
1750 #if defined(CONFIG_VR9)
1751 IFX_REG_W32(0x00, UTP_CFG
);
1754 g_xdata_addr
= NULL
;
1755 printk("leave showtime\n");
1759 extern struct ltq_atm_ops ar9_ops
;
1760 extern struct ltq_atm_ops vr9_ops
;
1761 extern struct ltq_atm_ops danube_ops
;
1762 extern struct ltq_atm_ops ase_ops
;
1764 static const struct of_device_id ltq_atm_match
[] = {
1765 #ifdef CONFIG_DANUBE
1766 { .compatible
= "lantiq,ppe-danube", .data
= &danube_ops
},
1767 #elif defined CONFIG_AMAZON_SE
1768 { .compatible
= "lantiq,ppe-ase", .data
= &ase_ops
},
1769 #elif defined CONFIG_AR9
1770 { .compatible
= "lantiq,ppe-arx100", .data
= &ar9_ops
},
1771 #elif defined CONFIG_VR9
1772 { .compatible
= "lantiq,ppe-xrx200", .data
= &vr9_ops
},
1776 MODULE_DEVICE_TABLE(of
, ltq_atm_match
);
1778 static int ltq_atm_probe(struct platform_device
*pdev
)
1780 const struct of_device_id
*match
;
1781 struct ltq_atm_ops
*ops
= NULL
;
1784 struct port_cell_info port_cell
= {0};
1788 match
= of_match_device(ltq_atm_match
, &pdev
->dev
);
1790 dev_err(&pdev
->dev
, "failed to find matching device\n");
1793 ops
= (struct ltq_atm_ops
*) match
->data
;
1797 ret
= init_priv_data();
1799 pr_err("INIT_PRIV_DATA_FAIL\n");
1800 goto INIT_PRIV_DATA_FAIL
;
1807 /* create devices */
1808 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ ) {
1809 g_atm_priv_data
.port
[port_num
].dev
= atm_dev_register("ifxmips_atm", NULL
, &g_ifx_atm_ops
, -1, NULL
);
1810 if ( !g_atm_priv_data
.port
[port_num
].dev
) {
1811 pr_err("failed to register atm device %d!\n", port_num
);
1813 goto ATM_DEV_REGISTER_FAIL
;
1815 g_atm_priv_data
.port
[port_num
].dev
->ci_range
.vpi_bits
= 8;
1816 g_atm_priv_data
.port
[port_num
].dev
->ci_range
.vci_bits
= 16;
1817 g_atm_priv_data
.port
[port_num
].dev
->link_rate
= g_atm_priv_data
.port
[port_num
].tx_max_cell_rate
;
1818 g_atm_priv_data
.port
[port_num
].dev
->dev_data
= (void*)port_num
;
1822 /* register interrupt handler */
1823 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, IRQF_DISABLED
, "atm_mailbox_isr", &g_atm_priv_data
);
1825 if ( ret
== -EBUSY
) {
1826 pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1828 pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT
);
1830 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
1832 disable_irq(PPE_MAILBOX_IGU1_INT
);
1835 ret
= ops
->start(0);
1837 pr_err("ifx_pp32_start fail!\n");
1838 goto PP32_START_FAIL
;
1841 port_cell
.port_num
= ATM_PORT_NUMBER
;
1842 ifx_mei_atm_showtime_check(&g_showtime
, &port_cell
, &g_xdata_addr
);
1844 for ( i
= 0; i
< ATM_PORT_NUMBER
; i
++ )
1845 if ( port_cell
.tx_link_rate
[i
] != 0 )
1847 for ( j
= 0; j
< ATM_PORT_NUMBER
; j
++ )
1848 g_atm_priv_data
.port
[j
].tx_max_cell_rate
=
1849 port_cell
.tx_link_rate
[j
] != 0 ? port_cell
.tx_link_rate
[j
] : port_cell
.tx_link_rate
[i
];
1853 validate_oam_htu_entry();
1855 ifx_mei_atm_showtime_enter
= atm_showtime_enter
;
1856 ifx_mei_atm_showtime_exit
= atm_showtime_exit
;
1858 ifx_atm_version(ops
, ver_str
);
1859 printk(KERN_INFO
"%s", ver_str
);
1860 platform_set_drvdata(pdev
, ops
);
1861 printk("ifxmips_atm: ATM init succeed\n");
1866 free_irq(PPE_MAILBOX_IGU1_INT
, &g_atm_priv_data
);
1867 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
:
1868 ATM_DEV_REGISTER_FAIL
:
1869 while ( port_num
-- > 0 )
1870 atm_dev_deregister(g_atm_priv_data
.port
[port_num
].dev
);
1871 INIT_PRIV_DATA_FAIL
:
1873 printk("ifxmips_atm: ATM init failed\n");
1877 static int ltq_atm_remove(struct platform_device
*pdev
)
1880 struct ltq_atm_ops
*ops
= platform_get_drvdata(pdev
);
1882 ifx_mei_atm_showtime_enter
= NULL
;
1883 ifx_mei_atm_showtime_exit
= NULL
;
1885 invalidate_oam_htu_entry();
1889 free_irq(PPE_MAILBOX_IGU1_INT
, &g_atm_priv_data
);
1891 for ( port_num
= 0; port_num
< ATM_PORT_NUMBER
; port_num
++ )
1892 atm_dev_deregister(g_atm_priv_data
.port
[port_num
].dev
);
1901 static struct platform_driver ltq_atm_driver
= {
1902 .probe
= ltq_atm_probe
,
1903 .remove
= ltq_atm_remove
,
1906 .owner
= THIS_MODULE
,
1907 .of_match_table
= ltq_atm_match
,
1911 module_platform_driver(ltq_atm_driver
);
1913 MODULE_LICENSE("Dual BSD/GPL");