1 /*****************************************************************************
2 ** FILE NAME : ifxhcd_intr.c
3 ** PROJECT : IFX USB sub-system V3
4 ** MODULES : IFX USB sub-system Host and Device driver
7 ** AUTHOR : Chen, Howard
8 ** DESCRIPTION : This file contains the implementation of the HCD Interrupt handlers.
11 ** REFERENCE : Synopsys DWC-OTG Driver 2.7
12 ** COPYRIGHT : Copyright (c) 2010
13 ** LANTIQ DEUTSCHLAND GMBH,
14 ** Am Campeon 3, 85579 Neubiberg, Germany
16 ** This program is free software; you can redistribute it and/or modify
17 ** it under the terms of the GNU General Public License as published by
18 ** the Free Software Foundation; either version 2 of the License, or
19 ** (at your option) any later version.
21 ** Version Control Section **
25 ** $Log$ Revision history
26 *****************************************************************************/
29 * This file contains code fragments from Synopsys HS OTG Linux Software Driver.
30 * For this code the following notice is applicable:
32 * ==========================================================================
34 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
35 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
36 * otherwise expressly agreed to in writing between Synopsys and you.
38 * The Software IS NOT an item of Licensed Software or Licensed Product under
39 * any End User Software License Agreement or Agreement for Licensed Product
40 * with Synopsys or any supplement thereto. You are permitted to use and
41 * redistribute this Software in source and binary forms, with or without
42 * modification, provided that redistributions of source code must retain this
43 * notice. You may not view, use, disclose, copy or distribute this file or
44 * any information contained herein except pursuant to this license grant from
45 * Synopsys. If you do not agree with this notice, including the disclaimer
46 * below, then you are not authorized to use the Software.
48 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
49 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
52 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
53 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
54 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
55 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
59 * ========================================================================== */
63 \ingroup IFXUSB_DRIVER_V3
64 \brief This file contains the implementation of the HCD Interrupt handlers.
68 #include <linux/version.h>
69 #include "ifxusb_version.h"
71 #include "ifxusb_plat.h"
72 #include "ifxusb_regs.h"
73 #include "ifxusb_cif.h"
77 /* Macro used to clear one channel interrupt */
78 #define clear_hc_int(_hc_regs_,_intr_) \
80 hcint_data_t hcint_clear = {.d32 = 0}; \
81 hcint_clear.b._intr_ = 1; \
82 ifxusb_wreg(&((_hc_regs_)->hcint), hcint_clear.d32); \
86 * Macro used to disable one channel interrupt. Channel interrupts are
87 * disabled when the channel is halted or released by the interrupt handler.
88 * There is no need to handle further interrupts of that type until the
89 * channel is re-assigned. In fact, subsequent handling may cause crashes
90 * because the channel structures are cleaned up when the channel is released.
92 #define disable_hc_int(_hc_regs_,_intr_) \
94 hcint_data_t hcintmsk = {.d32 = 0}; \
95 hcintmsk.b._intr_ = 1; \
96 ifxusb_mreg(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \
99 #define enable_hc_int(_hc_regs_,_intr_) \
101 hcint_data_t hcintmsk = {.d32 = 0}; \
102 hcintmsk.b._intr_ = 1; \
103 ifxusb_mreg(&((_hc_regs_)->hcintmsk),0, hcintmsk.d32); \
107 * Save the starting data toggle for the next transfer. The data toggle is
108 * saved in the QH for non-control transfers and it's saved in the QTD for
111 uint8_t read_data_toggle(ifxusb_hc_regs_t
*_hc_regs
)
113 hctsiz_data_t hctsiz
;
114 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
115 return(hctsiz
.b
.pid
);
119 static void release_channel_dump(ifxhcd_hc_t
*ifxhc
,
123 ifxhcd_halt_status_e halt_status
)
129 case HC_XFER_NO_HALT_STATUS
:
130 printk("HC_XFER_NO_HALT_STATUS");break;
131 case HC_XFER_URB_COMPLETE
:
132 printk("HC_XFER_URB_COMPLETE");break;
133 case HC_XFER_AHB_ERR
:
134 printk("HC_XFER_AHB_ERR");break;
136 printk("HC_XFER_STALL");break;
137 case HC_XFER_BABBLE_ERR
:
138 printk("HC_XFER_BABBLE_ERR");break;
139 case HC_XFER_XACT_ERR
:
140 printk("HC_XFER_XACT_ERR");break;
141 case HC_XFER_URB_DEQUEUE
:
142 printk("HC_XFER_URB_DEQUEUE");break;
143 case HC_XFER_FRAME_OVERRUN
:
144 printk("HC_XFER_FRAME_OVERRUN");break;
145 case HC_XFER_DATA_TOGGLE_ERR
:
146 printk("HC_XFER_DATA_TOGGLE_ERR");break;
149 printk("HC_XFER_NAK");break;
151 case HC_XFER_COMPLETE
:
152 printk("HC_XFER_COMPLETE");break;
154 printk("KNOWN");break;
157 printk("Ch %d %s%s S%d " , ifxhc
->hc_num
158 ,(ifxhc
->ep_type
== IFXUSB_EP_TYPE_CTRL
)?"CTRL-":
159 ((ifxhc
->ep_type
== IFXUSB_EP_TYPE_BULK
)?"BULK-":
160 ((ifxhc
->ep_type
== IFXUSB_EP_TYPE_INTR
)?"INTR-":
161 ((ifxhc
->ep_type
== IFXUSB_EP_TYPE_ISOC
)?"ISOC-":"????"
165 ,(ifxhc
->is_in
)?"IN":"OUT"
169 printk(" [NULL HC] ");
170 printk("urb=%p epqh=%p urbd=%p\n",urb
,epqh
,urbd
);
174 printk(KERN_INFO
" Device address: %d\n", usb_pipedevice(urb
->pipe
));
175 printk(KERN_INFO
" Endpoint: %d, %s\n", usb_pipeendpoint(urb
->pipe
),
176 (usb_pipein(urb
->pipe
) ? "IN" : "OUT"));
177 printk(KERN_INFO
" Endpoint type: %s\n",
179 switch (usb_pipetype(urb
->pipe
)) {
180 case PIPE_CONTROL
: pipetype
= "CTRL"; break;
181 case PIPE_BULK
: pipetype
= "BULK"; break;
182 case PIPE_INTERRUPT
: pipetype
= "INTR"; break;
183 case PIPE_ISOCHRONOUS
: pipetype
= "ISOC"; break;
184 default: pipetype
= "????"; break;
186 printk(KERN_INFO
" Speed: %s\n",
188 switch (urb
->dev
->speed
) {
189 case USB_SPEED_HIGH
: speed
= "HS"; break;
190 case USB_SPEED_FULL
: speed
= "FS"; break;
191 case USB_SPEED_LOW
: speed
= "LS"; break;
192 default: speed
= "????"; break;
194 printk(KERN_INFO
" Max packet size: %d\n",
195 usb_maxpacket(urb
->dev
, urb
->pipe
, usb_pipeout(urb
->pipe
)));
196 printk(KERN_INFO
" Data buffer length: %d/%d\n",urb
->actual_length
, urb
->transfer_buffer_length
);
197 printk(KERN_INFO
" Transfer buffer: %p, Transfer DMA: %p\n",
198 urb
->transfer_buffer
, (void *)urb
->transfer_dma
);
199 printk(KERN_INFO
" Setup buffer: %p, Setup DMA: %p\n",
200 urb
->setup_packet
, (void *)urb
->setup_dma
);
201 printk(KERN_INFO
" Interval: %d\n", urb
->interval
);
205 switch (urbd
->status
)
207 case HC_XFER_NO_HALT_STATUS
:
208 printk(KERN_INFO
" STATUS:HC_XFER_NO_HALT_STATUS\n");break;
209 case HC_XFER_URB_COMPLETE
:
210 printk(KERN_INFO
" STATUS:HC_XFER_URB_COMPLETE\n");break;
211 case HC_XFER_AHB_ERR
:
212 printk(KERN_INFO
" STATUS:HC_XFER_AHB_ERR\n");break;
214 printk(KERN_INFO
" STATUS:HC_XFER_STALL\n");break;
215 case HC_XFER_BABBLE_ERR
:
216 printk(KERN_INFO
" STATUS:HC_XFER_BABBLE_ERR\n");break;
217 case HC_XFER_XACT_ERR
:
218 printk(KERN_INFO
" STATUS:HC_XFER_XACT_ERR\n");break;
219 case HC_XFER_URB_DEQUEUE
:
220 printk(KERN_INFO
" STATUS:HC_XFER_URB_DEQUEUE\n");break;
221 case HC_XFER_FRAME_OVERRUN
:
222 printk(KERN_INFO
" STATUS:HC_XFER_FRAME_OVERRUN\n");break;
223 case HC_XFER_DATA_TOGGLE_ERR
:
224 printk(KERN_INFO
" STATUS:HC_XFER_DATA_TOGGLE_ERR\n");break;
225 case HC_XFER_COMPLETE
:
226 printk(KERN_INFO
" STATUS:HC_XFER_COMPLETE\n");break;
228 printk(KERN_INFO
" STATUS:UNKKNOWN %d\n",urbd
->status
);break;
235 \fn static void release_channel(ifxhcd_hcd_t *_ifxhcd,
237 ifxhcd_halt_status_e _halt_status)
238 \brief Release the halted channel.
239 \param _ifxhcd Pointer to the sate of HCD structure
240 \param _ifxhc Pointer to host channel descriptor
241 \param _halt_status Halt satus
246 static void release_channel(ifxhcd_hcd_t
*_ifxhcd
,
248 ifxhcd_halt_status_e _halt_status
)
250 ifxusb_hc_regs_t
*hc_regs
= _ifxhcd
->core_if
.hc_regs
[_ifxhc
->hc_num
];
251 struct urb
*urb
= NULL
;
252 ifxhcd_epqh_t
*epqh
= NULL
;
253 ifxhcd_urbd_t
*urbd
= NULL
;
255 IFX_DEBUGPL(DBG_HCDV
, " %s: channel %d, halt_status %d\n",
256 __func__
, _ifxhc
->hc_num
, _halt_status
);
262 if(_halt_status
!=HC_XFER_NO_EPQH
)
263 IFX_ERROR("%s epqh=null\n",__func__
);
269 IFX_ERROR("%s urbd=null\n",__func__
);
275 if(_halt_status
!=HC_XFER_NO_URB
)
276 IFX_ERROR("%s urb =null\n",__func__
);
280 if (read_data_toggle(hc_regs
) == IFXUSB_HCTSIZ_DATA0
)
281 usb_settoggle (urb
->dev
,usb_pipeendpoint (urb
->pipe
), (_ifxhc
->is_in
)?0:1,0);
282 else if (read_data_toggle(hc_regs
) == IFXUSB_HCTSIZ_DATA1
)
283 usb_settoggle (urb
->dev
,usb_pipeendpoint (urb
->pipe
), (_ifxhc
->is_in
)?0:1,1);
288 switch (_halt_status
)
290 case HC_XFER_NO_HALT_STATUS
:
291 IFX_ERROR("%s: No halt_status, channel %d\n", __func__
, _ifxhc
->hc_num
);
294 case HC_XFER_COMPLETE
:
295 IFX_ERROR("%s: Inavalid halt_status HC_XFER_COMPLETE, channel %d\n", __func__
, _ifxhc
->hc_num
);
300 case HC_XFER_NO_EPQH
:
302 case HC_XFER_URB_DEQUEUE
:
303 case HC_XFER_AHB_ERR
:
304 case HC_XFER_XACT_ERR
:
305 case HC_XFER_FRAME_OVERRUN
:
308 urbd
->phase
=URBD_DEQUEUEING
;
309 ifxhcd_complete_urb(_ifxhcd
, urbd
, urbd
->status
);
313 IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__
,__LINE__
,urbd
,urb
);
314 release_channel_dump(_ifxhc
,urb
,epqh
,urbd
,_halt_status
);
317 case HC_XFER_URB_COMPLETE
:
320 urbd
->phase
=URBD_COMPLETING
;
321 ifxhcd_complete_urb(_ifxhcd
, urbd
, urbd
->status
);
325 IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__
,__LINE__
,urbd
,urb
);
326 release_channel_dump(_ifxhc
,urb
,epqh
,urbd
,_halt_status
);
332 urbd
->phase
=URBD_DEQUEUEING
;
333 ifxhcd_complete_urb(_ifxhcd
, urbd
, -EPIPE
);
337 IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__
,__LINE__
,urbd
,urb
);
338 release_channel_dump(_ifxhc
,urb
,epqh
,urbd
,_halt_status
);
340 if(epqh
&& urb
&& urb
->dev
&& urb
->pipe
)
341 usb_settoggle(urb
->dev
, usb_pipeendpoint (urb
->pipe
), !usb_pipein(urb
->pipe
), IFXUSB_HC_PID_DATA0
);
343 case HC_XFER_BABBLE_ERR
:
344 case HC_XFER_DATA_TOGGLE_ERR
:
347 urbd
->phase
=URBD_DEQUEUEING
;
348 ifxhcd_complete_urb(_ifxhcd
, urbd
, -EOVERFLOW
);
352 IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__
,__LINE__
,urbd
,urb
);
353 release_channel_dump(_ifxhc
,urb
,epqh
,urbd
,_halt_status
);
362 urbd
->phase
=URBD_COMPLETING
;
363 ifxhcd_complete_urb(_ifxhcd
, urbd
, 0);
367 IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__
,__LINE__
,urbd
,urb
);
368 release_channel_dump(_ifxhc
,urb
,epqh
,urbd
,_halt_status
);
373 IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__
,__LINE__
,urbd
,urb
);
374 release_channel_dump(_ifxhc
,urb
,epqh
,urbd
,_halt_status
);
378 #if defined(__INTRNAKRETRY__) || defined(__INTRINCRETRY__)
379 case HC_XFER_INTR_NAK_RETRY
:
380 epqh
->phase
=EPQH_READY
;
381 urbd
->phase
=URBD_IDLE
;
382 ifxhcd_hc_cleanup(&_ifxhcd
->core_if
, _ifxhc
);
391 ifxhcd_epqh_idle(epqh
);
393 else if(_halt_status
!=HC_XFER_NO_EPQH
)
395 IFX_WARN("WARNING %s():%d epqh=%p\n",__func__
,__LINE__
,epqh
);
396 release_channel_dump(_ifxhc
,urb
,epqh
,urbd
,_halt_status
);
398 ifxhcd_hc_cleanup(&_ifxhcd
->core_if
, _ifxhc
);
403 * Updates the state of the URB after a Transfer Complete interrupt on the
404 * host channel. Updates the actual_length field of the URB based on the
405 * number of bytes transferred via the host channel. Sets the URB status
406 * if the data transfer is finished.
408 * @return 1 if the data transfer specified by the URB is completely finished,
411 static int update_urb_state_xfer_comp(ifxhcd_hc_t
*_ifxhc
,
412 ifxusb_hc_regs_t
*_hc_regs
,
414 ifxhcd_urbd_t
*_urbd
)
419 if(_urbd
->epqh
->ep_type
==IFXUSB_EP_TYPE_ISOC
)
421 struct usb_iso_packet_descriptor
*frame_desc
;
422 frame_desc
= &_urb
->iso_frame_desc
[_urbd
->isoc_frame_index
];
425 hctsiz_data_t hctsiz
;
426 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
427 frame_desc
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
428 if ((hctsiz
.b
.xfersize
!= 0) || (frame_desc
->actual_length
>= _urbd
->xfer_len
))
431 frame_desc
->status
= 0;
433 if (frame_desc
->actual_length
< frame_desc
->length
&& _urb
->transfer_flags
& URB_SHORT_NOT_OK
)
434 frame_desc
->status
= -EREMOTEIO
;
441 frame_desc
->actual_length
+= _ifxhc
->ssplit_out_xfer_count
;
443 frame_desc
->actual_length
+= _ifxhc
->xfer_len
;
444 if (frame_desc
->actual_length
>= _urbd
->xfer_len
)
447 frame_desc
->status
= 0;
455 hctsiz_data_t hctsiz
;
456 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
457 _urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
458 #ifdef __INTRINCRETRY__
459 if(_urbd
->epqh
->ep_type
==IFXUSB_EP_TYPE_INTR
)
461 if(_ifxhc
->xfer_len
!= hctsiz
.b
.xfersize
)
469 if ((hctsiz
.b
.xfersize
!= 0) || (_urb
->actual_length
>= _urb
->transfer_buffer_length
))
473 if(_urb
->transfer_flags
& URB_SHORT_NOT_OK
)
475 if (_urb
->actual_length
< _urb
->transfer_buffer_length
)
476 _urbd
->status
= -EREMOTEIO
;
480 else if(_urb
->transfer_buffer_length
%_ifxhc
->mps
) // OUT without ZLP
483 _urb
->actual_length
+= _ifxhc
->ssplit_out_xfer_count
;
485 _urb
->actual_length
+= _ifxhc
->xfer_len
;
486 if (_urb
->actual_length
>= _urb
->transfer_buffer_length
)
492 else if (_urb
->actual_length
>= _urb
->transfer_buffer_length
) //OUT with ZLP
497 else //OUT without ZLP, unfinished
500 _urb
->actual_length
+= _ifxhc
->ssplit_out_xfer_count
;
502 _urb
->actual_length
+= _ifxhc
->xfer_len
;
503 if (!_ifxhc
->short_rw
&& _urb
->actual_length
>= _urb
->transfer_buffer_length
)
512 hctsiz_data_t hctsiz
;
513 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
514 IFX_DEBUGPL(DBG_HCDV
, "IFXUSB: %s: %s, channel %d\n",
515 __func__
, (_ifxhc
->is_in
? "IN" : "OUT"), _ifxhc
->hc_num
);
516 IFX_DEBUGPL(DBG_HCDV
, " hc->xfer_len %d\n", _ifxhc
->xfer_len
);
517 IFX_DEBUGPL(DBG_HCDV
, " hctsiz.xfersize %d\n", hctsiz
.b
.xfersize
);
519 if(_urbd
->epqh
->ep_type
==IFXUSB_EP_TYPE_ISOC
)
521 IFX_DEBUGPL(DBG_HCDV
, " descritor # %d\n", _urbd
->isoc_frame_index
);
522 IFX_DEBUGPL(DBG_HCDV
, " buffer_length %d\n",
523 _urb
->iso_frame_desc
[_urbd
->isoc_frame_index
].length
);
524 IFX_DEBUGPL(DBG_HCDV
, " actual_length %d\n", _urb
->iso_frame_desc
[_urbd
->isoc_frame_index
].actual_length
);
529 IFX_DEBUGPL(DBG_HCDV
, " urb->transfer_buffer_length %d\n",
530 _urb
->transfer_buffer_length
);
531 IFX_DEBUGPL(DBG_HCDV
, " urb->actual_length %d\n", _urb
->actual_length
);
539 static void next_isoc_sub(unsigned long data
)
542 ifxhcd_hcd_t
*ifxhcd
;
544 urbd
=((ifxhcd_urbd_t
*)data
);
545 ifxhcd
=urbd
->epqh
->ifxhcd
;
548 IFX_ERROR("%s: invalid epqd\n",__func__
);
549 #if defined(__UNALIGNED_BUF_ADJ__)
552 if( urbd
->aligned_checked
&&
553 // urbd->using_aligned_buf &&
560 buf
+=urbd
->urb
->iso_frame_desc
[urbd
->isoc_frame_index
].offset
;
561 memcpy(buf
,urbd
->aligned_buf
,urbd
->urb
->iso_frame_desc
[urbd
->isoc_frame_index
].length
);
563 // urbd->using_aligned_buf=0;
564 // urbd->using_aligned_setup=0;
568 urbd
->isoc_frame_index
++;
569 if(urbd
->isoc_frame_index
>=urbd
->urb
->number_of_packets
)
570 release_channel(ifxhcd
,urbd
->epqh
->hc
,HC_XFER_URB_COMPLETE
);
577 \fn static void complete_channel(ifxhcd_hcd_t *_ifxhcd,
579 ifxhcd_urbd_t *_urbd)
580 \brief Complete the transaction on the channel.
581 \param _ifxhcd Pointer to the sate of HCD structure
582 \param _ifxhc Pointer to host channel descriptor
583 \param _urbd Pointer to URB descriptor
587 static void complete_channel(ifxhcd_hcd_t
*_ifxhcd
,
589 ifxhcd_urbd_t
*_urbd
)
591 ifxusb_hc_regs_t
*hc_regs
= _ifxhcd
->core_if
.hc_regs
[_ifxhc
->hc_num
];
592 struct urb
*urb
= NULL
;
593 ifxhcd_epqh_t
*epqh
= NULL
;
596 IFX_DEBUGPL(DBG_HCD
, "--Complete Channel %d : \n", _ifxhc
->hc_num
);
600 IFX_ERROR("ERROR %s():%d urbd=%p\n",__func__
,__LINE__
,_urbd
);
609 release_channel(_ifxhcd
,_ifxhc
,HC_XFER_NO_EPQH
);
612 if(!urb
|| (unsigned long)urb
->hcpriv
!=(unsigned long)_urbd
)
614 release_channel(_ifxhcd
,_ifxhc
,HC_XFER_NO_URB
);
621 switch (epqh
->ep_type
)
623 case IFXUSB_EP_TYPE_CTRL
:
624 switch (_ifxhc
->control_phase
)
626 case IFXHCD_CONTROL_SETUP
:
627 if (_urbd
->xfer_len
> 0)
629 _ifxhc
->control_phase
= IFXHCD_CONTROL_DATA
;
630 IFX_DEBUGPL(DBG_HCDV
, " Control setup transaction done Data Stage now\n");
631 _ifxhc
->is_in
= _urbd
->is_in
;
632 _ifxhc
->xfer_len
= _urbd
->xfer_len
;
633 #if defined(__UNALIGNED_BUF_ADJ__)
634 if(_urbd
->aligned_buf
)
635 _ifxhc
->xfer_buff
= _urbd
->aligned_buf
;
638 _ifxhc
->xfer_buff
= _urbd
->xfer_buff
;
642 #ifdef __INNAKSTOP_CTRL__
646 #ifdef __PINGSTOP_CTRL__
655 IFX_DEBUGPL(DBG_HCDV
, " Control setup transaction done Status Stage now\n");
656 _ifxhc
->control_phase
= IFXHCD_CONTROL_STATUS
;
658 _ifxhc
->xfer_len
= 0;
659 _ifxhc
->xfer_buff
= _ifxhcd
->status_buf
;
667 _ifxhc
->short_rw
=(urb
->transfer_flags
& URB_ZERO_PACKET
)?1:0;
668 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA1
;
669 _ifxhc
->xfer_count
= 0;
670 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
671 _ifxhc
->phase
=HC_WAITING
;
672 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
674 case IFXHCD_CONTROL_DATA
:
675 urb_xfer_done
= update_urb_state_xfer_comp(_ifxhc
, hc_regs
, urb
, _urbd
);
678 _ifxhc
->control_phase
= IFXHCD_CONTROL_STATUS
;
679 IFX_DEBUGPL(DBG_HCDV
, " Control data transaction done Status Stage now\n");
680 _ifxhc
->is_in
= (_urbd
->is_in
)?0:1;
681 _ifxhc
->xfer_len
= 0;
682 _ifxhc
->xfer_count
= 0;
683 _ifxhc
->xfer_buff
= _ifxhcd
->status_buf
;
684 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
685 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA1
;
696 IFX_DEBUGPL(DBG_HCDV
, " Control data transaction continue\n");
697 _ifxhc
->xfer_len
= _urbd
->xfer_len
- urb
->actual_length
;
698 _ifxhc
->xfer_count
= urb
->actual_length
;
699 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
700 _ifxhc
->data_pid_start
= read_data_toggle(hc_regs
);
702 _ifxhc
->phase
=HC_WAITING
;
703 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
705 case IFXHCD_CONTROL_STATUS
:
706 IFX_DEBUGPL(DBG_HCDV
, " Control status transaction done\n");
707 if (_urbd
->status
== -EINPROGRESS
)
709 release_channel(_ifxhcd
,_ifxhc
,HC_XFER_URB_COMPLETE
);
713 case IFXUSB_EP_TYPE_BULK
:
714 IFX_DEBUGPL(DBG_HCDV
, " Bulk transfer complete\n");
715 urb_xfer_done
= update_urb_state_xfer_comp(_ifxhc
, hc_regs
, urb
, _urbd
);
717 release_channel(_ifxhcd
,_ifxhc
,HC_XFER_URB_COMPLETE
);
720 _ifxhc
->xfer_len
= _urbd
->xfer_len
- urb
->actual_length
;
721 _ifxhc
->xfer_count
= urb
->actual_length
;
722 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
723 _ifxhc
->data_pid_start
= read_data_toggle(hc_regs
);
724 _ifxhc
->phase
=HC_WAITING
;
725 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
728 case IFXUSB_EP_TYPE_INTR
:
729 urb_xfer_done
= update_urb_state_xfer_comp(_ifxhc
, hc_regs
, urb
, _urbd
);
731 #ifdef __INTRINCRETRY__
733 release_channel(_ifxhcd
,_ifxhc
,HC_XFER_INTR_NAK_RETRY
);
736 release_channel(_ifxhcd
,_ifxhc
,HC_XFER_URB_COMPLETE
);
738 case IFXUSB_EP_TYPE_ISOC
:
740 urb_xfer_done
= update_urb_state_xfer_comp(_ifxhc
, hc_regs
, urb
, _urbd
);
743 #if defined(__UNALIGNED_BUF_ADJ__)
746 if(!epqh
->tasklet_next_isoc
.func
)
748 epqh
->tasklet_next_isoc
.next
= NULL
;
749 epqh
->tasklet_next_isoc
.state
= 0;
750 atomic_set( &epqh
->tasklet_next_isoc
.count
, 0);
751 epqh
->tasklet_next_isoc
.func
= next_isoc_sub
;
752 epqh
->tasklet_next_isoc
.data
= (unsigned long)_urbd
;
754 tasklet_schedule(&epqh
->tasklet_next_isoc
);
759 next_isoc_sub((unsigned long)_urbd
);
764 struct usb_iso_packet_descriptor
*frame_desc
;
765 frame_desc
= &urb
->iso_frame_desc
[_urbd
->isoc_frame_index
];
766 _ifxhc
->xfer_len
= _urbd
->xfer_len
- frame_desc
->actual_length
;
767 _ifxhc
->xfer_count
= frame_desc
->actual_length
;
768 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
769 _ifxhc
->data_pid_start
= read_data_toggle(hc_regs
);
770 _ifxhc
->phase
=HC_WAITING
;
771 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
780 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
781 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
782 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
783 static int32_t chhltd_ctrl_rx_nonsplit(ifxhcd_hcd_t
*_ifxhcd
,
785 ifxusb_hc_regs_t
*_hc_regs
,
786 ifxhcd_urbd_t
*_urbd
)
789 hcint_data_t hcintmsk
;
790 hctsiz_data_t hctsiz
;
792 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
793 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
794 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
796 disable_hc_int(_hc_regs
,ack
);
797 disable_hc_int(_hc_regs
,nak
);
798 disable_hc_int(_hc_regs
,nyet
);
800 #ifdef __INNAKSTOP_CTRL__
801 if (_ifxhc
->halt_status
== HC_XFER_NAK
)
803 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
806 actual_length
= _urbd
->urb
->actual_length
+ (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
808 if(_urbd
->xfer_len
&& actual_length
>= _urbd
->xfer_len
)
810 _urbd
->error_count
=0;
811 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
816 _urbd
->urb
->actual_length
= actual_length
;
817 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
818 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
819 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
820 _ifxhc
->phase
=HC_WAITING
;
821 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
826 printk(KERN_INFO
"Warning: %s() %d Invalid CTRL Phase:%d\n",__func__
,__LINE__
,_ifxhc
->control_phase
);
827 release_channel(_ifxhcd
, _ifxhc
, _ifxhc
->halt_status
);
833 if (hcint
.b
.xfercomp
|| hcint
.d32
== 0x02)
835 _urbd
->error_count
=0;
836 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
839 else if (hcint
.b
.stall
)
841 _urbd
->error_count
=0;
844 if(hctsiz
.b
.pktcnt
==0)
845 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
849 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_STATUS
)
850 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
854 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
855 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
856 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
857 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
861 else if (hcint
.b
.bblerr
)
863 _urbd
->error_count
=0;
867 if(hctsiz
.b
.pktcnt
==0)
868 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
872 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_STATUS
)
873 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
877 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
878 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
879 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
880 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
884 else if (hcint
.b
.xacterr
)
888 if(hctsiz
.b
.pktcnt
==0)
890 _urbd
->error_count
=0;
891 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
896 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_STATUS
)
898 _urbd
->error_count
=0;
899 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
903 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
906 _urbd
->error_count
=0;
907 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
910 actual_length
= _urbd
->urb
->actual_length
+ (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
911 if(actual_length
>= _urbd
->xfer_len
)
913 _urbd
->error_count
=0;
914 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
918 _urbd
->error_count
++;
920 _urbd
->urb
->actual_length
= actual_length
;
921 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
922 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
923 if (_urbd
->error_count
>= 3)
925 _urbd
->error_count
=0;
926 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
931 _ifxhc
->phase
=HC_WAITING
;
932 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
939 _urbd
->error_count
=0;
940 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
944 else if(hcint
.b
.datatglerr
)
948 _urbd
->error_count
=0;
949 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
952 actual_length
= _urbd
->urb
->actual_length
+ (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
953 if(actual_length
>=_urbd
->xfer_len
)
955 _urbd
->error_count
=0;
956 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
960 _urbd
->urb
->actual_length
= actual_length
;
961 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
962 _urbd
->error_count
=0;
963 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
967 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
968 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
969 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
970 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
974 else if(hcint
.b
.frmovrun
)
976 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
977 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
978 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
979 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
984 _urbd
->error_count
=0;
985 IFX_ERROR("ERROR %s():%d invalid chhlt condition %08X/%08X %d\n",__func__
,__LINE__
,hcint
.d32
,hcintmsk
.d32
,_ifxhc
->halt_status
);
986 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
992 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
993 static int32_t chhltd_ctrl_tx_nonsplit(ifxhcd_hcd_t
*_ifxhcd
,
995 ifxusb_hc_regs_t
*_hc_regs
,
996 ifxhcd_urbd_t
*_urbd
)
999 hcint_data_t hcintmsk
;
1000 hctsiz_data_t hctsiz
;
1002 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
1003 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
1004 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
1006 disable_hc_int(_hc_regs
,ack
);
1007 disable_hc_int(_hc_regs
,nak
);
1008 disable_hc_int(_hc_regs
,nyet
);
1010 #ifdef __PINGSTOP_CTRL__
1011 if (_ifxhc
->halt_status
== HC_XFER_NAK
)
1013 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
1016 actual_length
= _urbd
->urb
->actual_length
+ ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1018 if(_urbd
->xfer_len
&& actual_length
>= _urbd
->xfer_len
)
1020 _urbd
->error_count
=0;
1021 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1025 _ifxhc
->xfer_count
=
1026 _urbd
->urb
->actual_length
= actual_length
;
1027 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
1028 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1029 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
1030 _ifxhc
->phase
=HC_WAITING
;
1031 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1036 printk(KERN_INFO
"Warning: %s() %d Invalid CTRL Phase:%d\n",__func__
,__LINE__
,_ifxhc
->control_phase
);
1037 release_channel(_ifxhcd
, _ifxhc
, _ifxhc
->halt_status
);
1044 if (hcint
.b
.xfercomp
|| hcint
.d32
== 0x02)
1046 _urbd
->error_count
=0;
1047 if(_ifxhc
->xfer_len
==0 && !hcint
.b
.ack
&& hcint
.b
.nak
)
1049 // Walkaround: When sending ZLP and receive NAK but also issue CMPT intr
1050 // Solution: NoSplit: Resend at next SOF
1051 // Split : Resend at next SOF with SSPLIT
1053 _ifxhc
->epqh
->do_ping
=1;
1055 _ifxhc
->xfer_len
= 0;
1056 _ifxhc
->xfer_count
= 0;
1057 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
1058 _ifxhc
->phase
=HC_WAITING
;
1059 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1064 _ifxhc
->epqh
->do_ping
=1;
1065 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1069 else if (hcint
.b
.stall
)
1071 _urbd
->error_count
=0;
1075 if(hctsiz
.b
.pktcnt
==0)
1076 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1080 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
1082 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1083 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
1085 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
1089 else if (hcint
.b
.xacterr
)
1093 if(hctsiz
.b
.pktcnt
==0)
1095 _urbd
->error_count
=0;
1096 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1100 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_STATUS
)
1102 _urbd
->error_count
=0;
1103 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1105 else if(_ifxhc
->control_phase
== IFXHCD_CONTROL_SETUP
)
1107 _urbd
->error_count
=0;
1108 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1110 else if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
1113 _urbd
->error_count
=0;
1114 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1117 actual_length
= _urbd
->urb
->actual_length
+ ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1118 if(actual_length
>=_urbd
->xfer_len
)
1120 _urbd
->error_count
=0;
1121 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1125 _urbd
->error_count
++;
1126 _ifxhc
->xfer_count
=
1127 _urbd
->urb
->actual_length
= actual_length
;
1128 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
1129 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1130 if (_urbd
->error_count
>= 3)
1132 _urbd
->error_count
=0;
1133 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1138 _ifxhc
->phase
=HC_WAITING
;
1139 _ifxhc
->epqh
->do_ping
=1;
1140 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1147 _urbd
->error_count
=0;
1148 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1152 else if(hcint
.b
.bblerr
)
1154 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
1156 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1157 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
1159 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
1162 else if(hcint
.b
.nak
|| hcint
.b
.nyet
)
1164 #ifdef __PINGSTOP_CTRL__
1165 _urbd
->error_count
=0;
1166 IFX_ERROR("ERROR %s():%d invalid chhlt condition\n",__func__
,__LINE__
);
1167 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1171 if(hctsiz
.b
.pktcnt
==0)
1173 _urbd
->error_count
=0;
1174 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1178 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_STATUS
)
1180 _urbd
->error_count
=0;
1181 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1183 else if(_ifxhc
->control_phase
== IFXHCD_CONTROL_SETUP
)
1185 _urbd
->error_count
=0;
1186 IFX_ERROR("ERROR %s():%d invalid chhlt condition\n",__func__
,__LINE__
);
1187 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1189 else if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
1192 _ifxhc
->epqh
->do_ping
=1;
1193 _urbd
->error_count
=0;
1194 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1197 _ifxhc
->epqh
->do_ping
=1;
1198 actual_length
= _urbd
->urb
->actual_length
+ ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1199 if(actual_length
>=_urbd
->xfer_len
)
1201 _urbd
->error_count
=0;
1202 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1206 _ifxhc
->xfer_count
=
1207 _urbd
->urb
->actual_length
= actual_length
;
1208 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
1209 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1211 _ifxhc
->epqh
->do_ping
=1;
1212 _ifxhc
->phase
=HC_WAITING
;
1213 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1220 else if(hcint
.b
.datatglerr
)
1222 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
1224 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1225 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
1227 _urbd
->error_count
=0;
1228 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
1231 else if(hcint
.b
.frmovrun
)
1233 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
1235 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1236 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
1238 _urbd
->error_count
=0;
1239 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
1244 _urbd
->error_count
=0;
1245 IFX_ERROR("ERROR %s():%d invalid chhlt condition %08X/%08X %d\n",__func__
,__LINE__
,hcint
.d32
,hcintmsk
.d32
,_ifxhc
->halt_status
);
1246 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1251 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1252 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1253 static int32_t chhltd_bulk_rx_nonsplit(ifxhcd_hcd_t
*_ifxhcd
,
1254 ifxhcd_hc_t
*_ifxhc
,
1255 ifxusb_hc_regs_t
*_hc_regs
,
1256 ifxhcd_urbd_t
*_urbd
)
1259 hcint_data_t hcintmsk
;
1260 hctsiz_data_t hctsiz
;
1262 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
1263 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
1264 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
1266 disable_hc_int(_hc_regs
,ack
);
1267 disable_hc_int(_hc_regs
,nak
);
1268 disable_hc_int(_hc_regs
,nyet
);
1270 #ifdef __INNAKSTOP_BULK__
1271 if(_ifxhc
->halt_status
== HC_XFER_NAK
)
1274 actual_length
= _urbd
->urb
->actual_length
+ (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1277 (_urbd
->xfer_len
&& actual_length
>=_urbd
->xfer_len
)
1278 || hctsiz
.b
.pktcnt
==0
1279 || (hctsiz
.b
.xfersize
% _ifxhc
->mps
)>0
1282 _urbd
->error_count
=0;
1283 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1287 _urbd
->urb
->actual_length
= actual_length
;
1288 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
1289 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
1290 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1291 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
1292 _ifxhc
->phase
=HC_WAITING
;
1293 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1299 if (hcint
.b
.xfercomp
|| hcint
.d32
== 0x02)
1301 _urbd
->error_count
=0;
1302 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1305 else if (hcint
.b
.stall
)
1307 _urbd
->error_count
=0;
1310 if(hctsiz
.b
.pktcnt
==0)
1311 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1315 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1316 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
1320 else if (hcint
.b
.bblerr
)
1322 _urbd
->error_count
=0;
1326 if(hctsiz
.b
.pktcnt
==0)
1327 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1331 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1332 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
1336 else if (hcint
.b
.xacterr
)
1340 if(hctsiz
.b
.pktcnt
==0)
1342 _urbd
->error_count
=0;
1343 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1349 _urbd
->error_count
=0;
1350 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1353 actual_length
= _urbd
->urb
->actual_length
+ (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1354 if(actual_length
>= _urbd
->xfer_len
)
1356 _urbd
->error_count
=0;
1357 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1361 _urbd
->error_count
++;
1362 _ifxhc
->xfer_count
=
1363 _urbd
->urb
->actual_length
= actual_length
;
1364 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
1365 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1366 if (_urbd
->error_count
>= 3)
1368 _urbd
->error_count
=0;
1369 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1374 _ifxhc
->phase
=HC_WAITING
;
1375 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1382 else if(hcint
.b
.datatglerr
)
1386 _urbd
->error_count
=0;
1387 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1390 actual_length
= _urbd
->urb
->actual_length
+ (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1391 if(actual_length
>= _urbd
->xfer_len
)
1393 _urbd
->error_count
=0;
1394 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1398 _urbd
->urb
->actual_length
= actual_length
;
1399 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1400 _urbd
->error_count
=0;
1401 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
1405 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1406 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
1407 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
1411 else if(hcint
.b
.frmovrun
)
1413 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
1414 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
1419 _urbd
->error_count
=0;
1420 IFX_ERROR("ERROR %s():%d invalid chhlt condition %08X/%08X %d sz:%d/%d/%d/%d\n",__func__
,__LINE__
,hcint
.d32
,hcintmsk
.d32
,_ifxhc
->halt_status
, hctsiz
.b
.xfersize
, _ifxhc
->xfer_len
-_ifxhc
->xfer_len
,_ifxhc
->xfer_len
,_urbd
->xfer_len
);
1421 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1426 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1427 static int32_t chhltd_bulk_tx_nonsplit(ifxhcd_hcd_t
*_ifxhcd
,
1428 ifxhcd_hc_t
*_ifxhc
,
1429 ifxusb_hc_regs_t
*_hc_regs
,
1430 ifxhcd_urbd_t
*_urbd
)
1433 hcint_data_t hcintmsk
;
1434 hctsiz_data_t hctsiz
;
1435 int out_nak_enh
= 0;
1437 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
1440 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
1441 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
1442 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
1443 disable_hc_int(_hc_regs
,ack
);
1444 disable_hc_int(_hc_regs
,nak
);
1445 disable_hc_int(_hc_regs
,nyet
);
1447 #ifdef __PINGSTOP_BULK__
1448 if (_ifxhc
->halt_status
== HC_XFER_NAK
)
1451 actual_length
= _urbd
->urb
->actual_length
+ ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1453 if(_urbd
->xfer_len
&& actual_length
>= _urbd
->xfer_len
)
1455 _urbd
->error_count
=0;
1456 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1460 _ifxhc
->xfer_count
=
1461 _urbd
->urb
->actual_length
= actual_length
;
1462 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
1463 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1464 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
1465 _ifxhc
->phase
=HC_WAITING
;
1466 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1472 if (hcint
.b
.xfercomp
|| hcint
.d32
== 0x02)
1474 _urbd
->error_count
=0;
1475 if(_ifxhc
->xfer_len
==0 && !hcint
.b
.ack
&& hcint
.b
.nak
)
1477 // Walkaround: When sending ZLP and receive NAK but also issue CMPT intr
1478 // Solution: NoSplit: Resend at next SOF
1479 // Split : Resend at next SOF with SSPLIT
1481 _ifxhc
->epqh
->do_ping
=1;
1483 _ifxhc
->xfer_len
= 0;
1484 _ifxhc
->xfer_count
= 0;
1485 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
1486 _ifxhc
->phase
=HC_WAITING
;
1487 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1492 _ifxhc
->epqh
->do_ping
=1;
1493 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1497 else if (hcint
.b
.stall
)
1499 _urbd
->error_count
=0;
1503 if(hctsiz
.b
.pktcnt
==0)
1504 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1508 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1509 if(_urbd
->urb
->actual_length
>_urbd
->xfer_len
) _urbd
->urb
->actual_length
=_urbd
->xfer_len
;
1510 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
1514 else if (hcint
.b
.xacterr
)
1518 if(hctsiz
.b
.pktcnt
==0)
1520 _urbd
->error_count
=0;
1521 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1527 _urbd
->error_count
=0;
1528 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1531 actual_length
= _urbd
->urb
->actual_length
+ ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1532 if(actual_length
>= _urbd
->xfer_len
)
1534 _urbd
->error_count
=0;
1535 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1539 _urbd
->error_count
++;
1540 _ifxhc
->xfer_count
=
1541 _urbd
->urb
->actual_length
= actual_length
;
1542 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
1543 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1544 if (_urbd
->error_count
>= 3)
1546 _urbd
->error_count
=0;
1547 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1552 _ifxhc
->phase
=HC_WAITING
;
1553 _ifxhc
->epqh
->do_ping
=1;
1554 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1561 else if(hcint
.b
.bblerr
)
1563 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1564 if(_urbd
->urb
->actual_length
>_urbd
->xfer_len
) _urbd
->urb
->actual_length
=_urbd
->xfer_len
;
1565 IFX_ERROR("ERROR %s():%d invalid packet babble\n",__func__
,__LINE__
);
1566 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
1569 else if(hcint
.b
.nak
|| hcint
.b
.nyet
)
1571 #ifdef __PINGSTOP_BULK__
1572 _urbd
->error_count
=0;
1573 IFX_ERROR("ERROR %s():%d invalid chhlt condition\n",__func__
,__LINE__
);
1574 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1578 if(hctsiz
.b
.pktcnt
==0)
1580 _urbd
->error_count
=0;
1581 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1587 _ifxhc
->epqh
->do_ping
=1;
1588 _urbd
->error_count
=0;
1589 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1592 _ifxhc
->epqh
->do_ping
=1;
1593 actual_length
= _urbd
->urb
->actual_length
+ ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1594 if(actual_length
>=_urbd
->xfer_len
)
1596 _urbd
->error_count
=0;
1597 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1601 _ifxhc
->xfer_count
=
1602 _urbd
->urb
->actual_length
= actual_length
;
1603 _ifxhc
->xfer_len
= _urbd
->xfer_len
- actual_length
;
1604 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1606 _ifxhc
->epqh
->do_ping
=1;
1607 _ifxhc
->phase
=HC_WAITING
;
1608 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1615 else if(hcint
.b
.datatglerr
)
1617 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1618 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
1619 _urbd
->error_count
=0;
1620 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
1623 else if(hcint
.b
.frmovrun
)
1625 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1626 // if( _urbd->urb->actual_length > _ifxhc->xfer_len) _urbd->urb->actual_length = _urbd->xfer_len;
1627 _urbd
->error_count
=0;
1628 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
1633 _urbd
->error_count
=0;
1634 IFX_ERROR("ERROR %s():%d invalid chhlt condition %08X/%08X %d\n",__func__
,__LINE__
,hcint
.d32
,hcintmsk
.d32
,_ifxhc
->halt_status
);
1635 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1640 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1641 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1642 static int32_t chhltd_intr_rx_nonsplit(ifxhcd_hcd_t
*_ifxhcd
,
1643 ifxhcd_hc_t
*_ifxhc
,
1644 ifxusb_hc_regs_t
*_hc_regs
,
1645 ifxhcd_urbd_t
*_urbd
)
1648 hcint_data_t hcintmsk
;
1649 hctsiz_data_t hctsiz
;
1651 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
1652 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
1653 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
1654 disable_hc_int(_hc_regs
,ack
);
1655 disable_hc_int(_hc_regs
,nak
);
1656 disable_hc_int(_hc_regs
,nyet
);
1658 if (hcint
.b
.xfercomp
|| hcint
.d32
== 0x02)
1660 _urbd
->error_count
=0;
1661 //restart INTR immediately
1662 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1665 else if (hcint
.b
.stall
)
1667 _urbd
->error_count
=0;
1669 // Don't care shortcut
1671 if(hctsiz
.b
.pktcnt
==0)
1672 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1676 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1677 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
1681 else if (hcint
.b
.bblerr
)
1683 _urbd
->error_count
=0;
1685 // Don't care shortcut
1687 if(hctsiz
.b
.pktcnt
==0)
1688 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1692 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1693 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
1697 else if (hcint
.b
.datatglerr
|| hcint
.b
.frmovrun
)
1699 _urbd
->error_count
=0;
1700 //restart INTR immediately
1701 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1704 else if (hcint
.b
.xacterr
)
1708 if(hctsiz
.b
.pktcnt
==0)
1710 _urbd
->error_count
=0;
1711 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1716 _urbd
->error_count
++;
1717 if(_urbd
->error_count
>=3)
1719 _urbd
->error_count
=0;
1720 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1724 _ifxhc
->phase
=HC_WAITING
;
1725 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1730 else if(hcint
.b
.nyet
)
1734 else if (hcint
.b
.nak
)
1737 #ifdef __INTRNAKRETRY__
1740 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_INTR_NAK_RETRY
);
1744 _urbd
->error_count
=0;
1745 //restart INTR immediately
1746 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1751 _urbd
->error_count
=0;
1752 //restart INTR immediately
1754 if(hctsiz
.b
.pktcnt
>0)
1756 // TODO Re-initialize Channel (in next b_interval - 1 uF/F)
1757 _ifxhc
->phase
=HC_WAITING
;
1758 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1763 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1770 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1771 static int32_t chhltd_intr_tx_nonsplit(ifxhcd_hcd_t
*_ifxhcd
,
1772 ifxhcd_hc_t
*_ifxhc
,
1773 ifxusb_hc_regs_t
*_hc_regs
,
1774 ifxhcd_urbd_t
*_urbd
)
1777 hcint_data_t hcintmsk
;
1778 hctsiz_data_t hctsiz
;
1779 int out_nak_enh
= 0;
1781 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
1784 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
1785 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
1786 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
1788 if (hcint
.b
.xfercomp
|| hcint
.d32
== 0x02)
1790 disable_hc_int(_hc_regs
,ack
);
1791 disable_hc_int(_hc_regs
,nak
);
1792 disable_hc_int(_hc_regs
,nyet
);
1793 _urbd
->error_count
=0;
1794 //restart INTR immediately
1795 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1798 else if (hcint
.b
.stall
)
1800 disable_hc_int(_hc_regs
,ack
);
1801 disable_hc_int(_hc_regs
,nyet
);
1802 disable_hc_int(_hc_regs
,nak
);
1803 _urbd
->error_count
=0;
1805 // Don't care shortcut
1807 if(hctsiz
.b
.pktcnt
==0)
1808 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1812 if(_ifxhc
->xfer_len
!=0)// !_ifxhc->is_in
1813 _urbd
->urb
->actual_length
+= ((_ifxhc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * _ifxhc
->mps
);
1814 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
1818 else if(hcint
.b
.nak
|| hcint
.b
.frmovrun
)
1820 disable_hc_int(_hc_regs
,ack
);
1821 disable_hc_int(_hc_regs
,nyet
);
1822 disable_hc_int(_hc_regs
,nak
);
1823 _urbd
->error_count
=0;
1824 //restart INTR immediately
1825 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1828 else if(hcint
.b
.xacterr
)
1832 if(hctsiz
.b
.pktcnt
==0)
1834 _urbd
->error_count
=0;
1835 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1840 _urbd
->error_count
++;
1841 if(_urbd
->error_count
>=3)
1843 _urbd
->error_count
=0;
1844 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1848 _ifxhc
->phase
=HC_WAITING
;
1849 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1854 else if(hcint
.b
.bblerr
)
1856 _urbd
->error_count
=0;
1857 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
1860 else if(hcint
.b
.datatglerr
)
1862 _urbd
->error_count
=0;
1863 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
1868 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1869 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1870 static int32_t chhltd_isoc_rx_nonsplit(ifxhcd_hcd_t
*_ifxhcd
,
1871 ifxhcd_hc_t
*_ifxhc
,
1872 ifxusb_hc_regs_t
*_hc_regs
,
1873 ifxhcd_urbd_t
*_urbd
)
1877 hcint_data_t hcintmsk
;
1878 hctsiz_data_t hctsiz
;
1880 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
1881 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
1882 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
1884 if (hcint
.b
.xfercomp
|| hcint
.b
.frmovrun
|| hcint
.d32
== 0x02)
1886 _urbd
->error_count
=0;
1887 disable_hc_int(_hc_regs
,ack
);
1888 disable_hc_int(_hc_regs
,nak
);
1889 disable_hc_int(_hc_regs
,nyet
);
1890 if (hcint
.b
.xfercomp
)
1891 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1893 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
1895 else if (hcint
.b
.xacterr
|| hcint
.b
.bblerr
)
1898 if(hctsiz
.b
.pktcnt
==0)
1900 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1904 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1905 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
1906 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
1907 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1908 _urbd
->error_count
++;
1909 if(_urbd
->error_count
>=3)
1911 _urbd
->error_count
=0;
1913 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
1914 else if (hcint
.b
.xacterr
)
1915 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
1919 enable_hc_int(_hc_regs
,ack
);
1920 enable_hc_int(_hc_regs
,nak
);
1921 enable_hc_int(_hc_regs
,nyet
);
1922 _ifxhc
->phase
=HC_WAITING
;
1923 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
1928 else if(hcint
.b
.datatglerr
)
1932 else if(hcint
.b
.stall
)
1939 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1940 static int32_t chhltd_isoc_tx_nonsplit(ifxhcd_hcd_t
*_ifxhcd
,
1941 ifxhcd_hc_t
*_ifxhc
,
1942 ifxusb_hc_regs_t
*_hc_regs
,
1943 ifxhcd_urbd_t
*_urbd
)
1947 hcint_data_t hcintmsk
;
1948 hctsiz_data_t hctsiz
;
1949 int out_nak_enh
= 0;
1951 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
1954 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
1955 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
1956 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
1958 if (hcint
.b
.xfercomp
|| hcint
.d32
== 0x02)
1960 _urbd
->error_count
=0;
1961 disable_hc_int(_hc_regs
,ack
);
1962 disable_hc_int(_hc_regs
,nak
);
1963 disable_hc_int(_hc_regs
,nyet
);
1964 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1967 else if (hcint
.b
.frmovrun
)
1970 _urbd
->error_count
=0;
1971 disable_hc_int(_hc_regs
,ack
);
1972 disable_hc_int(_hc_regs
,nak
);
1973 disable_hc_int(_hc_regs
,nyet
);
1974 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
1977 else if(hcint
.b
.datatglerr
)
1981 else if(hcint
.b
.bblerr
)
1984 if(hctsiz
.b
.pktcnt
==0)
1986 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
1990 _urbd
->urb
->actual_length
+= (_ifxhc
->xfer_len
- hctsiz
.b
.xfersize
);
1991 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
1992 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
1993 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
1994 _urbd
->error_count
++;
1995 if(_urbd
->error_count
>=3)
1997 _urbd
->error_count
=0;
1998 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2002 enable_hc_int(_hc_regs
,ack
);
2003 enable_hc_int(_hc_regs
,nak
);
2004 enable_hc_int(_hc_regs
,nyet
);
2005 _ifxhc
->phase
=HC_WAITING
;
2006 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2011 else if(hcint
.b
.xacterr
)
2013 if(hctsiz
.b
.pktcnt
==0)
2015 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
2018 _urbd
->error_count
++;
2019 if(_urbd
->error_count
>=3)
2021 _urbd
->error_count
=0;
2022 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2026 _ifxhc
->phase
=HC_WAITING
;
2027 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2031 else if(hcint
.b
.stall
)
2038 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2039 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2040 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2041 static int32_t chhltd_ctrl_rx_ssplit(ifxhcd_hcd_t
*_ifxhcd
,
2042 ifxhcd_hc_t
*_ifxhc
,
2043 ifxusb_hc_regs_t
*_hc_regs
,
2044 ifxhcd_urbd_t
*_urbd
)
2047 hcint_data_t hcintmsk
;
2048 hctsiz_data_t hctsiz
;
2050 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2051 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2052 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2054 disable_hc_int(_hc_regs
,ack
);
2055 disable_hc_int(_hc_regs
,nak
);
2056 disable_hc_int(_hc_regs
,nyet
);
2060 _urbd
->error_count
=0;
2062 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
2063 _ifxhc
->phase
=HC_WAITING
;
2064 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2067 else if (hcint
.b
.nak
)
2069 _urbd
->error_count
= 0;
2070 _ifxhc
->phase
=HC_WAITING
;
2071 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2074 else if (hcint
.b
.xacterr
)
2076 _urbd
->error_count
++;
2077 if(_urbd
->error_count
>=3)
2079 _urbd
->error_count
=0;
2080 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2084 _ifxhc
->phase
=HC_WAITING
;
2085 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2089 else if(hcint
.b
.bblerr
)
2091 _urbd
->error_count
=0;
2092 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2095 else if(hcint
.b
.stall
)
2097 _urbd
->error_count
=0;
2098 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2101 else if(hcint
.b
.datatglerr
)
2103 _urbd
->error_count
=0;
2104 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
2107 else if(hcint
.b
.frmovrun
)
2109 _urbd
->error_count
=0;
2110 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
2113 else if(hcint
.b
.nyet
)
2116 else if(hcint
.b
.xfercomp
)
2121 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2122 static int32_t chhltd_ctrl_tx_ssplit(ifxhcd_hcd_t
*_ifxhcd
,
2123 ifxhcd_hc_t
*_ifxhc
,
2124 ifxusb_hc_regs_t
*_hc_regs
,
2125 ifxhcd_urbd_t
*_urbd
)
2128 hcint_data_t hcintmsk
;
2129 hctsiz_data_t hctsiz
;
2130 int out_nak_enh
= 0;
2132 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
2135 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2136 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2137 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2138 disable_hc_int(_hc_regs
,ack
);
2139 disable_hc_int(_hc_regs
,nak
);
2140 disable_hc_int(_hc_regs
,nyet
);
2144 _urbd
->error_count
=0;
2145 if (_ifxhc
->control_phase
!= IFXHCD_CONTROL_SETUP
)
2146 _ifxhc
->ssplit_out_xfer_count
= _ifxhc
->xfer_len
;
2148 _ifxhc
->data_pid_start
=read_data_toggle(_hc_regs
);
2149 _ifxhc
->phase
=HC_WAITING
;
2150 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2153 else if(hcint
.b
.nyet
)
2155 _urbd
->error_count
=0;
2156 if (_ifxhc
->control_phase
!= IFXHCD_CONTROL_SETUP
)
2157 _ifxhc
->ssplit_out_xfer_count
= _ifxhc
->xfer_len
;
2159 _ifxhc
->data_pid_start
=read_data_toggle(_hc_regs
);
2160 _ifxhc
->phase
=HC_WAITING
;
2161 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2164 else if(hcint
.b
.nak
)
2166 _urbd
->error_count
=0;
2167 _ifxhc
->phase
=HC_WAITING
;
2168 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2171 else if(hcint
.b
.xacterr
)
2173 _urbd
->error_count
++;
2174 if(_urbd
->error_count
>=3)
2176 _urbd
->error_count
=0;
2177 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2181 _ifxhc
->phase
=HC_WAITING
;
2182 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2186 else if(hcint
.b
.datatglerr
)
2188 _urbd
->error_count
=0;
2189 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
2192 else if(hcint
.b
.bblerr
)
2194 _urbd
->error_count
=0;
2195 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2198 else if(hcint
.b
.stall
)
2200 _urbd
->error_count
=0;
2201 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2204 else if(hcint
.b
.frmovrun
)
2206 _urbd
->error_count
=0;
2207 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
2210 else if(hcint
.b
.xfercomp
)
2212 printk(KERN_INFO
"Warning: %s() %d CTRL OUT SPLIT1 COMPLETE\n",__func__
,__LINE__
);
2216 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2217 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2218 static int32_t chhltd_bulk_rx_ssplit(ifxhcd_hcd_t
*_ifxhcd
,
2219 ifxhcd_hc_t
*_ifxhc
,
2220 ifxusb_hc_regs_t
*_hc_regs
,
2221 ifxhcd_urbd_t
*_urbd
)
2224 hcint_data_t hcintmsk
;
2225 hctsiz_data_t hctsiz
;
2227 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2228 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2229 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2231 disable_hc_int(_hc_regs
,ack
);
2232 disable_hc_int(_hc_regs
,nak
);
2233 disable_hc_int(_hc_regs
,nyet
);
2237 _urbd
->error_count
=0;
2239 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
2240 _ifxhc
->phase
=HC_WAITING
;
2241 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2244 else if (hcint
.b
.nak
)
2246 _urbd
->error_count
= 0;
2247 _ifxhc
->phase
=HC_WAITING
;
2248 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2251 else if (hcint
.b
.xacterr
)
2253 _urbd
->error_count
++;
2254 if(_urbd
->error_count
>=3)
2256 _urbd
->error_count
=0;
2257 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2261 _ifxhc
->phase
=HC_WAITING
;
2262 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2266 else if(hcint
.b
.bblerr
)
2268 _urbd
->error_count
=0;
2269 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2272 else if(hcint
.b
.stall
)
2274 _urbd
->error_count
=0;
2275 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2278 else if(hcint
.b
.datatglerr
)
2280 _urbd
->error_count
=0;
2281 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
2284 else if(hcint
.b
.frmovrun
)
2286 _urbd
->error_count
=0;
2287 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
2290 else if(hcint
.b
.nyet
)
2293 else if(hcint
.b
.xfercomp
)
2298 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2299 static int32_t chhltd_bulk_tx_ssplit(ifxhcd_hcd_t
*_ifxhcd
,
2300 ifxhcd_hc_t
*_ifxhc
,
2301 ifxusb_hc_regs_t
*_hc_regs
,
2302 ifxhcd_urbd_t
*_urbd
)
2305 hcint_data_t hcintmsk
;
2306 hctsiz_data_t hctsiz
;
2307 int out_nak_enh
= 0;
2309 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
2312 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2313 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2314 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2315 disable_hc_int(_hc_regs
,ack
);
2316 disable_hc_int(_hc_regs
,nak
);
2317 disable_hc_int(_hc_regs
,nyet
);
2321 _urbd
->error_count
=0;
2322 _ifxhc
->ssplit_out_xfer_count
= _ifxhc
->xfer_len
;
2324 _ifxhc
->data_pid_start
=read_data_toggle(_hc_regs
);
2325 _ifxhc
->phase
=HC_WAITING
;
2326 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2329 else if(hcint
.b
.nyet
)
2331 _urbd
->error_count
=0;
2332 _ifxhc
->ssplit_out_xfer_count
= _ifxhc
->xfer_len
;
2334 _ifxhc
->data_pid_start
=read_data_toggle(_hc_regs
);
2335 _ifxhc
->phase
=HC_WAITING
;
2336 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2339 else if(hcint
.b
.nak
)
2341 _urbd
->error_count
=0;
2342 _ifxhc
->phase
=HC_WAITING
;
2343 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2346 else if(hcint
.b
.xacterr
)
2348 _urbd
->error_count
++;
2349 if(_urbd
->error_count
>=3)
2351 _urbd
->error_count
=0;
2352 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2356 _ifxhc
->phase
=HC_WAITING
;
2357 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2361 else if(hcint
.b
.datatglerr
)
2363 _urbd
->error_count
=0;
2364 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
2367 else if(hcint
.b
.bblerr
)
2369 _urbd
->error_count
=0;
2370 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2373 else if(hcint
.b
.stall
)
2375 _urbd
->error_count
=0;
2376 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2379 else if(hcint
.b
.frmovrun
)
2381 _urbd
->error_count
=0;
2382 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
2385 else if(hcint
.b
.xfercomp
)
2387 printk(KERN_INFO
"Warning: %s() %d BULK OUT SPLIT1 COMPLETE\n",__func__
,__LINE__
);
2391 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2392 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2393 static int32_t chhltd_intr_rx_ssplit(ifxhcd_hcd_t
*_ifxhcd
,
2394 ifxhcd_hc_t
*_ifxhc
,
2395 ifxusb_hc_regs_t
*_hc_regs
,
2396 ifxhcd_urbd_t
*_urbd
)
2399 hcint_data_t hcintmsk
;
2400 hctsiz_data_t hctsiz
;
2402 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2403 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2404 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2406 disable_hc_int(_hc_regs
,ack
);
2407 disable_hc_int(_hc_regs
,nak
);
2408 disable_hc_int(_hc_regs
,nyet
);
2412 _urbd
->error_count
=0;
2414 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
2415 _ifxhc
->phase
=HC_WAITING
;
2416 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2419 else if(hcint
.b
.nak
)
2421 _urbd
->error_count
=0;
2422 _ifxhc
->phase
=HC_WAITING
;
2423 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2426 else if(hcint
.b
.xacterr
)
2428 hcchar_data_t hcchar
;
2429 hcchar
.d32
= ifxusb_rreg(&_hc_regs
->hcchar
);
2430 _urbd
->error_count
=hcchar
.b
.multicnt
;
2431 if(_urbd
->error_count
>=3)
2433 _urbd
->error_count
=0;
2434 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2438 _ifxhc
->phase
=HC_WAITING
;
2439 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2443 else if(hcint
.b
.stall
)
2445 _urbd
->error_count
=0;
2446 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2449 else if(hcint
.b
.bblerr
)
2451 _urbd
->error_count
=0;
2452 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2455 else if(hcint
.b
.frmovrun
)
2457 _ifxhc
->phase
=HC_WAITING
;
2458 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2461 else if(hcint
.b
.datatglerr
)
2463 _urbd
->error_count
=0;
2464 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
2467 else if(hcint
.b
.xfercomp
)
2472 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2473 static int32_t chhltd_intr_tx_ssplit(ifxhcd_hcd_t
*_ifxhcd
,
2474 ifxhcd_hc_t
*_ifxhc
,
2475 ifxusb_hc_regs_t
*_hc_regs
,
2476 ifxhcd_urbd_t
*_urbd
)
2479 hcint_data_t hcintmsk
;
2480 hctsiz_data_t hctsiz
;
2481 int out_nak_enh
= 0;
2483 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
2486 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2487 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2488 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2490 disable_hc_int(_hc_regs
,ack
);
2491 disable_hc_int(_hc_regs
,nak
);
2492 disable_hc_int(_hc_regs
,nyet
);
2496 _urbd
->error_count
=0;
2497 _ifxhc
->ssplit_out_xfer_count
= _ifxhc
->xfer_len
;
2499 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
2500 _ifxhc
->phase
=HC_WAITING
;
2501 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2504 else if(hcint
.b
.nyet
)
2506 _urbd
->error_count
=0;
2507 _ifxhc
->ssplit_out_xfer_count
= _ifxhc
->xfer_len
;
2509 _ifxhc
->data_pid_start
= read_data_toggle(_hc_regs
);
2510 _ifxhc
->phase
=HC_WAITING
;
2511 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2514 else if(hcint
.b
.nak
)
2516 _urbd
->error_count
=0;
2517 _ifxhc
->phase
=HC_WAITING
;
2518 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2521 else if(hcint
.b
.frmovrun
)
2523 _urbd
->error_count
=0;
2524 _ifxhc
->phase
=HC_WAITING
;
2525 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2528 else if(hcint
.b
.xacterr
)
2530 hcchar_data_t hcchar
;
2531 hcchar
.d32
= ifxusb_rreg(&_hc_regs
->hcchar
);
2532 _urbd
->error_count
=hcchar
.b
.multicnt
;
2533 if(_urbd
->error_count
>=3)
2535 _urbd
->error_count
=0;
2536 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2540 enable_hc_int(_hc_regs
,ack
);
2541 enable_hc_int(_hc_regs
,nak
);
2542 enable_hc_int(_hc_regs
,nyet
);
2543 _ifxhc
->phase
=HC_WAITING
;
2544 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2548 else if(hcint
.b
.datatglerr
)
2550 _urbd
->error_count
=0;
2551 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_DATA_TOGGLE_ERR
);
2554 else if(hcint
.b
.bblerr
)
2556 _urbd
->error_count
=0;
2557 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2560 else if(hcint
.b
.stall
)
2562 _urbd
->error_count
=0;
2563 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2566 else if(hcint
.b
.xfercomp
)
2571 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2572 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2573 static int32_t chhltd_isoc_rx_ssplit(ifxhcd_hcd_t
*_ifxhcd
,
2574 ifxhcd_hc_t
*_ifxhc
,
2575 ifxusb_hc_regs_t
*_hc_regs
,
2576 ifxhcd_urbd_t
*_urbd
)
2578 #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
2580 hcint_data_t hcintmsk
;
2581 hctsiz_data_t hctsiz
;
2583 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2584 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2585 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2590 else if(hcint
.b
.frmovrun
)
2592 Rewind Buffer Pointers
2593 Retry Start
Split (in next b_interval ¡V
1 uF
)
2595 else if(hcint
.b
.datatglerr
)
2599 else if(hcint
.b
.bblerr
)
2603 else if(hcint
.b
.xacterr
)
2607 else if(hcint
.b
.stall
)
2611 else if(hcint
.b
.nak
)
2615 else if(hcint
.b
.xfercomp
)
2619 else if(hcint
.b
.nyet
)
2626 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2627 static int32_t chhltd_isoc_tx_ssplit(ifxhcd_hcd_t
*_ifxhcd
,
2628 ifxhcd_hc_t
*_ifxhc
,
2629 ifxusb_hc_regs_t
*_hc_regs
,
2630 ifxhcd_urbd_t
*_urbd
)
2632 #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
2634 hcint_data_t hcintmsk
;
2635 hctsiz_data_t hctsiz
;
2636 int out_nak_enh
= 0;
2638 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
2641 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2642 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2643 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2646 //Do Next Start Split (in next b_interval ¡V 1 uF)
2648 else if(hcint
.b
.frmovrun
)
2650 //Do Next Transaction in next frame.
2652 else if(hcint
.b
.datatglerr
)
2656 else if(hcint
.b
.bblerr
)
2660 else if(hcint
.b
.xacterr
)
2664 else if(hcint
.b
.stall
)
2668 else if(hcint
.b
.nak
)
2672 else if(hcint
.b
.xfercomp
)
2676 else if(hcint
.b
.nyet
)
2683 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2684 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2685 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2686 static int32_t chhltd_ctrl_rx_csplit(ifxhcd_hcd_t
*_ifxhcd
,
2687 ifxhcd_hc_t
*_ifxhc
,
2688 ifxusb_hc_regs_t
*_hc_regs
,
2689 ifxhcd_urbd_t
*_urbd
)
2692 hcint_data_t hcintmsk
;
2693 hctsiz_data_t hctsiz
;
2695 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2696 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2697 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2698 disable_hc_int(_hc_regs
,ack
);
2699 disable_hc_int(_hc_regs
,nak
);
2700 disable_hc_int(_hc_regs
,nyet
);
2702 if (hcint
.b
.xfercomp
)
2704 _urbd
->error_count
=0;
2706 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
2709 else if (hcint
.b
.nak
)
2712 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
2714 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2715 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2717 _ifxhc
->phase
=HC_WAITING
;
2718 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2721 else if(hcint
.b
.nyet
)
2723 _urbd
->error_count
=0;
2724 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
2725 _ifxhc
->phase
=HC_WAITING
;
2726 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2729 else if(hcint
.b
.stall
|| hcint
.b
.bblerr
)
2731 _urbd
->error_count
=0;
2733 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2734 else if(hcint
.b
.bblerr
)
2735 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2738 else if(hcint
.b
.xacterr
)
2740 _urbd
->error_count
++;
2741 if(_urbd
->error_count
>=3)
2743 _urbd
->error_count
=0;
2744 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2749 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
2751 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2752 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2754 _ifxhc
->phase
=HC_WAITING
;
2755 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2759 else if(hcint
.b
.datatglerr
)
2761 if(_ifxhc
->data_pid_start
== IFXUSB_HC_PID_DATA0
)
2762 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA1
;
2764 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA0
;
2766 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
2768 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2769 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2771 _ifxhc
->phase
=HC_WAITING
;
2772 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2775 else if(hcint
.b
.frmovrun
)
2777 _urbd
->error_count
=0;
2778 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
2783 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2784 static int32_t chhltd_ctrl_tx_csplit(ifxhcd_hcd_t
*_ifxhcd
,
2785 ifxhcd_hc_t
*_ifxhc
,
2786 ifxusb_hc_regs_t
*_hc_regs
,
2787 ifxhcd_urbd_t
*_urbd
)
2790 hcint_data_t hcintmsk
;
2791 hctsiz_data_t hctsiz
;
2792 int out_nak_enh
= 0;
2794 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
2797 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2798 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2799 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2800 disable_hc_int(_hc_regs
,ack
);
2801 disable_hc_int(_hc_regs
,nak
);
2802 disable_hc_int(_hc_regs
,nyet
);
2804 if(hcint
.b
.xfercomp
)
2806 _urbd
->error_count
=0;
2809 if(_ifxhc
->xfer_len
==0 && !hcint
.b
.ack
&& (hcint
.b
.nak
|| hcint
.b
.nyet
))
2811 // Walkaround: When sending ZLP and receive NYEY or NAK but also issue CMPT intr
2812 // Solution: NoSplit: Resend at next SOF
2813 // Split : Resend at next SOF with SSPLIT
2814 _ifxhc
->xfer_len
= 0;
2815 _ifxhc
->xfer_count
= 0;
2816 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
2817 _ifxhc
->phase
=HC_WAITING
;
2818 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2823 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
2827 else if(hcint
.b
.nak
)
2830 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
2832 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2833 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2835 _ifxhc
->phase
=HC_WAITING
;
2836 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2839 else if(hcint
.b
.nyet
)
2841 //Retry Complete Split
2842 // Issue Retry instantly on next SOF, without gothrough process_channels
2843 _urbd
->error_count
=0;
2844 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
2845 _ifxhc
->phase
=HC_WAITING
;
2846 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2849 else if(hcint
.b
.stall
)
2851 _urbd
->error_count
=0;
2852 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2855 else if(hcint
.b
.xacterr
)
2857 _urbd
->error_count
++;
2858 if(_urbd
->error_count
>=3)
2860 _urbd
->error_count
=0;
2861 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2866 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
2868 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2869 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2871 _ifxhc
->phase
=HC_WAITING
;
2872 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2876 else if(hcint
.b
.datatglerr
)
2878 if(_ifxhc
->data_pid_start
== IFXUSB_HC_PID_DATA0
)
2879 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA1
;
2881 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA0
;
2883 if(_ifxhc
->control_phase
== IFXHCD_CONTROL_DATA
)
2885 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2886 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2888 _ifxhc
->phase
=HC_WAITING
;
2889 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2892 else if(hcint
.b
.frmovrun
)
2894 _urbd
->error_count
=0;
2895 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
2898 else if(hcint
.b
.bblerr
)
2900 _urbd
->error_count
=0;
2901 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2906 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2907 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2908 static int32_t chhltd_bulk_rx_csplit(ifxhcd_hcd_t
*_ifxhcd
,
2909 ifxhcd_hc_t
*_ifxhc
,
2910 ifxusb_hc_regs_t
*_hc_regs
,
2911 ifxhcd_urbd_t
*_urbd
)
2914 hcint_data_t hcintmsk
;
2915 hctsiz_data_t hctsiz
;
2917 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
2918 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
2919 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
2920 disable_hc_int(_hc_regs
,ack
);
2921 disable_hc_int(_hc_regs
,nak
);
2922 disable_hc_int(_hc_regs
,nyet
);
2924 if (hcint
.b
.xfercomp
)
2926 _urbd
->error_count
=0;
2928 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
2931 else if (hcint
.b
.nak
)
2934 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2935 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2936 _ifxhc
->phase
=HC_WAITING
;
2937 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2940 else if(hcint
.b
.nyet
)
2942 _urbd
->error_count
=0;
2943 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
2944 _ifxhc
->phase
=HC_WAITING
;
2945 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2948 else if(hcint
.b
.stall
|| hcint
.b
.bblerr
)
2950 _urbd
->error_count
=0;
2952 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
2953 else if(hcint
.b
.bblerr
)
2954 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
2957 else if(hcint
.b
.xacterr
)
2959 _urbd
->error_count
++;
2960 if(_urbd
->error_count
>=3)
2962 _urbd
->error_count
=0;
2963 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
2968 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2969 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2970 _ifxhc
->phase
=HC_WAITING
;
2971 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2975 else if(hcint
.b
.datatglerr
)
2977 if(_ifxhc
->data_pid_start
== IFXUSB_HC_PID_DATA0
)
2978 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA1
;
2980 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA0
;
2982 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
2983 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
2984 _ifxhc
->phase
=HC_WAITING
;
2985 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
2988 else if(hcint
.b
.frmovrun
)
2990 _urbd
->error_count
=0;
2991 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
2996 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2997 static int32_t chhltd_bulk_tx_csplit(ifxhcd_hcd_t
*_ifxhcd
,
2998 ifxhcd_hc_t
*_ifxhc
,
2999 ifxusb_hc_regs_t
*_hc_regs
,
3000 ifxhcd_urbd_t
*_urbd
)
3003 hcint_data_t hcintmsk
;
3004 hctsiz_data_t hctsiz
;
3005 int out_nak_enh
= 0;
3007 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
3010 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
3011 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
3012 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
3013 disable_hc_int(_hc_regs
,ack
);
3014 disable_hc_int(_hc_regs
,nak
);
3015 disable_hc_int(_hc_regs
,nyet
);
3017 if(hcint
.b
.xfercomp
)
3019 _urbd
->error_count
=0;
3022 if(_ifxhc
->xfer_len
==0 && !hcint
.b
.ack
&& (hcint
.b
.nak
|| hcint
.b
.nyet
))
3024 // Walkaround: When sending ZLP and receive NYEY or NAK but also issue CMPT intr
3025 // Solution: NoSplit: Resend at next SOF
3026 // Split : Resend at next SOF with SSPLIT
3027 _ifxhc
->xfer_len
= 0;
3028 _ifxhc
->xfer_count
= 0;
3029 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
3030 _ifxhc
->phase
=HC_WAITING
;
3031 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3036 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
3040 else if(hcint
.b
.nak
)
3043 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3044 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3045 _ifxhc
->phase
=HC_WAITING
;
3046 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3049 else if(hcint
.b
.nyet
)
3051 //Retry Complete Split
3052 // Issue Retry instantly on next SOF, without gothrough process_channels
3053 _urbd
->error_count
=0;
3054 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
3055 _ifxhc
->phase
=HC_WAITING
;
3056 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3059 else if(hcint
.b
.stall
)
3061 _urbd
->error_count
=0;
3062 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
3065 else if(hcint
.b
.xacterr
)
3067 _urbd
->error_count
++;
3068 if(_urbd
->error_count
>=3)
3070 _urbd
->error_count
=0;
3071 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
3076 _ifxhc
->epqh
->do_ping
=1;
3077 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3078 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3079 _ifxhc
->phase
=HC_WAITING
;
3080 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3084 else if(hcint
.b
.datatglerr
)
3086 if(_ifxhc
->data_pid_start
== IFXUSB_HC_PID_DATA0
)
3087 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA1
;
3089 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA0
;
3091 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3092 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3093 _ifxhc
->phase
=HC_WAITING
;
3094 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3097 else if(hcint
.b
.frmovrun
)
3099 _urbd
->error_count
=0;
3100 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
3103 else if(hcint
.b
.bblerr
)
3105 _urbd
->error_count
=0;
3106 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
3111 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3112 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3113 static int32_t chhltd_intr_rx_csplit(ifxhcd_hcd_t
*_ifxhcd
,
3114 ifxhcd_hc_t
*_ifxhc
,
3115 ifxusb_hc_regs_t
*_hc_regs
,
3116 ifxhcd_urbd_t
*_urbd
)
3119 hcint_data_t hcintmsk
;
3120 hctsiz_data_t hctsiz
;
3122 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
3123 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
3124 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
3125 disable_hc_int(_hc_regs
,ack
);
3126 disable_hc_int(_hc_regs
,nak
);
3127 disable_hc_int(_hc_regs
,nyet
);
3129 if (hcint
.b
.xfercomp
)
3131 _urbd
->error_count
=0;
3133 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
3136 else if(hcint
.b
.nak
)
3139 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3140 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3141 _ifxhc
->phase
=HC_WAITING
;
3142 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3145 else if(hcint
.b
.nyet
)
3147 _urbd
->error_count
=0;
3148 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
3149 _ifxhc
->phase
=HC_WAITING
;
3150 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3153 else if(hcint
.b
.frmovrun
|| hcint
.b
.bblerr
|| hcint
.b
.stall
)
3155 _urbd
->error_count
=0;
3157 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
3158 else if(hcint
.b
.bblerr
)
3159 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
3160 else if(hcint
.b
.frmovrun
)
3161 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
3164 else if(hcint
.b
.xacterr
)
3166 hcchar_data_t hcchar
;
3167 hcchar
.d32
= ifxusb_rreg(&_hc_regs
->hcchar
);
3168 _urbd
->error_count
=hcchar
.b
.multicnt
;
3169 if(_urbd
->error_count
>=3)
3171 _urbd
->error_count
=0;
3172 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
3177 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3178 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3179 _ifxhc
->phase
=HC_WAITING
;
3180 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3184 else if(hcint
.b
.datatglerr
)
3186 if(_ifxhc
->data_pid_start
== IFXUSB_HC_PID_DATA0
)
3187 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA1
;
3189 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA0
;
3191 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3192 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3193 _ifxhc
->phase
=HC_WAITING
;
3194 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3199 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3200 static int32_t chhltd_intr_tx_csplit(ifxhcd_hcd_t
*_ifxhcd
,
3201 ifxhcd_hc_t
*_ifxhc
,
3202 ifxusb_hc_regs_t
*_hc_regs
,
3203 ifxhcd_urbd_t
*_urbd
)
3206 hcint_data_t hcintmsk
;
3207 hctsiz_data_t hctsiz
;
3208 int out_nak_enh
= 0;
3210 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
3213 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
3214 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
3215 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
3216 disable_hc_int(_hc_regs
,ack
);
3217 disable_hc_int(_hc_regs
,nak
);
3218 disable_hc_int(_hc_regs
,nyet
);
3220 if(hcint
.b
.xfercomp
)
3222 _urbd
->error_count
=0;
3224 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
3227 else if(hcint
.b
.nak
)
3230 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3231 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3232 _ifxhc
->phase
=HC_WAITING
;
3233 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3236 else if(hcint
.b
.nyet
)
3238 _urbd
->error_count
=0;
3239 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
3240 _ifxhc
->phase
=HC_WAITING
;
3241 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3244 else if(hcint
.b
.stall
|| hcint
.b
.frmovrun
)
3246 _urbd
->error_count
=0;
3248 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
3249 else if(hcint
.b
.frmovrun
)
3250 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_FRAME_OVERRUN
);
3253 else if(hcint
.b
.xacterr
)
3255 hcchar_data_t hcchar
;
3256 hcchar
.d32
= ifxusb_rreg(&_hc_regs
->hcchar
);
3257 _urbd
->error_count
=hcchar
.b
.multicnt
;
3258 if(_urbd
->error_count
>=3)
3260 _urbd
->error_count
=0;
3261 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_XACT_ERR
);
3266 _ifxhc
->epqh
->do_ping
=1;
3267 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3268 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3269 _ifxhc
->phase
=HC_WAITING
;
3270 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3274 else if(hcint
.b
.datatglerr
)
3276 if(_ifxhc
->data_pid_start
== IFXUSB_HC_PID_DATA0
)
3277 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA1
;
3279 _ifxhc
->data_pid_start
= IFXUSB_HC_PID_DATA0
;
3281 _ifxhc
->epqh
->do_ping
=1;
3282 _ifxhc
->xfer_len
= _urbd
->xfer_len
- _urbd
->urb
->actual_length
;
3283 _ifxhc
->xfer_count
= _urbd
->urb
->actual_length
;
3284 _ifxhc
->phase
=HC_WAITING
;
3285 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3288 else if(hcint
.b
.bblerr
)
3290 _urbd
->error_count
=0;
3291 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_BABBLE_ERR
);
3296 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3297 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3298 static int32_t chhltd_isoc_rx_csplit(ifxhcd_hcd_t
*_ifxhcd
,
3299 ifxhcd_hc_t
*_ifxhc
,
3300 ifxusb_hc_regs_t
*_hc_regs
,
3301 ifxhcd_urbd_t
*_urbd
)
3303 #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
3305 hcint_data_t hcintmsk
;
3306 hctsiz_data_t hctsiz
;
3308 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
3309 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
3310 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
3311 if(hcint
.b
.xfercomp
)
3313 disable_hc_int(_hc_regs
,ack
);
3314 disable_hc_int(_hc_regs
,nak
);
3315 disable_hc_int(_hc_regs
,nyet
);
3316 _urbd
->error_count
=0;
3318 complete_channel(_ifxhcd
, _ifxhc
, _urbd
);
3321 else if(hcint
.b
.nak
)
3323 Retry Start
Split (in next b_interval ¡V
1 uF
)
3325 else if(hcint
.b
.nyet
)
3327 //Do Next Complete Split
3328 // Issue Retry instantly on next SOF, without gothrough process_channels
3329 _urbd
->error_count
=0;
3330 //disable_hc_int(_hc_regs,ack);
3331 //disable_hc_int(_hc_regs,nak);
3332 //disable_hc_int(_hc_regs,datatglerr);
3333 _ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
3334 _ifxhc
->phase
=HC_WAITING
;
3335 ifxhcd_hc_start(_ifxhcd
, _ifxhc
);
3338 else if(hcint
.b
.frmovrun
|| hcint
.b
.stall
|| hcint
.b
.bblerr
)
3340 _urbd
->error_count
=0;
3341 disable_hc_int(_hc_regs
,ack
);
3342 disable_hc_int(_hc_regs
,nyet
);
3343 disable_hc_int(_hc_regs
,nak
);
3344 _ifxhc
->wait_for_sof
= 0;
3346 //if(hctsiz.b.pktcnt==0)
3348 // complete_channel(_ifxhcd, _ifxhc, _urbd);
3352 // _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize);
3354 release_channel(_ifxhcd
, _ifxhc
, HC_XFER_STALL
);
3355 else if(hcint
.b
.frmovrun
)
3356 else if(hcint
.b
.bblerr
)
3359 else if(hcint
.b
.xacterr
)
3361 Rewind Buffer Pointers
3362 if (HCCHARn
.EC
= = 3) // ERR response received
3365 Do Next Start
Split (in next frame
)
3372 else if(hcint
.b
.datatglerr
)
3376 else if(hcint
.b
.ack
)
3383 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3384 static int32_t chhltd_isoc_tx_csplit(ifxhcd_hcd_t
*_ifxhcd
,
3385 ifxhcd_hc_t
*_ifxhc
,
3386 ifxusb_hc_regs_t
*_hc_regs
,
3387 ifxhcd_urbd_t
*_urbd
)
3389 #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
3391 hcint_data_t hcintmsk
;
3392 hctsiz_data_t hctsiz
;
3393 int out_nak_enh
= 0;
3395 if (_ifxhcd
->core_if
.snpsid
>= 0x4f54271a && _ifxhc
->speed
== IFXUSB_EP_SPEED_HIGH
)
3398 hcint
.d32
= ifxusb_rreg(&_hc_regs
->hcint
);
3399 hcintmsk
.d32
= ifxusb_rreg(&_hc_regs
->hcintmsk
);
3400 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
3405 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3406 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3407 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
3410 \fn static int32_t handle_hc_chhltd_intr(ifxhcd_hcd_t *_ifxhcd,
3411 ifxhcd_hc_t *_ifxhc,
3412 ifxusb_hc_regs_t *_hc_regs,
3413 ifxhcd_urbd_t *_urbd)
3414 \brief This function handles halted interrupts of host channels.
3415 \param _ifxhcd Pointer to the sate of HCD structure
3416 \param _ifxhc Pointer to host channel descriptor
3417 \param _hc_regs Pointer to host channel registers
3418 \param _urbd Pointer to URB descriptor
3423 int32_t handle_hc_chhltd_intr(ifxhcd_hcd_t
*_ifxhcd
,
3424 ifxhcd_hc_t
*_ifxhc
,
3425 ifxusb_hc_regs_t
*_hc_regs
,
3426 ifxhcd_urbd_t
*_urbd
)
3428 IFX_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: Channel Halted--\n", _ifxhc
->hc_num
);
3430 _ifxhc
->phase
= HC_STOPPED
;
3432 if(_ifxhc
->epqh
->urbd
)
3433 _ifxhc
->epqh
->urbd
->phase
=URBD_ACTIVE
;
3435 if (_ifxhc
->halt_status
== HC_XFER_URB_DEQUEUE
||
3436 _ifxhc
->halt_status
== HC_XFER_AHB_ERR
) {
3438 * Just release the channel. A dequeue can happen on a
3439 * transfer timeout. In the case of an AHB Error, the channel
3440 * was forced to halt because there's no way to gracefully
3444 if(_ifxhc
->epqh
->urbd
)
3445 _ifxhc
->epqh
->urbd
->phase
=URBD_DEQUEUEING
;
3446 release_channel(_ifxhcd
, _ifxhc
, _ifxhc
->halt_status
);
3450 if (_ifxhc
->ep_type
== IFXUSB_EP_TYPE_CTRL
)
3452 if (_ifxhc
->split
==0)
3455 return (chhltd_ctrl_rx_nonsplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3457 return (chhltd_ctrl_tx_nonsplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3459 else if(_ifxhc
->split
==1)
3462 return (chhltd_ctrl_rx_ssplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3464 return (chhltd_ctrl_tx_ssplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3466 else if(_ifxhc
->split
==2)
3469 return (chhltd_ctrl_rx_csplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3471 return (chhltd_ctrl_tx_csplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3474 else if(_ifxhc
->ep_type
== IFXUSB_EP_TYPE_BULK
)
3476 if (_ifxhc
->split
==0)
3479 return (chhltd_bulk_rx_nonsplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3481 return (chhltd_bulk_tx_nonsplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3483 else if(_ifxhc
->split
==1)
3486 return (chhltd_bulk_rx_ssplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3488 return (chhltd_bulk_tx_ssplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3490 else if(_ifxhc
->split
==2)
3493 return (chhltd_bulk_rx_csplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3495 return (chhltd_bulk_tx_csplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3498 else if(_ifxhc
->ep_type
== IFXUSB_EP_TYPE_INTR
)
3500 if (_ifxhc
->split
==0)
3503 return (chhltd_intr_rx_nonsplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3505 return (chhltd_intr_tx_nonsplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3507 else if(_ifxhc
->split
==1)
3510 return (chhltd_intr_rx_ssplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3512 return (chhltd_intr_tx_ssplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3514 else if(_ifxhc
->split
==2)
3517 return (chhltd_intr_rx_csplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3519 return (chhltd_intr_tx_csplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3522 else if(_ifxhc
->ep_type
== IFXUSB_EP_TYPE_ISOC
)
3524 if (_ifxhc
->split
==0)
3527 return (chhltd_isoc_rx_nonsplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3529 return (chhltd_isoc_tx_nonsplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3531 else if(_ifxhc
->split
==1)
3534 return (chhltd_isoc_rx_ssplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3536 return (chhltd_isoc_tx_ssplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3538 else if(_ifxhc
->split
==2)
3541 return (chhltd_isoc_rx_csplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3543 return (chhltd_isoc_tx_csplit(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
));
3550 * Handles a host channel AHB error interrupt. This handler is only called in
3553 static void hc_other_intr_dump(ifxhcd_hcd_t
*_ifxhcd
,
3554 ifxhcd_hc_t
*_ifxhc
,
3555 ifxusb_hc_regs_t
*_hc_regs
,
3556 ifxhcd_urbd_t
*_urbd
)
3559 hcchar_data_t hcchar
;
3560 hcsplt_data_t hcsplt
;
3561 hctsiz_data_t hctsiz
;
3563 struct urb
*urb
= _urbd
->urb
;
3564 hcchar
.d32
= ifxusb_rreg(&_hc_regs
->hcchar
);
3565 hcsplt
.d32
= ifxusb_rreg(&_hc_regs
->hcsplt
);
3566 hctsiz
.d32
= ifxusb_rreg(&_hc_regs
->hctsiz
);
3567 hcdma
= ifxusb_rreg(&_hc_regs
->hcdma
);
3569 IFX_ERROR("Channel %d\n", _ifxhc
->hc_num
);
3570 IFX_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar
.d32
, hcsplt
.d32
);
3571 IFX_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz
.d32
, hcdma
);
3572 IFX_ERROR(" Device address: %d\n", usb_pipedevice(urb
->pipe
));
3573 IFX_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb
->pipe
),
3574 (usb_pipein(urb
->pipe
) ? "IN" : "OUT"));
3575 IFX_ERROR(" Endpoint type: %s\n",
3577 switch (usb_pipetype(urb
->pipe
)) {
3578 case PIPE_CONTROL
: pipetype
= "CTRL"; break;
3579 case PIPE_BULK
: pipetype
= "BULK"; break;
3580 case PIPE_INTERRUPT
: pipetype
= "INTR"; break;
3581 case PIPE_ISOCHRONOUS
: pipetype
= "ISOC"; break;
3582 default: pipetype
= "????"; break;
3584 IFX_ERROR(" Speed: %s\n",
3586 switch (urb
->dev
->speed
) {
3587 case USB_SPEED_HIGH
: speed
= "HS"; break;
3588 case USB_SPEED_FULL
: speed
= "FS"; break;
3589 case USB_SPEED_LOW
: speed
= "LS"; break;
3590 default: speed
= "????"; break;
3592 IFX_ERROR(" Max packet size: %d\n",
3593 usb_maxpacket(urb
->dev
, urb
->pipe
, usb_pipeout(urb
->pipe
)));
3594 IFX_ERROR(" Data buffer length: %d\n", urb
->transfer_buffer_length
);
3595 IFX_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
3596 urb
->transfer_buffer
, (void *)urb
->transfer_dma
);
3597 IFX_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
3598 urb
->setup_packet
, (void *)urb
->setup_dma
);
3599 IFX_ERROR(" Interval: %d\n", urb
->interval
);
3604 * Handles a host channel ACK interrupt. This interrupt is enabled when
3605 * errors occur, and during Start Split transactions.
3608 int32_t handle_hc_ack_intr(ifxhcd_hcd_t
*_ifxhcd
,
3609 ifxhcd_hc_t
*_ifxhc
,
3610 ifxusb_hc_regs_t
*_hc_regs
,
3611 ifxhcd_urbd_t
*_urbd
)
3613 _urbd
->error_count
=0;
3616 disable_hc_int(_hc_regs
,nyet
);
3619 if(!_ifxhc
->stop_on
)
3621 disable_hc_int(_hc_regs
,ack
);
3622 disable_hc_int(_hc_regs
,nak
);
3625 disable_hc_int(_hc_regs
,ack
);
3626 disable_hc_int(_hc_regs
,nak
);
3632 * Handles a host channel ACK interrupt. This interrupt is enabled when
3633 * errors occur, and during Start Split transactions.
3636 int32_t handle_hc_nak_intr(ifxhcd_hcd_t
*_ifxhcd
,
3637 ifxhcd_hc_t
*_ifxhc
,
3638 ifxusb_hc_regs_t
*_hc_regs
,
3639 ifxhcd_urbd_t
*_urbd
)
3641 _urbd
->error_count
=0;
3643 disable_hc_int(_hc_regs
,nyet
);
3644 disable_hc_int(_hc_regs
,ack
);
3645 disable_hc_int(_hc_regs
,nak
);
3649 hcchar_data_t hcchar
;
3650 hcchar
.d32
= ifxusb_rreg(&_hc_regs
->hcchar
);
3654 _ifxhc
->halt_status
= HC_XFER_NAK
;
3655 ifxusb_wreg(&_hc_regs
->hcchar
, hcchar
.d32
);
3663 int32_t handle_hc_nyet_intr(ifxhcd_hcd_t
*_ifxhcd
,
3664 ifxhcd_hc_t
*_ifxhc
,
3665 ifxusb_hc_regs_t
*_hc_regs
,
3666 ifxhcd_urbd_t
*_urbd
)
3668 _urbd
->error_count
=0;
3671 disable_hc_int(_hc_regs
,nyet
);
3673 if(!_ifxhc
->stop_on
)
3675 disable_hc_int(_hc_regs
,ack
);
3676 disable_hc_int(_hc_regs
,nak
);
3679 disable_hc_int(_hc_regs
,ack
);
3680 disable_hc_int(_hc_regs
,nak
);
3686 * Handles a host channel AHB error interrupt. This handler is only called in
3689 static int32_t handle_hc_ahberr_intr(ifxhcd_hcd_t
*_ifxhcd
,
3690 ifxhcd_hc_t
*_ifxhc
,
3691 ifxusb_hc_regs_t
*_hc_regs
,
3692 ifxhcd_urbd_t
*_urbd
)
3694 IFX_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
3695 "AHB Error--\n", _ifxhc
->hc_num
);
3696 hc_other_intr_dump(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
);
3698 ifxhcd_hc_halt(&_ifxhcd
->core_if
, _ifxhc
, HC_XFER_AHB_ERR
);
3705 static int32_t handle_hc_datatglerr_intr(ifxhcd_hcd_t
*_ifxhcd
,
3706 ifxhcd_hc_t
*_ifxhc
,
3707 ifxusb_hc_regs_t
*_hc_regs
,
3708 ifxhcd_urbd_t
*_urbd
)
3710 IFX_ERROR( "--Host Channel %d Interrupt: "
3711 "DATATOGGLE Error--\n", _ifxhc
->hc_num
);
3712 hc_other_intr_dump(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
);
3713 disable_hc_int(_hc_regs
,datatglerr
);
3719 * Interrupts which should not been triggered
3721 static int32_t handle_hc_frmovrun_intr(ifxhcd_hcd_t
*_ifxhcd
,
3722 ifxhcd_hc_t
*_ifxhc
,
3723 ifxusb_hc_regs_t
*_hc_regs
,
3724 ifxhcd_urbd_t
*_urbd
)
3726 IFX_ERROR( "--Host Channel %d Interrupt: "
3727 "FrameOverRun Error--\n", _ifxhc
->hc_num
);
3728 hc_other_intr_dump(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
);
3729 disable_hc_int(_hc_regs
,frmovrun
);
3733 static int32_t handle_hc_bblerr_intr(ifxhcd_hcd_t
*_ifxhcd
,
3734 ifxhcd_hc_t
*_ifxhc
,
3735 ifxusb_hc_regs_t
*_hc_regs
,
3736 ifxhcd_urbd_t
*_urbd
)
3738 IFX_ERROR( "--Host Channel %d Interrupt: "
3739 "BBL Error--\n", _ifxhc
->hc_num
);
3740 hc_other_intr_dump(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
);
3741 disable_hc_int(_hc_regs
,bblerr
);
3745 static int32_t handle_hc_xacterr_intr(ifxhcd_hcd_t
*_ifxhcd
,
3746 ifxhcd_hc_t
*_ifxhc
,
3747 ifxusb_hc_regs_t
*_hc_regs
,
3748 ifxhcd_urbd_t
*_urbd
)
3750 IFX_ERROR( "--Host Channel %d Interrupt: "
3751 "XACT Error--\n", _ifxhc
->hc_num
);
3752 hc_other_intr_dump(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
);
3753 disable_hc_int(_hc_regs
,xacterr
);
3758 static int32_t handle_hc_stall_intr(ifxhcd_hcd_t
*_ifxhcd
,
3759 ifxhcd_hc_t
*_ifxhc
,
3760 ifxusb_hc_regs_t
*_hc_regs
,
3761 ifxhcd_urbd_t
*_urbd
)
3763 IFX_ERROR( "--Host Channel %d Interrupt: "
3764 "STALL--\n", _ifxhc
->hc_num
);
3765 hc_other_intr_dump(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
);
3766 disable_hc_int(_hc_regs
,stall
);
3770 static int32_t handle_hc_xfercomp_intr(ifxhcd_hcd_t
*_ifxhcd
,
3771 ifxhcd_hc_t
*_ifxhc
,
3772 ifxusb_hc_regs_t
*_hc_regs
,
3773 ifxhcd_urbd_t
*_urbd
)
3775 IFX_ERROR( "--Host Channel %d Interrupt: "
3776 "XFERCOMP--\n", _ifxhc
->hc_num
);
3777 hc_other_intr_dump(_ifxhcd
,_ifxhc
,_hc_regs
,_urbd
);
3778 disable_hc_int(_hc_regs
,xfercomp
);
3782 /* This interrupt indicates that the specified host channels has a pending
3783 * interrupt. There are multiple conditions that can cause each host channel
3784 * interrupt. This function determines which conditions have occurred for this
3785 * host channel interrupt and handles them appropriately. */
3786 static int32_t handle_hc_n_intr (ifxhcd_hcd_t
*_ifxhcd
, uint32_t _num
)
3788 uint32_t hcintval
,hcintmsk
;
3791 ifxusb_hc_regs_t
*hc_regs
;
3792 ifxhcd_urbd_t
*urbd
;
3796 IFX_DEBUGPL(DBG_HCDV
, "--Host Channel Interrupt--, Channel %d\n", _num
);
3798 ifxhc
= &_ifxhcd
->ifxhc
[_num
];
3799 hc_regs
= _ifxhcd
->core_if
.hc_regs
[_num
];
3801 hcintval
= ifxusb_rreg(&hc_regs
->hcint
);
3802 hcintmsk
= ifxusb_rreg(&hc_regs
->hcintmsk
);
3803 hcint
.d32
= hcintval
& hcintmsk
;
3804 IFX_DEBUGPL(DBG_HCDV
, " 0x%08x & 0x%08x = 0x%08x\n",
3805 hcintval
, hcintmsk
, hcint
.d32
);
3807 urbd
= ifxhc
->epqh
->urbd
;
3810 retval
|= handle_hc_ahberr_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3811 else if (hcint
.b
.chhltd
)
3812 retval
|= handle_hc_chhltd_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3815 if (hcint
.b
.datatglerr
)
3816 retval
|= handle_hc_datatglerr_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3817 if (hcint
.b
.frmovrun
)
3818 retval
|= handle_hc_frmovrun_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3820 retval
|= handle_hc_bblerr_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3821 if (hcint
.b
.xacterr
)
3822 retval
|= handle_hc_xacterr_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3824 retval
|= handle_hc_nyet_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3826 retval
|= handle_hc_ack_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3828 retval
|= handle_hc_nak_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3830 retval
|= handle_hc_stall_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3831 if (hcint
.b
.xfercomp
)
3832 retval
|= handle_hc_xfercomp_intr(_ifxhcd
, ifxhc
, hc_regs
, urbd
);
3835 ifxusb_wreg(&hc_regs
->hcint
,hcintval
);
3841 static uint8_t update_interval_counter(ifxhcd_epqh_t
*_epqh
,uint32_t _diff
)
3843 if(_diff
>=_epqh
->period_counter
)
3846 if(_diff
>_epqh
->interval
)
3847 _epqh
->period_counter
=1;
3849 _epqh
->period_counter
=_epqh
->period_counter
+_epqh
->interval
-_diff
;
3852 _epqh
->period_counter
=_epqh
->period_counter
-_diff
;
3857 void process_unaligned( ifxhcd_epqh_t
*_epqh
, ifxusb_core_if_t
*_core_if
)
3859 ifxhcd_urbd_t
*urbd
;
3862 #if defined(__UNALIGNED_BUF_ADJ__) || defined(__UNALIGNED_BUF_CHK__)
3863 if(!urbd
->aligned_checked
)
3865 #if defined(__UNALIGNED_BUF_ADJ__)
3867 xfer_len
=urbd
->xfer_len
;
3868 if(urbd
->is_in
&& xfer_len
<_epqh
->mps
)
3869 xfer_len
= _epqh
->mps
;
3870 // urbd->using_aligned_buf=0;
3872 if(xfer_len
> 0 && ((unsigned long)urbd
->xfer_buff
) & _core_if
->unaligned_mask
)
3874 if( urbd
->aligned_buf
3875 && urbd
->aligned_buf_len
> 0
3876 && urbd
->aligned_buf_len
< xfer_len
3879 ifxusb_free_buf_h(urbd
->aligned_buf
);
3880 urbd
->aligned_buf
=NULL
;
3881 urbd
->aligned_buf_len
=0;
3883 if(! urbd
->aligned_buf
|| ! urbd
->aligned_buf_len
)
3885 urbd
->aligned_buf
= ifxusb_alloc_buf_h(xfer_len
, urbd
->is_in
);
3886 if(urbd
->aligned_buf
)
3887 urbd
->aligned_buf_len
= xfer_len
;
3889 if(urbd
->aligned_buf
)
3892 memcpy(urbd
->aligned_buf
, urbd
->xfer_buff
, xfer_len
);
3893 // urbd->using_aligned_buf=1;
3894 _epqh
->hc
->xfer_buff
= urbd
->aligned_buf
;
3897 IFX_WARN("%s():%d\n",__func__
,__LINE__
);
3899 if(_epqh
->ep_type
==IFXUSB_EP_TYPE_CTRL
)
3901 // urbd->using_aligned_setup=0;
3902 if(((unsigned long)urbd
->setup_buff
) & _core_if
->unaligned_mask
)
3904 if(! urbd
->aligned_setup
)
3905 urbd
->aligned_setup
= ifxusb_alloc_buf_h(8,0);
3906 if(urbd
->aligned_setup
)
3908 memcpy(urbd
->aligned_setup
, urbd
->setup_buff
, 8);
3909 // urbd->using_aligned_setup=1;
3912 IFX_WARN("%s():%d\n",__func__
,__LINE__
);
3913 _epqh
->hc
->xfer_buff
= urbd
->aligned_setup
;
3916 #elif defined(__UNALIGNED_BUF_CHK__)
3917 if(_epqh
->urbd
->is_in
)
3919 if(_epqh
->urbd
->xfer_len
==0)
3920 IFX_WARN("%s():%d IN xfer while length is zero \n",__func__
,__LINE__
);
3922 if(_epqh
->urbd
->xfer_len
< _epqh
->mps
)
3923 IFX_WARN("%s():%d IN xfer while length < mps \n",__func__
,__LINE__
);
3924 if(((unsigned long)_epqh
->urbd
->xfer_buff
) & _core_if
->unaligned_mask
)
3925 IFX_WARN("%s():%d IN xfer Buffer UNALIGNED\n",__func__
,__LINE__
);
3930 if(_epqh
->urbd
->xfer_len
> 0 && (((unsigned long)_epqh
->urbd
->xfer_buff
) & _core_if
->unaligned_mask
))
3931 IFX_WARN("%s():%d OUT xfer Buffer UNALIGNED\n",__func__
,__LINE__
);
3933 if(_epqh
->ep_type
==IFXUSB_EP_TYPE_CTRL
)
3935 if(((unsigned long)_epqh
->urbd
->setup_buff
) & _core_if
->unaligned_mask
)
3936 IFX_WARN("%s():%d SETUP xfer Buffer UNALIGNED\n",__func__
,__LINE__
);
3940 urbd
->aligned_checked
=1;
3945 \brief Assigns transactions from a URBD to a free host channel and initializes the
3946 host channel to perform the transactions. The host channel is removed from
3948 \param _ifxhcd The HCD state structure.
3949 \param _epqh Transactions from the first URBD for this EPQH are selected and assigned to a free host channel.
3952 int assign_hc(ifxhcd_hcd_t
*_ifxhcd
, ifxhcd_epqh_t
*_epqh
,ifxhcd_urbd_t
*_urbd
)
3957 IFX_DEBUGPL(DBG_HCDV
, "%s(%p,%p)\n", __func__
, _ifxhcd
, _epqh
);
3959 if(_ifxhcd
->disconnecting
)
3961 printk(KERN_INFO
"Warning: %s() Port is in discoonection\n",__func__
);
3965 if(!_epqh
) return 0;
3966 if(!_urbd
) return 0;
3967 if(!_urbd
->urb
) return 0;
3971 int num_channels
= _ifxhcd
->core_if
.params
.host_channels
;
3972 for(i
=0;i
<num_channels
; i
++)
3974 hcchar_data_t hcchar
;
3975 ifxusb_hc_regs_t
*hc_regs
;
3976 hc_regs
= _ifxhcd
->core_if
.hc_regs
[i
];
3977 if(_ifxhcd
->ifxhc
[i
].phase
!=HC_IDLE
)
3981 hcchar
.d32
= ifxusb_rreg(&hc_regs
->hcchar
);
3982 if(hcchar
.b
.chen
|| hcchar
.b
.chdis
)
3991 ifxhc
=&_ifxhcd
->ifxhc
[i
];
3992 ifxhc
->phase
=HC_ASSIGNED
;
4000 _epqh
->urbd
= _urbd
;
4001 ifxhc
->epqh
= _epqh
;
4003 * Use usb_pipedevice to determine device address. This address is
4004 * 0 before the SET_ADDRESS command and the correct address afterward.
4006 ifxhc
->dev_addr
= usb_pipedevice(urb
->pipe
);
4007 ifxhc
->ep_num
= usb_pipeendpoint(urb
->pipe
);
4009 if (urb
->dev
->speed
== USB_SPEED_LOW
) ifxhc
->speed
= IFXUSB_EP_SPEED_LOW
;
4010 else if (urb
->dev
->speed
== USB_SPEED_FULL
) ifxhc
->speed
= IFXUSB_EP_SPEED_FULL
;
4011 else ifxhc
->speed
= IFXUSB_EP_SPEED_HIGH
;
4013 ifxhc
->mps
= _epqh
->mps
;
4014 ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
4015 ifxhc
->ep_type
= _epqh
->ep_type
;
4018 if (_epqh
->need_split
)
4021 ifxhc
->hub_addr
= urb
->dev
->tt
->hub
->devnum
;
4022 ifxhc
->port_addr
= urb
->dev
->ttport
;
4028 \brief Assigns transactions from a URBD to a free host channel and initializes the
4029 host channel to perform the transactions. The host channel is removed from
4031 \param _ifxhcd The HCD state structure.
4032 \param _epqh Transactions from the first URBD for this EPQH are selected and assigned to a free host channel.
4035 void init_hc(ifxhcd_epqh_t
*_epqh
)
4038 ifxhcd_urbd_t
*urbd
;
4040 ifxhcd_hcd_t
*ifxhcd
;
4042 IFX_DEBUGPL(DBG_HCDV
, "%s(%p)\n", __func__
, _epqh
);
4046 ifxhcd
=_epqh
->ifxhcd
;
4048 #if defined(__UNALIGNED_BUF_ADJ__) || defined(__UNALIGNED_BUF_CHK__)
4049 urbd
->aligned_checked
=0;
4052 ifxhc
->halt_status
= HC_XFER_NO_HALT_STATUS
;
4054 if(_epqh
->ep_type
==IFXUSB_EP_TYPE_CTRL
)
4056 ifxhc
->control_phase
=IFXHCD_CONTROL_SETUP
;
4058 ifxhc
->data_pid_start
= IFXUSB_HC_PID_SETUP
;
4059 ifxhc
->xfer_buff
= urbd
->setup_buff
;
4060 ifxhc
->xfer_len
= 8;
4061 ifxhc
->xfer_count
= 0;
4062 ifxhc
->short_rw
=(urb
->transfer_flags
& URB_ZERO_PACKET
)?1:0;
4063 ifxhc
->sof_delay
= 0;
4065 if(!ifxhc
->is_in
&& ifxhc
->split
==0)
4068 else if(_epqh
->ep_type
==IFXUSB_EP_TYPE_ISOC
)
4071 struct usb_iso_packet_descriptor
*frame_desc
;
4072 ifxhc
->is_in
= urbd
->is_in
;
4073 frame_desc
= &urb
->iso_frame_desc
[urbd
->isoc_frame_index
];
4074 urbd
->xfer_len
= ifxhc
->xfer_len
= frame_desc
->length
;
4075 ifxhc
->xfer_buff
= urbd
->xfer_buff
;
4076 ifxhc
->xfer_buff
+= frame_desc
->offset
;
4077 ifxhc
->xfer_count
= 0;
4078 ifxhc
->sof_delay
= 0;
4079 if(usb_gettoggle (urb
->dev
,usb_pipeendpoint (urb
->pipe
), (ifxhc
->is_in
)?0:1))
4080 ifxhc
->data_pid_start
= IFXUSB_HCTSIZ_DATA1
;
4082 ifxhc
->data_pid_start
= IFXUSB_HCTSIZ_DATA0
;
4087 ifxhc
->short_rw
=(urb
->transfer_flags
& URB_ZERO_PACKET
)?1:0;
4088 #ifdef __EN_ISOC_SPLIT__
4089 ifxhc
->isoc_xact_pos
= IFXUSB_HCSPLIT_XACTPOS_ALL
;
4092 _epqh
->isoc_frame_index
=0;
4094 _epqh
->isoc_start_frame
=0;
4095 if(_urb
->transfer_flags
&& URB_ISO_ASAP
)
4098 _epqh
->isoc_start_frame
=_urb
->start_frame
;
4099 #ifdef __EN_ISOC_SPLIT__
4100 _epqh
->isoc_split_pos
=0;
4101 _epqh
->isoc_split_offset
=0;
4108 ifxhc
->is_in
= urbd
->is_in
;
4109 ifxhc
->xfer_buff
= urbd
->xfer_buff
;
4110 ifxhc
->xfer_len
= urbd
->xfer_len
;
4111 ifxhc
->xfer_count
= 0;
4112 ifxhc
->sof_delay
= 0;
4113 // if(ifxhc->xfer_len==13 && ifxhc->is_in && _epqh->ep_type==IFXUSB_EP_TYPE_BULK && ifxhc->split==0)
4114 // ifxhc->sof_delay = 8;
4115 if(usb_gettoggle (urb
->dev
,usb_pipeendpoint (urb
->pipe
), (ifxhc
->is_in
)?0:1))
4116 ifxhc
->data_pid_start
= IFXUSB_HCTSIZ_DATA1
;
4118 ifxhc
->data_pid_start
= IFXUSB_HCTSIZ_DATA0
;
4122 ifxhc
->short_rw
=(urb
->transfer_flags
& URB_ZERO_PACKET
)?1:0;
4124 if(!ifxhc
->is_in
&& ifxhc
->split
==0)
4126 if(_epqh
->ep_type
==IFXUSB_EP_TYPE_BULK
) _epqh
->do_ping
=1;
4131 hcint_data_t hc_intr_mask
;
4132 uint8_t hc_num
= ifxhc
->hc_num
;
4133 ifxusb_hc_regs_t
*hc_regs
= ifxhcd
->core_if
.hc_regs
[hc_num
];
4135 /* Clear old interrupt conditions for this host channel. */
4136 hc_intr_mask
.d32
= 0xFFFFFFFF;
4137 hc_intr_mask
.b
.reserved
= 0;
4138 ifxusb_wreg(&hc_regs
->hcint
, hc_intr_mask
.d32
);
4140 /* Enable channel interrupts required for this transfer. */
4141 hc_intr_mask
.d32
= 0;
4142 hc_intr_mask
.b
.chhltd
= 1;
4143 hc_intr_mask
.b
.ahberr
= 1;
4145 ifxusb_wreg(&hc_regs
->hcintmsk
, hc_intr_mask
.d32
);
4147 /* Enable the top level host channel interrupt. */
4149 uint32_t intr_enable
;
4150 intr_enable
= (1 << hc_num
);
4151 ifxusb_mreg(&ifxhcd
->core_if
.host_global_regs
->haintmsk
, 0, intr_enable
);
4154 /* Make sure host channel interrupts are enabled. */
4156 gint_data_t gintmsk
={.d32
= 0};
4157 gintmsk
.b
.hcintr
= 1;
4158 ifxusb_mreg(&ifxhcd
->core_if
.core_global_regs
->gintmsk
, 0, gintmsk
.d32
);
4162 * Program the HCCHARn register with the endpoint characteristics for
4163 * the current transfer.
4166 hcchar_data_t hcchar
;
4169 hcchar
.b
.devaddr
= ifxhc
->dev_addr
;
4170 hcchar
.b
.epnum
= ifxhc
->ep_num
;
4171 hcchar
.b
.lspddev
= (ifxhc
->speed
== IFXUSB_EP_SPEED_LOW
);
4172 hcchar
.b
.eptype
= ifxhc
->ep_type
;
4173 hcchar
.b
.mps
= ifxhc
->mps
;
4174 ifxusb_wreg(&hc_regs
->hcchar
, hcchar
.d32
);
4176 IFX_DEBUGPL(DBG_HCDV
, "%s: Channel %d\n", __func__
, ifxhc
->hc_num
);
4177 IFX_DEBUGPL(DBG_HCDV
, " Dev Addr: %d\n" , hcchar
.b
.devaddr
);
4178 IFX_DEBUGPL(DBG_HCDV
, " Ep Num: %d\n" , hcchar
.b
.epnum
);
4179 IFX_DEBUGPL(DBG_HCDV
, " Is Low Speed: %d\n", hcchar
.b
.lspddev
);
4180 IFX_DEBUGPL(DBG_HCDV
, " Ep Type: %d\n" , hcchar
.b
.eptype
);
4181 IFX_DEBUGPL(DBG_HCDV
, " Max Pkt: %d\n" , hcchar
.b
.mps
);
4182 IFX_DEBUGPL(DBG_HCDV
, " Multi Cnt: %d\n" , hcchar
.b
.multicnt
);
4184 /* Program the HCSPLIT register for SPLITs */
4186 hcsplt_data_t hcsplt
;
4191 IFX_DEBUGPL(DBG_HCDV
, "Programming HC %d with split --> %s\n", ifxhc
->hc_num
,
4192 (ifxhc
->split
==2) ? "CSPLIT" : "SSPLIT");
4193 hcsplt
.b
.spltena
= 1;
4194 hcsplt
.b
.compsplt
= (ifxhc
->split
==2);
4195 #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__)
4196 if(_epqh
->ep_type
==IFXUSB_EP_TYPE_ISOC
)
4197 hcsplt
.b
.xactpos
= ifxhc
->isoc_xact_pos
;
4200 hcsplt
.b
.xactpos
= IFXUSB_HCSPLIT_XACTPOS_ALL
;
4201 hcsplt
.b
.hubaddr
= ifxhc
->hub_addr
;
4202 hcsplt
.b
.prtaddr
= ifxhc
->port_addr
;
4203 IFX_DEBUGPL(DBG_HCDV
, " comp split %d\n" , hcsplt
.b
.compsplt
);
4204 IFX_DEBUGPL(DBG_HCDV
, " xact pos %d\n" , hcsplt
.b
.xactpos
);
4205 IFX_DEBUGPL(DBG_HCDV
, " hub addr %d\n" , hcsplt
.b
.hubaddr
);
4206 IFX_DEBUGPL(DBG_HCDV
, " port addr %d\n" , hcsplt
.b
.prtaddr
);
4207 IFX_DEBUGPL(DBG_HCDV
, " is_in %d\n" , ifxhc
->is_in
);
4208 IFX_DEBUGPL(DBG_HCDV
, " Max Pkt: %d\n" , ifxhc
->mps
);
4209 IFX_DEBUGPL(DBG_HCDV
, " xferlen: %d\n" , ifxhc
->xfer_len
);
4211 ifxusb_wreg(&hc_regs
->hcsplt
, hcsplt
.d32
);
4214 process_unaligned(_epqh
,&ifxhcd
->core_if
);
4219 if (!ifxhc
->split
&& ifxhc
->ep_type
== IFXUSB_EP_TYPE_BULK
)
4221 #ifdef __INNAKSTOP_BULK__
4225 #ifdef __PINGSTOP_BULK__
4235 void select_eps_sub(ifxhcd_hcd_t
*_ifxhcd
)
4237 struct list_head
*epqh_ptr
;
4238 ifxhcd_epqh_t
*epqh
;
4239 struct list_head
*urbd_ptr
;
4240 unsigned long flags
;
4241 ifxhcd_urbd_t
*urbd
;
4246 if(_ifxhcd
->disconnecting
)
4248 // printk(KERN_INFO "Warning: %s() Port is in discoonection\n",__func__);
4252 local_irq_save(flags
);
4253 LOCK_EPQH_LIST(_ifxhcd
);
4255 hfnum
.d32
= ifxusb_rreg(&_ifxhcd
->core_if
.host_global_regs
->hfnum
);
4256 fndiff
= hfnum
.b
.frnum
;
4257 fndiff
+= 0x00004000;
4258 fndiff
-= _ifxhcd
->lastframe
;
4259 fndiff
&= 0x00003FFF;
4260 if(!fndiff
) fndiff
=1;
4263 epqh_ptr
= _ifxhcd
->epqh_list_isoc
.next
;
4264 while (epqh_ptr
!= &_ifxhcd
->epqh_list_isoc
)
4266 epqh
= list_entry(epqh_ptr
, ifxhcd_epqh_t
, ql
);
4267 epqh_ptr
= epqh_ptr
->next
;
4269 #ifdef __DYN_SOF_INTR__
4270 if (!list_empty(&epqh
->urbd_list
))
4271 _ifxhcd
->dyn_sof_count
= DYN_SOF_COUNT_DEF
;
4276 if(epqh
->phase
==EPQH_READY
)
4278 if(update_interval_counter(epqh
,fndiff
) || epqh
->isoc_now
)
4280 LOCK_URBD_LIST(epqh
);
4281 urbd_ptr
= epqh
->urbd_list
.next
;
4282 while (urbd_ptr
!= &epqh
->urbd_list
)
4284 urbd
= list_entry(urbd_ptr
, ifxhcd_urbd_t
, ql
);
4285 urbd_ptr
=urbd_ptr
->next
;
4286 if(urbd
->phase
==URBD_IDLE
)
4288 if(assign_hc(_ifxhcd
, epqh
,urbd
))
4290 IFX_DEBUGPL(DBG_HCD
, " select_eps ISOC\n");
4291 #ifdef __EPQD_DESTROY_TIMEOUT__
4292 del_timer(&epqh
->destroy_timer
);
4295 list_del_init (&epqh
->ql
);
4296 list_add_tail(&epqh
->ql
, &_ifxhcd
->epqh_list_isoc
);
4298 epqh
->phase
=EPQH_ACTIVE
;
4299 urbd
->phase
==URBD_ACTIVE
;
4300 epqh
->hc
.phase
=HC_WAITING
;
4301 ifxhcd_hc_start(_ifxhcd
, epqh
->hc
);
4306 UNLOCK_URBD_LIST(epqh
);
4310 #endif //__EN_ISOC__
4312 epqh_ptr
= _ifxhcd
->epqh_list_intr
.next
;
4313 while (epqh_ptr
!= &_ifxhcd
->epqh_list_intr
)
4315 epqh
= list_entry(epqh_ptr
, ifxhcd_epqh_t
, ql
);
4316 epqh_ptr
= epqh_ptr
->next
;
4317 #ifdef __DYN_SOF_INTR__
4318 if (!list_empty(&epqh
->urbd_list
))
4319 _ifxhcd
->dyn_sof_count
= DYN_SOF_COUNT_DEF
;
4323 if(epqh
->phase
==EPQH_READY
)
4325 if(update_interval_counter(epqh
,fndiff
))
4327 LOCK_URBD_LIST(epqh
);
4328 urbd_ptr
= epqh
->urbd_list
.next
;
4329 while (urbd_ptr
!= &epqh
->urbd_list
)
4331 urbd
= list_entry(urbd_ptr
, ifxhcd_urbd_t
, ql
);
4332 urbd_ptr
=urbd_ptr
->next
;
4333 if(urbd
->phase
==URBD_IDLE
)
4335 if(assign_hc(_ifxhcd
, epqh
,urbd
))
4337 IFX_DEBUGPL(DBG_HCD
, " select_eps INTR\n");
4338 #ifdef __EPQD_DESTROY_TIMEOUT__
4339 del_timer(&epqh
->destroy_timer
);
4341 list_del_init (&epqh
->ql
);
4342 list_add_tail(&epqh
->ql
, &_ifxhcd
->epqh_list_intr
);
4344 epqh
->phase
=EPQH_ACTIVE
;
4345 urbd
->phase
=URBD_ACTIVE
;
4346 epqh
->hc
->phase
=HC_WAITING
;
4347 ifxhcd_hc_start(_ifxhcd
, epqh
->hc
);
4352 UNLOCK_URBD_LIST(epqh
);
4355 else if(epqh
->phase
==EPQH_STDBY
)
4357 if(epqh
->period_counter
> 0 )
4358 epqh
->period_counter
--;
4359 if(epqh
->period_counter
== 0)
4360 ifxhcd_epqh_idle_periodic(epqh
);
4361 update_interval_counter(epqh
,fndiff
);
4364 update_interval_counter(epqh
,fndiff
);
4367 epqh_ptr
= _ifxhcd
->epqh_list_np
.next
;
4368 while (epqh_ptr
!= &_ifxhcd
->epqh_list_np
) // may need to preserve at lease one for period
4370 epqh
= list_entry(epqh_ptr
, ifxhcd_epqh_t
, ql
);
4371 epqh_ptr
= epqh_ptr
->next
;
4372 #ifdef __DYN_SOF_INTR__
4373 if (!list_empty(&epqh
->urbd_list
))
4374 _ifxhcd
->dyn_sof_count
= DYN_SOF_COUNT_DEF
;
4378 if(epqh
->phase
==EPQH_READY
)
4380 LOCK_URBD_LIST(epqh
);
4381 urbd_ptr
= epqh
->urbd_list
.next
;
4382 while (urbd_ptr
!= &epqh
->urbd_list
)
4384 urbd
= list_entry(urbd_ptr
, ifxhcd_urbd_t
, ql
);
4385 urbd_ptr
=urbd_ptr
->next
;
4386 if(urbd
->phase
==URBD_IDLE
)
4388 if(assign_hc(_ifxhcd
, epqh
,urbd
))
4390 IFX_DEBUGPL(DBG_HCD
, " select_eps Non-Period\n");
4391 #ifdef __EPQD_DESTROY_TIMEOUT__
4392 del_timer(&epqh
->destroy_timer
);
4394 list_del_init (&epqh
->ql
);
4395 list_add_tail(&epqh
->ql
, &_ifxhcd
->epqh_list_np
);
4397 epqh
->phase
=EPQH_ACTIVE
;
4398 urbd
->phase
=URBD_ACTIVE
;
4399 epqh
->hc
->phase
=HC_WAITING
;
4400 ifxhcd_hc_start(_ifxhcd
, epqh
->hc
);
4405 UNLOCK_URBD_LIST(epqh
);
4409 _ifxhcd
->lastframe
=hfnum
.b
.frnum
;
4411 UNLOCK_EPQH_LIST(_ifxhcd
);
4412 local_irq_restore(flags
);
4416 void select_eps_func(unsigned long data
)
4418 ifxhcd_hcd_t
*ifxhcd
;
4419 ifxhcd
=((ifxhcd_hcd_t
*)data
);
4421 select_eps_sub(ifxhcd
);
4425 \fn void select_eps(ifxhcd_hcd_t *_ifxhcd)
4426 \brief This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
4427 \param _ifxhcd Pointer to the sate of HCD structure
4430 void select_eps(ifxhcd_hcd_t
*_ifxhcd
)
4434 if(!_ifxhcd
->tasklet_select_eps
.func
)
4436 _ifxhcd
->tasklet_select_eps
.next
= NULL
;
4437 _ifxhcd
->tasklet_select_eps
.state
= 0;
4438 atomic_set( &_ifxhcd
->tasklet_select_eps
.count
, 0);
4439 _ifxhcd
->tasklet_select_eps
.func
= select_eps_func
;
4440 _ifxhcd
->tasklet_select_eps
.data
= (unsigned long)_ifxhcd
;
4442 tasklet_schedule(&_ifxhcd
->tasklet_select_eps
);
4446 select_eps_sub(_ifxhcd
);
4451 void ifxhcd_hc_kickstart(ifxhcd_hcd_t
*_ifxhcd
)
4454 ifxusb_hc_regs_t
*hc_regs
;
4457 num_channels
= _ifxhcd
->core_if
.params
.host_channels
;
4459 for (i
= 0; i
< num_channels
; i
++)
4461 ifxhc
=&_ifxhcd
->ifxhc
[i
];
4462 if(ifxhc
->phase
==HC_STARTING
)
4464 if(ifxhc
->sof_delay
) ifxhc
->sof_delay
--;
4465 if(!ifxhc
->sof_delay
)
4469 hc_regs
= _ifxhcd
->core_if
.hc_regs
[i
];
4470 hcint
.d32
=0xFFFFFFFF;
4471 ifxusb_wreg(&hc_regs
->hcint
, hcint
.d32
);
4472 hcint
.d32
=ifxusb_rreg(&hc_regs
->hcintmsk
);
4489 ifxusb_wreg(&hc_regs
->hcintmsk
, hcint
.d32
);
4490 ifxusb_wreg(&hc_regs
->hcchar
, ifxhc
->hcchar
);
4491 ifxhc
->phase
=HC_STARTED
;
4496 for (i
= 0; i
< num_channels
; i
++)
4498 ifxhc
=&_ifxhcd
->ifxhc
[i
];
4499 if(ifxhc
->phase
==HC_WAITING
&&
4500 (ifxhc
->ep_type
== IFXUSB_EP_TYPE_INTR
|| ifxhc
->ep_type
== IFXUSB_EP_TYPE_ISOC
)
4503 ifxhcd_hc_start(_ifxhcd
, ifxhc
);
4507 for (i
= 0; i
< num_channels
; i
++)
4509 ifxhc
=&_ifxhcd
->ifxhc
[i
];
4510 if(ifxhc
->phase
==HC_WAITING
)
4512 ifxhcd_hc_start(_ifxhcd
, ifxhc
);
4518 * Handles the start-of-frame interrupt in host mode. Non-periodic
4519 * transactions may be queued to the DWC_otg controller for the current
4520 * (micro)frame. Periodic transactions may be queued to the controller for the
4521 * next (micro)frame.
4524 int32_t handle_sof_intr (ifxhcd_hcd_t
*_ifxhcd
)
4526 _ifxhcd
->pkt_remaining
=_ifxhcd
->pkt_remaining_reload
;
4527 ifxhcd_hc_kickstart(_ifxhcd
);
4529 select_eps(_ifxhcd
);
4531 /* Clear interrupt */
4533 gint_data_t gintsts
;
4535 gintsts
.b
.sofintr
= 1;
4536 ifxusb_wreg(&_ifxhcd
->core_if
.core_global_regs
->gintsts
, gintsts
.d32
);
4538 #ifdef __DYN_SOF_INTR__
4539 if(_ifxhcd
->dyn_sof_count
)
4540 _ifxhcd
->dyn_sof_count
--;
4541 if(!_ifxhcd
->dyn_sof_count
)
4542 ifxusb_mreg(&_ifxhcd
->core_if
.core_global_regs
->gintmsk
, gintsts
.d32
,0);
4550 /* There are multiple conditions that can cause a port interrupt. This function
4551 * determines which interrupt conditions have occurred and handles them
4553 static int32_t handle_port_intr (ifxhcd_hcd_t
*_ifxhcd
)
4557 hprt0_data_t hprt0_modify
;
4560 hprt0_modify
.d32
= ifxusb_rreg(_ifxhcd
->core_if
.hprt0
);
4562 /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
4565 hprt0_modify
.b
.prtena
= 0;
4566 hprt0_modify
.b
.prtconndet
= 0;
4567 hprt0_modify
.b
.prtenchng
= 0;
4568 hprt0_modify
.b
.prtovrcurrchng
= 0;
4570 /* Port Connect Detected
4571 * Set flag and clear if detected */
4572 if (hprt0
.b
.prtconndet
) {
4573 IFX_DEBUGPL(DBG_HCD
, "--Port Interrupt HPRT0=0x%08x "
4574 "Port Connect Detected--\n", hprt0
.d32
);
4575 _ifxhcd
->flags
.b
.port_connect_status_change
= 1;
4576 _ifxhcd
->flags
.b
.port_connect_status
= 1;
4577 hprt0_modify
.b
.prtconndet
= 1;
4579 /* The Hub driver asserts a reset when it sees port connect
4580 * status change flag */
4584 /* Port Enable Changed
4585 * Clear if detected - Set internal flag if disabled */
4586 if (hprt0
.b
.prtenchng
) {
4587 IFX_DEBUGPL(DBG_HCD
, " --Port Interrupt HPRT0=0x%08x "
4588 "Port Enable Changed--\n", hprt0
.d32
);
4589 hprt0_modify
.b
.prtenchng
= 1;
4590 if (hprt0
.b
.prtena
== 1)
4592 /* Port has been enabled set the reset change flag */
4593 _ifxhcd
->flags
.b
.port_reset_change
= 1;
4594 if (hprt0
.b
.prtspd
== IFXUSB_HPRT0_PRTSPD_HIGH_SPEED
)
4595 _ifxhcd
->pkt_remaining_reload
=_ifxhcd
->pkt_remaining_reload_hs
;
4596 else if (hprt0
.b
.prtspd
== IFXUSB_HPRT0_PRTSPD_LOW_SPEED
)
4597 _ifxhcd
->pkt_remaining_reload
=_ifxhcd
->pkt_remaining_reload_ls
;
4599 _ifxhcd
->pkt_remaining_reload
=_ifxhcd
->pkt_remaining_reload_fs
;
4602 _ifxhcd
->flags
.b
.port_enable_change
= 1;
4606 /* Overcurrent Change Interrupt */
4608 if (hprt0
.b
.prtovrcurrchng
) {
4609 IFX_DEBUGPL(DBG_HCD
, " --Port Interrupt HPRT0=0x%08x "
4610 "Port Overcurrent Changed--\n", hprt0
.d32
);
4611 _ifxhcd
->flags
.b
.port_over_current_change
= 1;
4612 hprt0_modify
.b
.prtovrcurrchng
= 1;
4616 /* Clear Port Interrupts */
4617 ifxusb_wreg(_ifxhcd
->core_if
.hprt0
, hprt0_modify
.d32
);
4622 * This interrupt indicates that SUSPEND state has been detected on
4624 * No Functioning in Host Mode
4626 static int32_t handle_usb_suspend_intr(ifxhcd_hcd_t
*_ifxhcd
)
4628 gint_data_t gintsts
;
4629 IFX_DEBUGP("USB SUSPEND RECEIVED!\n");
4630 /* Clear interrupt */
4632 gintsts
.b
.usbsuspend
= 1;
4633 ifxusb_wreg(&_ifxhcd
->core_if
.core_global_regs
->gintsts
, gintsts
.d32
);
4638 * This interrupt indicates that the IFXUSB controller has detected a
4639 * resume or remote wakeup sequence. If the IFXUSB controller is in
4640 * low power mode, the handler must brings the controller out of low
4641 * power mode. The controller automatically begins resume
4642 * signaling. The handler schedules a time to stop resume signaling.
4644 static int32_t handle_wakeup_detected_intr(ifxhcd_hcd_t
*_ifxhcd
)
4646 gint_data_t gintsts
;
4647 hprt0_data_t hprt0
= {.d32
=0};
4648 pcgcctl_data_t pcgcctl
= {.d32
=0};
4649 ifxusb_core_if_t
*core_if
= &_ifxhcd
->core_if
;
4651 IFX_DEBUGPL(DBG_ANY
, "++Resume and Remote Wakeup Detected Interrupt++\n");
4654 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
4655 * so that OPT tests pass with all PHYs).
4657 /* Restart the Phy Clock */
4658 pcgcctl
.b
.stoppclk
= 1;
4659 ifxusb_mreg(core_if
->pcgcctl
, pcgcctl
.d32
, 0);
4662 /* Now wait for 70 ms. */
4663 hprt0
.d32
= ifxusb_read_hprt0( core_if
);
4664 IFX_DEBUGPL(DBG_ANY
,"Resume: HPRT0=%0x\n", hprt0
.d32
);
4666 hprt0
.b
.prtres
= 0; /* Resume */
4667 ifxusb_wreg(core_if
->hprt0
, hprt0
.d32
);
4668 IFX_DEBUGPL(DBG_ANY
,"Clear Resume: HPRT0=%0x\n", ifxusb_rreg(core_if
->hprt0
));
4670 /* Clear interrupt */
4672 gintsts
.b
.wkupintr
= 1;
4673 ifxusb_wreg(&core_if
->core_global_regs
->gintsts
, gintsts
.d32
);
4678 * This interrupt indicates that a device is initiating the Session
4679 * Request Protocol to request the host to turn on bus power so a new
4680 * session can begin. The handler responds by turning on bus power. If
4681 * the DWC_otg controller is in low power mode, the handler brings the
4682 * controller out of low power mode before turning on bus power.
4684 static int32_t handle_session_req_intr(ifxhcd_hcd_t
*_ifxhcd
)
4686 /* Clear interrupt */
4687 gint_data_t gintsts
= { .d32
= 0 };
4688 gintsts
.b
.sessreqintr
= 1;
4689 ifxusb_wreg(&_ifxhcd
->core_if
.core_global_regs
->gintsts
, gintsts
.d32
);
4694 * This interrupt indicates that a device has been disconnected from
4697 static int32_t handle_disconnect_intr(ifxhcd_hcd_t
*_ifxhcd
)
4699 gint_data_t gintsts
;
4701 ifxhcd_disconnect(_ifxhcd
);
4704 gintsts
.b
.disconnect
= 1;
4705 ifxusb_wreg(&_ifxhcd
->core_if
.core_global_regs
->gintsts
, gintsts
.d32
);
4710 * This function handles the Connector ID Status Change Interrupt. It
4711 * reads the OTG Interrupt Register (GOTCTL) to determine whether this
4712 * is a Device to Host Mode transition or a Host Mode to Device
4714 * This only occurs when the cable is connected/removed from the PHY
4717 static int32_t handle_conn_id_status_change_intr(ifxhcd_hcd_t
*_ifxhcd
)
4719 gint_data_t gintsts
;
4721 IFX_WARN("ID Status Change Interrupt: currently in %s mode\n",
4722 ifxusb_mode(&_ifxhcd
->core_if
) ? "Host" : "Device");
4725 gintsts
.b
.conidstschng
= 1;
4726 ifxusb_wreg(&_ifxhcd
->core_if
.core_global_regs
->gintsts
, gintsts
.d32
);
4730 static int32_t handle_otg_intr(ifxhcd_hcd_t
*_ifxhcd
)
4732 ifxusb_core_global_regs_t
*global_regs
= _ifxhcd
->core_if
.core_global_regs
;
4733 gotgint_data_t gotgint
;
4734 gotgint
.d32
= ifxusb_rreg( &global_regs
->gotgint
);
4736 ifxusb_wreg (&global_regs
->gotgint
, gotgint
.d32
);
4740 /** This function will log a debug message */
4741 static int32_t handle_mode_mismatch_intr(ifxhcd_hcd_t
*_ifxhcd
)
4743 gint_data_t gintsts
;
4745 IFX_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
4746 ifxusb_mode(&_ifxhcd
->core_if
) ? "Host" : "Device");
4748 gintsts
.b
.modemismatch
= 1;
4749 ifxusb_wreg(&_ifxhcd
->core_if
.core_global_regs
->gintsts
, gintsts
.d32
);
4753 /** This function handles interrupts for the HCD. */
4754 int32_t ifxhcd_handle_intr (ifxhcd_hcd_t
*_ifxhcd
)
4758 ifxusb_core_if_t
*core_if
= &_ifxhcd
->core_if
;
4759 gint_data_t gintsts
,gintsts2
;
4761 /* Check if HOST Mode */
4762 if (ifxusb_is_device_mode(core_if
))
4764 IFX_ERROR("%s() CRITICAL! IN DEVICE MODE\n", __func__
);
4768 gintsts
.d32
= ifxusb_read_core_intr(core_if
);
4775 if (gintsts
.b
.modemismatch
)
4777 retval
|= handle_mode_mismatch_intr(_ifxhcd
);
4778 gintsts
.b
.modemismatch
=0;
4779 gintsts2
.b
.modemismatch
=1;
4781 if (gintsts
.b
.otgintr
)
4783 retval
|= handle_otg_intr(_ifxhcd
);
4784 gintsts
.b
.otgintr
=0;
4785 gintsts2
.b
.otgintr
=1;
4787 if (gintsts
.b
.conidstschng
)
4789 retval
|= handle_conn_id_status_change_intr(_ifxhcd
);
4790 gintsts
.b
.conidstschng
=0;
4791 gintsts2
.b
.conidstschng
=1;
4793 if (gintsts
.b
.disconnect
)
4795 retval
|= handle_disconnect_intr(_ifxhcd
);
4796 gintsts
.b
.disconnect
=0;
4797 gintsts2
.b
.disconnect
=1;
4799 if (gintsts
.b
.sessreqintr
)
4801 retval
|= handle_session_req_intr(_ifxhcd
);
4802 gintsts
.b
.sessreqintr
=0;
4803 gintsts2
.b
.sessreqintr
=1;
4805 if (gintsts
.b
.wkupintr
)
4807 retval
|= handle_wakeup_detected_intr(_ifxhcd
);
4808 gintsts
.b
.wkupintr
=0;
4809 gintsts2
.b
.wkupintr
=1;
4811 if (gintsts
.b
.usbsuspend
)
4813 retval
|= handle_usb_suspend_intr(_ifxhcd
);
4814 gintsts
.b
.usbsuspend
=0;
4815 gintsts2
.b
.usbsuspend
=1;
4819 if (gintsts
.b
.sofintr
)
4821 retval
|= handle_sof_intr (_ifxhcd
);
4822 gintsts
.b
.sofintr
=0;
4823 gintsts2
.b
.sofintr
=1;
4825 if (gintsts
.b
.portintr
)
4827 retval
|= handle_port_intr (_ifxhcd
);
4828 gintsts
.b
.portintr
=0;
4829 gintsts2
.b
.portintr
=1;
4831 if (gintsts
.b
.hcintr
)
4835 haint
.d32
= ifxusb_read_host_all_channels_intr(core_if
);
4836 for (i
=0; i
<MAX_EPS_CHANNELS
&& i
< core_if
->params
.host_channels
; i
++)
4837 if (haint
.b2
.chint
& (1 << i
))
4838 retval
|= handle_hc_n_intr (_ifxhcd
, i
);
4840 gintsts2
.b
.hcintr
=1;