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[openwrt/svn-archive/archive.git] / package / rt2x00 / src / rt2500pci.c
1 /*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 /*
28 * Set enviroment defines for rt2x00.h
29 */
30 #define DRV_NAME "rt2500pci"
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/version.h>
35 #include <linux/init.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/delay.h>
39 #include <linux/etherdevice.h>
40 #include <linux/eeprom_93cx6.h>
41
42 #include <asm/io.h>
43
44 #include "rt2x00.h"
45 #include "rt2x00lib.h"
46 #include "rt2x00pci.h"
47 #include "rt2500pci.h"
48
49 /*
50 * Register access.
51 * All access to the CSR registers will go through the methods
52 * rt2x00pci_register_read and rt2x00pci_register_write.
53 * BBP and RF register require indirect register access,
54 * and use the CSR registers BBPCSR and RFCSR to achieve this.
55 * These indirect registers work with busy bits,
56 * and we will try maximal REGISTER_BUSY_COUNT times to access
57 * the register while taking a REGISTER_BUSY_DELAY us delay
58 * between each attampt. When the busy bit is still set at that time,
59 * the access attempt is considered to have failed,
60 * and we will print an error.
61 */
62 static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
63 {
64 u32 reg;
65 unsigned int i;
66
67 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
68 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
69 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
70 break;
71 udelay(REGISTER_BUSY_DELAY);
72 }
73
74 return reg;
75 }
76
77 static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
78 const u8 reg_id, const u8 value)
79 {
80 u32 reg;
81
82 /*
83 * Wait until the BBP becomes ready.
84 */
85 reg = rt2500pci_bbp_check(rt2x00dev);
86 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
87 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
88 return;
89 }
90
91 /*
92 * Write the data into the BBP.
93 */
94 reg = 0;
95 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
96 rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
97 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
98 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
99
100 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
101 }
102
103 static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
104 const u8 reg_id, u8 *value)
105 {
106 u32 reg;
107
108 /*
109 * Wait until the BBP becomes ready.
110 */
111 reg = rt2500pci_bbp_check(rt2x00dev);
112 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
113 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
114 return;
115 }
116
117 /*
118 * Write the request into the BBP.
119 */
120 reg = 0;
121 rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
122 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
123 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
124
125 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
126
127 /*
128 * Wait until the BBP becomes ready.
129 */
130 reg = rt2500pci_bbp_check(rt2x00dev);
131 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
132 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
133 *value = 0xff;
134 return;
135 }
136
137 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
138 }
139
140 static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
141 const u32 value)
142 {
143 u32 reg;
144 unsigned int i;
145
146 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
147 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
148 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
149 goto rf_write;
150 udelay(REGISTER_BUSY_DELAY);
151 }
152
153 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
154 return;
155
156 rf_write:
157 reg = 0;
158 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
159 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
160 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
161 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
162
163 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
164 }
165
166 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
167 {
168 struct rt2x00_dev *rt2x00dev = eeprom->data;
169 u32 reg;
170
171 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
172
173 eeprom->reg_data_in = !!rt2x00_get_field32(reg,
174 CSR21_EEPROM_DATA_IN);
175 eeprom->reg_data_out = !!rt2x00_get_field32(reg,
176 CSR21_EEPROM_DATA_OUT);
177 eeprom->reg_data_clock = !!rt2x00_get_field32(reg,
178 CSR21_EEPROM_DATA_CLOCK);
179 eeprom->reg_chip_select = !!rt2x00_get_field32(reg,
180 CSR21_EEPROM_CHIP_SELECT);
181 }
182
183 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
184 {
185 struct rt2x00_dev *rt2x00dev = eeprom->data;
186 u32 reg = 0;
187
188 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN,
189 !!eeprom->reg_data_in);
190 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT,
191 !!eeprom->reg_data_out);
192 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
193 !!eeprom->reg_data_clock);
194 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
195 !!eeprom->reg_chip_select);
196
197 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
198 }
199
200 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
201 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
202
203 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
204 const unsigned long word, void *data)
205 {
206 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
207 }
208
209 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
210 const unsigned long word, void *data)
211 {
212 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), *((u32*)data));
213 }
214
215 static void rt2500pci_read_eeprom(struct rt2x00_dev *rt2x00dev,
216 const unsigned long word, void *data)
217 {
218 rt2x00_eeprom_read(rt2x00dev, word, data);
219 }
220
221 static void rt2500pci_write_eeprom(struct rt2x00_dev *rt2x00dev,
222 const unsigned long word, void *data)
223 {
224 rt2x00_eeprom_write(rt2x00dev, word, *((u16*)data));
225 }
226
227 static void rt2500pci_read_bbp(struct rt2x00_dev *rt2x00dev,
228 const unsigned long word, void *data)
229 {
230 rt2500pci_bbp_read(rt2x00dev, word, data);
231 }
232
233 static void rt2500pci_write_bbp(struct rt2x00_dev *rt2x00dev,
234 const unsigned long word, void *data)
235 {
236 rt2500pci_bbp_write(rt2x00dev, word, *((u8*)data));
237 }
238
239 static const struct rt2x00debug rt2500pci_rt2x00debug = {
240 .owner = THIS_MODULE,
241 .reg_csr = {
242 .read = rt2500pci_read_csr,
243 .write = rt2500pci_write_csr,
244 .word_size = sizeof(u32),
245 .word_count = CSR_REG_SIZE / sizeof(u32),
246 },
247 .reg_eeprom = {
248 .read = rt2500pci_read_eeprom,
249 .write = rt2500pci_write_eeprom,
250 .word_size = sizeof(u16),
251 .word_count = EEPROM_SIZE / sizeof(u16),
252 },
253 .reg_bbp = {
254 .read = rt2500pci_read_bbp,
255 .write = rt2500pci_write_bbp,
256 .word_size = sizeof(u8),
257 .word_count = BBP_SIZE / sizeof(u8),
258 },
259 };
260 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
261
262 #ifdef CONFIG_RT2500PCI_RFKILL
263 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
264 {
265 u32 reg;
266
267 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
268 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
269 }
270 #endif /* CONFIG_RT2400PCI_RFKILL */
271
272 /*
273 * Configuration handlers.
274 */
275 static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
276 {
277 u32 reg[2];
278
279 memset(&reg, 0, sizeof(reg));
280 memcpy(&reg, bssid, ETH_ALEN);
281
282 /*
283 * The BSSID is passed to us as an array of bytes,
284 * that array is little endian, so no need for byte ordering.
285 */
286 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, &reg, sizeof(reg));
287 }
288
289 static void rt2500pci_config_promisc(struct rt2x00_dev *rt2x00dev,
290 const int promisc)
291 {
292 u32 reg;
293
294 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
295 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, !promisc);
296 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
297 }
298
299 static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev,
300 const int type)
301 {
302 u32 reg;
303
304 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
305
306 /*
307 * Apply hardware packet filter.
308 */
309 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
310
311 if (!is_monitor_present(&rt2x00dev->interface) &&
312 (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
313 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 1);
314 else
315 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 0);
316
317 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 1);
318 if (is_monitor_present(&rt2x00dev->interface)) {
319 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 0);
320 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 0);
321 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 0);
322 } else {
323 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 1);
324 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 1);
325 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
326 }
327
328 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST, 0);
329 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
330
331 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
332
333 /*
334 * Enable beacon config
335 */
336 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
337 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
338 PREAMBLE + get_duration(IEEE80211_HEADER, 2));
339 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
340 rt2x00_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON)
341 ->tx_params.cw_min);
342 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
343
344 /*
345 * Enable synchronisation.
346 */
347 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
348 if (is_interface_present(&rt2x00dev->interface)) {
349 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
350 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
351 }
352
353 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
354 if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
355 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
356 else if (type == IEEE80211_IF_TYPE_STA)
357 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
358 else if (is_monitor_present(&rt2x00dev->interface) &&
359 !is_interface_present(&rt2x00dev->interface))
360 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
361
362 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
363 }
364
365 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
366 const int value, const int channel, const int txpower)
367 {
368 u32 rf1 = rt2x00dev->rf1;
369 u32 rf2 = value;
370 u32 rf3 = rt2x00dev->rf3;
371 u32 rf4 = rt2x00dev->rf4;
372 u8 r70;
373
374 if (rt2x00_rf(&rt2x00dev->chip, RF2525) ||
375 rt2x00_rf(&rt2x00dev->chip, RF2525E))
376 rf2 |= 0x00080000;
377
378 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) && channel == 14)
379 rf4 |= 0x00000010;
380
381 if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
382 if (channel < 14) {
383 rf1 = 0x00022020;
384 rf4 = 0x00000a0b;
385 } else if (channel == 14) {
386 rf1 = 0x00022010;
387 rf4 = 0x00000a1b;
388 } else if (channel < 64) {
389 rf1 = 0x00022010;
390 rf4 = 0x00000a1f;
391 } else if (channel < 140) {
392 rf1 = 0x00022010;
393 rf4 = 0x00000a0f;
394 } else if (channel < 161) {
395 rf1 = 0x00022020;
396 rf4 = 0x00000a07;
397 }
398 }
399
400 /*
401 * Set TXpower.
402 */
403 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
404
405 /*
406 * Switch on tuning bits.
407 * For RT2523 devices we do not need to update the R1 register.
408 */
409 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
410 rt2x00_set_field32(&rf1, RF1_TUNER, 1);
411 rt2x00_set_field32(&rf3, RF3_TUNER, 1);
412
413 /*
414 * For RT2525 we should first set the channel to half band higher.
415 */
416 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
417 static const u32 vals[] = {
418 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
419 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
420 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
421 0x00080d2e, 0x00080d3a
422 };
423
424 rt2500pci_rf_write(rt2x00dev, rf1);
425 rt2500pci_rf_write(rt2x00dev, vals[channel - 1]);
426 rt2500pci_rf_write(rt2x00dev, rf3);
427 if (rf4)
428 rt2500pci_rf_write(rt2x00dev, rf4);
429 }
430
431 rt2500pci_rf_write(rt2x00dev, rf1);
432 rt2500pci_rf_write(rt2x00dev, rf2);
433 rt2500pci_rf_write(rt2x00dev, rf3);
434 if (rf4)
435 rt2500pci_rf_write(rt2x00dev, rf4);
436
437 /*
438 * Channel 14 requires the Japan filter bit to be set.
439 */
440 r70 = 0x46;
441 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, channel == 14);
442 rt2500pci_bbp_write(rt2x00dev, 70, r70);
443
444 msleep(1);
445
446 /*
447 * Switch off tuning bits.
448 * For RT2523 devices we do not need to update the R1 register.
449 */
450 rt2x00_set_field32(&rf1, RF1_TUNER, 0);
451 rt2x00_set_field32(&rf3, RF3_TUNER, 0);
452
453
454 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
455 rt2500pci_rf_write(rt2x00dev, rf1);
456
457 rt2500pci_rf_write(rt2x00dev, rf3);
458
459 /*
460 * Update rf fields
461 */
462 rt2x00dev->rf1 = rf1;
463 rt2x00dev->rf2 = rf2;
464 rt2x00dev->rf3 = rf3;
465 rt2x00dev->rf4 = rf4;
466 rt2x00dev->tx_power = txpower;
467
468 /*
469 * Clear false CRC during channel switch.
470 */
471 rt2x00pci_register_read(rt2x00dev, CNT0, &rf1);
472 }
473
474 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
475 const int txpower)
476 {
477 rt2x00_set_field32(&rt2x00dev->rf3, RF3_TXPOWER,
478 TXPOWER_TO_DEV(txpower));
479 rt2500pci_rf_write(rt2x00dev, rt2x00dev->rf3);
480
481 }
482
483 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
484 const int antenna_tx, const int antenna_rx)
485 {
486 u32 reg;
487 u8 r14;
488 u8 r2;
489
490 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
491 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
492 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
493
494 /*
495 * Configure the TX antenna.
496 */
497 if (antenna_tx == ANTENNA_DIVERSITY) {
498 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
499 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
500 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
501 } else if (antenna_tx == ANTENNA_A) {
502 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
503 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
504 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
505 } else if (antenna_tx == ANTENNA_B) {
506 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
507 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
508 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
509 }
510
511 /*
512 * Configure the RX antenna.
513 */
514 if (antenna_rx == ANTENNA_DIVERSITY)
515 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
516 else if (antenna_rx == ANTENNA_A)
517 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
518 else if (antenna_rx == ANTENNA_B)
519 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
520
521 /*
522 * RT2525E and RT5222 need to flip TX I/Q
523 */
524 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
525 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
526 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
527 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
528 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
529
530 /*
531 * RT2525E does not need RX I/Q Flip.
532 */
533 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
534 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
535 } else {
536 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
537 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
538 }
539
540 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
541 rt2500pci_bbp_write(rt2x00dev, 14, r14);
542 rt2500pci_bbp_write(rt2x00dev, 2, r2);
543 }
544
545 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
546 const int short_slot_time, const int beacon_int)
547 {
548 u32 reg;
549
550 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
551 rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
552 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
553 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
554
555 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
556 rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
557 rt2x00_set_field32(&reg, CSR18_PIFS,
558 short_slot_time ? SHORT_PIFS : PIFS);
559 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
560
561 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
562 rt2x00_set_field32(&reg, CSR19_DIFS,
563 short_slot_time ? SHORT_DIFS : DIFS);
564 rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
565 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
566
567 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
568 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
569 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
570 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
571
572 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
573 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
574 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
575 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
576 }
577
578 static void rt2500pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
579 {
580 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
581 u32 reg;
582 u32 preamble;
583 u16 value;
584
585 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE)
586 ? SHORT_PREAMBLE : PREAMBLE;
587
588 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATE;
589 rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
590
591 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
592 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
593 SHORT_DIFS : DIFS) +
594 PLCP + preamble + get_duration(ACK_SIZE, 10);
595 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
596 value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
597 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
598 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
599
600 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
601
602 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
603 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
604 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
605 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
606 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
607
608 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
609 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
610 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
611 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
612 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
613
614 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
615 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
616 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
617 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
618 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
619
620 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
621 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
622 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
623 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
624 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
625 }
626
627 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
628 const int phymode)
629 {
630 struct ieee80211_hw_mode *mode;
631 struct ieee80211_rate *rate;
632
633 if (phymode == MODE_IEEE80211A)
634 rt2x00dev->curr_hwmode = HWMODE_A;
635 else if (phymode == MODE_IEEE80211B)
636 rt2x00dev->curr_hwmode = HWMODE_B;
637 else
638 rt2x00dev->curr_hwmode = HWMODE_G;
639
640 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
641 rate = &mode->rates[mode->num_rates - 1];
642
643 rt2500pci_config_rate(rt2x00dev, rate->val2);
644 }
645
646 static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
647 {
648 u32 reg[2];
649
650 memset(&reg, 0, sizeof(reg));
651 memcpy(&reg, addr, ETH_ALEN);
652
653 /*
654 * The MAC address is passed to us as an array of bytes,
655 * that array is little endian, so no need for byte ordering.
656 */
657 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, &reg, sizeof(reg));
658 }
659
660 /*
661 * LED functions.
662 */
663 static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
664 {
665 u32 reg;
666
667 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
668
669 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
670 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
671
672 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
673 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
674 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
675 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
676 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
677 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
678 } else {
679 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
680 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
681 }
682
683 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
684 }
685
686 static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
687 {
688 u32 reg;
689
690 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
691 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
692 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
693 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
694 }
695
696 /*
697 * Link tuning
698 */
699 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
700 {
701 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
702 u32 reg;
703 u8 r17;
704
705 /*
706 * To prevent collisions with MAC ASIC on chipsets
707 * up to version C the link tuning should halt after 20
708 * seconds.
709 */
710 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
711 rt2x00dev->link.count > 20)
712 return;
713
714 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
715
716 /*
717 * Chipset versions C and lower should directly continue
718 * to the dynamic CCA tuning.
719 */
720 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
721 goto dynamic_cca_tune;
722
723 /*
724 * A too low RSSI will cause too much false CCA which will
725 * then corrupt the R17 tuning. To remidy this the tuning should
726 * be stopped (While making sure the R17 value will not exceed limits)
727 */
728 if (rssi < -80 && rt2x00dev->link.count > 20) {
729 if (r17 >= 0x41) {
730 r17 = rt2x00dev->rx_status.noise;
731 rt2500pci_bbp_write(rt2x00dev, 17, r17);
732 }
733 return;
734 }
735
736 /*
737 * Special big-R17 for short distance
738 */
739 if (rssi >= -58) {
740 if (r17 != 0x50)
741 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
742 return;
743 }
744
745 /*
746 * Special mid-R17 for middle distance
747 */
748 if (rssi >= -74) {
749 if (r17 != 0x41)
750 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
751 return;
752 }
753
754 /*
755 * Leave short or middle distance condition, restore r17
756 * to the dynamic tuning range.
757 */
758 if (r17 >= 0x41) {
759 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->rx_status.noise);
760 return;
761 }
762
763 dynamic_cca_tune:
764
765 /*
766 * R17 is inside the dynamic tuning range,
767 * start tuning the link based on the false cca counter.
768 */
769 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
770 rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
771
772 if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
773 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
774 rt2x00dev->rx_status.noise = r17;
775 } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
776 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
777 rt2x00dev->rx_status.noise = r17;
778 }
779 }
780
781 /*
782 * Initialization functions.
783 */
784 static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
785 {
786 struct data_desc *rxd;
787 unsigned int i;
788 u32 word;
789
790 memset(rt2x00dev->rx->data_addr, 0x00,
791 rt2x00_get_ring_size(rt2x00dev->rx));
792
793 for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
794 rxd = rt2x00dev->rx->entry[i].priv;
795
796 rt2x00_desc_read(rxd, 1, &word);
797 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
798 rt2x00dev->rx->entry[i].data_dma);
799 rt2x00_desc_write(rxd, 1, word);
800
801 rt2x00_desc_read(rxd, 0, &word);
802 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
803 rt2x00_desc_write(rxd, 0, word);
804 }
805
806 rt2x00_ring_index_clear(rt2x00dev->rx);
807 }
808
809 static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev,
810 const int queue)
811 {
812 struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
813 struct data_desc *txd;
814 unsigned int i;
815 u32 word;
816
817 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
818
819 for (i = 0; i < ring->stats.limit; i++) {
820 txd = ring->entry[i].priv;
821
822 rt2x00_desc_read(txd, 1, &word);
823 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
824 ring->entry[i].data_dma);
825 rt2x00_desc_write(txd, 1, word);
826
827 rt2x00_desc_read(txd, 0, &word);
828 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
829 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
830 rt2x00_desc_write(txd, 0, word);
831 }
832
833 rt2x00_ring_index_clear(ring);
834 }
835
836 static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
837 {
838 u32 reg;
839
840 /*
841 * Initialize rings.
842 */
843 rt2500pci_init_rxring(rt2x00dev);
844 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
845 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
846 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
847 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
848
849 /*
850 * Initialize registers.
851 */
852 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
853 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
854 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
855 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
856 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
857 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
858 rt2x00dev->bcn[1].stats.limit);
859 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
860 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
861 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
862
863 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
864 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
865 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
866 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
867
868 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
869 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
870 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
871 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
872
873 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
874 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
875 rt2x00dev->bcn[1].data_dma);
876 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
877
878 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
879 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
880 rt2x00dev->bcn[0].data_dma);
881 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
882
883 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
884 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE,
885 rt2x00dev->rx->desc_size);
886 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD,
887 rt2x00dev->rx->stats.limit);
888 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
889
890 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
891 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
892 rt2x00dev->rx->data_dma);
893 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
894
895 return 0;
896 }
897
898 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
899 {
900 u32 reg;
901
902 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
903 return -EBUSY;
904
905 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
906
907 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
908 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
909 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
910 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
911 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
912 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
913 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
914 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
915 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
916
917 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
918 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
919 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
920 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
921
922 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
923 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
924 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
925 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
926 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
927
928 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
929 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
930 rt2x00dev->rx->data_size / 128);
931 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
932
933 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
934
935 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
936 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
937
938 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
939 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
940
941 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
942 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
943 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
944
945 /*
946 * Always use CWmin and CWmax set in descriptor.
947 */
948 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
949 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
950 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
951
952 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
953 /*
954 * Signal.
955 */
956 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47);
957 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
958 /*
959 * Rssi.
960 */
961 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51);
962 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
963 /*
964 * OFDM Rate.
965 */
966 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42);
967 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
968 /*
969 * OFDM.
970 */
971 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51);
972 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
973 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
974
975 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
976 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
977 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
978 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
979 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
980 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
981 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
982 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
983
984 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
985
986 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
987
988 rt2x00pci_register_write(rt2x00dev, ARTCSR0, 0x7038140a);
989 rt2x00pci_register_write(rt2x00dev, ARTCSR1, 0x1d21252d);
990 rt2x00pci_register_write(rt2x00dev, ARTCSR2, 0x1919191d);
991
992 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
993 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
994 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
995 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
996 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
997
998 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
999 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
1000 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
1001 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
1002
1003 /*
1004 * We must clear the FCS and FIFO error count.
1005 * These registers are cleared on read,
1006 * so we may pass a useless variable to store the value.
1007 */
1008 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1009 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
1010
1011 return 0;
1012 }
1013
1014 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1015 {
1016 unsigned int i;
1017 u16 eeprom;
1018 u8 reg_id;
1019 u8 value;
1020
1021 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1022 rt2500pci_bbp_read(rt2x00dev, 0, &value);
1023 if ((value != 0xff) && (value != 0x00))
1024 goto continue_csr_init;
1025 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1026 udelay(REGISTER_BUSY_DELAY);
1027 }
1028
1029 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1030 return -EACCES;
1031
1032 continue_csr_init:
1033 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
1034 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
1035 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
1036 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
1037 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
1038 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
1039 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1040 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1041 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1042 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1043 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1044 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1045 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1046 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1047 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1048 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1049 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1050 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1051 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1052 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1053 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1054 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1055 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1056 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1057 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1058 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1059 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1060 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1061 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1062 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1063 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1064
1065 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1066 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1067 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1068
1069 if (eeprom != 0xffff && eeprom != 0x0000) {
1070 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1071 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1072 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1073 reg_id, value);
1074 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1075 }
1076 }
1077 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1078
1079 return 0;
1080 }
1081
1082 /*
1083 * Device state switch handlers.
1084 */
1085 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1086 enum dev_state state)
1087 {
1088 u32 reg;
1089
1090 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1091 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1092 state == STATE_RADIO_RX_OFF);
1093 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1094 }
1095
1096 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, int enabled)
1097 {
1098 u32 reg;
1099
1100 /*
1101 * When interrupts are being enabled, the interrupt registers
1102 * should clear the register to assure a clean state.
1103 */
1104 if (enabled) {
1105 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1106 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1107 }
1108
1109 /*
1110 * Only toggle the interrupts bits we are going to use.
1111 * Non-checked interrupt bits are disabled by default.
1112 */
1113 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1114 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, !enabled);
1115 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, !enabled);
1116 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, !enabled);
1117 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, !enabled);
1118 rt2x00_set_field32(&reg, CSR8_RXDONE, !enabled);
1119 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1120 }
1121
1122 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1123 {
1124 /*
1125 * Initialize all registers.
1126 */
1127 if (rt2500pci_init_rings(rt2x00dev) ||
1128 rt2500pci_init_registers(rt2x00dev) ||
1129 rt2500pci_init_bbp(rt2x00dev)) {
1130 ERROR(rt2x00dev, "Register initialization failed.\n");
1131 return -EIO;
1132 }
1133
1134 /*
1135 * Enable interrupts.
1136 */
1137 rt2500pci_toggle_irq(rt2x00dev, 1);
1138
1139 /*
1140 * Enable LED
1141 */
1142 rt2500pci_enable_led(rt2x00dev);
1143
1144 return 0;
1145 }
1146
1147 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1148 {
1149 u32 reg;
1150
1151 /*
1152 * Disable LED
1153 */
1154 rt2500pci_disable_led(rt2x00dev);
1155
1156 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1157
1158 /*
1159 * Disable synchronisation.
1160 */
1161 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1162
1163 /*
1164 * Cancel RX and TX.
1165 */
1166 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1167 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1168 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1169
1170 /*
1171 * Disable interrupts.
1172 */
1173 rt2500pci_toggle_irq(rt2x00dev, 0);
1174 }
1175
1176 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1177 enum dev_state state)
1178 {
1179 u32 reg;
1180 unsigned int i;
1181 char put_to_sleep;
1182 char bbp_state;
1183 char rf_state;
1184
1185 put_to_sleep = (state != STATE_AWAKE);
1186
1187 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1188 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1189 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1190 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1191 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1192 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1193
1194 /*
1195 * Device is not guaranteed to be in the requested state yet.
1196 * We must wait until the register indicates that the
1197 * device has entered the correct state.
1198 */
1199 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1200 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1201 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1202 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1203 if (bbp_state == state && rf_state == state)
1204 return 0;
1205 msleep(10);
1206 }
1207
1208 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1209 "current device state: bbp %d and rf %d.\n",
1210 state, bbp_state, rf_state);
1211
1212 return -EBUSY;
1213 }
1214
1215 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1216 enum dev_state state)
1217 {
1218 int retval = 0;
1219
1220 switch (state) {
1221 case STATE_RADIO_ON:
1222 retval = rt2500pci_enable_radio(rt2x00dev);
1223 break;
1224 case STATE_RADIO_OFF:
1225 rt2500pci_disable_radio(rt2x00dev);
1226 break;
1227 case STATE_RADIO_RX_ON:
1228 case STATE_RADIO_RX_OFF:
1229 rt2500pci_toggle_rx(rt2x00dev, state);
1230 break;
1231 case STATE_DEEP_SLEEP:
1232 case STATE_SLEEP:
1233 case STATE_STANDBY:
1234 case STATE_AWAKE:
1235 retval = rt2500pci_set_state(rt2x00dev, state);
1236 break;
1237 default:
1238 retval = -ENOTSUPP;
1239 break;
1240 }
1241
1242 return retval;
1243 }
1244
1245 /*
1246 * TX descriptor initialization
1247 */
1248 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1249 struct data_entry *entry, struct data_desc *txd,
1250 struct data_entry_desc *desc, struct ieee80211_hdr *ieee80211hdr,
1251 unsigned int length, struct ieee80211_tx_control *control)
1252 {
1253 u32 word;
1254
1255 /*
1256 * Start writing the descriptor words.
1257 */
1258 rt2x00_desc_read(txd, 2, &word);
1259 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1260 rt2x00_set_field32(&word, TXD_W2_AIFS, entry->ring->tx_params.aifs);
1261 rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->ring->tx_params.cw_min);
1262 rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->ring->tx_params.cw_max);
1263 rt2x00_desc_write(txd, 2, word);
1264
1265 rt2x00_desc_read(txd, 3, &word);
1266 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1267 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1268 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1269 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1270 rt2x00_desc_write(txd, 3, word);
1271
1272 rt2x00_desc_read(txd, 10, &word);
1273 rt2x00_set_field32(&word, TXD_W10_RTS,
1274 test_bit(ENTRY_TXD_RTS_FRAME, &entry->flags));
1275 rt2x00_desc_write(txd, 10, word);
1276
1277 rt2x00_desc_read(txd, 0, &word);
1278 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1279 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1280 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1281 test_bit(ENTRY_TXD_MORE_FRAG, &entry->flags));
1282 rt2x00_set_field32(&word, TXD_W0_ACK,
1283 test_bit(ENTRY_TXD_REQ_ACK, &entry->flags));
1284 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1285 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &entry->flags));
1286 rt2x00_set_field32(&word, TXD_W0_OFDM,
1287 test_bit(ENTRY_TXD_OFDM_RATE, &entry->flags));
1288 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1289 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1290 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 0);
1291 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1292 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1293 rt2x00_desc_write(txd, 0, word);
1294 }
1295
1296 /*
1297 * TX data initialization
1298 */
1299 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, int queue)
1300 {
1301 u32 reg;
1302
1303 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1304 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1305 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1306 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1307 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1308 }
1309 return;
1310 }
1311
1312 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1313 if (queue == IEEE80211_TX_QUEUE_DATA0)
1314 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1315 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1316 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1317 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1318 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1319 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1320 }
1321
1322 /*
1323 * RX control handlers
1324 */
1325 static int rt2500pci_fill_rxdone(struct data_entry *entry,
1326 int *signal, int *rssi, int *ofdm)
1327 {
1328 struct data_desc *rxd = entry->priv;
1329 u32 word0;
1330 u32 word2;
1331
1332 rt2x00_desc_read(rxd, 0, &word0);
1333 rt2x00_desc_read(rxd, 2, &word2);
1334
1335 /*
1336 * TODO: Don't we need to keep statistics
1337 * updated about these errors?
1338 */
1339 if (rt2x00_get_field32(word0, RXD_W0_CRC) ||
1340 rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1341 return -EINVAL;
1342
1343 *signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1344 *rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1345 entry->ring->rt2x00dev->rssi_offset;
1346 *ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1347
1348 return rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1349 }
1350
1351 /*
1352 * Interrupt functions.
1353 */
1354 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1355 {
1356 struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
1357 struct data_entry *entry;
1358 struct data_desc *txd;
1359 u32 word;
1360 int tx_status;
1361 int retry;
1362
1363 while (!rt2x00_ring_empty(ring)) {
1364 entry = rt2x00_get_data_entry_done(ring);
1365 txd = entry->priv;
1366 rt2x00_desc_read(txd, 0, &word);
1367
1368 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1369 !rt2x00_get_field32(word, TXD_W0_VALID))
1370 break;
1371
1372 /*
1373 * Obtain the status about this packet.
1374 */
1375 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1376 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1377
1378 rt2x00lib_txdone(entry, tx_status, retry);
1379
1380 /*
1381 * Make this entry available for reuse.
1382 */
1383 entry->flags = 0;
1384 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1385 rt2x00_desc_write(txd, 0, word);
1386 rt2x00_ring_index_done_inc(ring);
1387 }
1388
1389 /*
1390 * If the data ring was full before the txdone handler
1391 * we must make sure the packet queue in the mac80211 stack
1392 * is reenabled when the txdone handler has finished.
1393 */
1394 entry = ring->entry;
1395 if (!rt2x00_ring_full(ring))
1396 ieee80211_wake_queue(rt2x00dev->hw,
1397 entry->tx_status.control.queue);
1398 }
1399
1400 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1401 {
1402 struct rt2x00_dev *rt2x00dev = dev_instance;
1403 u32 reg;
1404
1405 /*
1406 * Get the interrupt sources & saved to local variable.
1407 * Write register value back to clear pending interrupts.
1408 */
1409 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1410 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1411
1412 if (!reg)
1413 return IRQ_NONE;
1414
1415 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1416 return IRQ_HANDLED;
1417
1418 /*
1419 * Handle interrupts, walk through all bits
1420 * and run the tasks, the bits are checked in order of
1421 * priority.
1422 */
1423
1424 /*
1425 * 1 - Beacon timer expired interrupt.
1426 */
1427 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1428 rt2x00pci_beacondone(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1429
1430 /*
1431 * 2 - Rx ring done interrupt.
1432 */
1433 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1434 rt2x00pci_rxdone(rt2x00dev);
1435
1436 /*
1437 * 3 - Atim ring transmit done interrupt.
1438 */
1439 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1440 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1441
1442 /*
1443 * 4 - Priority ring transmit done interrupt.
1444 */
1445 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1446 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1447
1448 /*
1449 * 5 - Tx ring transmit done interrupt.
1450 */
1451 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1452 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1453
1454 return IRQ_HANDLED;
1455 }
1456
1457 /*
1458 * Device initialization functions.
1459 */
1460 static int rt2500pci_alloc_eeprom(struct rt2x00_dev *rt2x00dev)
1461 {
1462 struct eeprom_93cx6 eeprom;
1463 u32 reg;
1464 u16 word;
1465 u8 *mac;
1466
1467 /*
1468 * Allocate the eeprom memory, check the eeprom width
1469 * and copy the entire eeprom into this allocated memory.
1470 */
1471 rt2x00dev->eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
1472 if (!rt2x00dev->eeprom)
1473 return -ENOMEM;
1474
1475 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1476
1477 eeprom.data = rt2x00dev;
1478 eeprom.register_read = rt2500pci_eepromregister_read;
1479 eeprom.register_write = rt2500pci_eepromregister_write;
1480 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1481 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1482 eeprom.reg_data_in = 0;
1483 eeprom.reg_data_out = 0;
1484 eeprom.reg_data_clock = 0;
1485 eeprom.reg_chip_select = 0;
1486
1487 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1488 EEPROM_SIZE / sizeof(u16));
1489
1490 /*
1491 * Start validation of the data that has been read.
1492 */
1493 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1494 if (!is_valid_ether_addr(mac)) {
1495 random_ether_addr(mac);
1496 EEPROM(rt2x00dev, "MAC: " MAC_FMT "\n", MAC_ARG(mac));
1497 }
1498
1499 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1500 if (word == 0xffff) {
1501 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1502 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
1503 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
1504 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
1505 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1506 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1507 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1508 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1509 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1510 }
1511
1512 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1513 if (word == 0xffff) {
1514 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1515 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1516 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1517 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1518 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1519 }
1520
1521 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1522 if (word == 0xffff) {
1523 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1524 DEFAULT_RSSI_OFFSET);
1525 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1526 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1527 }
1528
1529 return 0;
1530 }
1531
1532 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1533 {
1534 u32 reg;
1535 u16 value;
1536 u16 eeprom;
1537
1538 /*
1539 * Read EEPROM word for configuration.
1540 */
1541 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1542
1543 /*
1544 * Identify RF chipset.
1545 */
1546 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1547 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1548 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1549
1550 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1551 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1552 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1553 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1554 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1555 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1556 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1557 return -ENODEV;
1558 }
1559
1560 /*
1561 * Identify default antenna configuration.
1562 */
1563 rt2x00dev->hw->conf.antenna_sel_tx = rt2x00_get_field16(eeprom,
1564 EEPROM_ANTENNA_TX_DEFAULT);
1565 rt2x00dev->hw->conf.antenna_sel_rx = rt2x00_get_field16(eeprom,
1566 EEPROM_ANTENNA_RX_DEFAULT);
1567
1568 /*
1569 * Store led mode, for correct led behaviour.
1570 */
1571 rt2x00dev->led_mode = rt2x00_get_field16(eeprom,
1572 EEPROM_ANTENNA_LED_MODE);
1573
1574 /*
1575 * Detect if this device has an hardware controlled radio.
1576 */
1577 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1578 __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1579
1580 /*
1581 * Check if the BBP tuning should be enabled.
1582 */
1583 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1584
1585 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1586 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1587
1588 /*
1589 * Read the RSSI <-> dBm offset information.
1590 */
1591 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1592 rt2x00dev->rssi_offset =
1593 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1594
1595 return 0;
1596 }
1597
1598 static const struct {
1599 unsigned int chip;
1600 u32 val[3];
1601 } rf_vals[] = {
1602 { RF2522, { 0x00002050, 0x00000101, 0x00000000 } },
1603 { RF2523, { 0x00022010, 0x000e0111, 0x00000a1b } },
1604 { RF2524, { 0x00032020, 0x00000101, 0x00000a1b } },
1605 { RF2525, { 0x00022020, 0x00060111, 0x00000a1b } },
1606 { RF2525E, { 0x00022020, 0x00060111, 0x00000a0b } },
1607 { RF5222, { 0x00000000, 0x00000101, 0x00000000 } },
1608 };
1609
1610 /*
1611 * RF value list for RF2522
1612 * Supports: 2.4 GHz
1613 */
1614 static const u32 rf_vals_bg_2522[] = {
1615 0x000c1fda, 0x000c1fee, 0x000c2002, 0x000c2016, 0x000c202a,
1616 0x000c203e, 0x000c2052, 0x000c2066, 0x000c207a, 0x000c208e,
1617 0x000c20a2, 0x000c20b6, 0x000c20ca, 0x000c20fa
1618 };
1619
1620 /*
1621 * RF value list for RF2523, RF2524 & RF2525
1622 * Supports: 2.4 GHz
1623 */
1624 static const u32 rf_vals_bg_252x[] = {
1625 0x00000c9e, 0x00000ca2, 0x00000ca6, 0x00000caa, 0x00000cae,
1626 0x00000cb2, 0x00000cb6, 0x00000cba, 0x00000cbe, 0x00000d02,
1627 0x00000d06, 0x00000d0a, 0x00000d0e, 0x00000d1a
1628 };
1629
1630 /*
1631 * RF value list for RF2525E & RF5222
1632 * Supports: 2.4 GHz
1633 */
1634 static const u32 rf_vals_bg_5x[] = {
1635 0x00001136, 0x0000113a, 0x0000113e, 0x00001182, 0x00001186,
1636 0x0000118a, 0x0000118e, 0x00001192, 0x00001196, 0x0000119a,
1637 0x0000119e, 0x000011a2, 0x000011a6, 0x000011ae
1638 };
1639
1640 /*
1641 * RF value list for RF5222 (supplement to rf_vals_bg_5x)
1642 * Supports: 5.2 GHz
1643 */
1644 static const u32 rf_vals_a_5x[] = {
1645 0x00018896, 0x0001889a, 0x0001889e, 0x000188a2, 0x000188a6,
1646 0x000188aa, 0x000188ae, 0x000188b2, 0x00008802, 0x00008806,
1647 0x0000880a, 0x0000880e, 0x00008812, 0x00008816, 0x0000881a,
1648 0x0000881e, 0x00008822, 0x00008826, 0x0000882a, 0x000090a6,
1649 0x000090ae, 0x000090b6, 0x000090be
1650 };
1651
1652 static void rt2500pci_init_hw_mode(struct rt2x00_dev *rt2x00dev)
1653 {
1654 struct hw_mode_spec *spec = &rt2x00dev->spec;
1655 u8 *txpower;
1656 unsigned int i;
1657
1658 /*
1659 * Initialize all hw fields.
1660 */
1661 rt2x00dev->hw->flags = IEEE80211_HW_HOST_GEN_BEACON |
1662 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1663 IEEE80211_HW_WEP_INCLUDE_IV |
1664 IEEE80211_HW_DATA_NULLFUNC_ACK |
1665 IEEE80211_HW_NO_TKIP_WMM_HWACCEL |
1666 IEEE80211_HW_MONITOR_DURING_OPER |
1667 IEEE80211_HW_NO_PROBE_FILTERING;
1668 rt2x00dev->hw->extra_tx_headroom = 0;
1669 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1670 rt2x00dev->hw->max_noise = MAX_RX_NOISE;
1671 rt2x00dev->hw->queues = 2;
1672
1673 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1674 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1675 rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0));
1676
1677 /*
1678 * Set device specific, but channel independent RF values.
1679 */
1680 for (i = 0; i < ARRAY_SIZE(rf_vals); i++) {
1681 if (rt2x00_rf(&rt2x00dev->chip, rf_vals[i].chip)) {
1682 rt2x00dev->rf1 = rf_vals[i].val[0];
1683 rt2x00dev->rf3 = rf_vals[i].val[1];
1684 rt2x00dev->rf4 = rf_vals[i].val[2];
1685 }
1686 }
1687
1688 /*
1689 * Convert tx_power array in eeprom.
1690 */
1691 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1692 for (i = 0; i < 14; i++)
1693 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1694
1695 /*
1696 * Initialize hw_mode information.
1697 */
1698 spec->num_modes = 2;
1699 spec->num_rates = 12;
1700 spec->num_channels = 14;
1701 spec->tx_power_a = NULL;
1702 spec->tx_power_bg = txpower;
1703 spec->tx_power_default = DEFAULT_TXPOWER;
1704 spec->chan_val_a = NULL;
1705
1706 if (rt2x00_rf(&rt2x00dev->chip, RF2522))
1707 spec->chan_val_bg = rf_vals_bg_2522;
1708 else if (rt2x00_rf(&rt2x00dev->chip, RF2523) ||
1709 rt2x00_rf(&rt2x00dev->chip, RF2524) ||
1710 rt2x00_rf(&rt2x00dev->chip, RF2525))
1711 spec->chan_val_bg = rf_vals_bg_252x;
1712 else if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
1713 rt2x00_rf(&rt2x00dev->chip, RF5222))
1714 spec->chan_val_bg = rf_vals_bg_5x;
1715
1716 if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1717 spec->num_modes = 3;
1718 spec->num_channels += 23;
1719 spec->chan_val_a = rf_vals_a_5x;
1720 }
1721 }
1722
1723 static int rt2500pci_init_hw(struct rt2x00_dev *rt2x00dev)
1724 {
1725 int retval;
1726
1727 /*
1728 * Allocate eeprom data.
1729 */
1730 retval = rt2500pci_alloc_eeprom(rt2x00dev);
1731 if (retval)
1732 return retval;
1733
1734 retval = rt2500pci_init_eeprom(rt2x00dev);
1735 if (retval)
1736 return retval;
1737
1738 /*
1739 * Initialize hw specifications.
1740 */
1741 rt2500pci_init_hw_mode(rt2x00dev);
1742
1743 /*
1744 * This device supports ATIM
1745 */
1746 __set_bit(DEVICE_SUPPORT_ATIM, &rt2x00dev->flags);
1747
1748 return 0;
1749 }
1750
1751 /*
1752 * IEEE80211 stack callback functions.
1753 */
1754 static int rt2500pci_get_stats(struct ieee80211_hw *hw,
1755 struct ieee80211_low_level_stats *stats)
1756 {
1757 struct rt2x00_dev *rt2x00dev = hw->priv;
1758 u32 reg;
1759
1760 /*
1761 * Update FCS error count from register.
1762 * The dot11ACKFailureCount, dot11RTSFailureCount and
1763 * dot11RTSSuccessCount are updated in interrupt time.
1764 */
1765 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
1766 rt2x00dev->low_level_stats.dot11FCSErrorCount +=
1767 rt2x00_get_field32(reg, CNT0_FCS_ERROR);
1768
1769 memcpy(stats, &rt2x00dev->low_level_stats, sizeof(*stats));
1770
1771 return 0;
1772 }
1773
1774 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1775 u32 short_retry, u32 long_retry)
1776 {
1777 struct rt2x00_dev *rt2x00dev = hw->priv;
1778 u32 reg;
1779
1780 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1781 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1782 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1783 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1784
1785 return 0;
1786 }
1787
1788 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1789 {
1790 struct rt2x00_dev *rt2x00dev = hw->priv;
1791 u64 tsf;
1792 u32 reg;
1793
1794 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1795 tsf = (u64)rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1796 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1797 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1798
1799 return tsf;
1800 }
1801
1802 static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1803 {
1804 struct rt2x00_dev *rt2x00dev = hw->priv;
1805
1806 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1807 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1808 }
1809
1810 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1811 {
1812 struct rt2x00_dev *rt2x00dev = hw->priv;
1813 u32 reg;
1814
1815 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1816 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1817 }
1818
1819 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1820 .tx = rt2x00lib_tx,
1821 .reset = rt2x00lib_reset,
1822 .add_interface = rt2x00lib_add_interface,
1823 .remove_interface = rt2x00lib_remove_interface,
1824 .config = rt2x00lib_config,
1825 .config_interface = rt2x00lib_config_interface,
1826 .set_multicast_list = rt2x00lib_set_multicast_list,
1827 .get_stats = rt2500pci_get_stats,
1828 .set_retry_limit = rt2500pci_set_retry_limit,
1829 .conf_tx = rt2x00lib_conf_tx,
1830 .get_tx_stats = rt2x00lib_get_tx_stats,
1831 .get_tsf = rt2500pci_get_tsf,
1832 .reset_tsf = rt2500pci_reset_tsf,
1833 .beacon_update = rt2x00pci_beacon_update,
1834 .tx_last_beacon = rt2500pci_tx_last_beacon,
1835 };
1836
1837 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1838 .irq_handler = rt2500pci_interrupt,
1839 .init_hw = rt2500pci_init_hw,
1840 .initialize = rt2x00pci_initialize,
1841 .uninitialize = rt2x00pci_uninitialize,
1842 .set_device_state = rt2500pci_set_device_state,
1843 #ifdef CONFIG_RT2500PCI_RFKILL
1844 .rfkill_poll = rt2500pci_rfkill_poll,
1845 #endif /* CONFIG_RT2500PCI_RFKILL */
1846 .link_tuner = rt2500pci_link_tuner,
1847 .write_tx_desc = rt2500pci_write_tx_desc,
1848 .write_tx_data = rt2x00pci_write_tx_data,
1849 .kick_tx_queue = rt2500pci_kick_tx_queue,
1850 .fill_rxdone = rt2500pci_fill_rxdone,
1851 .config_type = rt2500pci_config_type,
1852 .config_phymode = rt2500pci_config_phymode,
1853 .config_channel = rt2500pci_config_channel,
1854 .config_mac_addr = rt2500pci_config_mac_addr,
1855 .config_bssid = rt2500pci_config_bssid,
1856 .config_promisc = rt2500pci_config_promisc,
1857 .config_txpower = rt2500pci_config_txpower,
1858 .config_antenna = rt2500pci_config_antenna,
1859 .config_duration = rt2500pci_config_duration,
1860 };
1861
1862 static const struct rt2x00_ops rt2500pci_ops = {
1863 .name = DRV_NAME,
1864 .rxd_size = RXD_DESC_SIZE,
1865 .txd_size = TXD_DESC_SIZE,
1866 .lib = &rt2500pci_rt2x00_ops,
1867 .hw = &rt2500pci_mac80211_ops,
1868 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1869 .debugfs = &rt2500pci_rt2x00debug,
1870 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1871 };
1872
1873 /*
1874 * RT2500pci module information.
1875 */
1876 static struct pci_device_id rt2500pci_device_table[] = {
1877 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1878 { 0, }
1879 };
1880
1881 MODULE_AUTHOR(DRV_PROJECT);
1882 MODULE_VERSION(DRV_VERSION);
1883 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1884 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1885 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1886 MODULE_LICENSE("GPL");
1887
1888 static struct pci_driver rt2500pci_driver = {
1889 .name = DRV_NAME,
1890 .id_table = rt2500pci_device_table,
1891 .probe = rt2x00pci_probe,
1892 .remove = __devexit_p(rt2x00pci_remove),
1893 #ifdef CONFIG_PM
1894 .suspend = rt2x00pci_suspend,
1895 .resume = rt2x00pci_resume,
1896 #endif /* CONFIG_PM */
1897 };
1898
1899 static int __init rt2500pci_init(void)
1900 {
1901 return pci_register_driver(&rt2500pci_driver);
1902 }
1903
1904 static void __exit rt2500pci_exit(void)
1905 {
1906 pci_unregister_driver(&rt2500pci_driver);
1907 }
1908
1909 module_init(rt2500pci_init);
1910 module_exit(rt2500pci_exit);
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