4734366929366317fef89e09b9fec3b9697214d3
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Thomas Langer, Ralph Hempel
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/addrspace.h>
32 #include <asm/danube.h>
33 #include <asm/reboot.h>
36 extern ulong
ifx_get_ddr_hz(void);
37 extern ulong
ifx_get_cpuclk(void);
39 /* definitions for external PHYs / Switches */
40 /* Split values into phy address and register address */
41 #define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
43 /* IDs and registers of known external switches */
44 #define ID_SAMURAI_0 0x1020
45 #define ID_SAMURAI_1 0x0007
46 #define SAMURAI_ID_REG0 0xA0
47 #define SAMURAI_ID_REG1 0xA1
49 #define ID_TANTOS 0x2599
51 void _machine_restart(void)
53 *DANUBE_RCU_RST_REQ
|=1<<30;
56 #ifdef CONFIG_SYS_RAMBOOT
57 phys_size_t
initdram(int board_type
)
59 return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, CONFIG_SYS_MAX_RAM
);
61 #elif defined(CONFIG_USE_DDR_RAM)
62 phys_size_t
initdram(int board_type
)
64 return (CONFIG_SYS_MAX_RAM
);
68 static ulong
max_sdram_size(void) /* per Chip Select */
70 /* The only supported SDRAM data width is 16bit.
74 /* The only supported number of SDRAM banks is 4.
78 ulong cfgpb0
= *DANUBE_SDRAM_MC_CFGPB0
;
79 int cols
= cfgpb0
& 0xF;
80 int rows
= (cfgpb0
& 0xF0) >> 4;
81 ulong size
= (1 << (rows
+ cols
)) * CFG_DW
* CFG_NB
;
87 * Check memory range for valid RAM. A simple memory test determines
88 * the actually available RAM size between addresses `base' and
92 static long int dram_size(long int *base
, long int maxsize
)
94 volatile long int *addr
;
96 ulong save
[32]; /* to make test non-destructive */
99 for (cnt
= (maxsize
/ sizeof (long)) >> 1; cnt
> 0; cnt
>>= 1) {
100 addr
= base
+ cnt
; /* pointer arith! */
106 /* write 0 to base address */
111 /* check at base address */
112 if ((val
= *addr
) != 0) {
117 for (cnt
= 1; cnt
< maxsize
/ sizeof (long); cnt
<<= 1) {
118 addr
= base
+ cnt
; /* pointer arith! */
124 return (cnt
* sizeof (long));
130 phys_size_t
initdram(int board_type
)
132 int rows
, cols
, best_val
= *DANUBE_SDRAM_MC_CFGPB0
;
133 ulong size
, max_size
= 0;
136 /* load t9 into our_address */
137 asm volatile ("move %0, $25" : "=r" (our_address
) :);
139 /* Can't probe for RAM size unless we are running from Flash.
140 * find out whether running from DRAM or Flash.
142 if (CPHYSADDR(our_address
) < CPHYSADDR(PHYS_FLASH_1
))
144 return max_sdram_size();
147 for (cols
= 0x8; cols
<= 0xC; cols
++)
149 for (rows
= 0xB; rows
<= 0xD; rows
++)
151 *DANUBE_SDRAM_MC_CFGPB0
= (0x14 << 8) |
153 size
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
,
158 best_val
= *DANUBE_SDRAM_MC_CFGPB0
;
164 *DANUBE_SDRAM_MC_CFGPB0
= best_val
;
169 int checkboard (void)
171 unsigned long chipid
= *DANUBE_MPS_CHIPID
;
176 part_num
= DANUBE_MPS_CHIPID_PARTNUM_GET(chipid
);
181 puts("Danube/Twinpass/Vinax-VE ");
184 printf ("unknown, chip part number 0x%03X ", part_num
);
187 printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid
));
189 printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
190 printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
195 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
196 int board_early_init_f(void)
198 #ifdef CONFIG_EBU_ADDSEL0
199 (*DANUBE_EBU_ADDSEL0
) = CONFIG_EBU_ADDSEL0
;
201 #ifdef CONFIG_EBU_ADDSEL1
202 (*DANUBE_EBU_ADDSEL1
) = CONFIG_EBU_ADDSEL1
;
204 #ifdef CONFIG_EBU_ADDSEL2
205 (*DANUBE_EBU_ADDSEL2
) = CONFIG_EBU_ADDSEL2
;
207 #ifdef CONFIG_EBU_ADDSEL3
208 (*DANUBE_EBU_ADDSEL3
) = CONFIG_EBU_ADDSEL3
;
210 #ifdef CONFIG_EBU_BUSCON0
211 (*DANUBE_EBU_BUSCON0
) = CONFIG_EBU_BUSCON0
;
213 #ifdef CONFIG_EBU_BUSCON1
214 (*DANUBE_EBU_BUSCON1
) = CONFIG_EBU_BUSCON1
;
216 #ifdef CONFIG_EBU_BUSCON2
217 (*DANUBE_EBU_BUSCON2
) = CONFIG_EBU_BUSCON2
;
219 #ifdef CONFIG_EBU_BUSCON3
220 (*DANUBE_EBU_BUSCON3
) = CONFIG_EBU_BUSCON3
;
225 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
227 #ifdef CONFIG_EXTRA_SWITCH
228 static int external_switch_init(void)
230 unsigned short chipid0
=0xdead, chipid1
=0xbeef;
231 static char * const name
= "lq_cpe_eth";
233 #ifdef CLK_OUT2_25MHZ
234 *DANUBE_GPIO_P0_DIR
=0x0000ae78;
235 *DANUBE_GPIO_P0_ALTSEL0
=0x00008078;
236 //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
237 *DANUBE_GPIO_P0_ALTSEL1
=0x80000000; //joelin for Mii-1
238 *DANUBE_CGU_IFCCR
=0x00400010;
239 *DANUBE_GPIO_P0_OD
=0x0000ae78;
242 /* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
245 debug("\nsearching for Samurai switch ... ");
246 if ( (miiphy_read(name
, PHYADDR(SAMURAI_ID_REG0
), &chipid0
)==0) &&
247 (miiphy_read(name
, PHYADDR(SAMURAI_ID_REG1
), &chipid1
)==0) ) {
248 if (((chipid0
& 0xFFF0) == ID_SAMURAI_0
) &&
249 ((chipid1
& 0x000F) == ID_SAMURAI_1
)) {
252 /* enable "Crossover Auto Detect" + defaults */
254 miiphy_write(name
, PHYADDR(0x01), 0x840F);
256 miiphy_write(name
, PHYADDR(0x03), 0x840F);
258 miiphy_write(name
, PHYADDR(0x05), 0x840F);
260 miiphy_write(name
, PHYADDR(0x07), 0x840F);
262 miiphy_write(name
, PHYADDR(0x08), 0x840F);
264 miiphy_write(name
, PHYADDR(0x09), 0x840F);
265 /* System Control 4: CPU on port 1 and other */
266 miiphy_write(name
, PHYADDR(0x12), 0x3602);
267 #ifdef CLK_OUT2_25MHZ
268 /* Bandwidth Control Enable Register: enable */
269 miiphy_write(name
, PHYADDR(0x33), 0x4000);
274 debug("\nsearching for TANTOS switch ... ");
275 if (miiphy_read(name
, PHYADDR(0x101), &chipid0
) == 0) {
276 if (chipid0
== ID_TANTOS
) {
279 /* P5 Basic Control: Force Link Up */
280 miiphy_write(name
, PHYADDR(0xA1), 0x0004);
281 /* P6 Basic Control: Force Link Up */
282 miiphy_write(name
, PHYADDR(0xC1), 0x0004);
283 /* RGMII/MII Port Control (P4/5/6) */
284 miiphy_write(name
, PHYADDR(0xF5), 0x0773);
286 /* Software workaround. */
287 /* PHY reset from P0 to P4. */
289 /* set data for indirect write */
290 miiphy_write(name
, PHYADDR(0x121), 0x8000);
293 miiphy_write(name
, PHYADDR(0x120), 0x0400);
296 miiphy_write(name
, PHYADDR(0x120), 0x0420);
299 miiphy_write(name
, PHYADDR(0x120), 0x0440);
302 miiphy_write(name
, PHYADDR(0x120), 0x0460);
305 miiphy_write(name
, PHYADDR(0x120), 0x0480);
313 #endif /* CONFIG_EXTRA_SWITCH */
315 int board_eth_init(bd_t
*bis
)
317 #if defined(CONFIG_IFX_ETOP)
319 *DANUBE_PMU_PWDCR
&= 0xFFFFEFDF;
320 *DANUBE_PMU_PWDCR
&=~(1<<DANUBE_PMU_DMA_SHIFT
);/*enable DMA from PMU*/
322 if (lq_eth_initialize(bis
)<0)
325 *DANUBE_RCU_RST_REQ
|=1;
327 *DANUBE_RCU_RST_REQ
&=(unsigned long)~1;
330 #ifdef CONFIG_EXTRA_SWITCH
331 if (external_switch_init()<0)
333 #endif /* CONFIG_EXTRA_SWITCH */
334 #endif /* CONFIG_IFX_ETOP */