plat/arm/board/fvp/fvp_def.h

   1 /*
   2  * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef FVP_DEF_H
   8 #define FVP_DEF_H
   9
  10 #include <utils_def.h>
  11
  12 #ifndef FVP_CLUSTER_COUNT
  13 #define FVP_CLUSTER_COUNT               2
  14 #endif
  15
  16 #ifndef FVP_MAX_CPUS_PER_CLUSTER
  17 #define FVP_MAX_CPUS_PER_CLUSTER        4
  18 #endif
  19
  20 #ifndef FVP_MAX_PE_PER_CPU
  21 # define FVP_MAX_PE_PER_CPU             1
  22 #endif
  23
  24 #define FVP_PRIMARY_CPU                 0x0
  25
  26 /* Defines for the Interconnect build selection */
  27 #define FVP_CCI                 1
  28 #define FVP_CCN                 2
  29
  30 /*******************************************************************************
  31  * FVP memory map related constants
  32  ******************************************************************************/
  33
  34 #define FLASH1_BASE                     UL(0x0c000000)
  35 #define FLASH1_SIZE                     UL(0x04000000)
  36
  37 #define PSRAM_BASE                      UL(0x14000000)
  38 #define PSRAM_SIZE                      UL(0x04000000)
  39
  40 #define VRAM_BASE                       UL(0x18000000)
  41 #define VRAM_SIZE                       UL(0x02000000)
  42
  43 /* Aggregate of all devices in the first GB */
  44 #define DEVICE0_BASE                    UL(0x20000000)
  45 #define DEVICE0_SIZE                    UL(0x0c200000)
  46
  47 /*
  48  *  In case of FVP models with CCN, the CCN register space overlaps into
  49  *  the NSRAM area.
  50  */
  51 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
  52 #define DEVICE1_BASE                    UL(0x2e000000)
  53 #define DEVICE1_SIZE                    UL(0x1A00000)
  54 #else
  55 #define DEVICE1_BASE                    UL(0x2f000000)
  56 #define DEVICE1_SIZE                    UL(0x200000)
  57 #define NSRAM_BASE                      UL(0x2e000000)
  58 #define NSRAM_SIZE                      UL(0x10000)
  59 #endif
  60 /* Devices in the second GB */
  61 #define DEVICE2_BASE                    UL(0x7fe00000)
  62 #define DEVICE2_SIZE                    UL(0x00200000)
  63
  64 #define PCIE_EXP_BASE                   UL(0x40000000)
  65 #define TZRNG_BASE                      UL(0x7fe60000)
  66
  67 /* Non-volatile counters */
  68 #define TRUSTED_NVCTR_BASE              UL(0x7fe70000)
  69 #define TFW_NVCTR_BASE                  (TRUSTED_NVCTR_BASE + UL(0x0000))
  70 #define TFW_NVCTR_SIZE                  UL(4)
  71 #define NTFW_CTR_BASE                   (TRUSTED_NVCTR_BASE + UL(0x0004))
  72 #define NTFW_CTR_SIZE                   UL(4)
  73
  74 /* Keys */
  75 #define SOC_KEYS_BASE                   UL(0x7fe80000)
  76 #define TZ_PUB_KEY_HASH_BASE            (SOC_KEYS_BASE + UL(0x0000))
  77 #define TZ_PUB_KEY_HASH_SIZE            UL(32)
  78 #define HU_KEY_BASE                     (SOC_KEYS_BASE + UL(0x0020))
  79 #define HU_KEY_SIZE                     UL(16)
  80 #define END_KEY_BASE                    (SOC_KEYS_BASE + UL(0x0044))
  81 #define END_KEY_SIZE                    UL(32)
  82
  83 /* Constants to distinguish FVP type */
  84 #define HBI_BASE_FVP                    U(0x020)
  85 #define REV_BASE_FVP_V0                 U(0x0)
  86 #define REV_BASE_FVP_REVC               U(0x2)
  87
  88 #define HBI_FOUNDATION_FVP              U(0x010)
  89 #define REV_FOUNDATION_FVP_V2_0         U(0x0)
  90 #define REV_FOUNDATION_FVP_V2_1         U(0x1)
  91 #define REV_FOUNDATION_FVP_v9_1         U(0x2)
  92 #define REV_FOUNDATION_FVP_v9_6         U(0x3)
  93
  94 #define BLD_GIC_VE_MMAP                 U(0x0)
  95 #define BLD_GIC_A53A57_MMAP             U(0x1)
  96
  97 #define ARCH_MODEL                      U(0x1)
  98
  99 /* FVP Power controller base address*/
 100 #define PWRC_BASE                       UL(0x1c100000)
 101
 102 /* FVP SP804 timer frequency is 35 MHz*/
 103 #define SP804_TIMER_CLKMULT             1
 104 #define SP804_TIMER_CLKDIV              35
 105
 106 /* SP810 controller. FVP specific flags */
 107 #define FVP_SP810_CTRL_TIM0_OV          BIT_32(16)
 108 #define FVP_SP810_CTRL_TIM1_OV          BIT_32(18)
 109 #define FVP_SP810_CTRL_TIM2_OV          BIT_32(20)
 110 #define FVP_SP810_CTRL_TIM3_OV          BIT_32(22)
 111
 112 /*******************************************************************************
 113  * GIC-400 & interrupt handling related constants
 114  ******************************************************************************/
 115 /* VE compatible GIC memory map */
 116 #define VE_GICD_BASE                    UL(0x2c001000)
 117 #define VE_GICC_BASE                    UL(0x2c002000)
 118 #define VE_GICH_BASE                    UL(0x2c004000)
 119 #define VE_GICV_BASE                    UL(0x2c006000)
 120
 121 /* Base FVP compatible GIC memory map */
 122 #define BASE_GICD_BASE                  UL(0x2f000000)
 123 #define BASE_GICR_BASE                  UL(0x2f100000)
 124 #define BASE_GICC_BASE                  UL(0x2c000000)
 125 #define BASE_GICH_BASE                  UL(0x2c010000)
 126 #define BASE_GICV_BASE                  UL(0x2c02f000)
 127
 128 #define FVP_IRQ_TZ_WDOG                 56
 129 #define FVP_IRQ_SEC_SYS_TIMER           57
 130
 131
 132 /*******************************************************************************
 133  * TrustZone address space controller related constants
 134  ******************************************************************************/
 135
 136 /* NSAIDs used by devices in TZC filter 0 on FVP */
 137 #define FVP_NSAID_DEFAULT               0
 138 #define FVP_NSAID_PCI                   1
 139 #define FVP_NSAID_VIRTIO                8  /* from FVP v5.6 onwards */
 140 #define FVP_NSAID_AP                    9  /* Application Processors */
 141 #define FVP_NSAID_VIRTIO_OLD            15 /* until FVP v5.5 */
 142
 143 /* NSAIDs used by devices in TZC filter 2 on FVP */
 144 #define FVP_NSAID_HDLCD0                2
 145 #define FVP_NSAID_CLCD                  7
 146
 147 /*******************************************************************************
 148  * Memprotect definitions
 149  ******************************************************************************/
 150 /* PSCI memory protect definitions:
 151  * This variable is stored in a non-secure flash because some ARM reference
 152  * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
 153  * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
 154  */
 155 #define PLAT_ARM_MEM_PROT_ADDR          (V2M_FLASH0_BASE + \
 156                                          V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 157
 158 #endif /* FVP_DEF_H */