plat/arm/board/fvp/include/platform_def.h

   1 /*
   2  * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef PLATFORM_DEF_H
   8 #define PLATFORM_DEF_H
   9
  10 #include <drivers/arm/tzc400.h>
  11 #include <lib/utils_def.h>
  12 #include <plat/arm/board/common/v2m_def.h>
  13 #include <plat/arm/common/arm_def.h>
  14 #include <plat/arm/common/arm_spm_def.h>
  15 #include <plat/common/common_def.h>
  16
  17 #include "../fvp_def.h"
  18
  19 /* Required platform porting definitions */
  20 #define PLATFORM_CORE_COUNT \
  21         (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU)
  22
  23 #define PLAT_NUM_PWR_DOMAINS            (FVP_CLUSTER_COUNT + \
  24                                         PLATFORM_CORE_COUNT) + 1
  25
  26 #define PLAT_MAX_PWR_LVL                ARM_PWR_LVL2
  27
  28 /*
  29  * Other platform porting definitions are provided by included headers
  30  */
  31
  32 /*
  33  * Required ARM standard platform porting definitions
  34  */
  35 #define PLAT_ARM_CLUSTER_COUNT          FVP_CLUSTER_COUNT
  36
  37 #define PLAT_ARM_TRUSTED_SRAM_SIZE      UL(0x00040000)  /* 256 KB */
  38
  39 #define PLAT_ARM_TRUSTED_ROM_BASE       UL(0x00000000)
  40 #define PLAT_ARM_TRUSTED_ROM_SIZE       UL(0x04000000)  /* 64 MB */
  41
  42 #define PLAT_ARM_TRUSTED_DRAM_BASE      UL(0x06000000)
  43 #define PLAT_ARM_TRUSTED_DRAM_SIZE      UL(0x02000000)  /* 32 MB */
  44
  45 /* virtual address used by dynamic mem_protect for chunk_base */
  46 #define PLAT_ARM_MEM_PROTEC_VA_FRAME    UL(0xc0000000)
  47
  48 /* No SCP in FVP */
  49 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE     UL(0x0)
  50
  51 #define PLAT_ARM_DRAM2_BASE             ULL(0x880000000)
  52 #define PLAT_ARM_DRAM2_SIZE             UL(0x80000000)
  53
  54 /*
  55  * Load address of BL33 for this platform port
  56  */
  57 #define PLAT_ARM_NS_IMAGE_BASE          (ARM_DRAM1_BASE + UL(0x8000000))
  58
  59 /*
  60  * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
  61  * plat_arm_mmap array defined for each BL stage.
  62  */
  63 #if defined(IMAGE_BL31)
  64 # if ENABLE_SPM
  65 #  define PLAT_ARM_MMAP_ENTRIES         9
  66 #  define MAX_XLAT_TABLES               9
  67 #  define PLAT_SP_IMAGE_MMAP_REGIONS    30
  68 #  define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
  69 # else
  70 #  define PLAT_ARM_MMAP_ENTRIES         8
  71 #  define MAX_XLAT_TABLES               5
  72 # endif
  73 #elif defined(IMAGE_BL32)
  74 # define PLAT_ARM_MMAP_ENTRIES          8
  75 # define MAX_XLAT_TABLES                5
  76 #elif !USE_ROMLIB
  77 # define PLAT_ARM_MMAP_ENTRIES          11
  78 # define MAX_XLAT_TABLES                5
  79 #else
  80 # define PLAT_ARM_MMAP_ENTRIES          12
  81 # define MAX_XLAT_TABLES                6
  82 #endif
  83
  84 /*
  85  * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
  86  * plus a little space for growth.
  87  */
  88 #define PLAT_ARM_MAX_BL1_RW_SIZE        UL(0xB000)
  89
  90 /*
  91  * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
  92  */
  93
  94 #if USE_ROMLIB
  95 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE     UL(0x1000)
  96 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE     UL(0xe000)
  97 #else
  98 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE     UL(0)
  99 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE     UL(0)
 100 #endif
 101
 102 /*
 103  * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
 104  * little space for growth.
 105  */
 106 #if TRUSTED_BOARD_BOOT
 107 # define PLAT_ARM_MAX_BL2_SIZE          UL(0x1D000)
 108 #else
 109 # define PLAT_ARM_MAX_BL2_SIZE          UL(0x11000)
 110 #endif
 111
 112 /*
 113  * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
 114  * calculated using the current BL31 PROGBITS debug size plus the sizes of
 115  * BL2 and BL1-RW
 116  */
 117 #if ENABLE_SPM && !SPM_MM
 118 #define PLAT_ARM_MAX_BL31_SIZE          UL(0x60000)
 119 #else
 120 #define PLAT_ARM_MAX_BL31_SIZE          UL(0x3B000)
 121 #endif
 122
 123 #ifndef __aarch64__
 124 /*
 125  * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
 126  * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
 127  * BL2 and BL1-RW
 128  */
 129 # define PLAT_ARM_MAX_BL32_SIZE         UL(0x3B000)
 130 #endif
 131
 132 /*
 133  * Size of cacheable stacks
 134  */
 135 #if defined(IMAGE_BL1)
 136 # if TRUSTED_BOARD_BOOT
 137 #  define PLATFORM_STACK_SIZE           UL(0x1000)
 138 # else
 139 #  define PLATFORM_STACK_SIZE           UL(0x440)
 140 # endif
 141 #elif defined(IMAGE_BL2)
 142 # if TRUSTED_BOARD_BOOT
 143 #  define PLATFORM_STACK_SIZE           UL(0x1000)
 144 # else
 145 #  define PLATFORM_STACK_SIZE           UL(0x400)
 146 # endif
 147 #elif defined(IMAGE_BL2U)
 148 # define PLATFORM_STACK_SIZE            UL(0x400)
 149 #elif defined(IMAGE_BL31)
 150 #  define PLATFORM_STACK_SIZE           UL(0x800)
 151 #elif defined(IMAGE_BL32)
 152 # define PLATFORM_STACK_SIZE            UL(0x440)
 153 #endif
 154
 155 #define MAX_IO_DEVICES                  3
 156 #define MAX_IO_HANDLES                  4
 157
 158 /* Reserve the last block of flash for PSCI MEM PROTECT flag */
 159 #define PLAT_ARM_FIP_BASE               V2M_FLASH0_BASE
 160 #define PLAT_ARM_FIP_MAX_SIZE           (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 161
 162 #define PLAT_ARM_NVM_BASE               V2M_FLASH0_BASE
 163 #define PLAT_ARM_NVM_SIZE               (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 164
 165 /*
 166  * PL011 related constants
 167  */
 168 #define PLAT_ARM_BOOT_UART_BASE         V2M_IOFPGA_UART0_BASE
 169 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ    V2M_IOFPGA_UART0_CLK_IN_HZ
 170
 171 #define PLAT_ARM_RUN_UART_BASE          V2M_IOFPGA_UART1_BASE
 172 #define PLAT_ARM_RUN_UART_CLK_IN_HZ     V2M_IOFPGA_UART1_CLK_IN_HZ
 173
 174 #define PLAT_ARM_CRASH_UART_BASE        PLAT_ARM_RUN_UART_BASE
 175 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ   PLAT_ARM_RUN_UART_CLK_IN_HZ
 176
 177 #define PLAT_ARM_TSP_UART_BASE          V2M_IOFPGA_UART2_BASE
 178 #define PLAT_ARM_TSP_UART_CLK_IN_HZ     V2M_IOFPGA_UART2_CLK_IN_HZ
 179
 180 #define PLAT_FVP_SMMUV3_BASE            UL(0x2b400000)
 181
 182 /* CCI related constants */
 183 #define PLAT_FVP_CCI400_BASE            UL(0x2c090000)
 184 #define PLAT_FVP_CCI400_CLUS0_SL_PORT   3
 185 #define PLAT_FVP_CCI400_CLUS1_SL_PORT   4
 186
 187 /* CCI-500/CCI-550 on Base platform */
 188 #define PLAT_FVP_CCI5XX_BASE            UL(0x2a000000)
 189 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT   5
 190 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT   6
 191
 192 /* CCN related constants. Only CCN 502 is currently supported */
 193 #define PLAT_ARM_CCN_BASE               UL(0x2e000000)
 194 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP  1, 5, 7, 11
 195
 196 /* System timer related constants */
 197 #define PLAT_ARM_NSTIMER_FRAME_ID               U(1)
 198
 199 /* Mailbox base address */
 200 #define PLAT_ARM_TRUSTED_MAILBOX_BASE   ARM_TRUSTED_SRAM_BASE
 201
 202
 203 /* TrustZone controller related constants
 204  *
 205  * Currently only filters 0 and 2 are connected on Base FVP.
 206  * Filter 0 : CPU clusters (no access to DRAM by default)
 207  * Filter 1 : not connected
 208  * Filter 2 : LCDs (access to VRAM allowed by default)
 209  * Filter 3 : not connected
 210  * Programming unconnected filters will have no effect at the
 211  * moment. These filter could, however, be connected in future.
 212  * So care should be taken not to configure the unused filters.
 213  *
 214  * Allow only non-secure access to all DRAM to supported devices.
 215  * Give access to the CPUs and Virtio. Some devices
 216  * would normally use the default ID so allow that too.
 217  */
 218 #define PLAT_ARM_TZC_BASE               UL(0x2a4a0000)
 219 #define PLAT_ARM_TZC_FILTERS            TZC_400_REGION_ATTR_FILTER_BIT(0)
 220
 221 #define PLAT_ARM_TZC_NS_DEV_ACCESS      (                               \
 222                 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT)       |       \
 223                 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI)           |       \
 224                 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP)            |       \
 225                 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO)        |       \
 226                 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
 227
 228 /*
 229  * GIC related constants to cater for both GICv2 and GICv3 instances of an
 230  * FVP. They could be overriden at runtime in case the FVP implements the legacy
 231  * VE memory map.
 232  */
 233 #define PLAT_ARM_GICD_BASE              BASE_GICD_BASE
 234 #define PLAT_ARM_GICR_BASE              BASE_GICR_BASE
 235 #define PLAT_ARM_GICC_BASE              BASE_GICC_BASE
 236
 237 /*
 238  * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
 239  * terminology. On a GICv2 system or mode, the lists will be merged and treated
 240  * as Group 0 interrupts.
 241  */
 242 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
 243         ARM_G1S_IRQ_PROPS(grp), \
 244         INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 245                         GIC_INTR_CFG_LEVEL), \
 246         INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 247                         GIC_INTR_CFG_LEVEL)
 248
 249 #define PLAT_ARM_G0_IRQ_PROPS(grp)      ARM_G0_IRQ_PROPS(grp)
 250
 251 #define PLAT_ARM_PRIVATE_SDEI_EVENTS    ARM_SDEI_PRIVATE_EVENTS
 252 #define PLAT_ARM_SHARED_SDEI_EVENTS     ARM_SDEI_SHARED_EVENTS
 253
 254 #define PLAT_ARM_SP_IMAGE_STACK_BASE    (PLAT_SP_IMAGE_NS_BUF_BASE +    \
 255                                          PLAT_SP_IMAGE_NS_BUF_SIZE)
 256
 257 #define PLAT_SP_PRI                     PLAT_RAS_PRI
 258
 259 /*
 260  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
 261  */
 262 #ifdef __aarch64__
 263 #define PLAT_PHY_ADDR_SPACE_SIZE        (1ULL << 36)
 264 #define PLAT_VIRT_ADDR_SPACE_SIZE       (1ULL << 36)
 265 #else
 266 #define PLAT_PHY_ADDR_SPACE_SIZE        (1ULL << 32)
 267 #define PLAT_VIRT_ADDR_SPACE_SIZE       (1ULL << 32)
 268 #endif
 269
 270 #endif /* PLATFORM_DEF_H */