plat/arm/common/arm_bl2_setup.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8 #include <string.h>
   9
  10 #include <platform_def.h>
  11
  12 #include <arch_helpers.h>
  13 #include <common/bl_common.h>
  14 #include <common/debug.h>
  15 #include <common/desc_image_load.h>
  16 #include <drivers/generic_delay_timer.h>
  17 #ifdef SPD_opteed
  18 #include <lib/optee_utils.h>
  19 #endif
  20 #include <lib/utils.h>
  21 #include <plat/arm/common/plat_arm.h>
  22 #include <plat/common/platform.h>
  23
  24 /* Data structure which holds the extents of the trusted SRAM for BL2 */
  25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
  26
  27 /*
  28  * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is
  29  * for `meminfo_t` data structure and fw_configs passed from BL1.
  30  */
  31 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
  32
  33 /* Weak definitions may be overridden in specific ARM standard platform */
  34 #pragma weak bl2_early_platform_setup2
  35 #pragma weak bl2_platform_setup
  36 #pragma weak bl2_plat_arch_setup
  37 #pragma weak bl2_plat_sec_mem_layout
  38
  39 #define MAP_BL2_TOTAL           MAP_REGION_FLAT(                        \
  40                                         bl2_tzram_layout.total_base,    \
  41                                         bl2_tzram_layout.total_size,    \
  42                                         MT_MEMORY | MT_RW | MT_SECURE)
  43
  44
  45 #pragma weak arm_bl2_plat_handle_post_image_load
  46
  47 /*******************************************************************************
  48  * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
  49  * in x0. This memory layout is sitting at the base of the free trusted SRAM.
  50  * Copy it to a safe location before its reclaimed by later BL2 functionality.
  51  ******************************************************************************/
  52 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config,
  53                                   struct meminfo *mem_layout)
  54 {
  55         /* Initialize the console to provide early debug support */
  56         arm_console_boot_init();
  57
  58         /* Setup the BL2 memory layout */
  59         bl2_tzram_layout = *mem_layout;
  60
  61         /* Initialise the IO layer and register platform IO devices */
  62         plat_arm_io_setup();
  63
  64         if (tb_fw_config != 0U)
  65                 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config);
  66 }
  67
  68 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
  69 {
  70         arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
  71
  72         generic_delay_timer_init();
  73 }
  74
  75 /*
  76  * Perform  BL2 preload setup. Currently we initialise the dynamic
  77  * configuration here.
  78  */
  79 void bl2_plat_preload_setup(void)
  80 {
  81         arm_bl2_dyn_cfg_init();
  82 }
  83
  84 /*
  85  * Perform ARM standard platform setup.
  86  */
  87 void arm_bl2_platform_setup(void)
  88 {
  89         /* Initialize the secure environment */
  90         plat_arm_security_setup();
  91
  92 #if defined(PLAT_ARM_MEM_PROT_ADDR)
  93         arm_nor_psci_do_static_mem_protect();
  94 #endif
  95 }
  96
  97 void bl2_platform_setup(void)
  98 {
  99         arm_bl2_platform_setup();
 100 }
 101
 102 /*******************************************************************************
 103  * Perform the very early platform specific architectural setup here. At the
 104  * moment this is only initializes the mmu in a quick and dirty way.
 105  ******************************************************************************/
 106 void arm_bl2_plat_arch_setup(void)
 107 {
 108 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
 109         /*
 110          * Ensure ARM platforms don't use coherent memory in BL2 unless
 111          * cryptocell integration is enabled.
 112          */
 113         assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
 114 #endif
 115
 116         const mmap_region_t bl_regions[] = {
 117                 MAP_BL2_TOTAL,
 118                 ARM_MAP_BL_RO,
 119 #if USE_ROMLIB
 120                 ARM_MAP_ROMLIB_CODE,
 121                 ARM_MAP_ROMLIB_DATA,
 122 #endif
 123 #if ARM_CRYPTOCELL_INTEG
 124                 ARM_MAP_BL_COHERENT_RAM,
 125 #endif
 126                 {0}
 127         };
 128
 129         setup_page_tables(bl_regions, plat_arm_get_mmap());
 130
 131 #ifdef __aarch64__
 132         enable_mmu_el1(0);
 133 #else
 134         enable_mmu_svc_mon(0);
 135 #endif
 136
 137         arm_setup_romlib();
 138 }
 139
 140 void bl2_plat_arch_setup(void)
 141 {
 142         arm_bl2_plat_arch_setup();
 143 }
 144
 145 int arm_bl2_handle_post_image_load(unsigned int image_id)
 146 {
 147         int err = 0;
 148         bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
 149 #ifdef SPD_opteed
 150         bl_mem_params_node_t *pager_mem_params = NULL;
 151         bl_mem_params_node_t *paged_mem_params = NULL;
 152 #endif
 153         assert(bl_mem_params);
 154
 155         switch (image_id) {
 156 #ifdef __aarch64__
 157         case BL32_IMAGE_ID:
 158 #ifdef SPD_opteed
 159                 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
 160                 assert(pager_mem_params);
 161
 162                 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
 163                 assert(paged_mem_params);
 164
 165                 err = parse_optee_header(&bl_mem_params->ep_info,
 166                                 &pager_mem_params->image_info,
 167                                 &paged_mem_params->image_info);
 168                 if (err != 0) {
 169                         WARN("OPTEE header parse error.\n");
 170                 }
 171 #endif
 172                 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
 173                 break;
 174 #endif
 175
 176         case BL33_IMAGE_ID:
 177                 /* BL33 expects to receive the primary CPU MPID (through r0) */
 178                 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
 179                 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
 180                 break;
 181
 182 #ifdef SCP_BL2_BASE
 183         case SCP_BL2_IMAGE_ID:
 184                 /* The subsequent handling of SCP_BL2 is platform specific */
 185                 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
 186                 if (err) {
 187                         WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
 188                 }
 189                 break;
 190 #endif
 191         default:
 192                 /* Do nothing in default case */
 193                 break;
 194         }
 195
 196         return err;
 197 }
 198
 199 /*******************************************************************************
 200  * This function can be used by the platforms to update/use image
 201  * information for given `image_id`.
 202  ******************************************************************************/
 203 int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
 204 {
 205         return arm_bl2_handle_post_image_load(image_id);
 206 }
 207
 208 int bl2_plat_handle_post_image_load(unsigned int image_id)
 209 {
 210         return arm_bl2_plat_handle_post_image_load(image_id);
 211 }