plat/arm/common/arm_gicv3.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <platform_def.h>
   8
   9 #include <common/interrupt_props.h>
  10 #include <drivers/arm/gicv3.h>
  11 #include <lib/utils.h>
  12 #include <plat/common/platform.h>
  13
  14 #include <arm_def.h>
  15 #include <plat_arm.h>
  16
  17 /******************************************************************************
  18  * The following functions are defined as weak to allow a platform to override
  19  * the way the GICv3 driver is initialised and used.
  20  *****************************************************************************/
  21 #pragma weak plat_arm_gic_driver_init
  22 #pragma weak plat_arm_gic_init
  23 #pragma weak plat_arm_gic_cpuif_enable
  24 #pragma weak plat_arm_gic_cpuif_disable
  25 #pragma weak plat_arm_gic_pcpu_init
  26 #pragma weak plat_arm_gic_redistif_on
  27 #pragma weak plat_arm_gic_redistif_off
  28
  29 /* The GICv3 driver only needs to be initialized in EL3 */
  30 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
  31
  32 static const interrupt_prop_t arm_interrupt_props[] = {
  33         PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
  34         PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
  35 };
  36
  37 /*
  38  * We save and restore the GICv3 context on system suspend. Allocate the
  39  * data in the designated EL3 Secure carve-out memory. The `volatile`
  40  * is used to prevent the compiler from removing the gicv3 contexts even
  41  * though the DEFINE_LOAD_SYM_ADDR creates a dummy reference to it.
  42  */
  43 static volatile gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
  44 static volatile gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
  45
  46 /* Define accessor function to get reference to the GICv3 context */
  47 DEFINE_LOAD_SYM_ADDR(rdist_ctx)
  48 DEFINE_LOAD_SYM_ADDR(dist_ctx)
  49
  50 /*
  51  * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
  52  * to core position.
  53  *
  54  * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
  55  * values read from GICR_TYPER don't have an MT field. To reuse the same
  56  * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
  57  * that read from GICR_TYPER.
  58  *
  59  * Assumptions:
  60  *
  61  *   - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
  62  *   - No CPUs implemented in the system use affinity level 3.
  63  */
  64 static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
  65 {
  66         mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
  67         return plat_arm_calc_core_pos(mpidr);
  68 }
  69
  70 static const gicv3_driver_data_t arm_gic_data __unused = {
  71         .gicd_base = PLAT_ARM_GICD_BASE,
  72         .gicr_base = PLAT_ARM_GICR_BASE,
  73         .interrupt_props = arm_interrupt_props,
  74         .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
  75         .rdistif_num = PLATFORM_CORE_COUNT,
  76         .rdistif_base_addrs = rdistif_base_addrs,
  77         .mpidr_to_core_pos = arm_gicv3_mpidr_hash
  78 };
  79
  80 void __init plat_arm_gic_driver_init(void)
  81 {
  82         /*
  83          * The GICv3 driver is initialized in EL3 and does not need
  84          * to be initialized again in SEL1. This is because the S-EL1
  85          * can use GIC system registers to manage interrupts and does
  86          * not need GIC interface base addresses to be configured.
  87          */
  88 #if (defined(AARCH32) && defined(IMAGE_BL32)) || \
  89         (defined(IMAGE_BL31) && !defined(AARCH32))
  90         gicv3_driver_init(&arm_gic_data);
  91 #endif
  92 }
  93
  94 /******************************************************************************
  95  * ARM common helper to initialize the GIC. Only invoked by BL31
  96  *****************************************************************************/
  97 void __init plat_arm_gic_init(void)
  98 {
  99         gicv3_distif_init();
 100         gicv3_rdistif_init(plat_my_core_pos());
 101         gicv3_cpuif_enable(plat_my_core_pos());
 102 }
 103
 104 /******************************************************************************
 105  * ARM common helper to enable the GIC CPU interface
 106  *****************************************************************************/
 107 void plat_arm_gic_cpuif_enable(void)
 108 {
 109         gicv3_cpuif_enable(plat_my_core_pos());
 110 }
 111
 112 /******************************************************************************
 113  * ARM common helper to disable the GIC CPU interface
 114  *****************************************************************************/
 115 void plat_arm_gic_cpuif_disable(void)
 116 {
 117         gicv3_cpuif_disable(plat_my_core_pos());
 118 }
 119
 120 /******************************************************************************
 121  * ARM common helper to initialize the per-cpu redistributor interface in GICv3
 122  *****************************************************************************/
 123 void plat_arm_gic_pcpu_init(void)
 124 {
 125         gicv3_rdistif_init(plat_my_core_pos());
 126 }
 127
 128 /******************************************************************************
 129  * ARM common helpers to power GIC redistributor interface
 130  *****************************************************************************/
 131 void plat_arm_gic_redistif_on(void)
 132 {
 133         gicv3_rdistif_on(plat_my_core_pos());
 134 }
 135
 136 void plat_arm_gic_redistif_off(void)
 137 {
 138         gicv3_rdistif_off(plat_my_core_pos());
 139 }
 140
 141 /******************************************************************************
 142  * ARM common helper to save & restore the GICv3 on resume from system suspend
 143  *****************************************************************************/
 144 void plat_arm_gic_save(void)
 145 {
 146         gicv3_redist_ctx_t * const rdist_context =
 147                         (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
 148         gicv3_dist_ctx_t * const dist_context =
 149                         (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
 150
 151         /*
 152          * If an ITS is available, save its context before
 153          * the Redistributor using:
 154          * gicv3_its_save_disable(gits_base, &its_ctx[i])
 155          * Additionnaly, an implementation-defined sequence may
 156          * be required to save the whole ITS state.
 157          */
 158
 159         /*
 160          * Save the GIC Redistributors and ITS contexts before the
 161          * Distributor context. As we only handle SYSTEM SUSPEND API,
 162          * we only need to save the context of the CPU that is issuing
 163          * the SYSTEM SUSPEND call, i.e. the current CPU.
 164          */
 165         gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
 166
 167         /* Save the GIC Distributor context */
 168         gicv3_distif_save(dist_context);
 169
 170         /*
 171          * From here, all the components of the GIC can be safely powered down
 172          * as long as there is an alternate way to handle wakeup interrupt
 173          * sources.
 174          */
 175 }
 176
 177 void plat_arm_gic_resume(void)
 178 {
 179         const gicv3_redist_ctx_t *rdist_context =
 180                         (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
 181         const gicv3_dist_ctx_t *dist_context =
 182                         (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
 183
 184         /* Restore the GIC Distributor context */
 185         gicv3_distif_init_restore(dist_context);
 186
 187         /*
 188          * Restore the GIC Redistributor and ITS contexts after the
 189          * Distributor context. As we only handle SYSTEM SUSPEND API,
 190          * we only need to restore the context of the CPU that issued
 191          * the SYSTEM SUSPEND call.
 192          */
 193         gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
 194
 195         /*
 196          * If an ITS is available, restore its context after
 197          * the Redistributor using:
 198          * gicv3_its_restore(gits_base, &its_ctx[i])
 199          * An implementation-defined sequence may be required to
 200          * restore the whole ITS state. The ITS must also be
 201          * re-enabled after this sequence has been executed.
 202          */
 203 }