plat/arm/css/sgi/sgi_plat.c

   1 /*
   2  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arm_def.h>
   8 #include <arm_spm_def.h>
   9 #include <assert.h>
  10 #include <bl_common.h>
  11 #include <ccn.h>
  12 #include <debug.h>
  13 #include <plat_arm.h>
  14 #include <platform_def.h>
  15 #include <platform.h>
  16 #include <secure_partition.h>
  17 #include "../../../../bl1/bl1_private.h"
  18
  19 #if USE_COHERENT_MEM
  20 /*
  21  * The next 2 constants identify the extents of the coherent memory region.
  22  * These addresses are used by the MMU setup code and therefore they must be
  23  * page-aligned.  It is the responsibility of the linker script to ensure that
  24  * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
  25  * refer to page-aligned addresses.
  26  */
  27 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
  28 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
  29 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
  30 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
  31
  32 #define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
  33 #define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
  34 #endif
  35
  36 #define SGI_MAP_FLASH0_RO       MAP_REGION_FLAT(V2M_FLASH0_BASE,\
  37                                                 V2M_FLASH0_SIZE,        \
  38                                                 MT_DEVICE | MT_RO | MT_SECURE)
  39 /*
  40  * Table of regions for different BL stages to map using the MMU.
  41  * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
  42  * arm_configure_mmu_elx() will give the available subset of that.
  43  *
  44  * Replace or extend the below regions as required
  45  */
  46 #if IMAGE_BL1
  47 const mmap_region_t plat_arm_mmap[] = {
  48         ARM_MAP_SHARED_RAM,
  49         SGI_MAP_FLASH0_RO,
  50         CSS_SGI_MAP_DEVICE,
  51         SOC_CSS_MAP_DEVICE,
  52         {0}
  53 };
  54 #endif
  55 #if IMAGE_BL2
  56 const mmap_region_t plat_arm_mmap[] = {
  57         ARM_MAP_SHARED_RAM,
  58         SGI_MAP_FLASH0_RO,
  59         CSS_SGI_MAP_DEVICE,
  60         SOC_CSS_MAP_DEVICE,
  61         ARM_MAP_NS_DRAM1,
  62 #if ARM_BL31_IN_DRAM
  63         ARM_MAP_BL31_SEC_DRAM,
  64 #endif
  65 #if ENABLE_SPM
  66         ARM_SP_IMAGE_MMAP,
  67 #endif
  68 #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
  69         ARM_MAP_BL1_RW,
  70 #endif
  71         {0}
  72 };
  73 #endif
  74 #if IMAGE_BL31
  75 const mmap_region_t plat_arm_mmap[] = {
  76         ARM_MAP_SHARED_RAM,
  77         V2M_MAP_IOFPGA,
  78         CSS_SGI_MAP_DEVICE,
  79         SOC_CSS_MAP_DEVICE,
  80 #if ENABLE_SPM
  81         ARM_SPM_BUF_EL3_MMAP,
  82 #endif
  83         {0}
  84 };
  85
  86 #if ENABLE_SPM && defined(IMAGE_BL31)
  87 const mmap_region_t plat_arm_secure_partition_mmap[] = {
  88         PLAT_ARM_SECURE_MAP_DEVICE,
  89         ARM_SP_IMAGE_MMAP,
  90         ARM_SP_IMAGE_NS_BUF_MMAP,
  91         ARM_SP_CPER_BUF_MMAP,
  92         ARM_SP_IMAGE_RW_MMAP,
  93         ARM_SPM_BUF_EL0_MMAP,
  94         {0}
  95 };
  96 #endif /* ENABLE_SPM && defined(IMAGE_BL31) */
  97 #endif
  98
  99 ARM_CASSERT_MMAP
 100
 101 #if ENABLE_SPM && defined(IMAGE_BL31)
 102 /*
 103  * Boot information passed to a secure partition during initialisation. Linear
 104  * indices in MP information will be filled at runtime.
 105  */
 106 static secure_partition_mp_info_t sp_mp_info[] = {
 107         [0] = {0x81000000, 0},
 108         [1] = {0x81000100, 0},
 109         [2] = {0x81000200, 0},
 110         [3] = {0x81000300, 0},
 111         [4] = {0x81010000, 0},
 112         [5] = {0x81010100, 0},
 113         [6] = {0x81010200, 0},
 114         [7] = {0x81010300, 0},
 115 };
 116
 117 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
 118         .h.type              = PARAM_SP_IMAGE_BOOT_INFO,
 119         .h.version           = VERSION_1,
 120         .h.size              = sizeof(secure_partition_boot_info_t),
 121         .h.attr              = 0,
 122         .sp_mem_base         = ARM_SP_IMAGE_BASE,
 123         .sp_mem_limit        = ARM_SP_IMAGE_LIMIT,
 124         .sp_image_base       = ARM_SP_IMAGE_BASE,
 125         .sp_stack_base       = PLAT_SP_IMAGE_STACK_BASE,
 126         .sp_heap_base        = ARM_SP_IMAGE_HEAP_BASE,
 127         .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE,
 128         .sp_shared_buf_base  = PLAT_SPM_BUF_BASE,
 129         .sp_image_size       = ARM_SP_IMAGE_SIZE,
 130         .sp_pcpu_stack_size  = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
 131         .sp_heap_size        = ARM_SP_IMAGE_HEAP_SIZE,
 132         .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE,
 133         .sp_shared_buf_size  = PLAT_SPM_BUF_SIZE,
 134         .num_sp_mem_regions  = ARM_SP_IMAGE_NUM_MEM_REGIONS,
 135         .num_cpus            = PLATFORM_CORE_COUNT,
 136         .mp_info             = &sp_mp_info[0],
 137 };
 138
 139 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
 140 {
 141         return plat_arm_secure_partition_mmap;
 142 }
 143
 144 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
 145                 void *cookie)
 146 {
 147         return &plat_arm_secure_partition_boot_info;
 148 }
 149 #endif /* ENABLE_SPM && defined(IMAGE_BL31) */
 150
 151 #if TRUSTED_BOARD_BOOT
 152 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
 153 {
 154         assert(heap_addr != NULL);
 155         assert(heap_size != NULL);
 156
 157         return arm_get_mbedtls_heap(heap_addr, heap_size);
 158 }
 159 #endif