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Add Broadcom's code for bcm63xx support
[project/bcm63xx/atf.git] / plat / bcm / include / BPCM.h
1 /*
2 <:copyright-BRCM:2013:DUAL/GPL:standard
3
4 Copyright (c) 2013 Broadcom
5 All Rights Reserved
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License, version 2, as published by
9 the Free Software Foundation (the "GPL").
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16
17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA.
20
21 :>
22 */
23 #ifndef BPCM_H
24 #define BPCM_H
25
26 #ifndef NULL
27 #define NULL ((void *)0)
28 #endif
29
30 #ifndef _TYPEDEFS_H_
31 #ifndef _UINT32_T_DECLARED
32 typedef unsigned int uint32_t;
33 #define _UINT32_T_DECLARED
34 #endif
35 #ifndef _UINT64_T_DECLARED
36 typedef unsigned long long uint64_t;
37 #define _UINT64_T_DECLARED
38 #endif
39 #endif
40
41 #ifndef IS_BCMCHIP
42 #define IS_BCMCHIP(num) (defined(_BCM9##num##_)||defined(CONFIG_BCM9##num)||\
43 defined(CONFIG_BCM##num))
44 #endif
45
46 typedef union {
47 struct {
48 #if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || IS_BCMCHIP(6878) || IS_BCMCHIP(63146)\
49 || IS_BCMCHIP(4912) || IS_BCMCHIP(6855)
50 uint32_t pmbAddr:12; // [11:00]
51 uint32_t map_rev:4; // [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below)
52 uint32_t island:4; // [19:16]
53 uint32_t devType:4; // [23:20] see enum above
54 uint32_t hw_rev:8; // [31:24]
55 #else
56 #ifdef PMC_LITTLE_ENDIAN
57 uint32_t pmb_Addr:8;
58 uint32_t hw_rev:8;
59 uint32_t sw_strap:16;
60 #else
61 uint32_t sw_strap:16;
62 uint32_t hw_rev:8;
63 uint32_t pmb_Addr:8;
64 #endif
65 #endif
66 } Bits;
67 uint32_t Reg32;
68 } BPCM_ID_REG;
69
70 #if IS_BCMCHIP(6846) || IS_BCMCHIP(6856)
71
72 typedef union {
73 struct {
74 uint32_t pmb_Addr:8; // [07:00]
75 uint32_t hw_rev:4; // [11:08]
76 uint32_t map_rev:4; // [15:12] always zero for classic devices (technically upper 4-bits of hw_rev)
77 uint32_t sw_strap:16; // [31:16]
78 } Bits;
79 uint32_t Reg32;
80 } CLASSIC_BPCM_ID_REG;
81 #endif
82
83 #if !IS_BCMCHIP(6878) && !IS_BCMCHIP(6855)
84 // types of PMB devices
85 enum {
86 kPMB_BPCM = 0,
87 kPMB_MIPS_PLL = 1,
88 kPMB_GEN_PLL = 2,
89 kPMB_LC_PLL = 3,
90 // 4..15 reserved
91 };
92 #else
93 enum {
94 kPMB_NO_DEVICE = 0,
95 kPMB_BPCM = 1, // in AVS3, this structure does not contain ARS registers (except for "classic" BPCM devices)
96 kPMB_MIPS_PLL = 2,
97 kPMB_GEN_PLL = 3,
98 kPMB_LC_PLL = 4,
99 kPMB_CLKRST = 5,
100 kPMB_PVTMON = 6, // used in in AVS3 when PVT is wrapped in a BPCM structure
101 kPMB_TMON_INTERNAL = 7, // ditto - used when TMON thermistor is on-die
102 kPMB_TMON_EXTERNAL = 8, // ditto - used when thermistor is off-die
103 kPMB_ARS = 9, // AVS Remote Sensors - remote oscillators and Power-Watchdog
104 // 10..15 reserved
105 };
106 #endif
107
108 typedef union {
109 struct {
110 #ifdef PMC_LITTLE_ENDIAN
111 #if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
112 uint32_t num_zones:6;
113 uint32_t reserved0:2;
114 #else
115 uint32_t num_zones:8;
116 #endif
117 uint32_t num_sr_bits:8;
118 uint32_t devType:4; // see enum above
119 uint32_t reserved1:12;
120 #else
121 uint32_t reserved1:12;
122 uint32_t devType:4; // see enum above
123 uint32_t num_sr_bits:8;
124 #if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
125 uint32_t reserved0:2;
126 uint32_t num_zones:6;
127 #else
128 uint32_t num_zones:8;
129 #endif
130 #endif
131 } Bits;
132 uint32_t Reg32;
133 } BPCM_CAPABILITES_REG;
134
135 typedef union {
136 struct {
137 #ifdef PMC_LITTLE_ENDIAN
138 uint32_t pwd_alert:1;
139 uint32_t reserved:31;
140 #else
141 uint32_t reserved:31;
142 uint32_t pwd_alert:1;
143 #endif
144 } Bits;
145 uint32_t Reg32;
146 } BPCM_STATUS_REG;
147
148 typedef union {
149 struct {
150 #ifdef PMC_LITTLE_ENDIAN
151 uint32_t ro_en_s:1;
152 uint32_t ro_en_h:1;
153 uint32_t ectr_en_s:1;
154 uint32_t ectr_en_h:1;
155 uint32_t thresh_en_s:1;
156 uint32_t thresh_en_h:1;
157 uint32_t continuous_s:1;
158 uint32_t continuous_h:1;
159 uint32_t reserved:4;
160 uint32_t valid_s:1;
161 uint32_t alert_s:1;
162 uint32_t valid_h:1;
163 uint32_t alert_h:1;
164 uint32_t interval:16;
165 #else
166 uint32_t interval:16;
167 uint32_t alert_h:1;
168 uint32_t valid_h:1;
169 uint32_t alert_s:1;
170 uint32_t valid_s:1;
171 uint32_t reserved:4;
172 uint32_t continuous_h:1;
173 uint32_t continuous_s:1;
174 uint32_t thresh_en_h:1;
175 uint32_t thresh_en_s:1;
176 uint32_t ectr_en_h:1;
177 uint32_t ectr_en_s:1;
178 uint32_t ro_en_h:1;
179 uint32_t ro_en_s:1;
180 #endif
181 } Bits;
182 uint32_t Reg32;
183 } BPCM_AVS_ROSC_CONTROL_REG;
184
185 typedef union {
186 struct {
187 #ifdef PMC_LITTLE_ENDIAN
188 uint32_t thresh_lo:16;
189 uint32_t thresh_hi:16;
190 #else
191 uint32_t thresh_hi:16;
192 uint32_t thresh_lo:16;
193 #endif
194 } Bits;
195 uint32_t Reg32;
196 } BPCM_AVS_ROSC_THRESHOLD;
197
198 typedef union {
199 struct {
200 #ifdef PMC_LITTLE_ENDIAN
201 uint32_t count_s:16;
202 uint32_t count_h:16;
203 #else
204 uint32_t count_h:16;
205 uint32_t count_s:16;
206 #endif
207 } Bits;
208 uint32_t Reg32;
209 } BPCM_AVS_ROSC_COUNT;
210
211 typedef union {
212 struct {
213 #ifdef PMC_LITTLE_ENDIAN
214 uint32_t pwd_en:1;
215 uint32_t pwd_alert_sel:1;
216 uint32_t start:6;
217 uint32_t pwd_tm_en:1;
218 uint32_t reserved2:6;
219 uint32_t alert:1;
220 uint32_t ccfg:8;
221 uint32_t rsel:3;
222 uint32_t clr_cfg:3;
223 uint32_t reserved1:2;
224 #else
225 uint32_t reserved1:2;
226 uint32_t clr_cfg:3;
227 uint32_t rsel:3;
228 uint32_t ccfg:8;
229 uint32_t alert:1;
230 uint32_t reserved2:6;
231 uint32_t pwd_tm_en:1;
232 uint32_t start:6;
233 uint32_t pwd_alert_sel:1;
234 uint32_t pwd_en:1;
235 #endif
236 } Bits;
237 uint32_t Reg32;
238 } BPCM_AVS_PWD_CONTROL;
239
240 typedef union {
241 struct {
242 uint32_t tbd:32;
243 } Bits;
244 uint32_t Reg32;
245 } BPCM_PWD_ACCUM_CONTROL;
246
247 typedef union {
248 struct {
249 #ifdef PMC_LITTLE_ENDIAN
250 uint32_t sr:8;
251 uint32_t gp:24;
252 #else
253 uint32_t gp:24;
254 uint32_t sr:8;
255 #endif
256 } Bits;
257 #if IS_BCMCHIP(6858)
258 struct {
259 #ifdef PMC_LITTLE_ENDIAN
260 uint32_t wan_main_rst_n:1;
261 uint32_t wan_top_bb_rst_n:1;
262 uint32_t epon_core_rst_n:1;
263 uint32_t epon_rx_rclk16_sw_reset_n:1;
264 uint32_t epon_rx_rbc125_sw_reset_n:1;
265 uint32_t epon_tx_tclk16_sw_reset_n:1;
266 uint32_t epon_tx_clk125_sw_reset_n:1;
267 uint32_t gpon_main_rst_n:1;
268 uint32_t gpon_rx_rst_n:1;
269 uint32_t gpon_tx_rst_n:1;
270 uint32_t gpon_8khz_rst_n:1;
271 uint32_t ngpon_main_rst_n:1;
272 uint32_t ngpon_rx_rst_n:1;
273 uint32_t ngpon_tx_rst_n:1;
274 uint32_t ngpon_8khz_rst_n:1;
275 uint32_t gpon_nco_rst_n:1;
276 uint32_t apm_rst_n:1;
277 uint32_t reserved:15;
278 #else
279 uint32_t reserved:15;
280 uint32_t apm_rst_n:1;
281 uint32_t gpon_nco_rst_n:1;
282 uint32_t ngpon_8khz_rst_n:1;
283 uint32_t ngpon_tx_rst_n:1;
284 uint32_t ngpon_rx_rst_n:1;
285 uint32_t ngpon_main_rst_n:1;
286 uint32_t gpon_8khz_rst_n:1;
287 uint32_t gpon_tx_rst_n:1;
288 uint32_t gpon_rx_rst_n:1;
289 uint32_t gpon_main_rst_n:1;
290 uint32_t epon_tx_clk125_sw_reset_n:1;
291 uint32_t epon_tx_tclk16_sw_reset_n:1;
292 uint32_t epon_rx_rbc125_sw_reset_n:1;
293 uint32_t epon_rx_rclk16_sw_reset_n:1;
294 uint32_t epon_core_rst_n:1;
295 uint32_t wan_top_bb_rst_n:1;
296 uint32_t wan_main_rst_n:1;
297 #endif
298 } Bits_Wantop;
299 #endif
300 #if IS_BCMCHIP(63158)
301 struct {
302 #ifdef PMC_LITTLE_ENDIAN
303 uint32_t wan_main_rst_n:1;
304 uint32_t wan_top_bb_rst_n:1;
305 uint32_t rbus_rst_n:1;
306 uint32_t reserved1:2;
307 uint32_t core_soft_rst_n:1;
308 uint32_t i_zn_sw_init:1;
309 uint32_t reserved2:1;
310 uint32_t epon_main_rst_n:1;
311 uint32_t epon_rx_rst_n:1;
312 uint32_t epon_tx_rst_n:1;
313 uint32_t epon_core_rst_n:1;
314 uint32_t ae_rx_rclk16_sw_reset_n:1;
315 uint32_t ae_rx_rbc125_sw_reset_n:1; /* for B0 */
316 uint32_t ae_tx_tclk16_sw_reset_n:1; /* for B0 */
317 uint32_t ae_tx_clk125_sw_reset_n:1;
318 uint32_t gpon_main_rst_n:1;
319 uint32_t gpon_rx_rst_n:1;
320 uint32_t gpon_tx_rst_n:1;
321 uint32_t gpon_8khz_rst_n:1;
322 uint32_t ngpon_main_rst_n:1;
323 uint32_t ngpon_rx_rst_n:1;
324 uint32_t ngpon_tx_rst_n:1;
325 uint32_t ngpon_8khz_rst_n:1;
326 uint32_t reserved3:2;
327 uint32_t gpon_nco_rst_n:1;
328 uint32_t epon_rx_rclk16_sw_reset_n:1; /* for B0 */
329 uint32_t epon_rx_rbc125_sw_reset_n:1; /* for B0 */
330 uint32_t epon_tx_tclk16_sw_reset_n:1; /* for B0 */
331 uint32_t epon_tx_clk125_sw_reset_n:1; /* for B0 */
332 uint32_t reserved4:1;
333 #else
334 uint32_t reserved4:1;
335 uint32_t epon_tx_clk125_sw_reset_n:1; /* for B0 */
336 uint32_t epon_tx_tclk16_sw_reset_n:1; /* for B0 */
337 uint32_t epon_rx_rbc125_sw_reset_n:1; /* for B0 */
338 uint32_t epon_rx_rclk16_sw_reset_n:1; /* for B0 */
339 uint32_t gpon_nco_rst_n:1;
340 uint32_t reserved3:2;
341 uint32_t ngpon_8khz_rst_n:1;
342 uint32_t ngpon_tx_rst_n:1;
343 uint32_t ngpon_rx_rst_n:1;
344 uint32_t ngpon_main_rst_n:1;
345 uint32_t gpon_8khz_rst_n:1;
346 uint32_t gpon_tx_rst_n:1;
347 uint32_t gpon_rx_rst_n:1;
348 uint32_t gpon_main_rst_n:1;
349 uint32_t ae_tx_clk125_sw_reset_n:1;
350 uint32_t ae_tx_tclk16_sw_reset_n:1; /* for B0 */
351 uint32_t ae_rx_rbc125_sw_reset_n:1; /* for B0 */
352 uint32_t ae_rx_rclk16_sw_reset_n:1;
353 uint32_t epon_core_rst_n:1;
354 uint32_t epon_tx_rst_n:1;
355 uint32_t epon_rx_rst_n:1;
356 uint32_t epon_main_rst_n:1;
357 uint32_t reserved2:1;
358 uint32_t i_zn_sw_init:1;
359 uint32_t core_soft_rst_n:1;
360 uint32_t reserved1:2;
361 uint32_t rbus_rst_n:1;
362 uint32_t wan_top_bb_rst_n:1;
363 uint32_t wan_main_rst_n:1;
364 #endif
365 } Bits_Wantop;
366 #endif
367 #if IS_BCMCHIP(63158) || IS_BCMCHIP(63178)
368 struct {
369 #ifdef PMC_LITTLE_ENDIAN
370 uint32_t vdsl_bpcm_early_reset:1;
371 uint32_t vdsl_bpcm_reset:1;
372 uint32_t mips_ubus_soft_reset_bpcm_reset:1;
373 uint32_t qproc_1_bpcm_reset:1;
374 uint32_t qproc_2_bpcm_reset:1;
375 uint32_t sar_bpcm_soft_reset:1;
376 uint32_t vdsl_ubus_soft_bpcm_reset:1;
377 uint32_t reserved1:1;
378 uint32_t gp:24;
379 #else
380 uint32_t gp:24;
381 uint32_t reserved1:1;
382 uint32_t vdsl_ubus_soft_bpcm_reset:1;
383 uint32_t sar_bpcm_soft_reset:1;
384 uint32_t qproc_2_bpcm_reset:1;
385 uint32_t qproc_1_bpcm_reset:1;
386 uint32_t mips_ubus_soft_reset_bpcm_reset:1;
387 uint32_t vdsl_bpcm_reset:1;
388 uint32_t vdsl_bpcm_early_reset:1;
389 #endif
390 } Bits_vdsl;
391 #endif
392 uint32_t Reg32;
393 } BPCM_SR_CONTROL;
394
395 typedef union{
396 struct {
397 uint32_t tbd:32;
398 } Bits;
399 uint32_t Reg32;
400 struct {
401 #ifdef PMC_LITTLE_ENDIAN
402 uint32_t vdsl_arm_por_reset_n:1;
403 uint32_t vdsl_arm_reset_n:1;
404 uint32_t vdsl_arm_debug_reset_n:1;
405 uint32_t vdsl_arm_l2_reset_n:1;
406 uint32_t vdsl_arm_cdbgrstreq_en:1;
407 uint32_t vdsl_arm_niden_a7_b0:1;
408 uint32_t vdsl_arm_spniden_a7_b0:1;
409 uint32_t vdsl_arm_nsocdbgreset_a7:1;
410 uint32_t axi4_ubus4_pass_through_disable:1;
411 uint32_t vdsl_arm_dbgen_a7_b0:1;
412 uint32_t vdsl_arm_spiden_a7_b0:1;
413 uint32_t vdsl_arm_scratch_reg:21;
414 #else
415 uint32_t vdsl_arm_scratch_reg:21;
416 uint32_t vdsl_arm_spiden_a7_b0:1;
417 uint32_t vdsl_arm_dbgen_a7_b0:1;
418 uint32_t axi4_ubus4_pass_through_disable:1;
419 uint32_t vdsl_arm_nsocdbgreset_a7:1;
420 uint32_t vdsl_arm_spniden_a7_b0:1;
421 uint32_t vdsl_arm_niden_a7_b0:1;
422 uint32_t vdsl_arm_cdbgrstreq_en:1;
423 uint32_t vdsl_arm_l2_reset_n:1;
424 uint32_t vdsl_arm_debug_reset_n:1;
425 uint32_t vdsl_arm_reset_n:1;
426 uint32_t vdsl_arm_por_reset_n:1;
427 #endif
428 } Bits_vdsl;
429 } BPCM_VDSL_ARM_RST_CTL;
430
431 #if IS_BCMCHIP(63138) || IS_BCMCHIP(4908) || IS_BCMCHIP(63158)
432 typedef union {
433 struct {
434 #ifdef PMC_LITTLE_ENDIAN
435 uint32_t z2_p_wan_phy_sel:3; /* 0-2 */
436 uint32_t reserved0:1; /* 3 */
437 uint32_t z2_switch_p3_phy_sel:3; /* 4-6 */
438 uint32_t reserved1:1; /* 7 */
439 uint32_t z2_switch_p4_phy_sel:3; /* 8-10 */
440 uint32_t reserved2:1; /* 11 */
441 uint32_t z0_mux_sel:1; /* 12 */
442 uint32_t z1_gphy_mux_sel:1; /* 13 */
443 uint32_t z2_gphy_mux_sel:1; /* 14 */
444 uint32_t z2_crossbar_mux_sel:1; /* 15 */
445 uint32_t reserved3:1; /* 16 */
446 uint32_t z1_pda_en:1; /* 17 */
447 uint32_t z1_ck250_clk_en:1; /* 18 */
448 uint32_t z1_ck25_clk_dis:1; /* 19 */
449 uint32_t reserved4:2; /* 20-21 */
450 uint32_t z2_ck250_clk_en:1; /* 22 */
451 uint32_t z2_ck25_clk_dis:1; /* 23 */
452 uint32_t z2_serdes_clk_en:1; /* 24 */
453 uint32_t z2_serdes_reset_mdioregs:1; /* 25 */
454 uint32_t z2_sedes_reset_pll:1; /* 26 */
455 uint32_t z2_serdes_reset:1; /* 27 */
456 uint32_t z2_serdes_mux_sel:1; /* 28 */
457 uint32_t reserved5:1; /* 29 */
458 uint32_t z1_gphy_reset:1; /* 30 */
459 uint32_t z2_gphy_reset:1; /* 31 */
460 #else
461 uint32_t z2_gphy_reset:1; /* 31 */
462 uint32_t z1_gphy_reset:1; /* 30 */
463 uint32_t reserved5:1; /* 29 */
464 uint32_t z2_serdes_mux_sel:1; /* 28 */
465 uint32_t z2_serdes_reset:1; /* 27 */
466 uint32_t z2_sedes_reset_pll:1; /* 26 */
467 uint32_t z2_serdes_reset_mdioregs:1; /* 25 */
468 uint32_t z2_serdes_clk_en:1; /* 24 */
469 uint32_t z2_ck25_clk_dis:1; /* 23 */
470 uint32_t z2_ck250_clk_en:1; /* 22 */
471 uint32_t reserved4:2; /* 20-21 */
472 uint32_t z1_ck25_clk_dis:1; /* 19 */
473 uint32_t z1_ck250_clk_en:1; /* 18 */
474 uint32_t z1_pda_en:1; /* 17 */
475 uint32_t reserved3:1; /* 16 */
476 uint32_t z2_crossbar_mux_sel:1; /* 15 */
477 uint32_t z2_gphy_mux_sel:1; /* 14 */
478 uint32_t z1_gphy_mux_sel:1; /* 13 */
479 uint32_t z0_mux_sel:1; /* 12 */
480 uint32_t reserved2:1; /* 11 */
481 uint32_t z2_switch_p4_phy_sel:3; /* 8-10 */
482 uint32_t reserved1:1; /* 7 */
483 uint32_t z2_switch_p3_phy_sel:3; /* 4-6 */
484 uint32_t reserved0:1; /* 3 */
485 uint32_t z2_p_wan_phy_sel:3; /* 0-2 */
486 #endif
487 } Bits;
488 uint32_t Reg32;
489 } BPCM_GLOBAL_CNTL;
490
491 #elif IS_BCMCHIP(6858) || IS_BCMCHIP(6846) || IS_BCMCHIP(6856) || \
492 IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || \
493 IS_BCMCHIP(63146) || IS_BCMCHIP(6855) || IS_BCMCHIP(4912) || \
494 IS_BCMCHIP(6756)
495
496 typedef union {
497 struct {
498 uint32_t tbd:32;
499 } Bits;
500 uint32_t Reg32;
501 } BPCM_GLOBAL_CNTL;
502 #else
503 typedef union {
504 struct {
505 #ifdef PMC_LITTLE_ENDIAN
506 uint32_t z0_mux_sel:1; /* 0 */
507 uint32_t reserved0:4; /* 1-4 */
508 uint32_t z1_gphy_reset:1; /* 5 */
509 uint32_t reserved1:3; /* 6-8 */
510 uint32_t z1_ck25_clk_dis:1; /* 9 */
511 uint32_t z1_ck250_clk_en:1; /* 10 */
512 uint32_t reserved2:1; /* 11 */
513 uint32_t z1_gphy_mux_sel:1; /* 12 */
514 uint32_t z1_pda_en:1; /* 13 */
515 uint32_t reserved3:3; /* 14-16 */
516 uint32_t z2_gphy_reset:1; /* 17 */
517 uint32_t z2_serdes_reset:1; /* 18 */
518 uint32_t z2_serdes_reset_mdioregs:1; /* 19 */
519 uint32_t z2_sedes_reset_pll:1; /* 20 */
520 uint32_t z2_ck250_clk_en:1; /* 21 */
521 uint32_t z2_ck25_clk_dis:1; /* 22 */
522 uint32_t z2_serdes_clk_en:1; /* 23 */
523 uint32_t reserved4:1; /* 24 */
524 uint32_t z2_serdes_mux_sel:1; /* 25 */
525 uint32_t z2_gphy_mux_sel:1; /* 26 */
526 uint32_t z2_crossbar_mux_sel:1; /* 27 */
527 uint32_t z2_p_wan_phy_sel:2; /* 28-29 */
528 uint32_t z2_switch_phy_sel:2; /* 30-31 */
529 #else
530 uint32_t z2_switch_phy_sel:2; /* 30-31 */
531 uint32_t z2_p_wan_phy_sel:2; /* 28-29 */
532 uint32_t z2_crossbar_mux_sel:1; /* 27 */
533 uint32_t z2_gphy_mux_sel:1; /* 26 */
534 uint32_t z2_serdes_mux_sel:1; /* 25 */
535 uint32_t reserved4:1; /* 24 */
536 uint32_t z2_serdes_clk_en:1; /* 23 */
537 uint32_t z2_ck25_clk_dis:1; /* 22 */
538 uint32_t z2_ck250_clk_en:1; /* 21 */
539 uint32_t z2_sedes_reset_pll:1; /* 20 */
540 uint32_t z2_serdes_reset_mdioregs:1; /* 19 */
541 uint32_t z2_serdes_reset:1; /* 18 */
542 uint32_t z2_gphy_reset:1; /* 17 */
543 uint32_t reserved3:3; /* 14-16 */
544 uint32_t z1_pda_en:1; /* 13 */
545 uint32_t z1_gphy_mux_sel:1; /* 12 */
546 uint32_t reserved2:1; /* 11 */
547 uint32_t z1_ck250_clk_en:1; /* 10 */
548 uint32_t z1_ck25_clk_dis:1; /* 9 */
549 uint32_t reserved1:3; /* 6-8 */
550 uint32_t z1_gphy_reset:1; /* 5 */
551 uint32_t reserved0:4; /* 1-4 */
552 uint32_t z0_mux_sel:1; /* 0 */
553 #endif
554 } Bits;
555 uint32_t Reg32;
556 } BPCM_GLOBAL_CNTL;
557 #endif
558
559 #if IS_BCMCHIP(63158)
560 typedef union {
561 struct {
562
563 #ifdef PMC_LITTLE_ENDIAN
564 uint32_t z0_mux_sel:1; // = r_Z0_GLOBAL_CNTL[0];
565 uint32_t reserverd_1:1; // unused
566 uint32_t z3_pda_en:1; // = r_Z0_GLOBAL_CNTL[2];
567 uint32_t rx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[3];
568 uint32_t tx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[4];
569 uint32_t gmii_rx_clk_en:1; // = r_Z0_GLOBAL_CNTL[5];
570 uint32_t gmii_tx_clk_en:1; // = r_Z0_GLOBAL_CNTL[6];
571 uint32_t rsrvd:25;
572 #else
573 uint32_t rsrvd:25;
574 uint32_t gmii_tx_clk_en:1; // = r_Z0_GLOBAL_CNTL[6];
575 uint32_t gmii_rx_clk_en:1; // = r_Z0_GLOBAL_CNTL[5];
576 uint32_t tx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[4];
577 uint32_t rx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[3];
578 uint32_t z3_pda_en:1; // = r_Z0_GLOBAL_CNTL[2];
579 uint32_t reserverd_1:1; // unused
580 uint32_t z0_mux_sel:1; // = r_Z0_GLOBAL_CNTL[0];
581 #endif
582
583 } Bits;
584 uint32_t Reg32;
585
586 } BPCM_GLOBAL_CNTL_0;
587
588 typedef union {
589 struct {
590
591 #ifdef PMC_LITTLE_ENDIAN
592 uint32_t z1_pda_en:1; //= r_Z1_GLOBAL_CNTL[0];
593 uint32_t reserved:2;
594 uint32_t z1_ck250_clk_en:1; //= r_Z1_GLOBAL_CNTL[3];
595 uint32_t z1_ref_clk_dis:1; //= r_Z1_GLOBAL_CNTL[4];
596 uint32_t z1_mux_sel:1; //= r_Z1_GLOBAL_CNTL[5];
597 uint32_t z1_gphy_reset:1; //= r_Z1_GLOBAL_CNTL[6];
598 uint32_t z1_gphy_iddq_global_pwr:1; //= r_Z1_GLOBAL_CNTL[7];
599 uint32_t z1_gphy_force_dll_en:1; //= r_Z1_GLOBAL_CNTL[8];
600 uint32_t z1_gphy_ext_pwr_down:4; //= r_Z1_GLOBAL_CNTL[12:9];
601 uint32_t z1_gphy_iddq_bias:1; //= r_Z1_GLOBAL_CNTL[13];
602 uint32_t z1_switch_p3_phy_sel:1; //= r_Z1_GLOBAL_CNTL[14];
603 uint32_t z1_switch_p8_sel:1; //= r_Z1_GLOBAL_CNTL[15];
604 uint32_t rsrvd:16;
605 #else
606 uint32_t rsrvd:16;
607 uint32_t z1_switch_p8_sel:1; //= r_Z1_GLOBAL_CNTL[15];
608 uint32_t z1_switch_p3_phy_sel:1; //= r_Z1_GLOBAL_CNTL[14];
609 uint32_t z1_gphy_iddq_bias:1; //= r_Z1_GLOBAL_CNTL[13];
610 uint32_t z1_gphy_ext_pwr_down:4; //= r_Z1_GLOBAL_CNTL[12:9];
611 uint32_t z1_gphy_force_dll_en:1; //= r_Z1_GLOBAL_CNTL[8];
612 uint32_t z1_gphy_iddq_global_pwr:1; //= r_Z1_GLOBAL_CNTL[7];
613 uint32_t z1_gphy_reset:1; //= r_Z1_GLOBAL_CNTL[6];
614 uint32_t z1_mux_sel:1; //= r_Z1_GLOBAL_CNTL[5];
615 uint32_t z1_ref_clk_dis:1; //= r_Z1_GLOBAL_CNTL[4];
616 uint32_t z1_ck250_clk_en:1; //= r_Z1_GLOBAL_CNTL[3];
617 uint32_t reserved:2;
618 uint32_t z1_pda_en:1; //= r_Z1_GLOBAL_CNTL[0];
619 #endif
620
621 } Bits;
622 uint32_t Reg32;
623
624 } BPCM_GLOBAL_CNTL_1;
625
626 typedef union {
627 struct {
628 #ifdef PMC_LITTLE_ENDIAN
629 uint32_t z2_pda_en:1; //= r_Z2_GLOBAL_CNTL[0];
630 uint32_t reserved:1;
631 uint32_t z2_ck250_clk_en:1; //= r_Z2_GLOBAL_CNTL[2];
632 uint32_t z2_ref_clk_dis:1; //= r_Z2_GLOBAL_CNTL[3];
633 uint32_t z2_serdes_clk_en:1; //= r_Z2_GLOBAL_CNTL[4];
634 uint32_t z2_gphy_mux_sel:1; //= r_Z2_GLOBAL_CNTL[5];
635 uint32_t z2_gphy_reset:1; //= r_Z2_GLOBAL_CNTL[6];
636 uint32_t z2_gphy_iddq_global_pwr:1; //= r_Z2_GLOBAL_CNTL[7];
637 uint32_t z2_gphy_force_dll_en:1; //= r_Z2_GLOBAL_CNTL[8];
638 uint32_t z2_gphy_ext_pwr_down:1; //= r_Z2_GLOBAL_CNTL[9];
639 uint32_t z2_gphy_iddq_bias:1; //= r_Z2_GLOBAL_CNTL[10];
640 uint32_t z2_crossbar_mux_sel:1; //= r_Z2_GLOBAL_CNTL[11];
641 uint32_t z2_p_wan_phy_sel:2; //= r_Z2_GLOBAL_CNTL[13:12];
642 uint32_t z2_switch_p4_phy_sel:2; //= r_Z2_GLOBAL_CNTL[15:14];
643 uint32_t z2_switch_p6_phy_sel:2; //= r_Z2_GLOBAL_CNTL[17:16];
644 uint32_t z2_serdes_mux_sel:1; //= r_Z2_GLOBAL_CNTL[18];
645 uint32_t z2_serdes_iddq:1; //= r_Z2_GLOBAL_CNTL[19];
646 uint32_t z2_serdes_pwrdwn:1; //= r_Z2_GLOBAL_CNTL[20];
647 uint32_t z2_serdes_reset:1; //= r_Z2_GLOBAL_CNTL[21];
648 uint32_t z2_serdes_reset_mdioregs:1; //= r_Z2_GLOBAL_CNTL[22];
649 uint32_t z2_serdes_reset_pll:1; //= r_Z2_GLOBAL_CNTL[23];
650 uint32_t z2_serdes_refclk_sel:3; //= r_Z2_GLOBAL_CNTL[26:24];
651 uint32_t z2_pll_clk125_250_sel:1; //= r_Z2_GLOBAL_CNTL[27];
652 uint32_t z2_pll_mux_clk250_sel:1; //= r_Z2_GLOBAL_CNTL[28];
653 uint32_t rsrvd:3;
654 #else
655 uint32_t rsrvd:3;
656 uint32_t z2_pll_mux_clk250_sel:1; //= r_Z2_GLOBAL_CNTL[28];
657 uint32_t z2_pll_clk125_250_sel:1; //= r_Z2_GLOBAL_CNTL[27];
658 uint32_t z2_serdes_refclk_sel:3; //= r_Z2_GLOBAL_CNTL[26:24];
659 uint32_t z2_serdes_reset_pll:1; //= r_Z2_GLOBAL_CNTL[23];
660 uint32_t z2_serdes_reset_mdioregs:1; //= r_Z2_GLOBAL_CNTL[22];
661 uint32_t z2_serdes_reset:1; //= r_Z2_GLOBAL_CNTL[21];
662 uint32_t z2_serdes_pwrdwn:1; //= r_Z2_GLOBAL_CNTL[20];
663 uint32_t z2_serdes_iddq:1; //= r_Z2_GLOBAL_CNTL[19];
664 uint32_t z2_serdes_mux_sel:1; //= r_Z2_GLOBAL_CNTL[18];
665 uint32_t z2_switch_p6_phy_sel:2; //= r_Z2_GLOBAL_CNTL[17:16];
666 uint32_t z2_switch_p4_phy_sel:2; //= r_Z2_GLOBAL_CNTL[15:14];
667 uint32_t z2_p_wan_phy_sel:2; //= r_Z2_GLOBAL_CNTL[13:12];
668 uint32_t z2_crossbar_mux_sel:1; //= r_Z2_GLOBAL_CNTL[11];
669 uint32_t z2_gphy_iddq_bias:1; //= r_Z2_GLOBAL_CNTL[10];
670 uint32_t z2_gphy_ext_pwr_down:1; //= r_Z2_GLOBAL_CNTL[9];
671 uint32_t z2_gphy_force_dll_en:1; //= r_Z2_GLOBAL_CNTL[8];
672 uint32_t z2_gphy_iddq_global_pwr:1; //= r_Z2_GLOBAL_CNTL[7];
673 uint32_t z2_gphy_reset:1; //= r_Z2_GLOBAL_CNTL[6];
674 uint32_t z2_gphy_mux_sel:1; //= r_Z2_GLOBAL_CNTL[5];
675 uint32_t z2_serdes_clk_en:1; //= r_Z2_GLOBAL_CNTL[4];
676 uint32_t z2_ref_clk_dis:1; //= r_Z2_GLOBAL_CNTL[3];
677 uint32_t z2_ck250_clk_en:1; //= r_Z2_GLOBAL_CNTL[2];
678 uint32_t reserved:1;
679 uint32_t z2_pda_en:1; //= r_Z2_GLOBAL_CNTL[0];
680 #endif
681
682 } Bits;
683 uint32_t Reg32;
684
685 } BPCM_GLOBAL_CNTL_2;
686 #endif
687
688 typedef union {
689 struct {
690 uint32_t ctl;
691 } Bits_sata_gp;
692 struct {
693 #ifdef PMC_LITTLE_ENDIAN
694 uint32_t iddq_bias:1; /* 0 */
695 uint32_t ext_pwr_down:4; /* 1-4 */
696 uint32_t force_dll_en:1; /* 5 */
697 uint32_t iddq_global_pwr:1; /* 6 */
698 uint32_t reserved:25;
699 #else
700 uint32_t reserved:25;
701 uint32_t iddq_global_pwr:1; /* 6 */
702 uint32_t force_dll_en:1; /* 5 */
703 uint32_t ext_pwr_down:4; /* 1-4 */
704 uint32_t iddq_bias:1; /* 0 */
705 #endif
706 } Bits_switch_z1_qgphy;
707 struct {
708 #ifdef PMC_LITTLE_ENDIAN
709 uint32_t iddq_bias:1; /* 0 */
710 uint32_t ext_pwr_down:1; /* 1 */
711 uint32_t force_dll_en:1; /* 2 */
712 uint32_t iddq_global_pwd:1; /* 3 */
713 uint32_t ck25_dis:1; /* 4 */
714 uint32_t phy_reset:1; /* 5 */
715 uint32_t reserved0:2;
716 uint32_t phy_ad:5; /* 8-12 */
717 uint32_t reserved1:18;
718 uint32_t ctrl_en:1; /* 31 */
719 #else
720 uint32_t ctrl_en:1; /* 31 */
721 uint32_t reserved1:18;
722 uint32_t phy_ad:5; /* 8-12 */
723 uint32_t reserved0:2;
724 uint32_t phy_reset:1; /* 5 */
725 uint32_t ck25_dis:1; /* 4 */
726 uint32_t iddq_global_pwd:1; /* 3 */
727 uint32_t force_dll_en:1; /* 2 */
728 uint32_t ext_pwr_down:1; /* 1 */
729 uint32_t iddq_bias:1; /* 0 */
730 #endif
731 } Bits_egphy_1port;
732 struct {
733 #ifdef PMC_LITTLE_ENDIAN
734 uint32_t iddq_bias:1; /* 0 */
735 uint32_t ext_pwr_down:4; /* 1-4 */
736 uint32_t force_dll_en:1; /* 5 */
737 uint32_t iddq_global_pwd:1; /* 6 */
738 uint32_t ck25_dis:1; /* 7 */
739 uint32_t phy_reset:1; /* 8 */
740 uint32_t reserved0:3;
741 uint32_t phy_ad:5; /* 12-16 */
742 uint32_t reserved1:14;
743 uint32_t ctrl_en:1; /* 31 */
744 #else
745 uint32_t ctrl_en:1; /* 31 */
746 uint32_t reserved1:14;
747 uint32_t phy_ad:5; /* 12-16 */
748 uint32_t reserved0:3;
749 uint32_t phy_reset:1; /* 8 */
750 uint32_t ck25_dis:1; /* 7 */
751 uint32_t iddq_global_pwd:1; /* 6 */
752 uint32_t force_dll_en:1; /* 5 */
753 uint32_t ext_pwr_down:4; /* 1-4 */
754 uint32_t iddq_bias:1; /* 0 */
755 #endif
756 } Bits_egphy_4port;
757 struct {
758 #ifdef PMC_LITTLE_ENDIAN
759 uint32_t iddq_bias:1; /* 0 */
760 uint32_t ext_pwr_down:4; /* 1-4 */
761 uint32_t force_dll_en:1; /* 5 */
762 uint32_t iddq_global_pwr:1; /* 6 */
763 uint32_t reserved0:25; /* 7-31 */
764 #else
765 uint32_t reserved0:25; /* 7-31 */
766 uint32_t iddq_global_pwr:1; /* 6 */
767 uint32_t force_dll_en:1; /* 5 */
768 uint32_t ext_pwr_down:4; /* 1-4 */
769 uint32_t iddq_bias:1; /* 0 */
770 #endif
771 } Bits_qgphy_cntl;
772 struct {
773 uint32_t ctl;
774 } Bits_vdsl_phy;
775 struct {
776 #ifdef PMC_LITTLE_ENDIAN
777 uint32_t alt_bfc_vector:12; /* 00-11 */
778 uint32_t reserved0:3;
779 uint32_t alt_bfc_en:1; /* 15 */
780 uint32_t reset_dly_cfg:2; /* 16-17 */
781 uint32_t reserved1:8;
782 uint32_t ext_mclk_en_reset:1; /* 26 */
783 uint32_t ext_mclk_en:1; /* 27 */
784 uint32_t por_reset_n_ctl:1; /* 28 */
785 uint32_t reset_n_ctl:1; /* 29 */
786 uint32_t reserved2:1;
787 uint32_t clken:1; /* 31 */
788 #else
789 uint32_t clken:1; /* 31 */
790 uint32_t reserved2:1;
791 uint32_t reset_n_ctl:1; /* 29 */
792 uint32_t por_reset_n_ctl:1; /* 28 */
793 uint32_t ext_mclk_en:1; /* 27 */
794 uint32_t ext_mclk_en_reset:1; /* 26 */
795 uint32_t reserved1:8;
796 uint32_t reset_dly_cfg:2; /* 16-17 */
797 uint32_t alt_bfc_en:1; /* 15 */
798 uint32_t reserved0:3;
799 uint32_t alt_bfc_vector:12; /* 00-11 */
800 #endif
801 } Bits_vdsl_mips;
802 uint32_t Reg32;
803 } BPCM_MISC_CONTROL;
804
805 typedef union {
806 struct {
807 uint32_t field;
808 } Bits_qgphy_status;
809 struct {
810 #ifdef PMC_LITTLE_ENDIAN
811 uint32_t alt_bfc_vector:12; /* 00-11 */
812 uint32_t reserved0:3;
813 uint32_t alt_bfc_en:1; /* 15 */
814 uint32_t reset_dly_cfg:2; /* 16-17 */
815 uint32_t reserved1:8;
816 uint32_t ext_mclk_en_reset:1; /* 26 */
817 uint32_t ext_mclk_en:1; /* 27 */
818 uint32_t por_reset_n_ctl:1; /* 28 */
819 uint32_t reset_n_ctl:1; /* 29 */
820 uint32_t reserved2:1;
821 uint32_t clken:1; /* 31 */
822 #else
823 uint32_t clken:1; /* 31 */
824 uint32_t reserved2:1;
825 uint32_t reset_n_ctl:1; /* 29 */
826 uint32_t por_reset_n_ctl:1; /* 28 */
827 uint32_t ext_mclk_en:1; /* 27 */
828 uint32_t ext_mclk_en_reset:1; /* 26 */
829 uint32_t reserved1:8;
830 uint32_t reset_dly_cfg:2; /* 16-17 */
831 uint32_t alt_bfc_en:1; /* 15 */
832 uint32_t reserved0:3;
833 uint32_t alt_bfc_vector:12; /* 00-11 */
834 #endif
835 } Bits_vdsl_mips; /* second PHY MIPS core */
836 uint32_t Reg32;
837 } BPCM_MISC_CONTROL2;
838
839 typedef union {
840 struct {
841 #ifdef PMC_LITTLE_ENDIAN
842 uint32_t gphy_iddq_bias:1; /* 00 */
843 uint32_t gphy_ext_pwr_down:1; /* 01 */
844 uint32_t gphy_force_dll_en:1; /* 02 */
845 uint32_t gphy_iddq_global_pwr:1; /* 03 */
846 uint32_t serdes_iddq:1; /* 04 */
847 uint32_t serdes_pwrdwn:1; /* 05 */
848 uint32_t reserved0:2; /* 07:06 */
849 uint32_t serdes_refclk_sel:3; /* 10:08 */
850 uint32_t reserved1:5; /* 15:11 */
851 uint32_t pll_clk125_250_sel:1; /* 16 */
852 uint32_t pll_mux_clk_250_sel:1; /* 17 */
853 uint32_t reserved2:14; /* 31:18 */
854 #else
855 uint32_t reserved2:14; /* 31:18 */
856 uint32_t pll_mux_clk_250_sel:1; /* 17 */
857 uint32_t pll_clk125_250_sel:1; /* 16 */
858 uint32_t reserved1:5; /* 15:11 */
859 uint32_t serdes_refclk_sel:3; /* 10:08 */
860 uint32_t reserved0:2; /* 07:06 */
861 uint32_t serdes_pwrdwn:1; /* 05 */
862 uint32_t serdes_iddq:1; /* 04 */
863 uint32_t gphy_iddq_global_pwr:1; /* 03 */
864 uint32_t gphy_force_dll_en:1; /* 02 */
865 uint32_t gphy_ext_pwr_down:1; /* 01 */
866 uint32_t gphy_iddq_bias:1; /* 00 */
867 #endif
868 } Bits;
869 uint32_t Reg32;
870 } BPCM_SGPHY_CNTL;
871
872 typedef union {
873 struct {
874 uint32_t field;
875 } Bits;
876 uint32_t Reg32;
877 } BPCM_SGPHY_STATUS;
878
879 typedef union {
880 struct {
881 #if IS_BCMCHIP(63138)
882 #ifdef PMC_LITTLE_ENDIAN
883 uint32_t core_pwr_ctrl:2; // 01:00 R/W
884 uint32_t reserved2:6; // 07:02 R/W
885 uint32_t pll_pwr_on:1; // 08:08 R/W
886 uint32_t pll_ldo_pwr_on:1; // 09:09 R/W
887 uint32_t pll_clamp_on:1; // 10:10 R/W
888 uint32_t reserved1:2; // 12:11 R/O
889 uint32_t cpu0_reset_n:1; // 13:13 R/W
890 uint32_t cpu1_reset_n:1; // 14:14 R/W
891 uint32_t neon_reset_n:1; // 15:15 R/W
892 uint32_t reserved0:12; // 27:16 R/O
893 uint32_t pwr_ctrl_sts:2; // 29:28 R/O
894 uint32_t power_down:2; // 31:30 R/O
895 #else
896 uint32_t power_down:2; // 31:30 R/O
897 uint32_t pwr_ctrl_sts:2; // 29:28 R/O
898 uint32_t reserved0:12; // 27:16 R/O
899 uint32_t neon_reset_n:1; // 15:15 R/W
900 uint32_t cpu1_reset_n:1; // 14:14 R/W
901 uint32_t cpu0_reset_n:1; // 13:13 R/W
902 uint32_t reserved1:2; // 12:11 R/O
903 uint32_t pll_clamp_on:1; // 10:10 R/W
904 uint32_t pll_ldo_pwr_on:1; // 09:09 R/W
905 uint32_t pll_pwr_on:1; // 08:08 R/W
906 uint32_t reserved2:6; // 07:02 R/W
907 uint32_t core_pwr_ctrl:2; // 01:00 R/W
908 #endif
909 #elif IS_BCMCHIP(63148)
910 #ifdef PMC_LITTLE_ENDIAN
911 uint32_t cpu0_reset_n:1; // 00:00 R/W
912 uint32_t power_down:1; // 01:01 R/W
913 uint32_t reserved:30; // 31:02 R/O
914 #else
915 uint32_t reserved:30; // 31:02 R/O
916 uint32_t power_down:1; // 01:01 R/W
917 uint32_t cpu0_reset_n:1; // 00:00 R/W
918 #endif
919 #elif IS_BCMCHIP(6858) || IS_BCMCHIP(63158) || IS_BCMCHIP(6846) || \
920 IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \
921 IS_BCMCHIP(6878) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || \
922 IS_BCMCHIP(6855) || IS_BCMCHIP(6756)
923 #ifdef PMC_LITTLE_ENDIAN
924 uint32_t cpu_reset_n:8; // 07:00 R/W
925 uint32_t c0l2_reset:1; // 08:08 R/W
926 uint32_t c1l2_reset:1; // 09:09 R/W
927 uint32_t reserved0:6; // 15:10 R/O
928 uint32_t cpu_bpcm_init_on:8; // 23:16 R/W
929 uint32_t c0l2_bpcm_init_on:1; // 24:24 R/W
930 uint32_t c1l2_bpcm_init_on:1; // 25:25 R/W
931 uint32_t ubus_sr:1; // 26:26 R/W
932 uint32_t cci_sr:1; // 27:27 R/W
933 uint32_t webcores_sr:1; // 28:28 R/W
934 uint32_t hw_done:1; // 29:29 R/O
935 uint32_t sw_done:1; // 30:30 R/W
936 uint32_t start:1; // 31:31 R/W
937 #else
938 uint32_t start:1; // 31:31 R/W
939 uint32_t sw_done:1; // 30:30 R/W
940 uint32_t hw_done:1; // 29:29 R/O
941 uint32_t webcores_sr:1; // 28:28 R/W
942 uint32_t cci_sr:1; // 27:27 R/W
943 uint32_t ubus_sr:1; // 26:26 R/W
944 uint32_t c1l2_bpcm_init_on:1; // 25:25 R/W
945 uint32_t c0l2_bpcm_init_on:1; // 24:24 R/W
946 uint32_t cpu_bpcm_init_on:8; // 23:16 R/W
947 uint32_t reserved0:6; // 15:10 R/O
948 uint32_t c1l2_reset:1; // 09:09 R/W
949 uint32_t c0l2_reset:1; // 08:08 R/W
950 uint32_t cpu_reset_n:8; // 07:00 R/W
951 #endif
952 #endif
953 } Bits;
954 uint32_t Reg32;
955 } ARM_CONTROL_REG;
956
957 typedef union {
958 struct {
959 #ifdef PMC_LITTLE_ENDIAN
960 uint32_t mem_pwr_ok:1; // 00:00 R/W
961 uint32_t mem_pwr_on:1; // 01:01 R/W
962 uint32_t mem_clamp_on:1; // 02:02 R/W
963 uint32_t reserved2:1; // 03:03 R/W
964 uint32_t mem_pwr_ok_status:1; // 04:04 R/O
965 uint32_t mem_pwr_on_status:1; // 05:05 R/O
966 uint32_t reserved1:2; // 07:06 R/W
967 uint32_t mem_pda:4; // 11:08 R/W only LS bit for CPU0/1, all four bits for neon_l2
968 uint32_t reserved0:3; // 14:12 R/W
969 uint32_t clamp_on:1; // 15:15 R/W
970 uint32_t pwr_ok:4; // 19:16 R/W ditto
971 uint32_t pwr_on:4; // 23:20 R/W ditto
972 uint32_t pwr_ok_status:4; // 27:24 R/O ditto
973 uint32_t pwr_on_status:4; // 31:28 R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
974 #else
975 uint32_t pwr_on_status:4; // 31:28 R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
976 uint32_t pwr_ok_status:4; // 27:24 R/O ditto
977 uint32_t pwr_on:4; // 23:20 R/W ditto
978 uint32_t pwr_ok:4; // 19:16 R/W ditto
979 uint32_t clamp_on:1; // 15:15 R/W
980 uint32_t reserved0:3; // 14:12 R/W
981 uint32_t mem_pda:4; // 11:08 R/W only LS bit for CPU0/1, all four bits for neon_l2
982 uint32_t reserved1:2; // 07:06 R/W
983 uint32_t mem_pwr_on_status:1; // 05:05 R/O
984 uint32_t mem_pwr_ok_status:1; // 04:04 R/O
985 uint32_t reserved2:1; // 03:03 R/W
986 uint32_t mem_clamp_on:1; // 02:02 R/W
987 uint32_t mem_pwr_on:1; // 01:01 R/W
988 uint32_t mem_pwr_ok:1; // 00:00 R/W
989 #endif
990 } Bits;
991 uint32_t Reg32;
992 } ARM_CPUx_PWR_CTRL_REG;
993
994 typedef union {
995 struct {
996 #ifdef PMC_LITTLE_ENDIAN
997 uint32_t resetb:1; // 00:00
998 uint32_t post_resetb:1; // 01:01
999 uint32_t pwrdwn:1; // 02:02
1000 uint32_t master_reset:1; // 03:03
1001 uint32_t pwrdwn_ldo:1; // 04:04
1002 uint32_t iso:1; // 05:05 // only used in afepll
1003 uint32_t reserved0:2; // 07:06
1004 uint32_t ldo_ctrl:6; // 13:08
1005 uint32_t reserved1:1; // 14:14
1006 uint32_t hold_ch_all:1; // 15:15
1007 uint32_t reserved2:4; // 16:19
1008 uint32_t byp_wait:1; // 20:20 // only used in b15pll
1009 uint32_t reserved3:11; // 21:31
1010 #else
1011 uint32_t reserved3:11; // 21:31
1012 uint32_t byp_wait:1; // 20:20 // only used in b15pll
1013 uint32_t reserved2:4; // 16:19
1014 uint32_t hold_ch_all:1; // 15:15
1015 uint32_t reserved1:1; // 14:14
1016 uint32_t ldo_ctrl:6; // 13:08
1017 uint32_t reserved0:2; // 07:06
1018 uint32_t iso:1; // 05:05 // only used in afepll
1019 uint32_t pwrdwn_ldo:1; // 04:04
1020 uint32_t master_reset:1; // 03:03
1021 uint32_t pwrdwn:1; // 02:02
1022 uint32_t post_resetb:1; // 01:01
1023 uint32_t resetb:1; // 00:00
1024 #endif
1025 } Bits;
1026 uint32_t Reg32;
1027 } PLL_CTRL_REG;
1028
1029 typedef union {
1030 struct {
1031 #ifdef PMC_LITTLE_ENDIAN
1032 uint32_t fb_offset:12; // 11:00
1033 uint32_t fb_phase_en:1; // 12:12
1034 uint32_t _8phase_en:1; // 13:13
1035 uint32_t sr:18; // 31:14
1036 #else
1037 uint32_t sr:18; // 31:14
1038 uint32_t _8phase_en:1; // 13:13
1039 uint32_t fb_phase_en:1; // 12:12
1040 uint32_t fb_offset:12; // 11:00
1041 #endif
1042 } Bits;
1043 uint32_t Reg32;
1044 } PLL_PHASE_REG;
1045
1046 #if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
1047 typedef union {
1048 struct {
1049 #ifdef PMC_LITTLE_ENDIAN
1050 uint32_t ndiv_int:10; // 09:00
1051 uint32_t reserved0:2; // 11:10
1052 uint32_t fref_eff_info:8; // 19:12
1053 uint32_t auto_cnfg_dsbl:8; // 27:20
1054 uint32_t reserved1:3; // 30:28
1055 uint32_t ndiv_override:1; // 31
1056 #else
1057 uint32_t ndiv_override:1; // 31
1058 uint32_t reserved1:3; // 30:28
1059 uint32_t auto_cnfg_dsbl:8; // 27:20
1060 uint32_t fref_eff_info:8; // 19:12
1061 uint32_t reserved0:2; // 11:10
1062 uint32_t ndiv_int:10; // 09:00
1063 #endif
1064 } Bits;
1065 uint32_t Reg32;
1066 } PLL_NDIV_REG;
1067
1068 typedef union {
1069 struct {
1070 #ifdef PMC_LITTLE_ENDIAN
1071 uint32_t pdiv:4; // 03:00
1072 uint32_t ndiv_frac:24; // 27:04
1073 uint32_t reserved0:3; // 30:28
1074 uint32_t ndiv_pdiv_override:1; // 31:31
1075 #else
1076 uint32_t ndiv_pdiv_override:1; // 31:31
1077 uint32_t reserved0:3; // 30:28
1078 uint32_t ndiv_frac:24; // 27:04
1079 uint32_t pdiv:4; // 03:00
1080 #endif
1081 } Bits;
1082 uint32_t Reg32;
1083 } PLL_PDIV_REG;
1084
1085 typedef union {
1086 struct {
1087 #ifdef PMC_LITTLE_ENDIAN
1088 uint32_t mdiv0:9; // 08:00
1089 uint32_t enableb_ch0:1; // 09:09
1090 uint32_t hold_ch0:1; // 10:10
1091 uint32_t mdel0:1; // 11:11
1092 uint32_t reserved0:3; // 14:12
1093 uint32_t mdiv_override0:1; // 15:15
1094 uint32_t mdiv1:9; // 24:16
1095 uint32_t enableb_ch1:1; // 25:25
1096 uint32_t hold_ch1:1; // 26:26
1097 uint32_t mdel1:1; // 27:27
1098 uint32_t reserved1:3; // 30:28
1099 uint32_t mdiv_override1:1; // 31:31
1100 #else
1101 uint32_t mdiv_override1:1; // 31:31
1102 uint32_t reserved1:3; // 30:28
1103 uint32_t mdel1:1; // 27:27
1104 uint32_t hold_ch1:1; // 26:26
1105 uint32_t enableb_ch1:1; // 25:25
1106 uint32_t mdiv1:9; // 24:16
1107 uint32_t mdiv_override0:1; // 15:15
1108 uint32_t reserved0:3; // 14:12
1109 uint32_t mdel0:1; // 11:11
1110 uint32_t hold_ch0:1; // 10:10
1111 uint32_t enableb_ch0:1; // 09:09
1112 uint32_t mdiv0:9; // 08:00
1113 #endif
1114 } Bits;
1115 uint32_t Reg32;
1116 } PLL_CHCFG_REG;
1117
1118 typedef union {
1119 struct {
1120 #ifdef PMC_LITTLE_ENDIAN
1121 uint32_t reserved0:8; // 07:00
1122 uint32_t stat_select:3; // 10:08
1123 uint32_t pq_mode:1; // 11:11
1124 uint32_t stat_mode:2; // 13:12
1125 uint32_t stat_reset:1; // 14:14
1126 uint32_t stat_update:1; // 15:15
1127 uint32_t ssc_step:16; // 31:16
1128 #else
1129 uint32_t ssc_step:16; // 31:16
1130 uint32_t stat_update:1; // 15:15
1131 uint32_t stat_reset:1; // 14:14
1132 uint32_t stat_mode:2; // 13:12
1133 uint32_t pq_mode:1; // 11:11
1134 uint32_t stat_select:3; // 10:08
1135 uint32_t reserved0:8; // 07:00
1136 #endif
1137 } Bits;
1138 uint32_t Reg32;
1139 } PLL_LOOP0_REG;
1140
1141 #else
1142 typedef union {
1143 struct {
1144 #ifdef PMC_LITTLE_ENDIAN
1145 uint32_t ndiv_int:10; // 09:00
1146 uint32_t ndiv_frac:20; // 29:10
1147 uint32_t reserved0:1; // 30
1148 uint32_t ndiv_override:1; // 31
1149 #else
1150 uint32_t ndiv_override:1; // 31
1151 uint32_t reserved0:1; // 30
1152 uint32_t ndiv_frac:20; // 29:10
1153 uint32_t ndiv_int:10; // 09:00
1154 #endif
1155 } Bits;
1156 uint32_t Reg32;
1157 } PLL_NDIV_REG;
1158
1159 typedef union {
1160 struct {
1161 #ifdef PMC_LITTLE_ENDIAN
1162 uint32_t pdiv:3; // 02:00
1163 uint32_t reserved0:28; // 30:03
1164 uint32_t ndiv_pdiv_override:1; // 31:31
1165 #else
1166 uint32_t ndiv_pdiv_override:1; // 31:31
1167 uint32_t reserved0:28; // 30:03
1168 uint32_t pdiv:3; // 02:00
1169 #endif
1170 } Bits;
1171 uint32_t Reg32;
1172 } PLL_PDIV_REG;
1173
1174 typedef union {
1175 struct {
1176 #ifdef PMC_LITTLE_ENDIAN
1177 uint32_t mdiv0:8; // 07:00
1178 uint32_t enableb_ch0:1; // 08:08
1179 uint32_t hold_ch0:1; // 09:09
1180 uint32_t load_en_ch0:1; // 10:10
1181 uint32_t mdel0:1; // 11:11
1182 uint32_t reserved0:3; // 14:12
1183 uint32_t mdiv_override0:1; // 15:15
1184 uint32_t mdiv1:8; // 23:16
1185 uint32_t enableb_ch1:1; // 24:24
1186 uint32_t hold_ch1:1; // 25:25
1187 uint32_t load_en_ch1:1; // 26:26
1188 uint32_t mdel1:1; // 27:27
1189 uint32_t reserved1:3; // 30:28
1190 uint32_t mdiv_override1:1; // 31:31
1191 #else
1192 uint32_t mdiv_override1:1; // 31:31
1193 uint32_t reserved1:3; // 30:28
1194 uint32_t mdel1:1; // 27:27
1195 uint32_t load_en_ch1:1; // 26:26
1196 uint32_t hold_ch1:1; // 25:25
1197 uint32_t enableb_ch1:1; // 24:24
1198 uint32_t mdiv1:8; // 23:16
1199 uint32_t mdiv_override0:1; // 15:15
1200 uint32_t reserved0:3; // 14:12
1201 uint32_t mdel0:1; // 11:11
1202 uint32_t load_en_ch0:1; // 10:10
1203 uint32_t hold_ch0:1; // 09:09
1204 uint32_t enableb_ch0:1; // 08:08
1205 uint32_t mdiv0:8; // 07:00
1206 #endif
1207 } Bits;
1208 uint32_t Reg32;
1209 } PLL_CHCFG_REG;
1210
1211 typedef union {
1212 struct {
1213 #ifdef PMC_LITTLE_ENDIAN
1214 uint32_t reserved0:4; // 03:00
1215 uint32_t ka:3; // 06:04
1216 uint32_t reserved1:1; // 07:07
1217 uint32_t ki:3; // 10:08
1218 uint32_t reserved2:1; // 11:11
1219 uint32_t kp:4; // 15:12
1220 uint32_t ssc_step:16; // 31:16
1221 #else
1222 uint32_t ssc_step:16; // 31:16
1223 uint32_t kp:4; // 15:12
1224 uint32_t reserved2:1; // 11:11
1225 uint32_t ki:3; // 10:08
1226 uint32_t reserved1:1; // 07:07
1227 uint32_t ka:3; // 06:04
1228 uint32_t reserved0:4; // 03:00
1229 #endif
1230 } Bits;
1231 uint32_t Reg32;
1232 } PLL_LOOP0_REG;
1233
1234 #endif
1235
1236 typedef union {
1237 struct {
1238 #ifdef PMC_LITTLE_ENDIAN
1239 uint32_t ssc_limit:22; // 21:00
1240 uint32_t reserved0:2; // 23:22
1241 uint32_t ssc_clkdiv:4; // 27:24
1242 uint32_t ssc_status:1; // 28:28
1243 uint32_t reserved1:2; // 30:29
1244 uint32_t ssc_mode:1; // 31:31
1245 #else
1246 uint32_t ssc_mode:1; // 31:31
1247 uint32_t reserved1:2; // 30:29
1248 uint32_t ssc_status:1; // 28:28
1249 uint32_t ssc_clkdiv:4; // 27:24
1250 uint32_t reserved0:2; // 23:22
1251 uint32_t ssc_limit:22; // 21:00
1252 #endif
1253 } Bits;
1254 uint32_t Reg32;
1255 } PLL_LOOP1_REG;
1256
1257 typedef union {
1258 struct {
1259 #ifdef PMC_LITTLE_ENDIAN
1260 uint32_t fdco_ctrl_bypass:16; // 15:00
1261 uint32_t fdco_bypass_en:1; // 16:16
1262 uint32_t fdco_dac_sel:1; // 17:17
1263 uint32_t state_reset:1; // 18:18
1264 uint32_t state_mode:2; // 20:19
1265 uint32_t state_sel:3; // 23:21
1266 uint32_t state_update:1; // 24:24
1267 uint32_t dco_en:1; // 25:25
1268 uint32_t dco_div2_div4:1; // 26:26
1269 uint32_t dco_bias_boost:1; // 27:27
1270 uint32_t bb_en:1; // 28:28
1271 uint32_t t2d_offset:3; // 31:29
1272 #else
1273 uint32_t t2d_offset:3; // 31:29
1274 uint32_t bb_en:1; // 28:28
1275 uint32_t dco_bias_boost:1; // 27:27
1276 uint32_t dco_div2_div4:1; // 26:26
1277 uint32_t dco_en:1; // 25:25
1278 uint32_t state_update:1; // 24:24
1279 uint32_t state_sel:3; // 23:21
1280 uint32_t state_mode:2; // 20:19
1281 uint32_t state_reset:1; // 18:18
1282 uint32_t fdco_dac_sel:1; // 17:17
1283 uint32_t fdco_bypass_en:1; // 16:16
1284 uint32_t fdco_ctrl_bypass:16; // 15:00
1285 #endif
1286 } Bits;
1287 uint32_t Reg32;
1288 } PLL_CFG0_REG;
1289
1290 typedef union {
1291 struct {
1292 #ifdef PMC_LITTLE_ENDIAN
1293 uint32_t t2d_offset_msb:1; // 00:00
1294 uint32_t t2d_clk_enable:1; // 01:01
1295 uint32_t t2d_clk_sel:1; // 02:02
1296 uint32_t kpp:4; // 06:03
1297 uint32_t pwm_ctrl:2; // 08:07
1298 uint32_t port_reset_mode:2; // 10:09
1299 uint32_t byp2_en:1; // 11:11
1300 uint32_t byp1_en:1; // 12:12
1301 uint32_t ref_diff_sel:1; // 13:13
1302 uint32_t ki_startlow:1; // 14:14
1303 uint32_t en_500ohm:1; // 15:15
1304 uint32_t refd2c_bias:3; // 18:16
1305 uint32_t post_div2_div3:1; // 19:19
1306 uint32_t ki_boost:1; // 20:20
1307 uint32_t reserved0:11; // 31:21
1308 #else
1309 uint32_t reserved0:11; // 31:21
1310 uint32_t ki_boost:1; // 20:20
1311 uint32_t post_div2_div3:1; // 19:19
1312 uint32_t refd2c_bias:3; // 18:16
1313 uint32_t en_500ohm:1; // 15:15
1314 uint32_t ki_startlow:1; // 14:14
1315 uint32_t ref_diff_sel:1; // 13:13
1316 uint32_t byp1_en:1; // 12:12
1317 uint32_t byp2_en:1; // 11:11
1318 uint32_t port_reset_mode:2; // 10:09
1319 uint32_t pwm_ctrl:2; // 08:07
1320 uint32_t kpp:4; // 06:03
1321 uint32_t t2d_clk_sel:1; // 02:02
1322 uint32_t t2d_clk_enable:1; // 01:01
1323 uint32_t t2d_offset_msb:1; // 00:00
1324 #endif
1325 } Bits;
1326 uint32_t Reg32;
1327 } PLL_CFG1_REG;
1328
1329 typedef union {
1330 struct {
1331 #ifdef PMC_LITTLE_ENDIAN
1332 uint32_t en_cml:3; // 02:00
1333 uint32_t tri_en:1; // 03:03
1334 uint32_t test_sel:3; // 06:04
1335 uint32_t test_en:1; // 07:07
1336 uint32_t reserved0:24;
1337 #else
1338 uint32_t reserved0:24;
1339 uint32_t test_en:1; // 07:07
1340 uint32_t test_sel:3; // 06:04
1341 uint32_t tri_en:1; // 03:03
1342 uint32_t en_cml:3; // 02:00
1343 #endif
1344 } Bits;
1345 uint32_t Reg32;
1346 } PLL_OCTRL_REG;
1347
1348 typedef union {
1349 struct {
1350 #ifdef PMC_LITTLE_ENDIAN
1351 uint32_t out:12; // 11:00
1352 uint32_t reserved:19; // 30:12
1353 uint32_t lock:1; // 31:31
1354 #else
1355 uint32_t lock:1; // 31:31
1356 uint32_t reserved:19; // 30:12
1357 uint32_t out:12; // 11:00
1358 #endif
1359 } Bits;
1360 uint32_t Reg32;
1361 } PLL_STAT_REG;
1362
1363 #if IS_BCMCHIP(6858) || IS_BCMCHIP(63158) || IS_BCMCHIP(6846) || \
1364 IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \
1365 IS_BCMCHIP(6878) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756)
1366 typedef union {
1367 struct {
1368 #ifdef PMC_LITTLE_ENDIAN
1369 uint32_t ndiv_int:10; // 09:00
1370 uint32_t reserved0:2; // 11:10
1371 uint32_t ndiv_frac:20; // 31:12
1372 #else
1373 uint32_t ndiv_frac:20; // 31:12
1374 uint32_t reserved0:2; // 11:10
1375 uint32_t ndiv_int:10; // 09:00
1376 #endif
1377 } Bits;
1378 uint32_t Reg32;
1379 } PLL_DECNDIV_REG;
1380
1381 typedef union {
1382 struct {
1383 #ifdef PMC_LITTLE_ENDIAN
1384 uint32_t pdiv:4; // 03:00
1385 uint32_t reserved0:12; // 15:04
1386 uint32_t mdiv0:8; // 23:16
1387 uint32_t mdiv1:8; // 31:24
1388 #else
1389 uint32_t mdiv1:8; // 31:24
1390 uint32_t mdiv0:8; // 23:16
1391 uint32_t reserved0:12; // 15:04
1392 uint32_t pdiv:4; // 03:00
1393 #endif
1394 } Bits;
1395 uint32_t Reg32;
1396 } PLL_DECPDIV_REG;
1397
1398 typedef union {
1399 struct {
1400 #ifdef PMC_LITTLE_ENDIAN
1401 uint32_t mdiv2:8; // 07:00
1402 uint32_t mdiv3:8; // 15:08
1403 uint32_t mdiv4:8; // 23:16
1404 uint32_t mdiv5:8; // 31:24
1405 #else
1406 uint32_t mdiv5:8; // 31:24
1407 uint32_t mdiv4:8; // 23:16
1408 uint32_t mdiv3:8; // 15:08
1409 uint32_t mdiv2:8; // 07:00
1410 #endif
1411 } Bits;
1412 uint32_t Reg32;
1413 } PLL_DECCH25_REG;
1414 #elif IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
1415 typedef union {
1416 struct {
1417 #ifdef PMC_LITTLE_ENDIAN
1418 uint32_t ndiv_int:10; // 9:0
1419 uint32_t ndiv_frac:22; // 31:10
1420
1421 #else
1422 uint32_t ndiv_frac:22; // 31:10
1423 uint32_t ndiv_int:10; // 9:0
1424 #endif
1425 } Bits;
1426 uint32_t Reg32;
1427 } PLL_DECNDIV_REG;
1428
1429 typedef union {
1430 struct {
1431 #ifdef PMC_LITTLE_ENDIAN
1432 uint32_t pdiv:4; // 03:00
1433 uint32_t mdiv5:9; // 12:04
1434 uint32_t mdiv0:9; // 21:13
1435 uint32_t mdiv1:9; // 30:22
1436 uint32_t reserved0:1; // 31:31
1437 #else
1438 uint32_t reserved0:1; // 31:31
1439 uint32_t mdiv1:9; // 30:22
1440 uint32_t mdiv0:9; // 21:13
1441 uint32_t mdiv5:9; // 12:04
1442 uint32_t pdiv:4; // 03:00
1443 #endif
1444 } Bits;
1445 uint32_t Reg32;
1446 } PLL_DECPDIV_REG;
1447
1448 typedef union {
1449 struct {
1450 #ifdef PMC_LITTLE_ENDIAN
1451 uint32_t mdiv2:9; // 08:00
1452 uint32_t mdiv3:9; // 17:09
1453 uint32_t mdiv4:9; // 26:18
1454 uint32_t reserved0:5; // 31:27
1455 #else
1456 uint32_t reserved0:5; // 31:27
1457 uint32_t mdiv4:9; // 26:18
1458 uint32_t mdiv3:9; // 17:09
1459 uint32_t mdiv2:9; // 08:00
1460 #endif
1461 } Bits;
1462 uint32_t Reg32;
1463 } PLL_DECCH25_REG;
1464 #endif
1465
1466 typedef union {
1467 struct {
1468 #ifdef PMC_LITTLE_ENDIAN
1469 uint32_t manual_clk_en:1;
1470 uint32_t manual_reset_ctl:1;
1471 uint32_t freq_scale_used:1; // R/O
1472 uint32_t dpg_capable:1; // R/O
1473 uint32_t manual_mem_pwr:2;
1474 uint32_t manual_iso_ctl:1;
1475 uint32_t manual_ctl:1;
1476 uint32_t dpg_ctl_en:1;
1477 uint32_t pwr_dn_req:1;
1478 uint32_t pwr_up_req:1;
1479 uint32_t mem_pwr_ctl_en:1;
1480 uint32_t blk_reset_assert:1;
1481 uint32_t mem_stby:1;
1482 uint32_t reserved:5;
1483 uint32_t pwr_cntl_state:5;
1484 uint32_t freq_scalar_dyn_sel:1; // R/O
1485 uint32_t pwr_off_state:1; // R/O
1486 uint32_t pwr_on_state:1; // R/O
1487 uint32_t pwr_good:1; // R/O
1488 uint32_t dpg_pwr_state:1; // R/O
1489 uint32_t mem_pwr_state:1; // R/O
1490 uint32_t iso_state:1; // R/O
1491 uint32_t reset_state:1; // R/O
1492 #else
1493 uint32_t reset_state:1; // R/O 31:31
1494 uint32_t iso_state:1; // R/O
1495 uint32_t mem_pwr_state:1; // R/O
1496 uint32_t dpg_pwr_state:1; // R/O
1497 uint32_t pwr_good:1; // R/O
1498 uint32_t pwr_on_state:1; // R/O
1499 uint32_t pwr_off_state:1; // R/O
1500 uint32_t freq_scalar_dyn_sel:1; // R/O
1501 uint32_t pwr_cntl_state:5;
1502 uint32_t reserved:5;
1503 uint32_t mem_stby:1;
1504 uint32_t blk_reset_assert:1; // 12:12
1505 uint32_t mem_pwr_ctl_en:1;
1506 uint32_t pwr_up_req:1;
1507 uint32_t pwr_dn_req:1;
1508 uint32_t dpg_ctl_en:1;
1509 uint32_t manual_ctl:1;
1510 uint32_t manual_iso_ctl:1;
1511 uint32_t manual_mem_pwr:2;
1512 uint32_t dpg_capable:1; // R/O
1513 uint32_t freq_scale_used:1; // R/O
1514 uint32_t manual_reset_ctl:1;
1515 uint32_t manual_clk_en:1;
1516 #endif
1517 } Bits;
1518 uint32_t Reg32;
1519 } BPCM_PWR_ZONE_N_CONTROL;
1520
1521 typedef union {
1522 struct {
1523 #ifdef PMC_LITTLE_ENDIAN
1524 uint32_t pwr_ok_delay_sel:3;
1525 uint32_t pwk_ok_thresh:2;
1526 uint32_t reserved:3;
1527 uint32_t iso_on_delay:4;
1528 uint32_t iso_off_delay:4;
1529 uint32_t clock_on_delay:4;
1530 uint32_t clock_off_delay:4;
1531 uint32_t reset_on_delay:4;
1532 uint32_t reset_off_delay:4;
1533 #else
1534 uint32_t reset_off_delay:4; // 31:28
1535 uint32_t reset_on_delay:4;
1536 uint32_t clock_off_delay:4;
1537 uint32_t clock_on_delay:4;
1538 uint32_t iso_off_delay:4;
1539 uint32_t iso_on_delay:4;
1540 uint32_t reserved:3;
1541 uint32_t pwk_ok_thresh:2;
1542 uint32_t pwr_ok_delay_sel:3;
1543 #endif
1544 } Bits;
1545 uint32_t Reg32;
1546 } BPCM_PWR_ZONE_N_CONFIG1;
1547
1548 typedef union {
1549 struct {
1550 #ifdef PMC_LITTLE_ENDIAN
1551 uint32_t delay_prescale_sel:3;
1552 uint32_t slew_prescale_sel:3;
1553 uint32_t reserved:6;
1554 uint32_t dpgn_on_delay:4;
1555 uint32_t dpg1_on_delay:4;
1556 uint32_t dpg_off_delay:4;
1557 uint32_t mem_on_delay:4;
1558 uint32_t mem_off_delay:4;
1559 #else
1560 uint32_t mem_off_delay:4; // 31:28
1561 uint32_t mem_on_delay:4;
1562 uint32_t dpg_off_delay:4;
1563 uint32_t dpg1_on_delay:4;
1564 uint32_t dpgn_on_delay:4;
1565 uint32_t reserved:6;
1566 uint32_t slew_prescale_sel:3;
1567 uint32_t delay_prescale_sel:3;
1568 #endif
1569 } Bits;
1570 uint32_t Reg32;
1571 } BPCM_PWR_ZONE_N_CONFIG2;
1572
1573 typedef union {
1574 struct {
1575 #ifdef PMC_LITTLE_ENDIAN
1576 uint32_t fs_bypass_en:1;
1577 uint32_t gear_sel:1;
1578 uint32_t use_dyn_gear_sel:1;
1579 uint32_t reserved2:1;
1580 uint32_t low_gear_div:3;
1581 uint32_t high_gear_div:3;
1582 uint32_t reserved:22;
1583 #else
1584 uint32_t reserved:22; // 31:10
1585 uint32_t high_gear_div:3;
1586 uint32_t low_gear_div:3;
1587 uint32_t reserved2:1;
1588 uint32_t use_dyn_gear_sel:1;
1589 uint32_t gear_sel:1;
1590 uint32_t fs_bypass_en:1;
1591 #endif
1592 } Bits;
1593 uint32_t Reg32;
1594 } BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
1595
1596 typedef struct {
1597 BPCM_PWR_ZONE_N_CONTROL control;
1598 BPCM_PWR_ZONE_N_CONFIG1 config1;
1599 BPCM_PWR_ZONE_N_CONFIG2 config2;
1600 #if IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || IS_BCMCHIP(63146)\
1601 || IS_BCMCHIP(4912) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756)
1602 uint32_t reserved0;
1603 uint32_t timer_control;
1604 uint32_t timer_status;
1605 uint32_t reserved1[2];
1606 #else
1607 BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
1608 #endif
1609 #if IS_BCMCHIP(6846) || IS_BCMCHIP(6856)
1610 uint32_t reserved[4];
1611 #endif
1612 } BPCM_ZONE;
1613
1614 #define BPCMZoneOffset(reg) offsetof(BPCM_ZONE,reg)
1615 #define BPCMZoneRegOffset(reg) (BPCMZoneOffset(reg) >> 2)
1616
1617 typedef union {
1618 struct {
1619 #ifdef PMC_LITTLE_ENDIAN
1620 uint32_t pmb_Addr:8;
1621 uint32_t hw_rev:8;
1622 uint32_t module_id:16;
1623 #else
1624 uint32_t module_id:16;
1625 uint32_t hw_rev:8;
1626 uint32_t pmb_Addr:8;
1627 #endif
1628 } Bits;
1629 uint32_t Reg32;
1630 } BPCM_UBUS_ID_REG;
1631
1632 typedef union {
1633 struct {
1634 #ifdef PMC_LITTLE_ENDIAN
1635 uint32_t num_zones:8;
1636 uint32_t sr_reg_bits:8;
1637 uint32_t pllType:2;
1638 uint32_t reserved0:1;
1639 uint32_t ubus:1;
1640 uint32_t reserved1:12;
1641 #else
1642 uint32_t reserved1:12;
1643 uint32_t ubus:1;
1644 uint32_t reserved0:1;
1645 uint32_t pllType:2;
1646 uint32_t sr_reg_bits:8;
1647 uint32_t num_zones:8;
1648 #endif
1649 } Bits;
1650 uint32_t Reg32;
1651 } BPCM_UBUS_CAPABILITES_REG;
1652
1653 typedef union {
1654 struct {
1655 #ifdef PMC_LITTLE_ENDIAN
1656 uint32_t ctrl_eswap:4;
1657 uint32_t reserved0:4;
1658 uint32_t ctrl_cd:4;
1659 uint32_t reserved1:4;
1660 uint32_t ctrl_seclev:8;
1661 uint32_t reqout_seclev:8;
1662 #else
1663 uint32_t reqout_seclev:8;
1664 uint32_t ctrl_seclev:8;
1665 uint32_t reserved1:4;
1666 uint32_t ctrl_cd:4;
1667 uint32_t reserved0:4;
1668 uint32_t ctrl_eswap:4;
1669 #endif
1670 } Bits;
1671 uint32_t Reg32;
1672 } BPCM_UBUS_CTRL_REG;
1673
1674 typedef union {
1675 struct {
1676 #ifdef PMC_LITTLE_ENDIAN
1677 uint64_t addr_in:24;
1678 uint64_t addr_out:24;
1679 uint64_t pid:8;
1680 uint64_t size:5;
1681 uint64_t cmddta:1;
1682 uint64_t en:2;
1683 #else
1684 uint64_t en:2;
1685 uint64_t cmddta:1;
1686 uint64_t size:5;
1687 uint64_t pid:8;
1688 uint64_t addr_out:24;
1689 uint64_t addr_in:24;
1690 #endif
1691 } Bits;
1692 struct {
1693 uint32_t word0;
1694 uint32_t word1;
1695 } Regs32;
1696 uint64_t Reg64;
1697 } BPCM_UBUS_CFG_REG;
1698
1699 #if IS_BCMCHIP(63178)
1700 typedef union {
1701 struct {
1702 #ifdef PMC_LITTLE_ENDIAN
1703 uint32_t counter:8;
1704 uint32_t reserved2:7;
1705 uint32_t enable:1;
1706 uint32_t reserved1:16;
1707 #else
1708 uint32_t reserved1:16;
1709 uint32_t enable:1;
1710 uint32_t reserved2:7;
1711 uint32_t counter:8;
1712 #endif
1713 } Bits;
1714 uint32_t Reg32;
1715 } BPCM_CLKRST_VREG_CONTROL;
1716 #endif
1717 #if IS_BCMCHIP(63146)
1718 typedef union {
1719 struct {
1720 #ifdef PMC_LITTLE_ENDIAN
1721 uint32_t ubus_soft_reset:1;
1722 uint32_t alt_ubus_clk_sel:1;
1723 uint32_t observe_clk_sw_init:1;
1724 uint32_t alt_emmc_clk_sel:1;
1725 uint32_t reserved:5;
1726 uint32_t enable:1;
1727 uint32_t counter:8;
1728 uint32_t reserved2:14;
1729 #else
1730 uint32_t reserved2:14;
1731 uint32_t counter:8;
1732 uint32_t enable:1;
1733 uint32_t reserved:5;
1734 uint32_t alt_emmc_clk_sel:1;
1735 uint32_t observe_clk_sw_init:1;
1736 uint32_t alt_ubus_clk_sel:1;
1737 uint32_t ubus_soft_reset:1;
1738
1739 #endif
1740 } Bits;
1741 uint32_t Reg32;
1742 } BPCM_CLKRST_VREG_CONTROL;
1743 #endif
1744
1745
1746 #if IS_BCMCHIP(47622) || IS_BCMCHIP(6756)
1747 typedef union {
1748 struct {
1749 #ifdef PMC_LITTLE_ENDIAN
1750 uint32_t ubus_soft_rst:1;
1751 uint32_t alt_ubus_clk_sel:1;
1752 uint32_t obsv_clk_swinit:1;
1753 uint32_t reserved0:17;
1754 uint32_t wl0_rf_enable:1;
1755 uint32_t wl1_rf_enable:1;
1756 uint32_t reserved1:10;
1757 #else
1758 uint32_t reserved1:10;
1759 uint32_t wl1_rf_enable:1;
1760 uint32_t wl0_rf_enable:1;
1761 uint32_t reserved0:17;
1762 uint32_t obsv_clk_swinit:1;
1763 uint32_t alt_ubus_clk_sel:1;
1764 uint32_t ubus_soft_rst:1;
1765 #endif
1766 } Bits;
1767 uint32_t Reg32;
1768 } BPCM_CLKRST_CONTROL;
1769 #endif
1770
1771 // There is a 20-bit address used to access any given BPCM register. The upper 8-bits
1772 // is the device address and the lower 12-bits is used to represent the BPCM register
1773 // set for that device. 32-bit registers are allocated on 4-byte boundaries
1774 // (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
1775 // Thus, to get the actual address of any given register within the device's address
1776 // space, I'll use the "C" offsetof macro and divide the result by 4
1777 // e.g.:
1778 // int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL); // yields the byte offset of the target register
1779 // int regAddress = regOffset/4; // yields the 32-bit word offset of the target register
1780 // The ReadBPCMReg and WriteBPCMReg functions will always take a device address
1781 // (address of the BPCM device) and register offset (like regOffset above). The offset
1782 // will be divided by 4 and used as the lower 12-bits of the actual target address, while the
1783 // device address will serve as the upper 8-bits of the actual address.
1784 typedef struct {
1785 #if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || \
1786 IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || IS_BCMCHIP(63146) || \
1787 IS_BCMCHIP(4912) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756)
1788 // PMB-slave:
1789 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
1790 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
1791 uint32_t reserved0[2]; // offset 0x08, PMB reg index 2/3
1792 // BPCM
1793 uint32_t control; // offset 0x10, PMB reg index 4
1794 BPCM_SR_CONTROL sr_control; // offset 0x14, PMB reg index 5
1795 uint32_t reserved1[2]; // offset 0x18, PMB reg index 6/7
1796 // Client-specific registers
1797 uint32_t client_specific[24]; // offset 0x20, PMB reg index 8..31
1798 // Zones
1799 BPCM_ZONE zones[]; // offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
1800 #else
1801 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
1802 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
1803 uint32_t control; // offset = 0x08, actual offset = 2
1804 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
1805 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
1806 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
1807 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
1808 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
1809 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
1810 BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9
1811 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
1812
1813 #if IS_BCMCHIP(63158)
1814 uint32_t reserved; // offset = 0x2c, actual offset = 11
1815 BPCM_GLOBAL_CNTL_0 global_control; // offset = 0x30, actual offset = 12
1816 BPCM_GLOBAL_CNTL_1 global_control_1; // offset = 0x34, actual offset = 13
1817 BPCM_GLOBAL_CNTL_2 global_control_2; // offset = 0x38, actual offset = 14
1818 uint32_t global_status; // offset = 0x3c, actual offset = 15
1819 #else
1820 BPCM_GLOBAL_CNTL global_control; // offset = 0x2c, actual offset = 11
1821 BPCM_MISC_CONTROL misc_control; // offset = 0x30, actual offset = 12
1822 BPCM_MISC_CONTROL2 misc_control2; // offset = 0x34, actual offset = 13
1823 BPCM_SGPHY_CNTL sgphy_cntl; // offset = 0x38, actual offset = 14
1824 BPCM_SGPHY_STATUS sgphy_status; // offset = 0x3c, actual offset = 15
1825 #endif
1826 BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
1827 #endif
1828 } BPCM_REGS; // total offset space = 4096
1829
1830 #define BPCM_OFFSET(reg) (offsetof(BPCM_REGS,reg)>>2)
1831
1832 #if !IS_BCMCHIP(6878) && !IS_BCMCHIP(6846) && !IS_BCMCHIP(6856) && !IS_BCMCHIP(6855)
1833 typedef struct {
1834 #if !IS_BCMCHIP(63178) && !IS_BCMCHIP(63146)
1835 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
1836 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
1837 uint32_t control; // offset = 0x08, actual offset = 2
1838 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
1839 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
1840 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
1841 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
1842 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
1843 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
1844 BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9
1845 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
1846 BPCM_GLOBAL_CNTL global_control; // offset = 0x2c, actual offset = 11
1847 BPCM_MISC_CONTROL misc_control; // offset = 0x30, actual offset = 12
1848 BPCM_MISC_CONTROL2 misc_control2; // offset = 0x34, actual offset = 13
1849 uint32_t rvrsd[2];
1850 BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
1851 #else
1852 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
1853 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
1854 uint32_t reserved0[2]; // offset = 0x08, actual offset = 2
1855 uint32_t cfg_control; // offset = 0x10, actual offset = 4
1856 BPCM_SR_CONTROL sr_control; // offset = 0x14, actual offset = 5
1857 #if IS_BCMCHIP(63146)
1858 uint32_t reserved1[2]; // offset = 0x18, actual offset = 6
1859 uint32_t vdsl_arm_sr; // offset = 0x20, actual offset = 8
1860 BPCM_VDSL_ARM_RST_CTL vdsl_arm_rst_control; // offset = 0x24, actual offset = 9
1861 uint32_t reserved2[2]; // offset = 0x28, actual offset = 10
1862 uint32_t vdsl_afe_config0; // offset = 0x30, actual offset = 12
1863 uint32_t vdsl_afe_config1; // offset = 0x34, actual offset = 13
1864 uint32_t reserved3[18]; // offset = 0x38, actual offset = 14
1865 #else
1866 uint32_t reserved1[10]; // offset = 0x18, actual offset = 6
1867 BPCM_MISC_CONTROL misc_control; // offset = 0x40, actual offset = 16
1868 uint32_t vdsl_phy_ctl; // offset = 0x44, actual offset = 17
1869 uint32_t vdsl_afe_ctl; // offset = 0x48, actual offset = 18
1870 uint32_t reserved2[13]; // offset = 0x4c, actual offset = 19
1871 #endif
1872 BPCM_ZONE zones; // offset = 0x80, actual offset = 32
1873 #endif
1874 } BPCM_VDSL_REGS; // total offset space = 4096
1875
1876 #define BPCMVDSLOffset(reg) offsetof(BPCM_VDSL_REGS,reg)
1877 #define BPCMVDSLRegOffset(reg) (BPCMVDSLOffset(reg) >> 2)
1878
1879 #endif
1880
1881 #define BPCMOffset(reg) offsetof(BPCM_REGS,reg)
1882 #define BPCMRegOffset(reg) (BPCMOffset(reg) >> 2)
1883
1884 #if IS_BCMCHIP(63138) || IS_BCMCHIP(63148) || IS_BCMCHIP(6858) || \
1885 IS_BCMCHIP(63158)
1886 // ARM BPCM addresses as used by 63138/63148 and possibly others (28nm)
1887 typedef struct {
1888 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
1889 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
1890 uint32_t control; // offset = 0x08, actual offset = 2
1891 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
1892 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
1893 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
1894 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
1895 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
1896 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
1897 BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9
1898 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
1899 uint32_t reserved; // offset = 0x2c, actual offset = 11
1900 ARM_CONTROL_REG arm_control; // offset = 0x30, actual offset = 12
1901 #if IS_BCMCHIP(63138)
1902 ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl_0; // offset = 0x34, actual offset = 13
1903 ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl_1; // offset = 0x38, actual offset = 14
1904 ARM_CPUx_PWR_CTRL_REG arm_neon_l2; // offset = 0x3c, actua; offset = 15
1905 #elif IS_BCMCHIP(63148)
1906 uint32_t reserved1[3]; // offset = 0x34, actual offset = 13..15
1907 #elif IS_BCMCHIP(6858)
1908 uint32_t biu_clk_control0; // offset = 0x34, actual offset = 13
1909 uint32_t reserved1[2]; // offset = 0x38, actual offset = 13..14
1910 #endif
1911 BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
1912 } ARM_BPCM_REGS;
1913 #define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg)
1914 #define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2)
1915
1916 #elif IS_BCMCHIP(6846) || IS_BCMCHIP(6856)
1917 typedef struct {
1918 CLASSIC_BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
1919 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
1920 uint32_t control; // offset = 0x08, actual offset = 2
1921 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
1922 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
1923 BPCM_AVS_ROSC_THRESHOLD rosc_thresh; // offset = 0x14, actual offset = 5
1924 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x18, actual offset = 6
1925 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x1c, actual offset = 7
1926 BPCM_SR_CONTROL sr_control; // offset = 0x20, actual offset = 8
1927 uint32_t reserved0[3]; // offset = 0x24, actual offset = 9
1928 ARM_CONTROL_REG arm_control; // offset = 0x30, actual offset = 12
1929 uint32_t biu_clk_control0; // offset = 0x34, actual offset = 13
1930 uint32_t reserved1[2]; // offset = 0x38, actual offset = 14
1931 BPCM_ZONE zones; // offset = 0x40, actual offset = 16
1932 } ARM_BPCM_REGS;
1933
1934 #define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg)
1935 #define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2)
1936
1937 #elif IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756)
1938 typedef struct {
1939 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
1940 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
1941 uint32_t reserved0[2]; // offset = 0x08, actual offset = 2
1942 uint32_t cfg_control; // offset = 0x10, actual offset = 4
1943 BPCM_SR_CONTROL sr_control; // offset = 0x14, actual offset = 5
1944 uint32_t reserved1[6]; // offset = 0x18, actual offset = 6
1945 ARM_CONTROL_REG arm_control; // offset = 0x30, actual offset = 12
1946 uint32_t biu_clk_control0; // offset = 0x34, actual offset = 13
1947 uint32_t tbd[18]; // offset = 0x38, actual offset = 14
1948 BPCM_ZONE zones; // offset = 0x80, actual offset = 32
1949 } ARM_BPCM_REGS;
1950 #define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg)
1951 #define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2)
1952
1953 #elif IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
1954 typedef struct {
1955 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
1956 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
1957 uint32_t reserved0[2]; // offset = 0x08, actual offset = 2
1958 uint32_t cfg_control; // offset = 0x10, actual offset = 4
1959 BPCM_SR_CONTROL sr_control; // offset = 0x14, actual offset = 5
1960 uint32_t reserved1[2]; // offset = 0x18, actual offset = 6
1961 BPCM_ZONE zones; // offset = 0x20, actual offset = 8
1962 ARM_CONTROL_REG arm_control; // offset = 0x40, actual offset = 16
1963 } ARM_BPCM_REGS;
1964 #define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg)
1965 #define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2)
1966
1967 #endif
1968
1969 #if IS_BCMCHIP(6846) || IS_BCMCHIP(6856)
1970 typedef struct {
1971 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
1972 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
1973 uint32_t reserved0[2]; // offset = 0x08..0x0c, actual offset 2..3
1974 PLL_CTRL_REG resets; // offset = 0x10, actual offset = 4
1975 PLL_CFG0_REG cfg0; // offset = 0x14, actual offset = 5
1976 PLL_CFG1_REG cfg1; // offset = 0x18, actual offset = 6
1977 PLL_NDIV_REG ndiv; // offset = 0x1c, actual offset = 7
1978 PLL_PDIV_REG pdiv; // offset = 0x20, actual offset = 8
1979 PLL_LOOP0_REG loop0; // offset = 0x24, actual offset = 9
1980 PLL_LOOP1_REG loop1; // offset = 0x28, actual offset = a
1981 PLL_CHCFG_REG ch01_cfg; // offset = 0x2c, actual offset = b
1982 PLL_CHCFG_REG ch23_cfg; // offset = 0x30, actual offset = c
1983 PLL_CHCFG_REG ch45_cfg; // offset = 0x34, actual offset = d
1984 PLL_OCTRL_REG octrl; // offset = 0x38, actual offset = e
1985 PLL_STAT_REG stat; // offset = 0x3c, actual offset = f
1986 uint32_t strap; // offset = 0x40, actual offset = 0x10
1987 PLL_DECNDIV_REG decndiv; // offset = 0x44, actual offset = 0x11
1988 PLL_DECPDIV_REG decpdiv; // offset = 0x48, actual offset = 0x12
1989 PLL_DECCH25_REG decch25; // offset = 0x4c, actual offset = 0x13
1990 } PLL_CLASSIC_BPCM_REGS;
1991
1992 #define PLLCLASSICBPCMOffset(reg) offsetof(PLL_CLASSIC_BPCM_REGS,reg)
1993 #define PLLCLASSICBPCMRegOffset(reg) (PLLCLASSICBPCMOffset(reg) >> 2)
1994
1995 #elif IS_BCMCHIP(6878)
1996 typedef struct {
1997 BPCM_ID_REG id_reg; // offset = 0x00
1998 BPCM_CAPABILITES_REG capabilities; // offset = 0x04
1999 uint32_t reserved0[6]; // offset = 0x08
2000 PLL_CTRL_REG resets; // offset = 0x20
2001 PLL_CFG0_REG cfg0; // offset = 0x24
2002 PLL_CFG1_REG cfg1; // offset = 0x28
2003 PLL_NDIV_REG ndiv; // offset = 0x2c
2004 PLL_PDIV_REG pdiv; // offset = 0x30
2005 PLL_LOOP0_REG loop0; // offset = 0x34
2006 uint32_t reserved1; // offset = 0x38
2007 PLL_LOOP1_REG loop1; // offset = 0x3c
2008 PLL_CHCFG_REG ch01_cfg; // offset = 0x40
2009 PLL_CHCFG_REG ch23_cfg; // offset = 0x44
2010 PLL_CHCFG_REG ch45_cfg; // offset = 0x48
2011 PLL_STAT_REG stat; // offset = 0x4c
2012 uint32_t strap; // offset = 0x50
2013 PLL_DECNDIV_REG decndiv; // offset = 0x54
2014 PLL_DECPDIV_REG decpdiv; // offset = 0x58
2015 PLL_DECCH25_REG decch25; // offset = 0x5c
2016 } PLL_CLASSIC_BPCM_REGS;
2017
2018 #define PLLCLASSICBPCMOffset(reg) offsetof(PLL_CLASSIC_BPCM_REGS,reg)
2019 #define PLLCLASSICBPCMRegOffset(reg) (PLLCLASSICBPCMOffset(reg) >> 2)
2020
2021 #endif
2022
2023 typedef struct {
2024 #if IS_BCMCHIP(6846) || IS_BCMCHIP(6856)
2025 BPCM_ID_REG id_reg; // offset = 0x00
2026 BPCM_CAPABILITES_REG capabilities; // offset = 0x04
2027 uint32_t reserved0[6]; // offset = 0x08
2028 PLL_CTRL_REG resets; // offset = 0x20
2029 PLL_CFG0_REG cfg0; // offset = 0x24
2030 PLL_CFG1_REG cfg1; // offset = 0x28
2031 PLL_NDIV_REG ndiv; // offset = 0x2c
2032 PLL_PDIV_REG pdiv; // offset = 0x30
2033 PLL_LOOP0_REG loop0; // offset = 0x34
2034 uint32_t reserved1; // offset = 0x38
2035 PLL_LOOP1_REG loop1; // offset = 0x3c
2036 PLL_CHCFG_REG ch01_cfg; // offset = 0x40
2037 PLL_CHCFG_REG ch23_cfg; // offset = 0x44
2038 PLL_CHCFG_REG ch45_cfg; // offset = 0x48
2039 PLL_STAT_REG stat; // offset = 0x4c
2040 uint32_t strap; // offset = 0x50
2041 PLL_DECNDIV_REG decndiv; // offset = 0x54
2042 PLL_DECPDIV_REG decpdiv; // offset = 0x58
2043 PLL_DECCH25_REG decch25; // offset = 0x5c
2044 #elif IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
2045 /* BIU PLL BCPM definition */
2046 BPCM_ID_REG id_reg; // offset = 0x00
2047 BPCM_CAPABILITES_REG capabilities; // offset = 0x04
2048 uint32_t reserved0[2]; // offset = 0x08..0x0c
2049 PLL_CTRL_REG resets; // offset = 0x10
2050 uint32_t reserved1[2]; // offset = 0x14
2051 PLL_NDIV_REG ndiv; // offset = 0x1c
2052 PLL_PDIV_REG pdiv; // offset = 0x20
2053 PLL_LOOP0_REG loop0; // offset = 0x24
2054 PLL_LOOP1_REG loop1; // offset = 0x28
2055 PLL_CHCFG_REG ch01_cfg; // offset = 0x2c
2056 PLL_CHCFG_REG ch23_cfg; // offset = 0x30
2057 PLL_CHCFG_REG ch45_cfg; // offset = 0x34
2058 uint32_t reserved2; // offset = 0x38
2059 PLL_STAT_REG stat; // offset = 0x3c
2060 uint32_t strap; // offset = 0x40
2061 PLL_DECNDIV_REG decndiv;// offset = 0x44
2062 PLL_DECPDIV_REG decpdiv;// offset = 0x48
2063 PLL_DECCH25_REG decch25;// offset = 0x4c
2064 #else
2065 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
2066 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
2067 uint32_t reserved0[2]; // offset = 0x08..0x0c, actual offset 2..3
2068 PLL_CTRL_REG resets; // offset = 0x10, actual offset = 4
2069 PLL_CFG0_REG cfg0; // offset = 0x14, actual offset = 5
2070 PLL_CFG1_REG cfg1; // offset = 0x18, actual offset = 6
2071 PLL_NDIV_REG ndiv; // offset = 0x1c, actual offset = 7
2072 PLL_PDIV_REG pdiv; // offset = 0x20, actual offset = 8
2073 PLL_LOOP0_REG loop0; // offset = 0x24, actual offset = 9
2074 PLL_LOOP1_REG loop1; // offset = 0x28, actual offset = a
2075 PLL_CHCFG_REG ch01_cfg; // offset = 0x2c, actual offset = b
2076 PLL_CHCFG_REG ch23_cfg; // offset = 0x30, actual offset = c
2077 PLL_CHCFG_REG ch45_cfg; // offset = 0x34, actual offset = d
2078 PLL_OCTRL_REG octrl; // offset = 0x38, actual offset = e
2079 PLL_STAT_REG stat; // offset = 0x3c, actual offset = f
2080 uint32_t strap; // offset = 0x40, actual offset = 0x10
2081 #if IS_BCMCHIP(6858) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \
2082 IS_BCMCHIP(6878) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756)
2083 PLL_DECNDIV_REG decndiv; // offset = 0x44, actual offset = 0x11
2084 PLL_DECPDIV_REG decpdiv; // offset = 0x48, actual offset = 0x12
2085 PLL_DECCH25_REG decch25; // offset = 0x4c, actual offset = 0x13
2086 #else
2087 uint32_t decndiv; // offset = 0x44, actual offset = 0x11
2088 uint32_t decpdiv; // offset = 0x48, actual offset = 0x12
2089 uint32_t decch25; // offset = 0x4c, actual offset = 0x13
2090 #endif
2091 #endif
2092 } PLL_BPCM_REGS;
2093
2094 #define PLLBPCMOffset(reg) offsetof(PLL_BPCM_REGS,reg)
2095 #define PLLBPCMRegOffset(reg) (PLLBPCMOffset(reg) >> 2)
2096
2097 #if IS_BCMCHIP(63146)
2098 typedef struct {
2099 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
2100 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
2101 uint32_t reserved0[2]; // offset = 0x08..0x0c, actual offset 2..3
2102 PLL_CTRL_REG resets; // offset = 0x10, actual offset = 4
2103 uint32_t reserved1[5]; // offset = 0x14, actual offset = 5
2104 PLL_NDIV_REG ndiv; // offset = 0x28, actual offset = a
2105 PLL_PDIV_REG pdiv; // offset = 0x2c, actual offset = b
2106 PLL_CHCFG_REG ch01_cfg; // offset = 0x30, actual offset = c
2107 PLL_CHCFG_REG ch23_cfg; // offset = 0x34, actual offset = d
2108 PLL_CHCFG_REG ch45_cfg; // offset = 0x38, actual offset = e
2109 PLL_LOOP0_REG loop0; // offset = 0x3c, actual offset = f
2110 PLL_LOOP1_REG loop1; // offset = 0x40, actual offset = 0x10
2111 PLL_STAT_REG stat; // offset = 0x44, actual offset = 0x11
2112 uint32_t strap; // offset = 0x48, actual offset = 0x12
2113 PLL_DECNDIV_REG decndiv;// offset = 0x4c, actual offset = 0x13
2114 PLL_DECPDIV_REG decpdiv;// offset = 0x50, actual offset = 0x14
2115 PLL_DECCH25_REG decch25;// offset = 0x54, actual offset = 0x15
2116 } AFEPLL_BPCM_REGS;
2117
2118 #define AFEPLLBPCMOffset(reg) offsetof(AFEPLL_BPCM_REGS,reg)
2119 #define AFEPLLBPCMRegOffset(reg) (AFEPLLBPCMOffset(reg) >> 2)
2120 #endif
2121
2122 #if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
2123 typedef struct {
2124 BPCM_ID_REG id_reg; // offset = 0x00
2125 BPCM_CAPABILITES_REG capabilities; // offset = 0x04
2126 uint32_t reserved0[2]; // offset = 0x08..0x0c
2127 PLL_CTRL_REG resets; // offset = 0x10
2128 uint32_t reserved1[5]; // offset = 0x14
2129 PLL_NDIV_REG ndiv; // offset = 0x28
2130 PLL_PDIV_REG pdiv; // offset = 0x2c
2131 PLL_CHCFG_REG ch01_cfg; // offset = 0x30
2132 PLL_CHCFG_REG ch23_cfg; // offset = 0x34
2133 PLL_CHCFG_REG ch45_cfg; // offset = 0x38
2134 PLL_STAT_REG stat; // offset = 0x3c
2135 uint32_t strap; // offset = 0x40
2136 PLL_DECNDIV_REG decndiv;// offset = 0x44
2137 PLL_DECPDIV_REG decpdiv;// offset = 0x48
2138 PLL_DECCH25_REG decch25;// offset = 0x4c
2139 } RDPPLL_BPCM_REGS;
2140
2141 #define RDPPLLBPCMOffset(reg) offsetof(RDPPLL_BPCM_REGS,reg)
2142 #define RDPPLLBPCMRegOffset(reg) (RDPPLLBPCMOffset(reg) >> 2)
2143
2144 #endif
2145
2146 #if IS_BCMCHIP(6878) || IS_BCMCHIP(6855)
2147 typedef union {
2148 struct {
2149 uint32_t dac_data:10; // [09:00]
2150 uint32_t vavs_minb0:1; // [10:10] - R/O iVDDC <= Vmin0
2151 uint32_t vavs_minb1:1; // [11:11] - R/O iVDDC <= Vmin1
2152 uint32_t vavs_warnb0:1; // [12:12] - R/O iVDDC <= Vwarn0
2153 uint32_t vavs_warnb1:1; // [13:13] - R/O iVDDC <= Vwarn1
2154 uint32_t vavs_maxb0:1; // [14:14] - R/O iVDDC <= Vmax0
2155 uint32_t vavs_maxb1:1; // [15:15] - R/O iVDDC <= Vmax1
2156 uint32_t adc_data:10; // [25:16] - R/O ADC output data in offset binary format
2157 uint32_t adc_data_valid:1; // [26:26] - R/O
2158 uint32_t reserved:5; // [31:27] - R/O
2159 } Bits;
2160 uint32_t Reg32;
2161 } APVTMON_DATA_REG;
2162
2163 typedef union {
2164 // little endian - from page 5 of "ANA_VTMON_TS16FF_S0 & ANA_VTMON_PAD_TS16FF_Sx Module Specification"
2165 // defaut value = 0x00000001
2166 struct {
2167 uint32_t bg_adj:3; // [02:00] - default = 1
2168 uint32_t vtest_sel:4; // [06:03] - VTest = i_VDCC * (<value>+1)/20, default = 0
2169 uint32_t rmon_sel:3; // [09:07]
2170 uint32_t mode:3; // [12:10]
2171 uint32_t adc_insel:2; // [14:13] - only used in expert mode (mode = 0b111)
2172 uint32_t dac_en:1; // [15:15] - only used in expert mode (mode = 0b111)
2173 uint32_t con_pad:1; // [16:16] - only used in expert mode (mode = 0b111)
2174 uint32_t burnin_en:1; // [17:17] - only used in expert mode (mode = 0b111)
2175 uint32_t reserved:1; // [18:18]
2176 uint32_t vdccmon_refadj_max1:1; // [19:19]
2177 uint32_t vdccmon_refadj_min0:4; // [23:20]
2178 uint32_t vdccmon_refadj_min1:3; // [26:24]
2179 uint32_t dac_reset:1; // [27:27]
2180 uint32_t dac_set:1; // [28:28]
2181 uint32_t vdccmon_refadj_max0:3; // [31:29]
2182 } Bits;
2183 uint32_t Reg32;
2184 } APVTMON_CONTROL_REG;
2185
2186 typedef union {
2187 struct {
2188 uint32_t rstb:1; // [00:00] - low active. default = 0 (i.e. in reset)
2189 uint32_t pwr_dn:1; // [01:01] - high-active. default = 1 (i.e. powered down)
2190 uint32_t clk_en:1; // [02:02]
2191 uint32_t reserved0:1; // [03:03]
2192 uint32_t sel:3; // [06:04] - see enum below - reset value = 0
2193 uint32_t reserved1:1; // [07:07]
2194 uint32_t clk_div:5; // [12:08] - value needed to divide pm_clk by (2*clk_div) to generate a 5MHz clock
2195 uint32_t reserved2:19; // [31:13]
2196 } Bits;
2197 uint32_t Reg32;
2198 } APVTMON_CONFIG_STATUS_REG;
2199
2200 typedef union {
2201 struct {
2202 uint32_t accum_en:1; // [00:00]
2203 uint32_t round_en:1; // [01:01] defaults to 1 (rounding enabled)
2204 uint32_t reserved1:6; // [07:02]
2205 uint32_t skip_len:4; // [11:08] how many samples to skip prior to starting averaging, default = 3
2206 uint32_t reserved0:20; // [31:12]
2207 } Bits;
2208 uint32_t Reg32;
2209 } APVTMON_ACQ_CONFIG_REG;
2210
2211 typedef union {
2212 struct {
2213 uint32_t warn_threshold:10; // [09:00] - in ADC counts
2214 uint32_t warn_en:1; // [10:10]
2215 uint32_t reserved0:3; // [13:11]
2216 uint32_t clear_warn:1; // [14:14] - Write only
2217 uint32_t warn:1; // [15:15] - Read only
2218 uint32_t reset_threshold:10; // [25:16] - in ADC counts
2219 uint32_t reset_en:1; // [26:26]
2220 uint32_t reserved1:3; // [29:27]
2221 uint32_t clear_reset:1; // [30:30] - Write only
2222 uint32_t reset:1; // [31:31] - Read only
2223 } Bits;
2224 uint32_t Reg32;
2225 } APVTMON_TEMP_WARN_RESET_REG;
2226
2227 typedef union {
2228 struct {
2229 uint32_t reset_value:10; // [09:00]
2230 uint32_t reserved:22; // [31:10]
2231 } Bits;
2232 uint32_t Reg32;
2233 } APVTMON_RESET_TEMP_REG;
2234
2235 typedef union {
2236 struct {
2237 uint32_t value:10; // [09:00] - there are <meas_len> fractional bits
2238 uint32_t reserved0:8; // [17:10]
2239 uint32_t valid:1; // [18:18]
2240 uint32_t busy:1; // [19:19]
2241 uint32_t reserved1:4; // [23:20]
2242 uint32_t meas_len:3; // [26:24] #samples = 2^<value>
2243 uint32_t reserved2:4; // [30:27]
2244 uint32_t enable:1; // [31:31]
2245 } Bits;
2246 uint32_t Reg32;
2247 } APVTMON_ACCUM_REG;
2248
2249 typedef union {
2250 struct {
2251 uint32_t sel:6; // [05:00] - ring oscillator select (0..35)
2252 uint32_t reserved2:2; // [07:06]
2253 uint32_t srm_ind_en:1; // [08:08]
2254 uint32_t srm_ind_od:1; // [09:09]
2255 uint32_t srm_ind_sel:2; // [11:10]
2256 uint32_t reserved1:4; // [15:12]
2257 uint32_t out:1; // [16:16]
2258 uint32_t all_idl_low_oscs:1; // [17:17]
2259 uint32_t all_idl_hi_oscs:1; // [18:18]
2260 uint32_t reserved0:13; // [31:19]
2261 } Bits;
2262 uint32_t Reg32;
2263 } ROSC_CTRL_STS_REG;
2264
2265 typedef union {
2266 struct {
2267 uint32_t count:16; // [15:00]
2268 uint32_t valid:1; // [16:16]
2269 uint32_t too_lo:1; // [17:17] - count <= thresh_lo (only when THRESH_EN == 1)
2270 uint32_t too_hi:1; // [18:18] - count <= thresh_hi (only when THRESH_EN == 1)
2271 uint32_t reserved0:5; // [23:19]
2272 uint32_t continuous:1; // [24:24]
2273 uint32_t thresh_en:1; // [25:25] - enable threshold detection
2274 uint32_t ectr_en:1; // [26:26] - enable counter
2275 uint32_t src_en:1; // [27:27] - enable event source (may not do anything???)
2276 uint32_t meas_len:4; // [31:28] - interval = 2^(<meas_len>+1)
2277 } Bits;
2278 uint32_t Reg32;
2279 } ECTR_CTRL_STS_REG;
2280
2281 typedef union {
2282 struct {
2283 uint32_t thresh_lo:16; // [15:00]
2284 uint32_t thresh_hi:16; // [31:16]
2285 } Bits;
2286 uint32_t Reg32;
2287 } ECTR_THRESH_REG;
2288
2289 typedef struct {
2290 ECTR_CTRL_STS_REG count_reg;
2291 ECTR_THRESH_REG thresh_reg;
2292 } ROSC_REGS;
2293
2294 typedef struct {
2295 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
2296 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
2297 uint32_t reserved0[2]; // offset 0x08, PMB reg index 2/3
2298 uint32_t reserved1[12]; // offset 0x10, PMB reg index 4-15 (future proofing )
2299 APVTMON_CONTROL_REG control; // offset 0x40, PMB reg index 16
2300 APVTMON_CONFIG_STATUS_REG config; // offset 0x44, PMB reg index 17
2301 APVTMON_DATA_REG adc_data; // offset 0x48, PMB reg index 18
2302 uint32_t reserved2; // offset 0x4c, PMB reg index 19
2303 APVTMON_ACQ_CONFIG_REG accum_config; // offset 0x50, PMB reg index 20
2304 APVTMON_TEMP_WARN_RESET_REG warn_rst; // offset 0x54, PMB reg index 21
2305 uint32_t reserved3[2]; // offset 0x58, PMB reg index 23
2306 APVTMON_ACCUM_REG acq_accum_regs[8]; // offset 0x60, PMB reg index 24-31
2307 ROSC_CTRL_STS_REG rosc_ctrl_sts; // offset 0x80, PMB reg index 32
2308 uint32_t rosc_en_lo; // offset 0x84, PMB reg index 33
2309 uint32_t rosc_en_hi; // offset 0x88, PMB reg index 34
2310 uint32_t rosc_idle_lo; // offset 0x8c, PMB reg index 35
2311 uint32_t rosc_idle_hi; // offset 0x90, PMB reg index 36
2312 uint32_t reserved4[3]; // offset 0x94, PMB reg index 37-39
2313 ROSC_REGS ectr_regs; // offset 0xa0, PMB reg index 40/41
2314 } PVTMON_REGS;
2315 // retrieves the BYTE offset of a PVTMON register:
2316 #define PVTMON_OFFSET(reg) (offsetof(PVTMON_REGS,reg)>>2)
2317
2318 typedef struct {
2319 // PMB-slave
2320 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
2321 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
2322 uint32_t reserved0[6]; // offset 0x08, PMB reg index 2-7
2323 // ROSC registers
2324 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset 0x20, PMB reg index 8
2325 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset 0x24, PMB reg index 9
2326 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset 0x28, PMB reg index 10
2327 BPCM_AVS_ROSC_COUNT rosc_count; // offset 0x2c, PMB reg index 11
2328 BPCM_AVS_PWD_CONTROL pwd_ctrl; // offset 0x30, PMB reg index 12
2329 BPCM_PWD_ACCUM_CONTROL pwd_accum; // offset 0x34, PMB reg index 13
2330 } ARS_REGS;
2331 // retrieves the BYTE offset of an ARS register:
2332 #define ARS_OFFSET(reg) (offsetof(ARS_REGS, reg)>>2)
2333
2334 #endif
2335
2336 typedef struct {
2337 BPCM_UBUS_ID_REG id_reg; /* offset = 0x00, actual offset = 0 */
2338 BPCM_UBUS_CAPABILITES_REG capabilities; /* offset = 0x04, actual offset = 1 */
2339 uint32_t reserved0; /* offset = 0x08, actual offset = 2 */
2340 BPCM_UBUS_CTRL_REG ctrl; /* offset = 0x0c, actual offset = 3 */
2341 BPCM_UBUS_CFG_REG cfg[4]; /* offset = 0x10..0x2c, actual offset = 4..11 */
2342 } BPCM_UBUS_REG;
2343
2344 #define UBUSBPCMOffset(reg) offsetof(BPCM_UBUS_REG,reg)
2345 #define UBUSBPCMRegOffset(reg) (UBUSBPCMOffset(reg) >> 2)
2346
2347 #if IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6756)
2348 typedef struct {
2349 // PMB-slave:
2350 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
2351 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
2352 uint32_t reserved0[7]; // offset 0x08-0x20, PMB reg index 2-8
2353 uint32_t control; // offset 0x24, PMB reg index 9
2354 #if IS_BCMCHIP(47622) || IS_BCMCHIP(6756)
2355 uint32_t observe_cntrl; // offset 0x28, PMB reg index 10
2356 uint32_t observe_div; // offset 0x2c, PMB reg index 11
2357 uint32_t observe_enable; // offset 0x30, PMB reg index 12
2358 BPCM_CLKRST_CONTROL clkrst_control; // offset 0x34, PMB reg index 13
2359 #elif IS_BCMCHIP(63146)
2360 uint32_t unused[3]; // offset 0x28, PMB reg index 10
2361 BPCM_CLKRST_VREG_CONTROL vreg_control; // offset 0x34, PMB reg index ??
2362 #elif IS_BCMCHIP(63178)
2363 uint32_t unused[10]; // offset 0x28, PMB reg index 10
2364 BPCM_CLKRST_VREG_CONTROL vreg_control; // offset 0x50, PMB reg index 19
2365 #endif
2366 } BPCM_CLKRST_REGS;
2367 #else
2368 typedef struct {
2369 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
2370 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
2371 uint32_t control; // offset = 0x08, actual offset = 2
2372 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
2373 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
2374 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
2375 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
2376 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
2377 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
2378 #if IS_BCMCHIP(6878)
2379 uint32_t bpcm_ctrl; // offset = 0x24, actual offset = 9
2380 uint32_t clkrst_control; // offset = 0x28, actual offset = 10
2381 uint32_t ext_observe_ctrl; // offset = 0x2c, actual offset = 11
2382 uint32_t reserved0[2]; // offset = 0x30-0x34, actual offset 12-13
2383 uint32_t xtal_control; // offset = 0x38, actual offset = 14
2384 uint32_t clkrst_stat; // offset = 0x3c, actual offset = 15
2385 uint32_t reserved1; // offset = 0x40, actual offset = 16
2386 uint32_t clkrst_ena_clk_31_0; // offset = 0x44, actual offset = 17
2387 uint32_t clkrst_ena_clk_63_32; // offset = 0x48, actual offset = 18
2388 uint32_t clkrst_ena_clk_95_64; // offset = 0x4c, actual offset = 19
2389 uint32_t reserved2[11]; // offset = 0x50-0x78, actual offset = 20-30
2390 uint32_t clkrst_ena_reset_31_0; // offset = 0x7c, actual offset = 31
2391 uint32_t clkrst_ena_reset_63_32; // offset = 0x80, actual offset = 32
2392 uint32_t clkrst_pll_observe_clk; // offset = 0x84, actual offset = 33
2393 uint32_t clkrst_ref_cnt_thresh; // offset = 0x88, actual offset = 34
2394 uint32_t clkrst_pll_clk_low_th; // offset = 0x8c, actual offset = 35
2395 uint32_t clkrst_pll_clk_hi_th; // offset = 0x90, actual offset = 36
2396 uint32_t clkrst_pll_clk_stat; // offset = 0x94, actual offset = 37
2397 uint32_t clkrst_sticky_bit_stat; // offset = 0x98, actual offset = 38
2398 uint32_t clkrst_clk250_src_sel; // offset = 0x9c, actual offset = 39
2399 uint32_t clkrst_ena_force; // offset = 0xa0, actual offset = 40
2400 uint32_t reserved3; // offset = 0xa4, actual offset = 41
2401 uint32_t pmd_xtal_cntl; // offset = 0xa8, actual offset = 42
2402 uint32_t pmd_xtal_cntl2; // offset = 0xac, actual offset = 43
2403 #else
2404 uint32_t reserved0; // offset = 0x24, actual offset = 9
2405 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
2406 uint32_t reserved1; // offset = 0x2c, actual offset = 11
2407 uint32_t clkrst_cfg; // offset = 0x30, actual offset = 12
2408 #if IS_BCMCHIP(63146)
2409 BPCM_CLKRST_VREG_CONTROL vreg_control; // offset 0x50, PMB reg index 19
2410 #else
2411 uint32_t clkrst_control; // offset = 0x34, actual offset = 13
2412 #endif
2413 uint32_t xtal_control; // offset = 0x38, actual offset = 14
2414 uint32_t clkrst_stat; // offset = 0x3c, actual offset = 15
2415 #endif
2416 } BPCM_CLKRST_REGS;
2417 #endif
2418
2419 #define CLKRSTBPCMOffset(reg) offsetof(BPCM_CLKRST_REGS, reg)
2420 #define CLKRSTBPCMRegOffset(reg) (CLKRSTBPCMOffset(reg) >> 2)
2421
2422 #if IS_BCMCHIP(47622) || IS_BCMCHIP(6756)
2423 typedef struct {
2424 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
2425 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
2426 uint32_t reserved0[2]; // offset 0x08, PMB reg index 2/3
2427 // BPCM
2428 uint32_t control; // offset 0x10, PMB reg index 4
2429 BPCM_SR_CONTROL sr_control; // offset 0x14, PMB reg index 5
2430
2431 uint32_t z0_pm_cntl; // offset 0x18
2432 uint32_t z0_pm_status; // offset 0x1c
2433 uint32_t z1_pm_cntl; // offset 0x20
2434 uint32_t z2_pm_cntl; // offset 0x24
2435 uint32_t reserved1[22]; // reserved from 0x28 to 0x7F
2436 BPCM_ZONE zones[];
2437
2438 } BPCM_SYSPORT_REGS;
2439
2440 #define SYSPOffset(reg) offsetof(BPCM_SYSPORT_REGS,reg)
2441 #define SYSPRegOffset(reg) (SYSPOffset(reg) >> 2)
2442
2443 #endif
2444
2445 #if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
2446 typedef struct {
2447 // ETH_PMB
2448 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
2449 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
2450 uint32_t reserved8[2]; // offset 0x08, PMB reg index 2/3
2451 // ETH_CFG
2452 uint32_t dpg_zones; // offset 0x10, PMB reg index 4
2453 uint32_t soft_rst;; // offset 0x14, PMB reg index 5
2454 uint32_t reserved18[2]; // offset 0x18, PMB reg index 6/7
2455 // ETH_CORE
2456 #if IS_BCMCHIP(63146)
2457 uint32_t qphy_cntrl; // offset 0x20
2458 uint32_t qphy_status; // offset 0x24
2459 uint32_t sphy_cntrl; // offset 0x28
2460 uint32_t sphy_status; // offset 0x2c
2461 uint32_t serdes0_cntrl; // offset 0x30
2462 uint32_t serdes0_status;// offset 0x34
2463 uint32_t serdes0_an_st; // offset 0x38
2464 uint32_t serdes1_cntrl; // offset 0x3c
2465 uint32_t serdes1_status;// offset 0x40
2466 uint32_t serdes1_an_st; // offset 0x44
2467 uint32_t reserved48[3];
2468 uint32_t rgmii_cntrl; // offset 0x54
2469 uint32_t reserved58[2];
2470 uint32_t serdes0_st1; // offset 0x60
2471 uint32_t serdes1_st1; // offset 0x64
2472 uint32_t reserved68;
2473 uint32_t serdes0_pwr_cntrl;// offset 0x6c
2474 uint32_t serdes1_pwr_cntrl;// offset 0x70
2475 #endif
2476 #if IS_BCMCHIP(4912)
2477 uint32_t qphy_cntrl; // offset 0x20
2478 uint32_t qphy_status; // offset 0x24
2479 uint32_t reserved28[2];
2480 uint32_t serdes0_cntrl; // offset 0x30
2481 uint32_t serdes0_status;// offset 0x34
2482 uint32_t serdes0_an_st; // offset 0x38
2483 uint32_t serdes1_cntrl; // offset 0x3c
2484 uint32_t serdes1_status;// offset 0x40
2485 uint32_t serdes1_an_st; // offset 0x44
2486 uint32_t serdes2_cntrl; // offset 0x48
2487 uint32_t serdes2_status;// offset 0x4c
2488 uint32_t serdes2_an_st; // offset 0x50
2489 uint32_t rgmii_cntrl; // offset 0x54
2490 uint32_t xport0_cntrl; // offset 0x58
2491 uint32_t xport1_cntrl; // offset 0x5c
2492 uint32_t serdes0_st1; // offset 0x60
2493 uint32_t serdes1_st1; // offset 0x64
2494 uint32_t serdes2_st1; // offset 0x68
2495 uint32_t serdes0_pwr_cntrl;// offset 0x6c
2496 uint32_t serdes1_pwr_cntrl;// offset 0x70
2497 uint32_t serdes2_pwr_cntrl;// offset 0x74
2498 #endif
2499 } BPCM_ETH_REGS;
2500
2501 #define BPCMETHOffset(reg) offsetof(BPCM_ETH_REGS,reg)
2502 #define BPCMETHRegOffset(reg) (BPCMETHOffset(reg) >> 2)
2503
2504 #endif
2505
2506 // *************************** macros ******************************
2507 #ifndef offsetof
2508 #define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
2509 #endif
2510
2511 #endif
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