plat/bcm/include/bcm963xx/63138_map_part.h

   1 /*
   2 <:copyright-BRCM:2013:DUAL/GPL:standard
   3
   4    Copyright (c) 2013 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef __BCM63138_MAP_PART_H
  25 #define __BCM63138_MAP_PART_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #include "bcmtypes.h"
  32
  33 #define PER_BASE                0xfffe0000
  34 #define REG_BASE                0x80000000
  35
  36 #define MEMC_PHYS_BASE          (REG_BASE + 0x00002000)  /* DDR IO Buf Control */
  37 #define MEMC_SIZE               0x20000
  38
  39 #define PMC_PHYS_BASE           (REG_BASE + 0x00400000)
  40 #define PROC_MON_PHYS_BASE      (REG_BASE + 0x00480000)
  41 #define GICC_PHYS_BASE          (REG_BASE + 0x0001e100)
  42 #define GICD_PHYS_BASE          (REG_BASE + 0x0001f000)
  43
  44 #define PERF_PHYS_BASE          (PER_BASE + 0x00008000)  /* chip control */
  45 #define TIMR_PHYS_BASE          (PER_BASE + 0x00008080)  /* timer registers */
  46 #define BOOTLUT_PHYS_BASE       (PER_BASE + 0x00010000)
  47
  48 #define PMC_BASE                PMC_PHYS_BASE
  49 #define PROC_MON_BASE           PROC_MON_PHYS_BASE
  50 #define TIMR_BASE               TIMR_PHYS_BASE
  51 #define BOOTLUT_BASE            BOOTLUT_PHYS_BASE
  52 #define GICC_BASE               GICC_PHYS_BASE
  53 #define GICD_BASE               GICD_PHYS_BASE
  54
  55
  56 #ifndef __ASSEMBLER__
  57
  58 /*
  59  * Power Management Control
  60  */
  61 typedef struct PmcCtrlReg {
  62    /* 0x00 */
  63    uint32 l1Irq4keMask;
  64    uint32 l1Irq4keStatus;
  65    uint32 l1IrqMipsMask;
  66    uint32 l1IrqMipsStatus;
  67    /* 0x10 */
  68    uint32 l2IrqGpMask;
  69    uint32 l2IrqGpStatus;
  70    uint32 gpTmr0Ctl;
  71    uint32 gpTmr0Cnt;
  72    /* 0x20 */
  73    uint32 gpTmr1Ctl;
  74    uint32 gpTmr1Cnt;
  75    uint32 hostMboxIn;
  76    uint32 hostMboxOut;
  77    /* 0x30 */
  78 #define PMC_CTRL_GP_FLASH_BOOT_STALL                  0x00000080
  79    uint32 gpOut;
  80    uint32 gpIn;
  81    uint32 gpInIrqMask;
  82    uint32 gpInIrqStatus;
  83    /* 0x40 */
  84    uint32 dmaCtrl;
  85    uint32 dmaStatus;
  86    uint32 dma0_3FifoStatus;
  87    uint32 unused0[3];   /* 0x4c-0x57 */
  88    /* 0x58 */
  89    uint32 l1IrqMips1Mask;
  90    uint32 diagControl;
  91    /* 0x60 */
  92    uint32 diagHigh;
  93    uint32 diagLow;
  94    uint32 badAddr;
  95    uint32 addr1WndwMask;
  96    /* 0x70 */
  97    uint32 addr1WndwBaseIn;
  98    uint32 addr1WndwBaseOut;
  99    uint32 addr2WndwMask;
 100    uint32 addr2WndwBaseIn;
 101    /* 0x80 */
 102    uint32 addr2WndwBaseOut;
 103    uint32 scratch;
 104    uint32 tm;
 105    uint32 softResets;
 106    /* 0x90 */
 107    uint32 eb2ubusTimeout;
 108    uint32 m4keCoreStatus;
 109    uint32 gpInIrqSense;
 110    uint32 ubSlaveTimeout;
 111    /* 0xa0 */
 112    uint32 diagEn;
 113    uint32 devTimeout;
 114    uint32 ubusErrorOutMask;
 115    uint32 diagCaptStopMask;
 116    /* 0xb0 */
 117    uint32 revId;
 118    uint32 gpTmr2Ctl;
 119    uint32 gpTmr2Cnt;
 120    uint32 legacyMode;
 121    /* 0xc0 */
 122    uint32 smisbMonitor;
 123    uint32 diagCtrl;
 124    uint32 diagStat;
 125    uint32 diagMask;
 126    /* 0xd0 */
 127    uint32 diagRslt;
 128    uint32 diagCmp;
 129    uint32 diagCapt;
 130    uint32 diagCnt;
 131    /* 0xe0 */
 132    uint32 diagEdgeCnt;
 133    uint32 unused1[4];   /* 0xe4-0xf3 */
 134    /* 0xf4 */
 135    uint32 iopPeriphBaseAddr;
 136    uint32 lfsr;
 137    uint32 unused2;      /* 0xfc-0xff */
 138 } PmcCtrlReg;
 139
 140 typedef struct PmcOutFifoReg {
 141    uint32 msgCtrl;      /* 0x00 */
 142    uint32 msgSts;    /* 0x04 */
 143    uint32 unused[14];   /* 0x08-0x3f */
 144    uint32 msgData[16];  /* 0x40-0x7c */
 145 } PmcOutFifoReg;
 146
 147 typedef struct PmcInFifoReg {
 148    uint32 msgCtrl;      /* 0x00 */
 149    uint32 msgSts;    /* 0x04 */
 150    uint32 unused[13];   /* 0x08-0x3b */
 151    uint32 msgLast;      /* 0x3c */
 152    uint32 msgData[16];  /* 0x40-0x7c */
 153 } PmcInFifoReg;
 154
 155 typedef struct PmcDmaReg {
 156    /* 0x00 */
 157    uint32 src;
 158    uint32 dest;
 159    uint32 cmdList;
 160    uint32 lenCtl;
 161    /* 0x10 */
 162    uint32 rsltSrc;
 163    uint32 rsltDest;
 164    uint32 rsltHcs;
 165    uint32 rsltLenStat;
 166 } PmcDmaReg;
 167
 168 typedef struct PmcTokenReg {
 169    /* 0x00 */
 170    uint32 bufSize;
 171    uint32 bufBase;
 172    uint32 idx2ptrIdx;
 173    uint32 idx2ptrPtr;
 174    /* 0x10 */
 175    uint32 unused[2];
 176    uint32 bufSize2;
 177 } PmcTokenReg;
 178
 179 typedef struct PmcPerfPowReg {
 180    /* 0x00 */
 181    uint32 dcacheHit;
 182    uint32 dcacheMiss;
 183    uint32 icacheHit;
 184    uint32 icacheMiss;
 185    /* 0x10 */
 186    uint32 instnComplete;
 187    uint32 wtbMerge;
 188    uint32 wtbNoMerge;
 189    uint32 itlbHit;
 190    /* 0x20 */
 191    uint32 itlbMiss;
 192    uint32 dtlbHit;
 193    uint32 dtlbMiss;
 194    uint32 jtlbHit;
 195    /* 0x30 */
 196    uint32 jtlbMiss;
 197    uint32 powerSubZone;
 198    uint32 powerMemPda;
 199    uint32 freqScalarCtrl;
 200    /* 0x40 */
 201    uint32 freqScalarMask;
 202 } PmcPerfPowReg;
 203
 204 typedef struct PmcDQMReg {
 205    /* 0x00 */
 206    uint32 cfg;
 207    uint32 _4keLowWtmkIrqMask;
 208    uint32 mipsLowWtmkIrqMask;
 209    uint32 lowWtmkIrqMask;
 210    /* 0x10 */
 211    uint32 _4keNotEmptyIrqMask;
 212    uint32 mipsNotEmptyIrqMask;
 213    uint32 notEmptyIrqSts;
 214    uint32 queueRst;
 215    /* 0x20 */
 216    uint32 notEmptySts;
 217    uint32 nextAvailMask;
 218    uint32 nextAvailQueue;
 219    uint32 mips1LowWtmkIrqMask;
 220    /* 0x30 */
 221    uint32 mips1NotEmptyIrqMask;
 222    uint32 autoSrcPidInsert;
 223 } PmcDQMReg;
 224
 225 typedef struct PmcCntReg {
 226    uint32 cntr[10];
 227    uint32 unused[6]; /* 0x28-0x3f */
 228    uint32 cntrIrqMask;
 229    uint32 cntrIrqSts;
 230 } PmcCntReg;
 231
 232 typedef struct PmcDqmQCtrlReg {
 233    uint32 size;
 234    uint32 cfga;
 235    uint32 cfgb;
 236    uint32 cfgc;
 237 } PmcDqmQCtrlReg;
 238
 239 typedef struct PmcDqmQDataReg {
 240    uint32 word[4];
 241 } PmcDqmQDataReg;
 242
 243 typedef struct PmcDqmQMibReg {
 244    uint32 qNumFull[32];
 245    uint32 qNumEmpty[32];
 246    uint32 qNumPushed[32];
 247 } PmcDqmQMibReg;
 248
 249 typedef struct Pmc {
 250    uint32 baseReserved;    /* 0x0000 */
 251    uint32 unused0[1023];
 252    PmcCtrlReg ctrl;     /* 0x1000 */
 253
 254    PmcOutFifoReg outFifo;     /* 0x1100 */
 255    uint32 unused1[32];     /* 0x1180-0x11ff */
 256    PmcInFifoReg inFifo;    /* 0x1200 */
 257    uint32 unused2[32];     /* 0x1280-0x12ff */
 258
 259    PmcDmaReg dma[2];    /* 0x1300 */
 260    uint32 unused3[48];     /* 0x1340-0x13ff */
 261
 262    PmcTokenReg token;      /* 0x1400 */
 263    uint32 unused4[121];    /* 0x141c-0x15ff */
 264
 265    PmcPerfPowReg perfPower;   /* 0x1600 */
 266    uint32 unused5[47];     /* 0x1644-0x16ff */
 267
 268    uint32 msgId[32];    /* 0x1700 */
 269    uint32 unused6[32];     /* 0x1780-0x17ff */
 270
 271    PmcDQMReg dqm;       /* 0x1800 */
 272    uint32 unused7[50];     /* 0x1838-0x18ff */
 273
 274    PmcCntReg hwCounter;    /* 0x1900 */
 275    uint32 unused8[46];     /* 0x1948-0x19ff */
 276
 277    PmcDqmQCtrlReg dqmQCtrl[32];  /* 0x1a00 */
 278    PmcDqmQDataReg dqmQData[32];  /* 0x1c00 */
 279    uint32 unused9[64];     /* 0x1e00-0x1eff */
 280
 281    uint32 qStatus[32];     /* 0x1f00 */
 282    uint32 unused10[32];    /* 0x1f80-0x1fff */
 283
 284    PmcDqmQMibReg qMib;     /* 0x2000 */
 285    uint32 unused11[1952];     /* 0x2180-0x3ffff */
 286
 287    uint32 sharedMem[8192];    /* 0x4000-0xbffc */
 288 } Pmc;
 289
 290 #define PMC ((volatile Pmc * const) PMC_BASE)
 291
 292
 293
 294 /*
 295  * Process Monitor Module
 296  */
 297 typedef struct PMRingOscillatorControl {
 298    uint32 control;
 299    uint32 en_lo;
 300    uint32 en_mid;
 301    uint32 en_hi;
 302    uint32 idle_lo;
 303    uint32 idle_mid;
 304    uint32 idle_hi;
 305 } PMRingOscillatorControl;
 306
 307 #define RCAL_0P25UM_HORZ          0
 308 #define RCAL_0P25UM_VERT          1
 309 #define RCAL_0P5UM_HORZ           2
 310 #define RCAL_0P5UM_VERT           3
 311 #define RCAL_1UM_HORZ             4
 312 #define RCAL_1UM_VERT             5
 313 #define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
 314 #define PMMISC_RMON_VALID_MASK    (0x1<<16)
 315 typedef struct PMMiscControl {
 316    uint32 gp_out;
 317    uint32 clock_select;
 318    uint32 unused[2];
 319    uint32 misc[4];
 320 } PMMiscControl;
 321
 322 typedef struct PMSSBMasterControl {
 323    uint32 control;
 324 #define PMC_SSBM_CONTROL_SSB_START  (1<<15)
 325 #define PMC_SSBM_CONTROL_SSB_ADPRE  (1<<13)
 326 #define PMC_SSBM_CONTROL_SSB_EN     (1<<12)
 327 #define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10)
 328 #define PMC_SSBM_CONTROL_SSB_CMD_MASK  (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT)
 329 #define PMC_SSBM_CONTROL_SSB_CMD_READ  (2)
 330 #define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1)
 331 #define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT   (0)
 332 #define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT)
 333    uint32 wr_data;
 334    uint32 rd_data;
 335 } PMSSBMasterControl;
 336
 337 typedef struct PMEctrControl {
 338    uint32 control;
 339    uint32 interval;
 340    uint32 thresh_lo;
 341    uint32 thresh_hi;
 342    uint32 count;
 343 } PMEctrControl;
 344
 345 typedef struct PMBMaster {
 346    uint32 ctrl;
 347 #define PMC_PMBM_START     (1 << 31)
 348 #define PMC_PMBM_TIMEOUT   (1 << 30)
 349 #define PMC_PMBM_SLAVE_ERR (1 << 29)
 350 #define PMC_PMBM_BUSY      (1 << 28)
 351 #define PMC_PMBM_Read      (0 << 20)
 352 #define PMC_PMBM_Write     (1 << 20)
 353    uint32 wr_data;
 354    uint32 timeout;
 355    uint32 rd_data;
 356    uint32 unused[4];
 357 } PMBMaster;
 358
 359 typedef struct PMAPVTMONControl {
 360    uint32 control;
 361    uint32 reserved;
 362    uint32 cfg_lo;
 363    uint32 cfg_hi;
 364    uint32 data;
 365    uint32 vref_data;
 366    uint32 unused[2];
 367    uint32 ascan_cfg;
 368    uint32 warn_temp;
 369    uint32 reset_temp;
 370    uint32 temp_value;
 371    uint32 data1_value;
 372    uint32 data2_value;
 373    uint32 data3_value;
 374 } PMAPVTMONControl;
 375
 376 typedef struct PMUBUSCfg {
 377    uint32 window[8];
 378    uint32 control;
 379 } PMUBUSCfg;
 380
 381 typedef struct ProcessMonitorRegs {
 382    uint32 MonitorCtrl;     /* 0x00 */
 383    uint32 unused0[7];
 384    PMRingOscillatorControl ROSC; /* 0x20 */
 385    uint32 unused1;
 386    PMMiscControl Misc;     /* 0x40 */
 387    PMSSBMasterControl SSBMaster; /* 0x60 */
 388    uint32 unused2[5];
 389    PMEctrControl Ectr;     /* 0x80 */
 390    uint32 unused3[11];
 391    PMBMaster PMBM[2];      /* 0xc0 */
 392    PMAPVTMONControl APvtmonCtrl; /* 0x100 */
 393    uint32 unused4[9];
 394    PMUBUSCfg UBUSCfg;      /* 0x160 */
 395 } ProcessMonitorRegs;
 396
 397 #define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
 398
 399
 400 /*
 401  * Timer
 402  */
 403 typedef struct Timer {
 404    uint32 TimerCtl0; /* 0x00 */
 405    uint32 TimerCtl1; /* 0x04 */
 406    uint32 TimerCtl2; /* 0x08 */
 407    uint32 TimerCtl3; /* 0x0c */
 408 #define TIMERENABLE     (1 << 31)
 409 #define RSTCNTCLR    (1 << 30)
 410
 411    uint32 TimerCnt0; /* 0x10 */
 412    uint32 TimerCnt1; /* 0x14 */
 413    uint32 TimerCnt2; /* 0x18 */
 414    uint32 TimerCnt3; /* 0x1c */
 415 #define TIMER_COUNT_MASK   0x3FFFFFFF
 416
 417    uint32 TimerMask; /* 0x20 */
 418 #define TIMER0EN     (1 << 0)
 419 #define TIMER1EN     (1 << 1)
 420 #define TIMER2EN     (1 << 2)
 421 #define TIMER3EN     (1 << 3)
 422
 423    uint32 TimerInts; /* 0x24 */
 424 #define TIMER0       (1 << 0)
 425 #define TIMER1       (1 << 1)
 426 #define TIMER2       (1 << 2)
 427 #define TIMER3       (1 << 3)
 428 #define WATCHDOG     (1 << 4)
 429
 430    uint32 WatchDogDefCount;   /* 0x28 */
 431
 432    /* Write 0xff00 0x00ff to Start timer
 433     * Write 0xee00 0x00ee to Stop and re-load default count
 434     * Read from this register returns current watch dog count
 435     */
 436    uint32 WatchDogCtl;  /* 0x2c */
 437
 438    /* Number of 50-MHz ticks for WD Reset pulse to last */
 439    uint32 WDResetCount; /* 0x30 */
 440    uint32 SoftRst;           /* 0x34 */
 441 #define SOFT_RESET              (1 << 0)
 442    uint32 ResetStatus;   /* 0x38 */
 443 #define PCIE_RESET_STATUS       0x10000000
 444 #define SW_RESET_STATUS         0x20000000
 445 #define HW_RESET_STATUS         0x40000000
 446 #define POR_RESET_STATUS        0x80000000
 447 #define RESET_STATUS_MASK       0xF0000000
 448 } Timer;
 449
 450 #define TIMER ((volatile Timer * const) TIMR_BASE)
 451
 452 #endif /* __ASSEMBLER__ */
 453
 454 #ifdef __cplusplus
 455 }
 456 #endif
 457
 458 #endif