plat/bcm/include/bcm963xx/63178_map_part.h

   1 /*
   2 <:copyright-BRCM:2015:DUAL/GPL:standard
   3
   4    Copyright (c) 2015 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22
  23 */
  24
  25 #ifndef __BCM63178_MAP_PART_H
  26 #define __BCM63178_MAP_PART_H
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #include "bcmtypes.h"
  32
  33 #define MEMC_PHYS_BASE          0x80180000
  34 #define MEMC_SIZE               0x24000
  35
  36 #define PMC_PHYS_BASE           0x80200000
  37 #define PMC_SIZE                0x00200000
  38 #define PMC_OFFSET              0x00100000
  39 #define PROC_MON_OFFSET         0x00100000
  40 #define PMB_OFFSET              0x00120100
  41
  42 #define PERF_PHYS_BASE          0xff800000
  43 #define PERF_SIZE               0x13000
  44 #define TIMR_OFFSET             0x0400
  45 #define WDTIMR0_OFFSET          0x0480
  46 #define WDTIMR1_OFFSET          0x04c0
  47
  48 #define BIUCFG_PHYS_BASE        0x81060000
  49 #define BIUCFG_SIZE             0x3000
  50 #define BIUCFG_OFFSET           0x0000
  51
  52 #define BOOTLUT_PHYS_BASE       0xffff0000
  53 #define BOOTLUT_SIZE            0x1000
  54
  55 #define GIC_PHYS_BASE           0x81000000
  56 #define GIC_SIZE                0x10000
  57 #define GIC_OFFSET              0x0000
  58 #define GICD_OFFSET             0x1000
  59 #define GICC_OFFSET             0x2000
  60
  61 #define PMC_BASE                (PMC_PHYS_BASE + PMC_OFFSET)
  62 #define PMB_BASE                (PMC_PHYS_BASE + PMB_OFFSET)
  63 #define PROC_MON_BASE           (PMC_PHYS_BASE + PROC_MON_OFFSET)
  64
  65 #define WDTIMR0_BASE            (PERF_PHYS_BASE + WDTIMR0_OFFSET)
  66 #define TIMR_BASE               (PERF_PHYS_BASE + TIMR_OFFSET)
  67
  68 #define BIUCFG_BASE             (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
  69
  70
  71 #ifndef __ASSEMBLER__
  72
  73 /*
  74  * Power Management Control
  75  */
  76 typedef struct PmcCtrlReg {
  77     uint32 gpTmr0Ctl;           /* 0x018 */
  78     uint32 gpTmr0Cnt;           /* 0x01c */
  79     uint32 gpTmr1Ctl;           /* 0x020 */
  80     uint32 gpTmr1Cnt;           /* 0x024 */
  81     uint32 hostMboxIn;          /* 0x028 */
  82     uint32 hostMboxOut;         /* 0x02c */
  83     uint32 reserved[4];         /* 0x030 */
  84     uint32 dmaCtrl;             /* 0x040 */
  85     uint32 dmaStatus;           /* 0x044 */
  86     uint32 dma0_3FifoStatus;    /* 0x048 */
  87     uint32 reserved1[4];            /* 0x04c */
  88     uint32 diagControl;         /* 0x05c */
  89     uint32 diagHigh;            /* 0x060 */
  90     uint32 diagLow;             /* 0x064 */
  91     uint32 reserved8;           /* 0x068 */
  92     uint32 addr1WndwMask;       /* 0x06c */
  93     uint32 addr1WndwBaseIn;     /* 0x070 */
  94     uint32 addr1WndwBaseOut;    /* 0x074 */
  95     uint32 addr2WndwMask;       /* 0x078 */
  96     uint32 addr2WndwBaseIn;     /* 0x07c */
  97     uint32 addr2WndwBaseOut;    /* 0x080 */
  98     uint32 scratch;             /* 0x084 */
  99     uint32 reserved9;           /* 0x088 */
 100     uint32 softResets;          /* 0x08c */
 101     uint32 reserved2;           /* 0x090 */
 102     uint32 m4keCoreStatus;      /* 0x094 */
 103     uint32 reserved3;           /* 0x098 */
 104     uint32 ubSlaveTimeout;      /* 0x09c */
 105     uint32 diagEn;              /* 0x0a0 */
 106     uint32 devTimeout;          /* 0x0a4 */
 107     uint32 ubusErrorOutMask;    /* 0x0a8 */
 108     uint32 diagCaptStopMask;    /* 0x0ac */
 109     uint32 revId;               /* 0x0b0 */
 110     uint32 reserved4[4];        /* 0x0b4 */
 111     uint32 diagCtrl;            /* 0x0c4 */
 112     uint32 diagStat;            /* 0x0c8 */
 113     uint32 diagMask;            /* 0x0cc */
 114     uint32 diagRslt;            /* 0x0d0 */
 115     uint32 diagCmp;             /* 0x0d4 */
 116     uint32 diagCapt;            /* 0x0d8 */
 117     uint32 diagCnt;             /* 0x0dc */
 118     uint32 diagEdgeCnt;         /* 0x0e0 */
 119     uint32 reserved5[4];            /* 0x0e4 */
 120     uint32 smisc_bus_config;    /* 0x0f4 */
 121     uint32 lfsr;                /* 0x0f8 */
 122     uint32 dqm_pac_lock;        /* 0x0fc */
 123     uint32 l1_irq_4ke_mask;     /* 0x100 */
 124     uint32 l1_irq_4ke_status;   /* 0x104 */
 125     uint32 l1_irq_mips_mask;    /* 0x108 */
 126     uint32 l1_irq_mips_status;  /* 0x10c */
 127     uint32 l1_irq_mips1_mask;   /* 0x110 */
 128     uint32 reserved6[3];        /* 0x114 */
 129     uint32 l2_irq_gp_mask;      /* 0x120 */
 130     uint32 l2_irq_gp_status;    /* 0x124 */
 131     uint32 l2_irq_gp_set;       /* 0x128 */
 132     uint32 reserved7;           /* 0x12c */
 133     uint32 gp_in_irq_mask;      /* 0x130 */
 134     uint32 gp_in_irq_status;    /* 0x134 */
 135     uint32 gp_in_irq_set;       /* 0x138 */
 136     uint32 gp_in_irq_sense;     /* 0x13c */
 137     uint32 gp_in;               /* 0x140 */
 138     uint32 gp_out;              /* 0x144 */
 139 } PmcCtrlReg;
 140
 141 typedef struct PmcDmaReg {
 142         /* 0x00 */
 143         uint32 src;
 144         uint32 dest;
 145         uint32 cmdList;
 146         uint32 lenCtl;
 147         /* 0x10 */
 148         uint32 rsltSrc;
 149         uint32 rsltDest;
 150         uint32 rsltHcs;
 151         uint32 rsltLenStat;
 152 } PmcDmaReg;
 153
 154 typedef struct PmcTokenReg {
 155         /* 0x00 */
 156         uint32 bufSize;
 157         uint32 bufBase;
 158         uint32 idx2ptrIdx;
 159         uint32 idx2ptrPtr;
 160         /* 0x10 */
 161         uint32 unused[2];
 162         uint32 bufSize2;
 163 } PmcTokenReg;
 164
 165 typedef struct PmcPerfPowReg {
 166         uint32 freqScalarCtrl; /* 0x3c */
 167         uint32 freqScalarMask; /* 0x40 */
 168 } PmcPerfPowReg;
 169
 170 typedef struct PmcDQMPac {
 171     uint32 dqmPac[32];
 172 } PmcDQMPac;
 173
 174 typedef struct PmcDQMReg {
 175         uint32 cfg;                     /* 0x1c00 */
 176         uint32 _4keLowWtmkIrqMask;      /* 0x1c04 */
 177         uint32 mipsLowWtmkIrqMask;      /* 0x1c08 */
 178         uint32 lowWtmkIrqMask;          /* 0x1c0c */
 179         uint32 _4keNotEmptyIrqMask;     /* 0x1c10 */
 180         uint32 mipsNotEmptyIrqMask;     /* 0x1c14 */
 181         uint32 notEmptyIrqSts;          /* 0x1c18 */
 182         uint32 queueRst;                /* 0x1c1c */
 183         uint32 notEmptySts;             /* 0x1c20 */
 184         uint32 nextAvailMask;           /* 0x1c24 */
 185         uint32 nextAvailQueue;          /* 0x1c28 */
 186         uint32 mips1LowWtmkIrqMask;     /* 0x1c2c */
 187         uint32 mips1NotEmptyIrqMask;    /* 0x1c30 */
 188         uint32 autoSrcPidInsert;        /* 0x1c34 */
 189     uint32 timerIrqStatus;          /* 0x1c38 */
 190     uint32 timerStatus;             /* 0x1c3c */
 191     uint32 _4keTimerIrqMask;        /* 0x1c40 */
 192     uint32 mipsTimerIrqMask;        /* 0x1c44 */
 193     uint32 mips1TimerIrqMask;       /* 0x1c48 */
 194 } PmcDQMReg;
 195
 196 typedef struct PmcCntReg {
 197         uint32 cntr[10];
 198         uint32 unused[6];       /* 0x28-0x3f */
 199         uint32 cntrIrqMask;
 200         uint32 cntrIrqSts;
 201 } PmcCntReg;
 202
 203 typedef struct PmcDqmQCtrlReg {
 204         uint32 size;
 205         uint32 cfga;
 206         uint32 cfgb;
 207         uint32 cfgc;
 208 } PmcDqmQCtrlReg;
 209
 210 typedef struct PmcDqmQDataReg {
 211         uint32 word[4];
 212 } PmcDqmQDataReg;
 213
 214 typedef struct PmcDqmQMibReg {
 215         uint32 qNumFull[32];
 216         uint32 qNumEmpty[32];
 217         uint32 qNumPushed[32];
 218 } PmcDqmQMibReg;
 219
 220 typedef struct SSBMaster {
 221     uint32 ssbmControl;     /* 0x0060 */
 222     uint32 ssbmWrData;      /* 0x0064 */
 223     uint32 ssbmRdData;      /* 0x0068 */
 224     uint32 ssbmStatus;      /* 0x006c */
 225 } SSBMaster;
 226
 227 typedef struct PmmReg {
 228     uint32 memPowerCtrl;            /* 0x0000 */
 229     uint32 regSecurityConfig;       /* 0x0004 */
 230 } PmmReg;
 231
 232 typedef struct keyholeReg {
 233     uint32 ctrlSts;
 234     uint32 wrData;
 235     uint32 mutex;
 236     uint32 rdData;
 237 } keyholeReg;
 238
 239 typedef struct PmbBus {
 240     uint32 config;          /* 0x0100 */
 241     uint32 arbiter;         /* 0x0104 */
 242     uint32 timeout;         /* 0x0108 */
 243     uint32 unused1;         /* 0x010c */
 244     keyholeReg keyhole[4];  /* 0x0110-0x014f */
 245     uint32 unused2[44];     /* 0x0150-0x01ff */
 246     uint32 map[64];         /* 0x0200-0x02ff */
 247 }PmbBus;
 248
 249 typedef struct  CoreCtrl {
 250     uint32  coreEnable;         /* 0x0400 */
 251     uint32  autoresetControl;   /* 0x0404 */
 252     uint32  coreIdle;           /* 0x0408 */
 253     uint32  coreResetCause;     /* 0x040c */
 254     uint32  memPwrDownCtrl0;    /* 0x0410 */
 255     uint32  memPwrDownSts0;     /* 0x0414 */
 256     uint32  memPwrDownCtrl1;    /* 0x0418 */
 257     uint32  memPwrDownSts1;     /* 0x041c */
 258     uint32  sysFlg0Status;      /* 0x0420 */
 259     uint32  sysFlg0Set;         /* 0x0424 */
 260     uint32  sysFlg0Clear;       /* 0x0428 */
 261     uint32  unused1;            /* 0x042c */
 262     uint32  usrFlg0Status;      /* 0x0430 */
 263     uint32  usrFlg0Set;         /* 0x0434 */
 264     uint32  usrFlg0Clear;       /* 0x0438 */
 265     uint32  unused2;            /* 0x043c */
 266     uint32  subsystemRev;       /* 0x0440 */
 267     uint32  resetVector;        /* 0x0444 */
 268 } CoreCtrl;
 269
 270 typedef struct  CoreState {
 271     uint32  sysMbx[8];          /* 0x0480 */
 272     uint32  usrMbx[8];          /* 0x04a0 */
 273     uint32  sysMtx[4];          /* 0x04c0 */
 274     uint32  usrMtx[8];          /* 0x04d0 */
 275 } CoreState;
 276
 277 typedef struct  CoreIntr {
 278     uint32  irqStatus;          /* 0x0500 */
 279     uint32  irqSet;             /* 0x0504 */
 280     uint32  irqClear;           /* 0x0508 */
 281     uint32  unused1;            /* 0x050c */
 282     uint32  srqStatus;          /* 0x0510 */
 283     uint32  srqSet;             /* 0x0514 */
 284     uint32  srqClear;           /* 0x0518 */
 285     uint32  unused2;            /* 0x051c */
 286     uint32  drqStatus;          /* 0x0520 */
 287     uint32  drqSet;             /* 0x0524 */
 288     uint32  drqClear;           /* 0x0528 */
 289     uint32  unused3;            /* 0x052c */
 290     uint32  frqStatus;          /* 0x0530 */
 291     uint32  frqSet;             /* 0x0534 */
 292     uint32  frqClear;           /* 0x0538 */
 293     uint32  unused4;            /* 0x053c */
 294     uint32  hostIrqLatched;     /* 0x0540 */
 295     uint32  hostIrqSet;         /* 0x0544 */
 296     uint32  hostIrqClear;       /* 0x0548 */
 297     uint32  hostIrqEnable;      /* 0x054c */
 298     uint32  obusFaultStatus;    /* 0x0550 */
 299     uint32  obusFaultClear;     /* 0x0554 */
 300     uint32  obusFaultAddr;      /* 0x0558 */
 301 } CoreIntr;
 302
 303 typedef struct CoreProfile {
 304     uint32  mutex;              /* 0x0580 */
 305     uint32  lastConfPcLo;       /* 0x0584 */
 306     uint32  lastConfPcHi;       /* 0x0588 */
 307     uint32  lastPcLo;           /* 0x058c */
 308     uint32  lastPcHi;           /* 0x0590 */
 309     uint32  braTargetPc0Lo;     /* 0x0594 */
 310     uint32  braTargetPc0Hi;     /* 0x0598 */
 311     uint32  braTargetPc1Lo;     /* 0x059c */
 312     uint32  braTargetPc1Hi;     /* 0x05a0 */
 313     uint32  braTargetPc2Lo;     /* 0x05a4 */
 314     uint32  braTargetPc2Hi;     /* 0x05a8 */
 315     uint32  braTargetPc3Lo;     /* 0x05ac */
 316     uint32  braTargetPc3Hi;     /* 0x05b0 */
 317     uint32  unused[3];          /* 0x05b4-0x05bf */
 318     uint32  profSampleW[4];     /* 0x05c0 */
 319 } CoreProfile;
 320
 321 typedef struct MaestroMisc {
 322     CoreCtrl coreCtrl;          /* 0x0400 */
 323     uint32   unused1[14];       /* 0x0448-0x047f */
 324     CoreState coreState;        /* 0x0480 */
 325     uint32   unused2[4];        /* 0x04f0-0x04ff */
 326     CoreIntr interrupt;         /* 0x0500 */
 327     uint32   unused3[9];        /* 0x055c-0x057f */
 328     CoreProfile profile;        /* 0x0580 */
 329 } MaestroMisc;
 330
 331 typedef struct Pmc {
 332     uint32 unused0[1030];
 333     PmcCtrlReg ctrl;                        /* 0x1018 */
 334     uint32 unused1[622];                    /* 0x1148-0x1cff */
 335     PmcDQMPac dqmPac;                   /* 0x1b00 */
 336     uint32 unused5[32];                 /* 0x1b80-0x1bff */
 337     PmcDQMReg dqm;                                  /* 0x1c00 */
 338     uint32 unused6[749];                        /* 0x1c4c-0x27ff */
 339     uint32 qStatus[32];                     /* 0x2800 */
 340     uint32 unused7[480];                    /* 0x2880-0x2fff */
 341     PmcDqmQMibReg qMib;                     /* 0x3000 */
 342     uint32 unused8[928];                    /* 0x3180-0x3fff */
 343     PmcDqmQCtrlReg dqmQCtrl[8];             /* 0x4000 */
 344     uint32 unused9[992];                /* 0x4080-0x4fff */
 345     PmcDqmQDataReg dqmQData[8];             /* 0x5000 */
 346 } Pmc;
 347 #define PMC ((volatile Pmc * const) PMC_BASE)
 348
 349 typedef struct Procmon {
 350     uint32 unused00[256];
 351     MaestroMisc maestroReg;             /* 0x00400 */
 352     uint32 unused10[32396];             /* 0x005d0-0x1ffff */
 353     PmmReg  pmm;                        /* 0x20000 */
 354     uint32 unused11[22];                /* 0x20008-0x2005f */
 355     SSBMaster ssbMasterCtrl;            /* 0x20060 */
 356     uint32 unused12[36];                /* 0x20070-0x200ff */
 357     PmbBus pmb;                         /* 0x20100 */
 358     uint32 unused13[32576];             /* 0x20300-0x3ffff */
 359     uint32 qsm[128];                    /* 0x40000-0x401ff */
 360     uint32 unused14[65408];             /* 0x40200-0x7ffff */
 361     uint32 dtcm[1024];                  /* 0x80000-0x80fff */
 362 } Procmon;
 363 #define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
 364
 365 typedef struct PMSSBMasterControl {
 366         uint32 control;
 367         uint32 wr_data;
 368         uint32 rd_data;
 369 } PMSSBMasterControl;
 370
 371 typedef struct
 372 {
 373     uint32  control;
 374 #define PMC_PMBM_START                      (1 << 31)
 375 #define PMC_PMBM_TIMEOUT                    (1 << 30)
 376 #define PMC_PMBM_SLAVE_ERR                  (1 << 29)
 377 #define PMC_PMBM_BUSY                       (1 << 28)
 378 #define PMC_PMBM_BUS_SHIFT                  (20)
 379 #define PMC_PMBM_Read                       (0 << 24)
 380 #define PMC_PMBM_Write                      (1 << 24)
 381     uint32  wr_data;
 382     uint32  mutex;
 383     uint32  rd_data;
 384 } PMB_keyhole_reg;
 385
 386 typedef struct PMBMaster {
 387     uint32 config;
 388 #define PMB_NUM_REGS_SHIFT (20)
 389 #define PMB_NUM_REGS_MASK  (0x3ff)
 390     uint32 arbitger;
 391     uint32 timeout;
 392     uint32 reserved;
 393     PMB_keyhole_reg keyhole[4];
 394     uint32 reserved1[44];
 395     uint32 map[64];
 396 } PMBMaster;
 397 #define PMB ((volatile PMBMaster * const) PMB_BASE)
 398
 399 /* WatchDog */
 400 typedef struct WDTimer {
 401     uint32        WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer
 402      * Write 0xee00 0x00ee to Stop and re-load default count
 403      *      *      * Read from this register returns current watch dog count
 404      *           *           */
 405     uint32        WatchDogCtl;
 406
 407     /* Number of 50-MHz ticks for WD Reset pulse to last */
 408     uint32        WDResetCount;
 409
 410 #define SOFT_RESET              0x00000001
 411     uint32        WDTimerCtl;
 412
 413     uint32        WDAccessCtl;
 414 } WDTimer;
 415
 416 #define TIMER ((volatile Timer * const) TIMR_BASE)
 417 #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE)
 418
 419
 420 /* BIU - Bus Interface Unit */
 421 typedef struct BIUCFG_Access {
 422     uint32 permission;        /* 0x0 */
 423     uint32 sbox;              /* 0x4 */
 424     uint32 cpu_defeature;     /* 0x8 */
 425     uint32 dbg_security;      /* 0xc */
 426     uint32 rsvd1[32];         /* 0x10 - 0x8f */
 427     uint64 violation[2];      /* 0x90 - 0x9f */
 428     uint32 ts_access[2];      /* 0xa0 - 0xa7 */
 429     uint32 rsvd2[22];         /* 0xa8 - 0xff */
 430 }BIUCFG_Access;
 431
 432
 433
 434
 435 typedef struct BIUCFG_Cluster {
 436     uint32 permission;        /* 0x0 */
 437     uint32 config;            /* 0x4 */
 438     uint32 status;            /* 0x8 */
 439     uint32 control;           /* 0xc */
 440     uint32 cpucfg;            /* 0x10 */
 441     uint32 dbgrom;            /* 0x14 */
 442     uint32 rsvd1[2];          /* 0x18 - 0x1f */
 443     uint64 rvbar_addr[4];     /* 0x20 - 0x3f */
 444     uint32 rsvd2[48];         /* 0x40 - 0xff */
 445 }BIUCFG_Cluster;
 446
 447 typedef struct BIUCFG_Bac {
 448     uint32 bac_permission;    /* 0x00 */
 449     uint32 bac_periphbase;    /* 0x04 */
 450     uint32 rsvd[2];           /* 0x08 - 0x0f */
 451     uint32 bac_event;         /* 0x10 */
 452     uint32 rsvd_1[3];         /* 0x14 - 0x1f */
 453     uint32 bac_ccicfg;        /* 0x20 */
 454     uint32 bac_cciaddr;       /* 0x24 */
 455     uint32 rsvd_2[4];         /* 0x28 - 0x37 */
 456     uint32 bac_ccievs2;       /* 0x38 */
 457     uint32 bac_ccievs3;       /* 0x3c */
 458     uint32 bac_ccievs4;       /* 0x40 */
 459     uint32 rsvd_3[3];         /* 0x44 - 0x4f */
 460     uint32 bac_ccievm0;       /* 0x50 */
 461     uint32 bac_ccievm1;       /* 0x54 */
 462     uint32 rsvd_4[2];         /* 0x58 - 0x5f */
 463     uint32 bac_dapapbcfg;     /* 0x60 */
 464     uint32 bac_status;        /* 0x64 */
 465     uint32 rsvd_5[2];         /* 0x68 - 0x6f */
 466     uint32 cpu_therm_irq_cfg; /* 0x70 */
 467     uint32 cpu_therm_threshold_cfg; /* 0x74 */
 468     uint32 rsvd_6;            /* 0x78 */
 469     uint32 cpu_therm_temp;    /* 0x7c */
 470     uint32 rsvd_7[32];        /* 0x80 - 0xff */
 471 } BIUCFG_Bac;
 472
 473 typedef struct BIUCFG_Aux {
 474     uint32 aux_permission;    /* 0x00 */
 475     uint32 rsvd[3];           /* 0x04 - 0x0f */
 476     uint32 c0_clk_control;    /* 0x10 */
 477     uint32 c0_clk_ramp;       /* 0x14 */
 478     uint32 c0_clk_pattern;    /* 0x18 */
 479     uint32 rsvd_1;            /* 0x1c */
 480     uint32 c1_clk_control;    /* 0x20 */
 481     uint32 c1_clk_ramp;       /* 0x24 */
 482     uint32 c1_clk_pattern;    /* 0x28 */
 483     uint32 rsvd_2[53];        /* 0x2c - 0xff */
 484 } BIUCFG_Aux;
 485
 486 typedef struct BIUCFG {
 487     BIUCFG_Access access;         /* 0x0 - 0xff*/
 488     BIUCFG_Cluster cluster[2];    /* 0x100 - 0x2ff*/
 489     BIUCFG_Bac bac;               /* 0x300 - 0x3ff */
 490     uint32 anonymous[192];        /* 0x400 - 0x6ff */
 491     BIUCFG_Aux aux;               /* 0x700 - 0x7ff */
 492     uint32 anonymous_1[2560];     /* 0x800 - 0x2fff */
 493 }BIUCFG;
 494 #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
 495
 496 #endif /* __ASSEMBLER__ */
 497
 498 #ifdef __cplusplus
 499 }
 500 #endif
 501
 502 #endif
 503